xref: /linux/drivers/gpu/drm/i915/i915_irq.h (revision b4db9f840283caca0d904436f187ef56a9126eaa)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2019 Intel Corporation
4  */
5 
6 #ifndef __I915_IRQ_H__
7 #define __I915_IRQ_H__
8 
9 #include <linux/ktime.h>
10 #include <linux/types.h>
11 
12 #include "i915_reg_defs.h"
13 
14 enum pipe;
15 struct drm_crtc;
16 struct drm_device;
17 struct drm_display_mode;
18 struct drm_i915_private;
19 struct intel_crtc;
20 struct intel_encoder;
21 struct intel_uncore;
22 
23 void intel_irq_init(struct drm_i915_private *dev_priv);
24 void intel_irq_fini(struct drm_i915_private *dev_priv);
25 int intel_irq_install(struct drm_i915_private *dev_priv);
26 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
27 
28 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
29 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
30 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
31 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
32 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
33 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
34 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
35 u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915, u32 mask);
36 
37 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
38 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
39 bool intel_irqs_enabled(struct drm_i915_private *dev_priv);
40 void intel_synchronize_irq(struct drm_i915_private *i915);
41 void intel_synchronize_hardirq(struct drm_i915_private *i915);
42 
43 void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg);
44 
45 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
46 		    i915_reg_t iir, i915_reg_t ier);
47 
48 void gen3_irq_init(struct intel_uncore *uncore,
49 		   i915_reg_t imr, u32 imr_val,
50 		   i915_reg_t ier, u32 ier_val,
51 		   i915_reg_t iir);
52 
53 #define GEN8_IRQ_RESET_NDX(uncore, type, which) \
54 ({ \
55 	unsigned int which_ = which; \
56 	gen3_irq_reset((uncore), GEN8_##type##_IMR(which_), \
57 		       GEN8_##type##_IIR(which_), GEN8_##type##_IER(which_)); \
58 })
59 
60 #define GEN3_IRQ_RESET(uncore, type) \
61 	gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER)
62 
63 #define GEN8_IRQ_INIT_NDX(uncore, type, which, imr_val, ier_val) \
64 ({ \
65 	unsigned int which_ = which; \
66 	gen3_irq_init((uncore), \
67 		      GEN8_##type##_IMR(which_), imr_val, \
68 		      GEN8_##type##_IER(which_), ier_val, \
69 		      GEN8_##type##_IIR(which_)); \
70 })
71 
72 #define GEN3_IRQ_INIT(uncore, type, imr_val, ier_val) \
73 	gen3_irq_init((uncore), \
74 		      type##IMR, imr_val, \
75 		      type##IER, ier_val, \
76 		      type##IIR)
77 
78 #endif /* __I915_IRQ_H__ */
79