1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- 2 */ 3 /* 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 */ 28 29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 30 31 #include <linux/slab.h> 32 #include <linux/sysrq.h> 33 34 #include <drm/drm_drv.h> 35 #include <drm/drm_print.h> 36 #include <drm/intel/display_parent_interface.h> 37 #include <drm/intel/intel_gmd_interrupt_regs.h> 38 39 #include "display/intel_display_irq.h" 40 #include "display/intel_hotplug.h" 41 #include "display/intel_hotplug_irq.h" 42 #include "display/intel_lpe_audio.h" 43 44 #include "gt/intel_breadcrumbs.h" 45 #include "gt/intel_gt.h" 46 #include "gt/intel_gt_irq.h" 47 #include "gt/intel_gt_pm_irq.h" 48 #include "gt/intel_gt_regs.h" 49 #include "gt/intel_rps.h" 50 51 #include "i915_driver.h" 52 #include "i915_drv.h" 53 #include "i915_irq.h" 54 #include "i915_reg.h" 55 56 /** 57 * DOC: interrupt handling 58 * 59 * These functions provide the basic support for enabling and disabling the 60 * interrupt handling support. There's a lot more functionality in i915_irq.c 61 * and related files, but that will be described in separate chapters. 62 */ 63 64 /* 65 * Interrupt statistic for PMU. Increments the counter only if the 66 * interrupt originated from the GPU so interrupts from a device which 67 * shares the interrupt line are not accounted. 68 */ 69 static inline void pmu_irq_stats(struct drm_i915_private *i915, 70 irqreturn_t res) 71 { 72 if (unlikely(res != IRQ_HANDLED)) 73 return; 74 75 /* 76 * A clever compiler translates that into INC. A not so clever one 77 * should at least prevent store tearing. 78 */ 79 WRITE_ONCE(i915->pmu.irq_count, i915->pmu.irq_count + 1); 80 } 81 82 void gen2_irq_reset(struct intel_uncore *uncore, struct i915_irq_regs regs) 83 { 84 intel_uncore_write(uncore, regs.imr, 0xffffffff); 85 intel_uncore_posting_read(uncore, regs.imr); 86 87 intel_uncore_write(uncore, regs.ier, 0); 88 89 /* IIR can theoretically queue up two events. Be paranoid. */ 90 intel_uncore_write(uncore, regs.iir, 0xffffffff); 91 intel_uncore_posting_read(uncore, regs.iir); 92 intel_uncore_write(uncore, regs.iir, 0xffffffff); 93 intel_uncore_posting_read(uncore, regs.iir); 94 } 95 96 /* 97 * We should clear IMR at preinstall/uninstall, and just check at postinstall. 98 */ 99 void gen2_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg) 100 { 101 u32 val = intel_uncore_read(uncore, reg); 102 103 if (val == 0) 104 return; 105 106 drm_WARN(&uncore->i915->drm, 1, 107 "Interrupt register 0x%x is not zero: 0x%08x\n", 108 i915_mmio_reg_offset(reg), val); 109 intel_uncore_write(uncore, reg, 0xffffffff); 110 intel_uncore_posting_read(uncore, reg); 111 intel_uncore_write(uncore, reg, 0xffffffff); 112 intel_uncore_posting_read(uncore, reg); 113 } 114 115 void gen2_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs, 116 u32 imr_val, u32 ier_val) 117 { 118 gen2_assert_iir_is_zero(uncore, regs.iir); 119 120 intel_uncore_write(uncore, regs.ier, ier_val); 121 intel_uncore_write(uncore, regs.imr, imr_val); 122 intel_uncore_posting_read(uncore, regs.imr); 123 } 124 125 void gen2_error_reset(struct intel_uncore *uncore, struct i915_error_regs regs) 126 { 127 intel_uncore_write(uncore, regs.emr, 0xffffffff); 128 intel_uncore_posting_read(uncore, regs.emr); 129 130 intel_uncore_write(uncore, regs.eir, 0xffffffff); 131 intel_uncore_posting_read(uncore, regs.eir); 132 intel_uncore_write(uncore, regs.eir, 0xffffffff); 133 intel_uncore_posting_read(uncore, regs.eir); 134 } 135 136 void gen2_error_init(struct intel_uncore *uncore, struct i915_error_regs regs, 137 u32 emr_val) 138 { 139 intel_uncore_write(uncore, regs.eir, 0xffffffff); 140 intel_uncore_posting_read(uncore, regs.eir); 141 intel_uncore_write(uncore, regs.eir, 0xffffffff); 142 intel_uncore_posting_read(uncore, regs.eir); 143 144 intel_uncore_write(uncore, regs.emr, emr_val); 145 intel_uncore_posting_read(uncore, regs.emr); 146 } 147 148 /** 149 * ivb_parity_work - Workqueue called when a parity error interrupt 150 * occurred. 151 * @work: workqueue struct 152 * 153 * Doesn't actually do anything except notify userspace. As a consequence of 154 * this event, userspace should try to remap the bad rows since statistically 155 * it is likely the same row is more likely to go bad again. 156 */ 157 static void ivb_parity_work(struct work_struct *work) 158 { 159 struct drm_i915_private *dev_priv = 160 container_of(work, typeof(*dev_priv), l3_parity.error_work); 161 struct intel_gt *gt = to_gt(dev_priv); 162 u32 error_status, row, bank, subbank; 163 char *parity_event[6]; 164 u32 misccpctl; 165 u8 slice = 0; 166 167 168 /* If we've screwed up tracking, just let the interrupt fire again */ 169 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice)) 170 goto out; 171 172 misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL, 173 GEN7_DOP_CLOCK_GATE_ENABLE, 0); 174 intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL); 175 176 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { 177 i915_reg_t reg; 178 179 slice--; 180 if (drm_WARN_ON_ONCE(&dev_priv->drm, 181 slice >= NUM_L3_SLICES(dev_priv))) 182 break; 183 184 dev_priv->l3_parity.which_slice &= ~(1<<slice); 185 186 reg = GEN7_L3CDERRST1(slice); 187 188 error_status = intel_uncore_read(&dev_priv->uncore, reg); 189 row = GEN7_PARITY_ERROR_ROW(error_status); 190 bank = GEN7_PARITY_ERROR_BANK(error_status); 191 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); 192 193 intel_uncore_write(&dev_priv->uncore, reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); 194 intel_uncore_posting_read(&dev_priv->uncore, reg); 195 196 parity_event[0] = I915_L3_PARITY_UEVENT "=1"; 197 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); 198 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); 199 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); 200 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); 201 parity_event[5] = NULL; 202 203 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj, 204 KOBJ_CHANGE, parity_event); 205 206 drm_dbg(&dev_priv->drm, 207 "Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", 208 slice, row, bank, subbank); 209 210 kfree(parity_event[4]); 211 kfree(parity_event[3]); 212 kfree(parity_event[2]); 213 kfree(parity_event[1]); 214 } 215 216 intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl); 217 218 out: 219 drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice); 220 spin_lock_irq(gt->irq_lock); 221 gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv)); 222 spin_unlock_irq(gt->irq_lock); 223 224 } 225 226 static irqreturn_t valleyview_irq_handler(int irq, void *arg) 227 { 228 struct drm_i915_private *dev_priv = arg; 229 struct intel_display *display = dev_priv->display; 230 irqreturn_t ret = IRQ_NONE; 231 232 if (!intel_irqs_enabled(dev_priv)) 233 return IRQ_NONE; 234 235 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 236 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 237 238 do { 239 u32 iir, gt_iir, pm_iir; 240 u32 eir = 0, dpinvgtt = 0; 241 u32 pipe_stats[I915_MAX_PIPES] = {}; 242 u32 hotplug_status = 0; 243 u32 ier = 0; 244 245 gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR); 246 pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR); 247 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR); 248 249 if (gt_iir == 0 && pm_iir == 0 && iir == 0) 250 break; 251 252 ret = IRQ_HANDLED; 253 254 /* 255 * Theory on interrupt generation, based on empirical evidence: 256 * 257 * x = ((VLV_IIR & VLV_IER) || 258 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) && 259 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE))); 260 * 261 * A CPU interrupt will only be raised when 'x' has a 0->1 edge. 262 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to 263 * guarantee the CPU interrupt will be raised again even if we 264 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR 265 * bits this time around. 266 */ 267 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0); 268 ier = intel_uncore_rmw(&dev_priv->uncore, VLV_IER, ~0, 0); 269 270 if (gt_iir) 271 intel_uncore_write(&dev_priv->uncore, GTIIR, gt_iir); 272 if (pm_iir) 273 intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir); 274 275 if (iir & I915_DISPLAY_PORT_INTERRUPT) 276 hotplug_status = i9xx_hpd_irq_ack(display); 277 278 if (iir & I915_MASTER_ERROR_INTERRUPT) 279 vlv_display_error_irq_ack(display, &eir, &dpinvgtt); 280 281 /* Call regardless, as some status bits might not be 282 * signalled in IIR */ 283 i9xx_pipestat_irq_ack(display, iir, pipe_stats); 284 285 if (iir & (I915_LPE_PIPE_A_INTERRUPT | 286 I915_LPE_PIPE_B_INTERRUPT)) 287 intel_lpe_audio_irq_handler(display); 288 289 /* 290 * VLV_IIR is single buffered, and reflects the level 291 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. 292 */ 293 if (iir) 294 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir); 295 296 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier); 297 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); 298 299 if (gt_iir) 300 gen6_gt_irq_handler(to_gt(dev_priv), gt_iir); 301 if (pm_iir) 302 gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir); 303 304 if (hotplug_status) 305 i9xx_hpd_irq_handler(display, hotplug_status); 306 307 if (iir & I915_MASTER_ERROR_INTERRUPT) 308 vlv_display_error_irq_handler(display, eir, dpinvgtt); 309 310 valleyview_pipestat_irq_handler(display, pipe_stats); 311 } while (0); 312 313 pmu_irq_stats(dev_priv, ret); 314 315 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 316 317 return ret; 318 } 319 320 static irqreturn_t cherryview_irq_handler(int irq, void *arg) 321 { 322 struct drm_i915_private *dev_priv = arg; 323 struct intel_display *display = dev_priv->display; 324 irqreturn_t ret = IRQ_NONE; 325 326 if (!intel_irqs_enabled(dev_priv)) 327 return IRQ_NONE; 328 329 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 330 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 331 332 do { 333 u32 master_ctl, iir; 334 u32 eir = 0, dpinvgtt = 0; 335 u32 pipe_stats[I915_MAX_PIPES] = {}; 336 u32 hotplug_status = 0; 337 u32 ier = 0; 338 339 master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; 340 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR); 341 342 if (master_ctl == 0 && iir == 0) 343 break; 344 345 ret = IRQ_HANDLED; 346 347 /* 348 * Theory on interrupt generation, based on empirical evidence: 349 * 350 * x = ((VLV_IIR & VLV_IER) || 351 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) && 352 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL))); 353 * 354 * A CPU interrupt will only be raised when 'x' has a 0->1 edge. 355 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to 356 * guarantee the CPU interrupt will be raised again even if we 357 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL 358 * bits this time around. 359 */ 360 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0); 361 ier = intel_uncore_rmw(&dev_priv->uncore, VLV_IER, ~0, 0); 362 363 gen8_gt_irq_handler(to_gt(dev_priv), master_ctl); 364 365 if (iir & I915_DISPLAY_PORT_INTERRUPT) 366 hotplug_status = i9xx_hpd_irq_ack(display); 367 368 if (iir & I915_MASTER_ERROR_INTERRUPT) 369 vlv_display_error_irq_ack(display, &eir, &dpinvgtt); 370 371 /* Call regardless, as some status bits might not be 372 * signalled in IIR */ 373 i9xx_pipestat_irq_ack(display, iir, pipe_stats); 374 375 if (iir & (I915_LPE_PIPE_A_INTERRUPT | 376 I915_LPE_PIPE_B_INTERRUPT | 377 I915_LPE_PIPE_C_INTERRUPT)) 378 intel_lpe_audio_irq_handler(display); 379 380 /* 381 * VLV_IIR is single buffered, and reflects the level 382 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. 383 */ 384 if (iir) 385 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir); 386 387 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier); 388 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); 389 390 if (hotplug_status) 391 i9xx_hpd_irq_handler(display, hotplug_status); 392 393 if (iir & I915_MASTER_ERROR_INTERRUPT) 394 vlv_display_error_irq_handler(display, eir, dpinvgtt); 395 396 valleyview_pipestat_irq_handler(display, pipe_stats); 397 } while (0); 398 399 pmu_irq_stats(dev_priv, ret); 400 401 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 402 403 return ret; 404 } 405 406 /* 407 * To handle irqs with the minimum potential races with fresh interrupts, we: 408 * 1 - Disable Master Interrupt Control. 409 * 2 - Find the source(s) of the interrupt. 410 * 3 - Clear the Interrupt Identity bits (IIR). 411 * 4 - Process the interrupt(s) that had bits set in the IIRs. 412 * 5 - Re-enable Master Interrupt Control. 413 */ 414 static irqreturn_t ilk_irq_handler(int irq, void *arg) 415 { 416 struct drm_i915_private *i915 = arg; 417 struct intel_display *display = i915->display; 418 void __iomem * const regs = intel_uncore_regs(&i915->uncore); 419 u32 gt_iir, de_ier = 0, sde_ier = 0; 420 irqreturn_t ret = IRQ_NONE; 421 422 if (unlikely(!intel_irqs_enabled(i915))) 423 return IRQ_NONE; 424 425 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 426 disable_rpm_wakeref_asserts(&i915->runtime_pm); 427 428 /* Disable master and south interrupts */ 429 ilk_display_irq_master_disable(display, &de_ier, &sde_ier); 430 431 /* Find, clear, then process each source of interrupt */ 432 433 gt_iir = raw_reg_read(regs, GTIIR); 434 if (gt_iir) { 435 raw_reg_write(regs, GTIIR, gt_iir); 436 if (GRAPHICS_VER(i915) >= 6) 437 gen6_gt_irq_handler(to_gt(i915), gt_iir); 438 else 439 gen5_gt_irq_handler(to_gt(i915), gt_iir); 440 ret = IRQ_HANDLED; 441 } 442 443 if (ilk_display_irq_handler(display)) 444 ret = IRQ_HANDLED; 445 446 if (GRAPHICS_VER(i915) >= 6) { 447 u32 pm_iir = raw_reg_read(regs, GEN6_PMIIR); 448 if (pm_iir) { 449 raw_reg_write(regs, GEN6_PMIIR, pm_iir); 450 gen6_rps_irq_handler(&to_gt(i915)->rps, pm_iir); 451 ret = IRQ_HANDLED; 452 } 453 } 454 455 /* Re-enable master and south interrupts */ 456 ilk_display_irq_master_enable(display, de_ier, sde_ier); 457 458 pmu_irq_stats(i915, ret); 459 460 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 461 enable_rpm_wakeref_asserts(&i915->runtime_pm); 462 463 return ret; 464 } 465 466 static inline u32 gen8_master_intr_disable(void __iomem * const regs) 467 { 468 raw_reg_write(regs, GEN8_MASTER_IRQ, 0); 469 470 /* 471 * Now with master disabled, get a sample of level indications 472 * for this interrupt. Indications will be cleared on related acks. 473 * New indications can and will light up during processing, 474 * and will generate new interrupt after enabling master. 475 */ 476 return raw_reg_read(regs, GEN8_MASTER_IRQ); 477 } 478 479 static inline void gen8_master_intr_enable(void __iomem * const regs) 480 { 481 raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); 482 } 483 484 static irqreturn_t gen8_irq_handler(int irq, void *arg) 485 { 486 struct drm_i915_private *dev_priv = arg; 487 struct intel_display *display = dev_priv->display; 488 void __iomem * const regs = intel_uncore_regs(&dev_priv->uncore); 489 u32 master_ctl; 490 491 if (!intel_irqs_enabled(dev_priv)) 492 return IRQ_NONE; 493 494 master_ctl = gen8_master_intr_disable(regs); 495 if (!master_ctl) { 496 gen8_master_intr_enable(regs); 497 return IRQ_NONE; 498 } 499 500 /* Find, queue (onto bottom-halves), then clear each source */ 501 gen8_gt_irq_handler(to_gt(dev_priv), master_ctl); 502 503 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 504 if (master_ctl & ~GEN8_GT_IRQS) { 505 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 506 gen8_de_irq_handler(display, master_ctl); 507 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 508 } 509 510 gen8_master_intr_enable(regs); 511 512 pmu_irq_stats(dev_priv, IRQ_HANDLED); 513 514 return IRQ_HANDLED; 515 } 516 517 static inline u32 gen11_master_intr_disable(void __iomem * const regs) 518 { 519 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0); 520 521 /* 522 * Now with master disabled, get a sample of level indications 523 * for this interrupt. Indications will be cleared on related acks. 524 * New indications can and will light up during processing, 525 * and will generate new interrupt after enabling master. 526 */ 527 return raw_reg_read(regs, GEN11_GFX_MSTR_IRQ); 528 } 529 530 static inline void gen11_master_intr_enable(void __iomem * const regs) 531 { 532 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ); 533 } 534 535 static irqreturn_t gen11_irq_handler(int irq, void *arg) 536 { 537 struct drm_i915_private *i915 = arg; 538 struct intel_display *display = i915->display; 539 void __iomem * const regs = intel_uncore_regs(&i915->uncore); 540 struct intel_gt *gt = to_gt(i915); 541 u32 master_ctl; 542 u32 gu_misc_iir; 543 544 if (!intel_irqs_enabled(i915)) 545 return IRQ_NONE; 546 547 master_ctl = gen11_master_intr_disable(regs); 548 if (!master_ctl) { 549 gen11_master_intr_enable(regs); 550 return IRQ_NONE; 551 } 552 553 /* Find, queue (onto bottom-halves), then clear each source */ 554 gen11_gt_irq_handler(gt, master_ctl); 555 556 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 557 if (master_ctl & GEN11_DISPLAY_IRQ) 558 gen11_display_irq_handler(display); 559 560 gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl); 561 562 gen11_master_intr_enable(regs); 563 564 gen11_gu_misc_irq_handler(display, gu_misc_iir); 565 566 pmu_irq_stats(i915, IRQ_HANDLED); 567 568 return IRQ_HANDLED; 569 } 570 571 static inline u32 dg1_master_intr_disable(void __iomem * const regs) 572 { 573 u32 val; 574 575 /* First disable interrupts */ 576 raw_reg_write(regs, DG1_MSTR_TILE_INTR, 0); 577 578 /* Get the indication levels and ack the master unit */ 579 val = raw_reg_read(regs, DG1_MSTR_TILE_INTR); 580 if (unlikely(!val)) 581 return 0; 582 583 raw_reg_write(regs, DG1_MSTR_TILE_INTR, val); 584 585 return val; 586 } 587 588 static inline void dg1_master_intr_enable(void __iomem * const regs) 589 { 590 raw_reg_write(regs, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ); 591 } 592 593 static irqreturn_t dg1_irq_handler(int irq, void *arg) 594 { 595 struct drm_i915_private * const i915 = arg; 596 struct intel_display *display = i915->display; 597 struct intel_gt *gt = to_gt(i915); 598 void __iomem * const regs = intel_uncore_regs(gt->uncore); 599 u32 master_tile_ctl, master_ctl; 600 u32 gu_misc_iir; 601 602 if (!intel_irqs_enabled(i915)) 603 return IRQ_NONE; 604 605 master_tile_ctl = dg1_master_intr_disable(regs); 606 if (!master_tile_ctl) { 607 dg1_master_intr_enable(regs); 608 return IRQ_NONE; 609 } 610 611 /* FIXME: we only support tile 0 for now. */ 612 if (master_tile_ctl & DG1_MSTR_TILE(0)) { 613 master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ); 614 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, master_ctl); 615 } else { 616 drm_err(&i915->drm, "Tile not supported: 0x%08x\n", 617 master_tile_ctl); 618 dg1_master_intr_enable(regs); 619 return IRQ_NONE; 620 } 621 622 gen11_gt_irq_handler(gt, master_ctl); 623 624 if (master_ctl & GEN11_DISPLAY_IRQ) 625 gen11_display_irq_handler(display); 626 627 gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl); 628 629 dg1_master_intr_enable(regs); 630 631 gen11_gu_misc_irq_handler(display, gu_misc_iir); 632 633 pmu_irq_stats(i915, IRQ_HANDLED); 634 635 return IRQ_HANDLED; 636 } 637 638 static void ilk_irq_reset(struct drm_i915_private *dev_priv) 639 { 640 struct intel_display *display = dev_priv->display; 641 642 /* The master interrupt enable is in DEIER, reset display irq first */ 643 ilk_display_irq_reset(display); 644 gen5_gt_irq_reset(to_gt(dev_priv)); 645 } 646 647 static void valleyview_irq_reset(struct drm_i915_private *dev_priv) 648 { 649 struct intel_display *display = dev_priv->display; 650 651 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0); 652 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER); 653 654 gen5_gt_irq_reset(to_gt(dev_priv)); 655 656 vlv_display_irq_reset(display); 657 } 658 659 static void gen8_irq_reset(struct drm_i915_private *dev_priv) 660 { 661 struct intel_display *display = dev_priv->display; 662 struct intel_uncore *uncore = &dev_priv->uncore; 663 664 gen8_master_intr_disable(intel_uncore_regs(uncore)); 665 666 gen8_gt_irq_reset(to_gt(dev_priv)); 667 gen8_display_irq_reset(display); 668 gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS); 669 } 670 671 static void gen11_irq_reset(struct drm_i915_private *dev_priv) 672 { 673 struct intel_display *display = dev_priv->display; 674 struct intel_gt *gt = to_gt(dev_priv); 675 struct intel_uncore *uncore = gt->uncore; 676 677 gen11_master_intr_disable(intel_uncore_regs(&dev_priv->uncore)); 678 679 gen11_gt_irq_reset(gt); 680 gen11_display_irq_reset(display); 681 682 gen2_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS); 683 gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS); 684 } 685 686 static void dg1_irq_reset(struct drm_i915_private *dev_priv) 687 { 688 struct intel_display *display = dev_priv->display; 689 struct intel_uncore *uncore = &dev_priv->uncore; 690 struct intel_gt *gt; 691 unsigned int i; 692 693 dg1_master_intr_disable(intel_uncore_regs(&dev_priv->uncore)); 694 695 for_each_gt(gt, dev_priv, i) 696 gen11_gt_irq_reset(gt); 697 698 gen11_display_irq_reset(display); 699 700 gen2_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS); 701 gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS); 702 703 intel_uncore_write(uncore, GEN11_GFX_MSTR_IRQ, ~0); 704 } 705 706 static void cherryview_irq_reset(struct drm_i915_private *dev_priv) 707 { 708 struct intel_display *display = dev_priv->display; 709 struct intel_uncore *uncore = &dev_priv->uncore; 710 711 intel_uncore_write(uncore, GEN8_MASTER_IRQ, 0); 712 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ); 713 714 gen8_gt_irq_reset(to_gt(dev_priv)); 715 716 gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS); 717 718 vlv_display_irq_reset(display); 719 } 720 721 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv) 722 { 723 struct intel_display *display = dev_priv->display; 724 725 gen5_gt_irq_postinstall(to_gt(dev_priv)); 726 727 ilk_de_irq_postinstall(display); 728 } 729 730 static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv) 731 { 732 struct intel_display *display = dev_priv->display; 733 734 gen5_gt_irq_postinstall(to_gt(dev_priv)); 735 736 vlv_display_irq_postinstall(display); 737 738 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); 739 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER); 740 } 741 742 static void gen8_irq_postinstall(struct drm_i915_private *dev_priv) 743 { 744 struct intel_display *display = dev_priv->display; 745 746 gen8_gt_irq_postinstall(to_gt(dev_priv)); 747 gen8_de_irq_postinstall(display); 748 749 gen8_master_intr_enable(intel_uncore_regs(&dev_priv->uncore)); 750 } 751 752 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv) 753 { 754 struct intel_display *display = dev_priv->display; 755 struct intel_gt *gt = to_gt(dev_priv); 756 struct intel_uncore *uncore = gt->uncore; 757 u32 gu_misc_masked = GEN11_GU_MISC_GSE; 758 759 gen11_gt_irq_postinstall(gt); 760 gen11_de_irq_postinstall(display); 761 762 gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked); 763 764 gen11_master_intr_enable(intel_uncore_regs(uncore)); 765 intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ); 766 } 767 768 static void dg1_irq_postinstall(struct drm_i915_private *dev_priv) 769 { 770 struct intel_display *display = dev_priv->display; 771 struct intel_uncore *uncore = &dev_priv->uncore; 772 u32 gu_misc_masked = GEN11_GU_MISC_GSE; 773 struct intel_gt *gt; 774 unsigned int i; 775 776 for_each_gt(gt, dev_priv, i) 777 gen11_gt_irq_postinstall(gt); 778 779 gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked); 780 781 dg1_de_irq_postinstall(display); 782 783 dg1_master_intr_enable(intel_uncore_regs(uncore)); 784 intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR); 785 } 786 787 static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv) 788 { 789 struct intel_display *display = dev_priv->display; 790 791 gen8_gt_irq_postinstall(to_gt(dev_priv)); 792 793 vlv_display_irq_postinstall(display); 794 795 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); 796 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ); 797 } 798 799 #define I9XX_HAS_FBC(i915) (IS_I85X(i915) || IS_I865G(i915) || IS_I915GM(i915) || IS_I945GM(i915)) 800 801 static u32 i9xx_error_mask(struct drm_i915_private *i915) 802 { 803 /* 804 * On gen2/3 FBC generates (seemingly spurious) 805 * display INVALID_GTT/INVALID_GTT_PTE table errors. 806 * 807 * Also gen3 bspec has this to say: 808 * "DISPA_INVALID_GTT_PTE 809 " [DevNapa] : Reserved. This bit does not reflect the page 810 " table error for the display plane A." 811 * 812 * Unfortunately we can't mask off individual PGTBL_ER bits, 813 * so we just have to mask off all page table errors via EMR. 814 */ 815 if (I9XX_HAS_FBC(i915)) 816 return I915_ERROR_MEMORY_REFRESH; 817 else 818 return I915_ERROR_PAGE_TABLE | 819 I915_ERROR_MEMORY_REFRESH; 820 } 821 822 static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv, 823 u32 *eir, u32 *eir_stuck) 824 { 825 u32 emr; 826 827 *eir = intel_uncore_read(&dev_priv->uncore, EIR); 828 intel_uncore_write(&dev_priv->uncore, EIR, *eir); 829 830 *eir_stuck = intel_uncore_read(&dev_priv->uncore, EIR); 831 if (*eir_stuck == 0) 832 return; 833 834 /* 835 * Toggle all EMR bits to make sure we get an edge 836 * in the ISR master error bit if we don't clear 837 * all the EIR bits. Otherwise the edge triggered 838 * IIR on i965/g4x wouldn't notice that an interrupt 839 * is still pending. Also some EIR bits can't be 840 * cleared except by handling the underlying error 841 * (or by a GPU reset) so we mask any bit that 842 * remains set. 843 */ 844 emr = intel_uncore_read(&dev_priv->uncore, EMR); 845 intel_uncore_write(&dev_priv->uncore, EMR, 0xffffffff); 846 intel_uncore_write(&dev_priv->uncore, EMR, emr | *eir_stuck); 847 } 848 849 static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv, 850 u32 eir, u32 eir_stuck) 851 { 852 drm_dbg(&dev_priv->drm, "Master Error, EIR 0x%08x\n", eir); 853 854 if (eir_stuck) 855 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n", 856 eir_stuck); 857 858 drm_dbg(&dev_priv->drm, "PGTBL_ER: 0x%08x\n", 859 intel_uncore_read(&dev_priv->uncore, PGTBL_ER)); 860 } 861 862 static void i915_irq_reset(struct drm_i915_private *dev_priv) 863 { 864 struct intel_display *display = dev_priv->display; 865 struct intel_uncore *uncore = &dev_priv->uncore; 866 867 i9xx_display_irq_reset(display); 868 869 gen2_error_reset(uncore, GEN2_ERROR_REGS); 870 gen2_irq_reset(uncore, GEN2_IRQ_REGS); 871 dev_priv->gen2_imr_mask = ~0u; 872 } 873 874 static void i915_irq_postinstall(struct drm_i915_private *dev_priv) 875 { 876 struct intel_display *display = dev_priv->display; 877 struct intel_uncore *uncore = &dev_priv->uncore; 878 u32 enable_mask; 879 880 gen2_error_init(uncore, GEN2_ERROR_REGS, ~i9xx_error_mask(dev_priv)); 881 882 enable_mask = i9xx_display_irq_enable_mask(display) | 883 I915_MASTER_ERROR_INTERRUPT; 884 885 dev_priv->gen2_imr_mask = ~enable_mask; 886 887 enable_mask |= I915_USER_INTERRUPT; 888 889 gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->gen2_imr_mask, enable_mask); 890 891 i915_display_irq_postinstall(display); 892 } 893 894 static irqreturn_t i915_irq_handler(int irq, void *arg) 895 { 896 struct drm_i915_private *dev_priv = arg; 897 struct intel_display *display = dev_priv->display; 898 irqreturn_t ret = IRQ_NONE; 899 900 if (!intel_irqs_enabled(dev_priv)) 901 return IRQ_NONE; 902 903 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 904 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 905 906 do { 907 u32 pipe_stats[I915_MAX_PIPES] = {}; 908 u32 eir = 0, eir_stuck = 0; 909 u32 hotplug_status = 0; 910 u32 iir; 911 912 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR); 913 if (iir == 0) 914 break; 915 916 ret = IRQ_HANDLED; 917 918 if (iir & I915_DISPLAY_PORT_INTERRUPT) 919 hotplug_status = i9xx_hpd_irq_ack(display); 920 921 /* Call regardless, as some status bits might not be 922 * signalled in IIR */ 923 i9xx_pipestat_irq_ack(display, iir, pipe_stats); 924 925 if (iir & I915_MASTER_ERROR_INTERRUPT) 926 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck); 927 928 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir); 929 930 if (iir & I915_USER_INTERRUPT) 931 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir); 932 933 if (iir & I915_MASTER_ERROR_INTERRUPT) 934 i9xx_error_irq_handler(dev_priv, eir, eir_stuck); 935 936 if (hotplug_status) 937 i9xx_hpd_irq_handler(display, hotplug_status); 938 939 i915_pipestat_irq_handler(display, iir, pipe_stats); 940 } while (0); 941 942 pmu_irq_stats(dev_priv, ret); 943 944 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 945 946 return ret; 947 } 948 949 static void i965_irq_reset(struct drm_i915_private *dev_priv) 950 { 951 struct intel_display *display = dev_priv->display; 952 struct intel_uncore *uncore = &dev_priv->uncore; 953 954 i9xx_display_irq_reset(display); 955 956 gen2_error_reset(uncore, GEN2_ERROR_REGS); 957 gen2_irq_reset(uncore, GEN2_IRQ_REGS); 958 dev_priv->gen2_imr_mask = ~0u; 959 } 960 961 static u32 i965_error_mask(struct drm_i915_private *i915) 962 { 963 /* 964 * Enable some error detection, note the instruction error mask 965 * bit is reserved, so we leave it masked. 966 * 967 * i965 FBC no longer generates spurious GTT errors, 968 * so we can always enable the page table errors. 969 */ 970 if (IS_G4X(i915)) 971 return GM45_ERROR_PAGE_TABLE | 972 GM45_ERROR_MEM_PRIV | 973 GM45_ERROR_CP_PRIV | 974 I915_ERROR_MEMORY_REFRESH; 975 else 976 return I915_ERROR_PAGE_TABLE | 977 I915_ERROR_MEMORY_REFRESH; 978 } 979 980 static void i965_irq_postinstall(struct drm_i915_private *dev_priv) 981 { 982 struct intel_display *display = dev_priv->display; 983 struct intel_uncore *uncore = &dev_priv->uncore; 984 u32 enable_mask; 985 986 gen2_error_init(uncore, GEN2_ERROR_REGS, ~i965_error_mask(dev_priv)); 987 988 enable_mask = i9xx_display_irq_enable_mask(display) | 989 I915_MASTER_ERROR_INTERRUPT; 990 991 dev_priv->gen2_imr_mask = ~enable_mask; 992 993 enable_mask |= I915_USER_INTERRUPT; 994 995 if (IS_G4X(dev_priv)) 996 enable_mask |= I915_BSD_USER_INTERRUPT; 997 998 gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->gen2_imr_mask, enable_mask); 999 1000 i965_display_irq_postinstall(display); 1001 } 1002 1003 static irqreturn_t i965_irq_handler(int irq, void *arg) 1004 { 1005 struct drm_i915_private *dev_priv = arg; 1006 struct intel_display *display = dev_priv->display; 1007 irqreturn_t ret = IRQ_NONE; 1008 1009 if (!intel_irqs_enabled(dev_priv)) 1010 return IRQ_NONE; 1011 1012 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 1013 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1014 1015 do { 1016 u32 pipe_stats[I915_MAX_PIPES] = {}; 1017 u32 eir = 0, eir_stuck = 0; 1018 u32 hotplug_status = 0; 1019 u32 iir; 1020 1021 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR); 1022 if (iir == 0) 1023 break; 1024 1025 ret = IRQ_HANDLED; 1026 1027 if (iir & I915_DISPLAY_PORT_INTERRUPT) 1028 hotplug_status = i9xx_hpd_irq_ack(display); 1029 1030 /* Call regardless, as some status bits might not be 1031 * signalled in IIR */ 1032 i9xx_pipestat_irq_ack(display, iir, pipe_stats); 1033 1034 if (iir & I915_MASTER_ERROR_INTERRUPT) 1035 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck); 1036 1037 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir); 1038 1039 if (iir & I915_USER_INTERRUPT) 1040 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], 1041 iir); 1042 1043 if (iir & I915_BSD_USER_INTERRUPT) 1044 intel_engine_cs_irq(to_gt(dev_priv)->engine[VCS0], 1045 iir >> 25); 1046 1047 if (iir & I915_MASTER_ERROR_INTERRUPT) 1048 i9xx_error_irq_handler(dev_priv, eir, eir_stuck); 1049 1050 if (hotplug_status) 1051 i9xx_hpd_irq_handler(display, hotplug_status); 1052 1053 i965_pipestat_irq_handler(display, iir, pipe_stats); 1054 } while (0); 1055 1056 pmu_irq_stats(dev_priv, IRQ_HANDLED); 1057 1058 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1059 1060 return ret; 1061 } 1062 1063 /** 1064 * intel_irq_init - initializes irq support 1065 * @dev_priv: i915 device instance 1066 * 1067 * This function initializes all the irq support including work items, timers 1068 * and all the vtables. It does not setup the interrupt itself though. 1069 */ 1070 void intel_irq_init(struct drm_i915_private *dev_priv) 1071 { 1072 int i; 1073 1074 INIT_WORK(&dev_priv->l3_parity.error_work, ivb_parity_work); 1075 for (i = 0; i < MAX_L3_SLICES; ++i) 1076 dev_priv->l3_parity.remap_info[i] = NULL; 1077 1078 /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */ 1079 if (HAS_GT_UC(dev_priv) && GRAPHICS_VER(dev_priv) < 11) 1080 to_gt(dev_priv)->pm_guc_events = GUC_INTR_GUC2HOST << 16; 1081 } 1082 1083 /** 1084 * intel_irq_fini - deinitializes IRQ support 1085 * @i915: i915 device instance 1086 * 1087 * This function deinitializes all the IRQ support. 1088 */ 1089 void intel_irq_fini(struct drm_i915_private *i915) 1090 { 1091 int i; 1092 1093 for (i = 0; i < MAX_L3_SLICES; ++i) 1094 kfree(i915->l3_parity.remap_info[i]); 1095 } 1096 1097 static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv) 1098 { 1099 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10)) 1100 return dg1_irq_handler; 1101 else if (GRAPHICS_VER(dev_priv) >= 11) 1102 return gen11_irq_handler; 1103 else if (IS_CHERRYVIEW(dev_priv)) 1104 return cherryview_irq_handler; 1105 else if (GRAPHICS_VER(dev_priv) >= 8) 1106 return gen8_irq_handler; 1107 else if (IS_VALLEYVIEW(dev_priv)) 1108 return valleyview_irq_handler; 1109 else if (GRAPHICS_VER(dev_priv) >= 5) 1110 return ilk_irq_handler; 1111 else if (GRAPHICS_VER(dev_priv) == 4) 1112 return i965_irq_handler; 1113 else 1114 return i915_irq_handler; 1115 } 1116 1117 static void intel_irq_reset(struct drm_i915_private *dev_priv) 1118 { 1119 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10)) 1120 dg1_irq_reset(dev_priv); 1121 else if (GRAPHICS_VER(dev_priv) >= 11) 1122 gen11_irq_reset(dev_priv); 1123 else if (IS_CHERRYVIEW(dev_priv)) 1124 cherryview_irq_reset(dev_priv); 1125 else if (GRAPHICS_VER(dev_priv) >= 8) 1126 gen8_irq_reset(dev_priv); 1127 else if (IS_VALLEYVIEW(dev_priv)) 1128 valleyview_irq_reset(dev_priv); 1129 else if (GRAPHICS_VER(dev_priv) >= 5) 1130 ilk_irq_reset(dev_priv); 1131 else if (GRAPHICS_VER(dev_priv) == 4) 1132 i965_irq_reset(dev_priv); 1133 else 1134 i915_irq_reset(dev_priv); 1135 } 1136 1137 static void intel_irq_postinstall(struct drm_i915_private *dev_priv) 1138 { 1139 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10)) 1140 dg1_irq_postinstall(dev_priv); 1141 else if (GRAPHICS_VER(dev_priv) >= 11) 1142 gen11_irq_postinstall(dev_priv); 1143 else if (IS_CHERRYVIEW(dev_priv)) 1144 cherryview_irq_postinstall(dev_priv); 1145 else if (GRAPHICS_VER(dev_priv) >= 8) 1146 gen8_irq_postinstall(dev_priv); 1147 else if (IS_VALLEYVIEW(dev_priv)) 1148 valleyview_irq_postinstall(dev_priv); 1149 else if (GRAPHICS_VER(dev_priv) >= 5) 1150 ilk_irq_postinstall(dev_priv); 1151 else if (GRAPHICS_VER(dev_priv) == 4) 1152 i965_irq_postinstall(dev_priv); 1153 else 1154 i915_irq_postinstall(dev_priv); 1155 } 1156 1157 /** 1158 * intel_irq_install - enables the hardware interrupt 1159 * @dev_priv: i915 device instance 1160 * 1161 * This function enables the hardware interrupt handling, but leaves the hotplug 1162 * handling still disabled. It is called after intel_irq_init(). 1163 * 1164 * In the driver load and resume code we need working interrupts in a few places 1165 * but don't want to deal with the hassle of concurrent probe and hotplug 1166 * workers. Hence the split into this two-stage approach. 1167 */ 1168 int intel_irq_install(struct drm_i915_private *dev_priv) 1169 { 1170 int irq = to_pci_dev(dev_priv->drm.dev)->irq; 1171 int ret; 1172 1173 /* 1174 * We enable some interrupt sources in our postinstall hooks, so mark 1175 * interrupts as enabled _before_ actually enabling them to avoid 1176 * special cases in our ordering checks. 1177 */ 1178 dev_priv->irqs_enabled = true; 1179 1180 intel_irq_reset(dev_priv); 1181 1182 ret = request_irq(irq, intel_irq_handler(dev_priv), 1183 IRQF_SHARED, DRIVER_NAME, dev_priv); 1184 if (ret < 0) { 1185 dev_priv->irqs_enabled = false; 1186 return ret; 1187 } 1188 1189 intel_irq_postinstall(dev_priv); 1190 1191 return ret; 1192 } 1193 1194 /** 1195 * intel_irq_uninstall - finalizes all irq handling 1196 * @dev_priv: i915 device instance 1197 * 1198 * This stops interrupt and hotplug handling and unregisters and frees all 1199 * resources acquired in the init functions. 1200 */ 1201 void intel_irq_uninstall(struct drm_i915_private *dev_priv) 1202 { 1203 struct intel_display *display = dev_priv->display; 1204 int irq = to_pci_dev(dev_priv->drm.dev)->irq; 1205 1206 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->irqs_enabled)) 1207 return; 1208 1209 intel_irq_reset(dev_priv); 1210 1211 free_irq(irq, dev_priv); 1212 1213 intel_hpd_cancel_work(display); 1214 dev_priv->irqs_enabled = false; 1215 } 1216 1217 /** 1218 * intel_irq_suspend - Suspend interrupts 1219 * @i915: i915 device instance 1220 * 1221 * This function is used to disable interrupts at runtime. 1222 */ 1223 void intel_irq_suspend(struct drm_i915_private *i915) 1224 { 1225 intel_irq_reset(i915); 1226 i915->irqs_enabled = false; 1227 intel_synchronize_irq(i915); 1228 } 1229 1230 /** 1231 * intel_irq_resume - Resume interrupts 1232 * @i915: i915 device instance 1233 * 1234 * This function is used to enable interrupts at runtime. 1235 */ 1236 void intel_irq_resume(struct drm_i915_private *i915) 1237 { 1238 i915->irqs_enabled = true; 1239 intel_irq_reset(i915); 1240 intel_irq_postinstall(i915); 1241 } 1242 1243 bool intel_irqs_enabled(struct drm_i915_private *dev_priv) 1244 { 1245 return dev_priv->irqs_enabled; 1246 } 1247 1248 void intel_synchronize_irq(struct drm_i915_private *i915) 1249 { 1250 synchronize_irq(to_pci_dev(i915->drm.dev)->irq); 1251 } 1252 1253 void intel_synchronize_hardirq(struct drm_i915_private *i915) 1254 { 1255 synchronize_hardirq(to_pci_dev(i915->drm.dev)->irq); 1256 } 1257 1258 static bool _intel_irq_enabled(struct drm_device *drm) 1259 { 1260 return intel_irqs_enabled(to_i915(drm)); 1261 } 1262 1263 static void _intel_irq_synchronize(struct drm_device *drm) 1264 { 1265 return intel_synchronize_irq(to_i915(drm)); 1266 } 1267 1268 const struct intel_display_irq_interface i915_display_irq_interface = { 1269 .enabled = _intel_irq_enabled, 1270 .synchronize = _intel_irq_synchronize, 1271 }; 1272