1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- 2 */ 3 /* 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 */ 28 29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 30 31 #include <linux/slab.h> 32 #include <linux/sysrq.h> 33 34 #include <drm/drm_drv.h> 35 36 #include "display/intel_display_irq.h" 37 #include "display/intel_hotplug.h" 38 #include "display/intel_hotplug_irq.h" 39 #include "display/intel_lpe_audio.h" 40 #include "display/intel_psr_regs.h" 41 42 #include "gt/intel_breadcrumbs.h" 43 #include "gt/intel_gt.h" 44 #include "gt/intel_gt_irq.h" 45 #include "gt/intel_gt_pm_irq.h" 46 #include "gt/intel_gt_regs.h" 47 #include "gt/intel_rps.h" 48 49 #include "i915_driver.h" 50 #include "i915_drv.h" 51 #include "i915_irq.h" 52 #include "i915_reg.h" 53 54 /** 55 * DOC: interrupt handling 56 * 57 * These functions provide the basic support for enabling and disabling the 58 * interrupt handling support. There's a lot more functionality in i915_irq.c 59 * and related files, but that will be described in separate chapters. 60 */ 61 62 /* 63 * Interrupt statistic for PMU. Increments the counter only if the 64 * interrupt originated from the GPU so interrupts from a device which 65 * shares the interrupt line are not accounted. 66 */ 67 static inline void pmu_irq_stats(struct drm_i915_private *i915, 68 irqreturn_t res) 69 { 70 if (unlikely(res != IRQ_HANDLED)) 71 return; 72 73 /* 74 * A clever compiler translates that into INC. A not so clever one 75 * should at least prevent store tearing. 76 */ 77 WRITE_ONCE(i915->pmu.irq_count, i915->pmu.irq_count + 1); 78 } 79 80 void gen2_irq_reset(struct intel_uncore *uncore, struct i915_irq_regs regs) 81 { 82 intel_uncore_write(uncore, regs.imr, 0xffffffff); 83 intel_uncore_posting_read(uncore, regs.imr); 84 85 intel_uncore_write(uncore, regs.ier, 0); 86 87 /* IIR can theoretically queue up two events. Be paranoid. */ 88 intel_uncore_write(uncore, regs.iir, 0xffffffff); 89 intel_uncore_posting_read(uncore, regs.iir); 90 intel_uncore_write(uncore, regs.iir, 0xffffffff); 91 intel_uncore_posting_read(uncore, regs.iir); 92 } 93 94 /* 95 * We should clear IMR at preinstall/uninstall, and just check at postinstall. 96 */ 97 void gen2_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg) 98 { 99 u32 val = intel_uncore_read(uncore, reg); 100 101 if (val == 0) 102 return; 103 104 drm_WARN(&uncore->i915->drm, 1, 105 "Interrupt register 0x%x is not zero: 0x%08x\n", 106 i915_mmio_reg_offset(reg), val); 107 intel_uncore_write(uncore, reg, 0xffffffff); 108 intel_uncore_posting_read(uncore, reg); 109 intel_uncore_write(uncore, reg, 0xffffffff); 110 intel_uncore_posting_read(uncore, reg); 111 } 112 113 void gen2_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs, 114 u32 imr_val, u32 ier_val) 115 { 116 gen2_assert_iir_is_zero(uncore, regs.iir); 117 118 intel_uncore_write(uncore, regs.ier, ier_val); 119 intel_uncore_write(uncore, regs.imr, imr_val); 120 intel_uncore_posting_read(uncore, regs.imr); 121 } 122 123 /** 124 * ivb_parity_work - Workqueue called when a parity error interrupt 125 * occurred. 126 * @work: workqueue struct 127 * 128 * Doesn't actually do anything except notify userspace. As a consequence of 129 * this event, userspace should try to remap the bad rows since statistically 130 * it is likely the same row is more likely to go bad again. 131 */ 132 static void ivb_parity_work(struct work_struct *work) 133 { 134 struct drm_i915_private *dev_priv = 135 container_of(work, typeof(*dev_priv), l3_parity.error_work); 136 struct intel_gt *gt = to_gt(dev_priv); 137 u32 error_status, row, bank, subbank; 138 char *parity_event[6]; 139 u32 misccpctl; 140 u8 slice = 0; 141 142 /* We must turn off DOP level clock gating to access the L3 registers. 143 * In order to prevent a get/put style interface, acquire struct mutex 144 * any time we access those registers. 145 */ 146 mutex_lock(&dev_priv->drm.struct_mutex); 147 148 /* If we've screwed up tracking, just let the interrupt fire again */ 149 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice)) 150 goto out; 151 152 misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL, 153 GEN7_DOP_CLOCK_GATE_ENABLE, 0); 154 intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL); 155 156 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { 157 i915_reg_t reg; 158 159 slice--; 160 if (drm_WARN_ON_ONCE(&dev_priv->drm, 161 slice >= NUM_L3_SLICES(dev_priv))) 162 break; 163 164 dev_priv->l3_parity.which_slice &= ~(1<<slice); 165 166 reg = GEN7_L3CDERRST1(slice); 167 168 error_status = intel_uncore_read(&dev_priv->uncore, reg); 169 row = GEN7_PARITY_ERROR_ROW(error_status); 170 bank = GEN7_PARITY_ERROR_BANK(error_status); 171 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); 172 173 intel_uncore_write(&dev_priv->uncore, reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); 174 intel_uncore_posting_read(&dev_priv->uncore, reg); 175 176 parity_event[0] = I915_L3_PARITY_UEVENT "=1"; 177 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); 178 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); 179 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); 180 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); 181 parity_event[5] = NULL; 182 183 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj, 184 KOBJ_CHANGE, parity_event); 185 186 drm_dbg(&dev_priv->drm, 187 "Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", 188 slice, row, bank, subbank); 189 190 kfree(parity_event[4]); 191 kfree(parity_event[3]); 192 kfree(parity_event[2]); 193 kfree(parity_event[1]); 194 } 195 196 intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl); 197 198 out: 199 drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice); 200 spin_lock_irq(gt->irq_lock); 201 gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv)); 202 spin_unlock_irq(gt->irq_lock); 203 204 mutex_unlock(&dev_priv->drm.struct_mutex); 205 } 206 207 static irqreturn_t valleyview_irq_handler(int irq, void *arg) 208 { 209 struct drm_i915_private *dev_priv = arg; 210 struct intel_display *display = &dev_priv->display; 211 irqreturn_t ret = IRQ_NONE; 212 213 if (!intel_irqs_enabled(dev_priv)) 214 return IRQ_NONE; 215 216 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 217 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 218 219 do { 220 u32 iir, gt_iir, pm_iir; 221 u32 pipe_stats[I915_MAX_PIPES] = {}; 222 u32 hotplug_status = 0; 223 u32 ier = 0; 224 225 gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR); 226 pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR); 227 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR); 228 229 if (gt_iir == 0 && pm_iir == 0 && iir == 0) 230 break; 231 232 ret = IRQ_HANDLED; 233 234 /* 235 * Theory on interrupt generation, based on empirical evidence: 236 * 237 * x = ((VLV_IIR & VLV_IER) || 238 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) && 239 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE))); 240 * 241 * A CPU interrupt will only be raised when 'x' has a 0->1 edge. 242 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to 243 * guarantee the CPU interrupt will be raised again even if we 244 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR 245 * bits this time around. 246 */ 247 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0); 248 ier = intel_uncore_rmw(&dev_priv->uncore, VLV_IER, ~0, 0); 249 250 if (gt_iir) 251 intel_uncore_write(&dev_priv->uncore, GTIIR, gt_iir); 252 if (pm_iir) 253 intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir); 254 255 if (iir & I915_DISPLAY_PORT_INTERRUPT) 256 hotplug_status = i9xx_hpd_irq_ack(dev_priv); 257 258 /* Call regardless, as some status bits might not be 259 * signalled in IIR */ 260 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); 261 262 if (iir & (I915_LPE_PIPE_A_INTERRUPT | 263 I915_LPE_PIPE_B_INTERRUPT)) 264 intel_lpe_audio_irq_handler(display); 265 266 /* 267 * VLV_IIR is single buffered, and reflects the level 268 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. 269 */ 270 if (iir) 271 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir); 272 273 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier); 274 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); 275 276 if (gt_iir) 277 gen6_gt_irq_handler(to_gt(dev_priv), gt_iir); 278 if (pm_iir) 279 gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir); 280 281 if (hotplug_status) 282 i9xx_hpd_irq_handler(dev_priv, hotplug_status); 283 284 valleyview_pipestat_irq_handler(dev_priv, pipe_stats); 285 } while (0); 286 287 pmu_irq_stats(dev_priv, ret); 288 289 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 290 291 return ret; 292 } 293 294 static irqreturn_t cherryview_irq_handler(int irq, void *arg) 295 { 296 struct drm_i915_private *dev_priv = arg; 297 struct intel_display *display = &dev_priv->display; 298 irqreturn_t ret = IRQ_NONE; 299 300 if (!intel_irqs_enabled(dev_priv)) 301 return IRQ_NONE; 302 303 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 304 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 305 306 do { 307 u32 master_ctl, iir; 308 u32 pipe_stats[I915_MAX_PIPES] = {}; 309 u32 hotplug_status = 0; 310 u32 ier = 0; 311 312 master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; 313 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR); 314 315 if (master_ctl == 0 && iir == 0) 316 break; 317 318 ret = IRQ_HANDLED; 319 320 /* 321 * Theory on interrupt generation, based on empirical evidence: 322 * 323 * x = ((VLV_IIR & VLV_IER) || 324 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) && 325 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL))); 326 * 327 * A CPU interrupt will only be raised when 'x' has a 0->1 edge. 328 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to 329 * guarantee the CPU interrupt will be raised again even if we 330 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL 331 * bits this time around. 332 */ 333 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0); 334 ier = intel_uncore_rmw(&dev_priv->uncore, VLV_IER, ~0, 0); 335 336 gen8_gt_irq_handler(to_gt(dev_priv), master_ctl); 337 338 if (iir & I915_DISPLAY_PORT_INTERRUPT) 339 hotplug_status = i9xx_hpd_irq_ack(dev_priv); 340 341 /* Call regardless, as some status bits might not be 342 * signalled in IIR */ 343 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); 344 345 if (iir & (I915_LPE_PIPE_A_INTERRUPT | 346 I915_LPE_PIPE_B_INTERRUPT | 347 I915_LPE_PIPE_C_INTERRUPT)) 348 intel_lpe_audio_irq_handler(display); 349 350 /* 351 * VLV_IIR is single buffered, and reflects the level 352 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. 353 */ 354 if (iir) 355 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir); 356 357 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier); 358 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); 359 360 if (hotplug_status) 361 i9xx_hpd_irq_handler(dev_priv, hotplug_status); 362 363 valleyview_pipestat_irq_handler(dev_priv, pipe_stats); 364 } while (0); 365 366 pmu_irq_stats(dev_priv, ret); 367 368 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 369 370 return ret; 371 } 372 373 /* 374 * To handle irqs with the minimum potential races with fresh interrupts, we: 375 * 1 - Disable Master Interrupt Control. 376 * 2 - Find the source(s) of the interrupt. 377 * 3 - Clear the Interrupt Identity bits (IIR). 378 * 4 - Process the interrupt(s) that had bits set in the IIRs. 379 * 5 - Re-enable Master Interrupt Control. 380 */ 381 static irqreturn_t ilk_irq_handler(int irq, void *arg) 382 { 383 struct drm_i915_private *i915 = arg; 384 void __iomem * const regs = intel_uncore_regs(&i915->uncore); 385 u32 de_iir, gt_iir, de_ier, sde_ier = 0; 386 irqreturn_t ret = IRQ_NONE; 387 388 if (unlikely(!intel_irqs_enabled(i915))) 389 return IRQ_NONE; 390 391 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 392 disable_rpm_wakeref_asserts(&i915->runtime_pm); 393 394 /* disable master interrupt before clearing iir */ 395 de_ier = raw_reg_read(regs, DEIER); 396 raw_reg_write(regs, DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); 397 398 /* Disable south interrupts. We'll only write to SDEIIR once, so further 399 * interrupts will will be stored on its back queue, and then we'll be 400 * able to process them after we restore SDEIER (as soon as we restore 401 * it, we'll get an interrupt if SDEIIR still has something to process 402 * due to its back queue). */ 403 if (!HAS_PCH_NOP(i915)) { 404 sde_ier = raw_reg_read(regs, SDEIER); 405 raw_reg_write(regs, SDEIER, 0); 406 } 407 408 /* Find, clear, then process each source of interrupt */ 409 410 gt_iir = raw_reg_read(regs, GTIIR); 411 if (gt_iir) { 412 raw_reg_write(regs, GTIIR, gt_iir); 413 if (GRAPHICS_VER(i915) >= 6) 414 gen6_gt_irq_handler(to_gt(i915), gt_iir); 415 else 416 gen5_gt_irq_handler(to_gt(i915), gt_iir); 417 ret = IRQ_HANDLED; 418 } 419 420 de_iir = raw_reg_read(regs, DEIIR); 421 if (de_iir) { 422 raw_reg_write(regs, DEIIR, de_iir); 423 if (DISPLAY_VER(i915) >= 7) 424 ivb_display_irq_handler(i915, de_iir); 425 else 426 ilk_display_irq_handler(i915, de_iir); 427 ret = IRQ_HANDLED; 428 } 429 430 if (GRAPHICS_VER(i915) >= 6) { 431 u32 pm_iir = raw_reg_read(regs, GEN6_PMIIR); 432 if (pm_iir) { 433 raw_reg_write(regs, GEN6_PMIIR, pm_iir); 434 gen6_rps_irq_handler(&to_gt(i915)->rps, pm_iir); 435 ret = IRQ_HANDLED; 436 } 437 } 438 439 raw_reg_write(regs, DEIER, de_ier); 440 if (sde_ier) 441 raw_reg_write(regs, SDEIER, sde_ier); 442 443 pmu_irq_stats(i915, ret); 444 445 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 446 enable_rpm_wakeref_asserts(&i915->runtime_pm); 447 448 return ret; 449 } 450 451 static inline u32 gen8_master_intr_disable(void __iomem * const regs) 452 { 453 raw_reg_write(regs, GEN8_MASTER_IRQ, 0); 454 455 /* 456 * Now with master disabled, get a sample of level indications 457 * for this interrupt. Indications will be cleared on related acks. 458 * New indications can and will light up during processing, 459 * and will generate new interrupt after enabling master. 460 */ 461 return raw_reg_read(regs, GEN8_MASTER_IRQ); 462 } 463 464 static inline void gen8_master_intr_enable(void __iomem * const regs) 465 { 466 raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); 467 } 468 469 static irqreturn_t gen8_irq_handler(int irq, void *arg) 470 { 471 struct drm_i915_private *dev_priv = arg; 472 void __iomem * const regs = intel_uncore_regs(&dev_priv->uncore); 473 u32 master_ctl; 474 475 if (!intel_irqs_enabled(dev_priv)) 476 return IRQ_NONE; 477 478 master_ctl = gen8_master_intr_disable(regs); 479 if (!master_ctl) { 480 gen8_master_intr_enable(regs); 481 return IRQ_NONE; 482 } 483 484 /* Find, queue (onto bottom-halves), then clear each source */ 485 gen8_gt_irq_handler(to_gt(dev_priv), master_ctl); 486 487 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 488 if (master_ctl & ~GEN8_GT_IRQS) { 489 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 490 gen8_de_irq_handler(dev_priv, master_ctl); 491 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 492 } 493 494 gen8_master_intr_enable(regs); 495 496 pmu_irq_stats(dev_priv, IRQ_HANDLED); 497 498 return IRQ_HANDLED; 499 } 500 501 static inline u32 gen11_master_intr_disable(void __iomem * const regs) 502 { 503 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0); 504 505 /* 506 * Now with master disabled, get a sample of level indications 507 * for this interrupt. Indications will be cleared on related acks. 508 * New indications can and will light up during processing, 509 * and will generate new interrupt after enabling master. 510 */ 511 return raw_reg_read(regs, GEN11_GFX_MSTR_IRQ); 512 } 513 514 static inline void gen11_master_intr_enable(void __iomem * const regs) 515 { 516 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ); 517 } 518 519 static irqreturn_t gen11_irq_handler(int irq, void *arg) 520 { 521 struct drm_i915_private *i915 = arg; 522 void __iomem * const regs = intel_uncore_regs(&i915->uncore); 523 struct intel_gt *gt = to_gt(i915); 524 u32 master_ctl; 525 u32 gu_misc_iir; 526 527 if (!intel_irqs_enabled(i915)) 528 return IRQ_NONE; 529 530 master_ctl = gen11_master_intr_disable(regs); 531 if (!master_ctl) { 532 gen11_master_intr_enable(regs); 533 return IRQ_NONE; 534 } 535 536 /* Find, queue (onto bottom-halves), then clear each source */ 537 gen11_gt_irq_handler(gt, master_ctl); 538 539 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 540 if (master_ctl & GEN11_DISPLAY_IRQ) 541 gen11_display_irq_handler(i915); 542 543 gu_misc_iir = gen11_gu_misc_irq_ack(i915, master_ctl); 544 545 gen11_master_intr_enable(regs); 546 547 gen11_gu_misc_irq_handler(i915, gu_misc_iir); 548 549 pmu_irq_stats(i915, IRQ_HANDLED); 550 551 return IRQ_HANDLED; 552 } 553 554 static inline u32 dg1_master_intr_disable(void __iomem * const regs) 555 { 556 u32 val; 557 558 /* First disable interrupts */ 559 raw_reg_write(regs, DG1_MSTR_TILE_INTR, 0); 560 561 /* Get the indication levels and ack the master unit */ 562 val = raw_reg_read(regs, DG1_MSTR_TILE_INTR); 563 if (unlikely(!val)) 564 return 0; 565 566 raw_reg_write(regs, DG1_MSTR_TILE_INTR, val); 567 568 return val; 569 } 570 571 static inline void dg1_master_intr_enable(void __iomem * const regs) 572 { 573 raw_reg_write(regs, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ); 574 } 575 576 static irqreturn_t dg1_irq_handler(int irq, void *arg) 577 { 578 struct drm_i915_private * const i915 = arg; 579 struct intel_gt *gt = to_gt(i915); 580 void __iomem * const regs = intel_uncore_regs(gt->uncore); 581 u32 master_tile_ctl, master_ctl; 582 u32 gu_misc_iir; 583 584 if (!intel_irqs_enabled(i915)) 585 return IRQ_NONE; 586 587 master_tile_ctl = dg1_master_intr_disable(regs); 588 if (!master_tile_ctl) { 589 dg1_master_intr_enable(regs); 590 return IRQ_NONE; 591 } 592 593 /* FIXME: we only support tile 0 for now. */ 594 if (master_tile_ctl & DG1_MSTR_TILE(0)) { 595 master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ); 596 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, master_ctl); 597 } else { 598 drm_err(&i915->drm, "Tile not supported: 0x%08x\n", 599 master_tile_ctl); 600 dg1_master_intr_enable(regs); 601 return IRQ_NONE; 602 } 603 604 gen11_gt_irq_handler(gt, master_ctl); 605 606 if (master_ctl & GEN11_DISPLAY_IRQ) 607 gen11_display_irq_handler(i915); 608 609 gu_misc_iir = gen11_gu_misc_irq_ack(i915, master_ctl); 610 611 dg1_master_intr_enable(regs); 612 613 gen11_gu_misc_irq_handler(i915, gu_misc_iir); 614 615 pmu_irq_stats(i915, IRQ_HANDLED); 616 617 return IRQ_HANDLED; 618 } 619 620 static void ibx_irq_reset(struct drm_i915_private *dev_priv) 621 { 622 struct intel_uncore *uncore = &dev_priv->uncore; 623 624 if (HAS_PCH_NOP(dev_priv)) 625 return; 626 627 gen2_irq_reset(uncore, SDE_IRQ_REGS); 628 629 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) 630 intel_uncore_write(&dev_priv->uncore, SERR_INT, 0xffffffff); 631 } 632 633 /* drm_dma.h hooks 634 */ 635 static void ilk_irq_reset(struct drm_i915_private *dev_priv) 636 { 637 struct intel_uncore *uncore = &dev_priv->uncore; 638 639 gen2_irq_reset(uncore, DE_IRQ_REGS); 640 dev_priv->irq_mask = ~0u; 641 642 if (GRAPHICS_VER(dev_priv) == 7) 643 intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff); 644 645 if (IS_HASWELL(dev_priv)) { 646 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff); 647 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff); 648 } 649 650 gen5_gt_irq_reset(to_gt(dev_priv)); 651 652 ibx_irq_reset(dev_priv); 653 } 654 655 static void valleyview_irq_reset(struct drm_i915_private *dev_priv) 656 { 657 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0); 658 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER); 659 660 gen5_gt_irq_reset(to_gt(dev_priv)); 661 662 spin_lock_irq(&dev_priv->irq_lock); 663 vlv_display_irq_reset(dev_priv); 664 spin_unlock_irq(&dev_priv->irq_lock); 665 } 666 667 static void gen8_irq_reset(struct drm_i915_private *dev_priv) 668 { 669 struct intel_uncore *uncore = &dev_priv->uncore; 670 671 gen8_master_intr_disable(intel_uncore_regs(uncore)); 672 673 gen8_gt_irq_reset(to_gt(dev_priv)); 674 gen8_display_irq_reset(dev_priv); 675 gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS); 676 677 if (HAS_PCH_SPLIT(dev_priv)) 678 ibx_irq_reset(dev_priv); 679 680 } 681 682 static void gen11_irq_reset(struct drm_i915_private *dev_priv) 683 { 684 struct intel_gt *gt = to_gt(dev_priv); 685 struct intel_uncore *uncore = gt->uncore; 686 687 gen11_master_intr_disable(intel_uncore_regs(&dev_priv->uncore)); 688 689 gen11_gt_irq_reset(gt); 690 gen11_display_irq_reset(dev_priv); 691 692 gen2_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS); 693 gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS); 694 } 695 696 static void dg1_irq_reset(struct drm_i915_private *dev_priv) 697 { 698 struct intel_uncore *uncore = &dev_priv->uncore; 699 struct intel_gt *gt; 700 unsigned int i; 701 702 dg1_master_intr_disable(intel_uncore_regs(&dev_priv->uncore)); 703 704 for_each_gt(gt, dev_priv, i) 705 gen11_gt_irq_reset(gt); 706 707 gen11_display_irq_reset(dev_priv); 708 709 gen2_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS); 710 gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS); 711 712 intel_uncore_write(uncore, GEN11_GFX_MSTR_IRQ, ~0); 713 } 714 715 static void cherryview_irq_reset(struct drm_i915_private *dev_priv) 716 { 717 struct intel_uncore *uncore = &dev_priv->uncore; 718 719 intel_uncore_write(uncore, GEN8_MASTER_IRQ, 0); 720 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ); 721 722 gen8_gt_irq_reset(to_gt(dev_priv)); 723 724 gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS); 725 726 spin_lock_irq(&dev_priv->irq_lock); 727 vlv_display_irq_reset(dev_priv); 728 spin_unlock_irq(&dev_priv->irq_lock); 729 } 730 731 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv) 732 { 733 gen5_gt_irq_postinstall(to_gt(dev_priv)); 734 735 ilk_de_irq_postinstall(dev_priv); 736 } 737 738 static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv) 739 { 740 gen5_gt_irq_postinstall(to_gt(dev_priv)); 741 742 spin_lock_irq(&dev_priv->irq_lock); 743 vlv_display_irq_postinstall(dev_priv); 744 spin_unlock_irq(&dev_priv->irq_lock); 745 746 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); 747 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER); 748 } 749 750 static void gen8_irq_postinstall(struct drm_i915_private *dev_priv) 751 { 752 gen8_gt_irq_postinstall(to_gt(dev_priv)); 753 gen8_de_irq_postinstall(dev_priv); 754 755 gen8_master_intr_enable(intel_uncore_regs(&dev_priv->uncore)); 756 } 757 758 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv) 759 { 760 struct intel_gt *gt = to_gt(dev_priv); 761 struct intel_uncore *uncore = gt->uncore; 762 u32 gu_misc_masked = GEN11_GU_MISC_GSE; 763 764 gen11_gt_irq_postinstall(gt); 765 gen11_de_irq_postinstall(dev_priv); 766 767 gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked); 768 769 gen11_master_intr_enable(intel_uncore_regs(uncore)); 770 intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ); 771 } 772 773 static void dg1_irq_postinstall(struct drm_i915_private *dev_priv) 774 { 775 struct intel_uncore *uncore = &dev_priv->uncore; 776 u32 gu_misc_masked = GEN11_GU_MISC_GSE; 777 struct intel_gt *gt; 778 unsigned int i; 779 780 for_each_gt(gt, dev_priv, i) 781 gen11_gt_irq_postinstall(gt); 782 783 gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked); 784 785 dg1_de_irq_postinstall(dev_priv); 786 787 dg1_master_intr_enable(intel_uncore_regs(uncore)); 788 intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR); 789 } 790 791 static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv) 792 { 793 gen8_gt_irq_postinstall(to_gt(dev_priv)); 794 795 spin_lock_irq(&dev_priv->irq_lock); 796 vlv_display_irq_postinstall(dev_priv); 797 spin_unlock_irq(&dev_priv->irq_lock); 798 799 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); 800 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ); 801 } 802 803 static u32 i9xx_error_mask(struct drm_i915_private *i915) 804 { 805 /* 806 * On gen2/3 FBC generates (seemingly spurious) 807 * display INVALID_GTT/INVALID_GTT_PTE table errors. 808 * 809 * Also gen3 bspec has this to say: 810 * "DISPA_INVALID_GTT_PTE 811 " [DevNapa] : Reserved. This bit does not reflect the page 812 " table error for the display plane A." 813 * 814 * Unfortunately we can't mask off individual PGTBL_ER bits, 815 * so we just have to mask off all page table errors via EMR. 816 */ 817 if (HAS_FBC(i915)) 818 return ~I915_ERROR_MEMORY_REFRESH; 819 else 820 return ~(I915_ERROR_PAGE_TABLE | 821 I915_ERROR_MEMORY_REFRESH); 822 } 823 824 static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv, 825 u32 *eir, u32 *eir_stuck) 826 { 827 u32 emr; 828 829 *eir = intel_uncore_read(&dev_priv->uncore, EIR); 830 intel_uncore_write(&dev_priv->uncore, EIR, *eir); 831 832 *eir_stuck = intel_uncore_read(&dev_priv->uncore, EIR); 833 if (*eir_stuck == 0) 834 return; 835 836 /* 837 * Toggle all EMR bits to make sure we get an edge 838 * in the ISR master error bit if we don't clear 839 * all the EIR bits. Otherwise the edge triggered 840 * IIR on i965/g4x wouldn't notice that an interrupt 841 * is still pending. Also some EIR bits can't be 842 * cleared except by handling the underlying error 843 * (or by a GPU reset) so we mask any bit that 844 * remains set. 845 */ 846 emr = intel_uncore_read(&dev_priv->uncore, EMR); 847 intel_uncore_write(&dev_priv->uncore, EMR, 0xffffffff); 848 intel_uncore_write(&dev_priv->uncore, EMR, emr | *eir_stuck); 849 } 850 851 static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv, 852 u32 eir, u32 eir_stuck) 853 { 854 drm_dbg(&dev_priv->drm, "Master Error, EIR 0x%08x\n", eir); 855 856 if (eir_stuck) 857 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n", 858 eir_stuck); 859 860 drm_dbg(&dev_priv->drm, "PGTBL_ER: 0x%08x\n", 861 intel_uncore_read(&dev_priv->uncore, PGTBL_ER)); 862 } 863 864 static void i915_irq_reset(struct drm_i915_private *dev_priv) 865 { 866 struct intel_uncore *uncore = &dev_priv->uncore; 867 868 i9xx_display_irq_reset(dev_priv); 869 870 gen2_irq_reset(uncore, GEN2_IRQ_REGS); 871 dev_priv->irq_mask = ~0u; 872 } 873 874 static void i915_irq_postinstall(struct drm_i915_private *dev_priv) 875 { 876 struct intel_uncore *uncore = &dev_priv->uncore; 877 u32 enable_mask; 878 879 intel_uncore_write(uncore, EMR, i9xx_error_mask(dev_priv)); 880 881 dev_priv->irq_mask = 882 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 883 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 884 I915_MASTER_ERROR_INTERRUPT); 885 886 enable_mask = 887 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 888 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 889 I915_MASTER_ERROR_INTERRUPT | 890 I915_USER_INTERRUPT; 891 892 if (DISPLAY_VER(dev_priv) >= 3) { 893 dev_priv->irq_mask &= ~I915_ASLE_INTERRUPT; 894 enable_mask |= I915_ASLE_INTERRUPT; 895 } 896 897 if (I915_HAS_HOTPLUG(dev_priv)) { 898 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; 899 enable_mask |= I915_DISPLAY_PORT_INTERRUPT; 900 } 901 902 gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->irq_mask, enable_mask); 903 904 /* Interrupt setup is already guaranteed to be single-threaded, this is 905 * just to make the assert_spin_locked check happy. */ 906 spin_lock_irq(&dev_priv->irq_lock); 907 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); 908 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); 909 spin_unlock_irq(&dev_priv->irq_lock); 910 911 i915_enable_asle_pipestat(dev_priv); 912 } 913 914 static irqreturn_t i915_irq_handler(int irq, void *arg) 915 { 916 struct drm_i915_private *dev_priv = arg; 917 irqreturn_t ret = IRQ_NONE; 918 919 if (!intel_irqs_enabled(dev_priv)) 920 return IRQ_NONE; 921 922 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 923 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 924 925 do { 926 u32 pipe_stats[I915_MAX_PIPES] = {}; 927 u32 eir = 0, eir_stuck = 0; 928 u32 hotplug_status = 0; 929 u32 iir; 930 931 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR); 932 if (iir == 0) 933 break; 934 935 ret = IRQ_HANDLED; 936 937 if (I915_HAS_HOTPLUG(dev_priv) && 938 iir & I915_DISPLAY_PORT_INTERRUPT) 939 hotplug_status = i9xx_hpd_irq_ack(dev_priv); 940 941 /* Call regardless, as some status bits might not be 942 * signalled in IIR */ 943 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); 944 945 if (iir & I915_MASTER_ERROR_INTERRUPT) 946 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck); 947 948 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir); 949 950 if (iir & I915_USER_INTERRUPT) 951 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir); 952 953 if (iir & I915_MASTER_ERROR_INTERRUPT) 954 i9xx_error_irq_handler(dev_priv, eir, eir_stuck); 955 956 if (hotplug_status) 957 i9xx_hpd_irq_handler(dev_priv, hotplug_status); 958 959 i915_pipestat_irq_handler(dev_priv, iir, pipe_stats); 960 } while (0); 961 962 pmu_irq_stats(dev_priv, ret); 963 964 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 965 966 return ret; 967 } 968 969 static void i965_irq_reset(struct drm_i915_private *dev_priv) 970 { 971 struct intel_uncore *uncore = &dev_priv->uncore; 972 973 i9xx_display_irq_reset(dev_priv); 974 975 gen2_irq_reset(uncore, GEN2_IRQ_REGS); 976 dev_priv->irq_mask = ~0u; 977 } 978 979 static u32 i965_error_mask(struct drm_i915_private *i915) 980 { 981 /* 982 * Enable some error detection, note the instruction error mask 983 * bit is reserved, so we leave it masked. 984 * 985 * i965 FBC no longer generates spurious GTT errors, 986 * so we can always enable the page table errors. 987 */ 988 if (IS_G4X(i915)) 989 return ~(GM45_ERROR_PAGE_TABLE | 990 GM45_ERROR_MEM_PRIV | 991 GM45_ERROR_CP_PRIV | 992 I915_ERROR_MEMORY_REFRESH); 993 else 994 return ~(I915_ERROR_PAGE_TABLE | 995 I915_ERROR_MEMORY_REFRESH); 996 } 997 998 static void i965_irq_postinstall(struct drm_i915_private *dev_priv) 999 { 1000 struct intel_uncore *uncore = &dev_priv->uncore; 1001 u32 enable_mask; 1002 1003 intel_uncore_write(uncore, EMR, i965_error_mask(dev_priv)); 1004 1005 dev_priv->irq_mask = 1006 ~(I915_ASLE_INTERRUPT | 1007 I915_DISPLAY_PORT_INTERRUPT | 1008 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 1009 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 1010 I915_MASTER_ERROR_INTERRUPT); 1011 1012 enable_mask = 1013 I915_ASLE_INTERRUPT | 1014 I915_DISPLAY_PORT_INTERRUPT | 1015 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 1016 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 1017 I915_MASTER_ERROR_INTERRUPT | 1018 I915_USER_INTERRUPT; 1019 1020 if (IS_G4X(dev_priv)) 1021 enable_mask |= I915_BSD_USER_INTERRUPT; 1022 1023 gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->irq_mask, enable_mask); 1024 1025 /* Interrupt setup is already guaranteed to be single-threaded, this is 1026 * just to make the assert_spin_locked check happy. */ 1027 spin_lock_irq(&dev_priv->irq_lock); 1028 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); 1029 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); 1030 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); 1031 spin_unlock_irq(&dev_priv->irq_lock); 1032 1033 i915_enable_asle_pipestat(dev_priv); 1034 } 1035 1036 static irqreturn_t i965_irq_handler(int irq, void *arg) 1037 { 1038 struct drm_i915_private *dev_priv = arg; 1039 irqreturn_t ret = IRQ_NONE; 1040 1041 if (!intel_irqs_enabled(dev_priv)) 1042 return IRQ_NONE; 1043 1044 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 1045 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1046 1047 do { 1048 u32 pipe_stats[I915_MAX_PIPES] = {}; 1049 u32 eir = 0, eir_stuck = 0; 1050 u32 hotplug_status = 0; 1051 u32 iir; 1052 1053 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR); 1054 if (iir == 0) 1055 break; 1056 1057 ret = IRQ_HANDLED; 1058 1059 if (iir & I915_DISPLAY_PORT_INTERRUPT) 1060 hotplug_status = i9xx_hpd_irq_ack(dev_priv); 1061 1062 /* Call regardless, as some status bits might not be 1063 * signalled in IIR */ 1064 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); 1065 1066 if (iir & I915_MASTER_ERROR_INTERRUPT) 1067 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck); 1068 1069 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir); 1070 1071 if (iir & I915_USER_INTERRUPT) 1072 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], 1073 iir); 1074 1075 if (iir & I915_BSD_USER_INTERRUPT) 1076 intel_engine_cs_irq(to_gt(dev_priv)->engine[VCS0], 1077 iir >> 25); 1078 1079 if (iir & I915_MASTER_ERROR_INTERRUPT) 1080 i9xx_error_irq_handler(dev_priv, eir, eir_stuck); 1081 1082 if (hotplug_status) 1083 i9xx_hpd_irq_handler(dev_priv, hotplug_status); 1084 1085 i965_pipestat_irq_handler(dev_priv, iir, pipe_stats); 1086 } while (0); 1087 1088 pmu_irq_stats(dev_priv, IRQ_HANDLED); 1089 1090 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1091 1092 return ret; 1093 } 1094 1095 /** 1096 * intel_irq_init - initializes irq support 1097 * @dev_priv: i915 device instance 1098 * 1099 * This function initializes all the irq support including work items, timers 1100 * and all the vtables. It does not setup the interrupt itself though. 1101 */ 1102 void intel_irq_init(struct drm_i915_private *dev_priv) 1103 { 1104 int i; 1105 1106 INIT_WORK(&dev_priv->l3_parity.error_work, ivb_parity_work); 1107 for (i = 0; i < MAX_L3_SLICES; ++i) 1108 dev_priv->l3_parity.remap_info[i] = NULL; 1109 1110 /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */ 1111 if (HAS_GT_UC(dev_priv) && GRAPHICS_VER(dev_priv) < 11) 1112 to_gt(dev_priv)->pm_guc_events = GUC_INTR_GUC2HOST << 16; 1113 } 1114 1115 /** 1116 * intel_irq_fini - deinitializes IRQ support 1117 * @i915: i915 device instance 1118 * 1119 * This function deinitializes all the IRQ support. 1120 */ 1121 void intel_irq_fini(struct drm_i915_private *i915) 1122 { 1123 int i; 1124 1125 for (i = 0; i < MAX_L3_SLICES; ++i) 1126 kfree(i915->l3_parity.remap_info[i]); 1127 } 1128 1129 static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv) 1130 { 1131 if (HAS_GMCH(dev_priv)) { 1132 if (IS_CHERRYVIEW(dev_priv)) 1133 return cherryview_irq_handler; 1134 else if (IS_VALLEYVIEW(dev_priv)) 1135 return valleyview_irq_handler; 1136 else if (GRAPHICS_VER(dev_priv) == 4) 1137 return i965_irq_handler; 1138 else 1139 return i915_irq_handler; 1140 } else { 1141 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10)) 1142 return dg1_irq_handler; 1143 else if (GRAPHICS_VER(dev_priv) >= 11) 1144 return gen11_irq_handler; 1145 else if (GRAPHICS_VER(dev_priv) >= 8) 1146 return gen8_irq_handler; 1147 else 1148 return ilk_irq_handler; 1149 } 1150 } 1151 1152 static void intel_irq_reset(struct drm_i915_private *dev_priv) 1153 { 1154 if (HAS_GMCH(dev_priv)) { 1155 if (IS_CHERRYVIEW(dev_priv)) 1156 cherryview_irq_reset(dev_priv); 1157 else if (IS_VALLEYVIEW(dev_priv)) 1158 valleyview_irq_reset(dev_priv); 1159 else if (GRAPHICS_VER(dev_priv) == 4) 1160 i965_irq_reset(dev_priv); 1161 else 1162 i915_irq_reset(dev_priv); 1163 } else { 1164 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10)) 1165 dg1_irq_reset(dev_priv); 1166 else if (GRAPHICS_VER(dev_priv) >= 11) 1167 gen11_irq_reset(dev_priv); 1168 else if (GRAPHICS_VER(dev_priv) >= 8) 1169 gen8_irq_reset(dev_priv); 1170 else 1171 ilk_irq_reset(dev_priv); 1172 } 1173 } 1174 1175 static void intel_irq_postinstall(struct drm_i915_private *dev_priv) 1176 { 1177 if (HAS_GMCH(dev_priv)) { 1178 if (IS_CHERRYVIEW(dev_priv)) 1179 cherryview_irq_postinstall(dev_priv); 1180 else if (IS_VALLEYVIEW(dev_priv)) 1181 valleyview_irq_postinstall(dev_priv); 1182 else if (GRAPHICS_VER(dev_priv) == 4) 1183 i965_irq_postinstall(dev_priv); 1184 else 1185 i915_irq_postinstall(dev_priv); 1186 } else { 1187 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10)) 1188 dg1_irq_postinstall(dev_priv); 1189 else if (GRAPHICS_VER(dev_priv) >= 11) 1190 gen11_irq_postinstall(dev_priv); 1191 else if (GRAPHICS_VER(dev_priv) >= 8) 1192 gen8_irq_postinstall(dev_priv); 1193 else 1194 ilk_irq_postinstall(dev_priv); 1195 } 1196 } 1197 1198 /** 1199 * intel_irq_install - enables the hardware interrupt 1200 * @dev_priv: i915 device instance 1201 * 1202 * This function enables the hardware interrupt handling, but leaves the hotplug 1203 * handling still disabled. It is called after intel_irq_init(). 1204 * 1205 * In the driver load and resume code we need working interrupts in a few places 1206 * but don't want to deal with the hassle of concurrent probe and hotplug 1207 * workers. Hence the split into this two-stage approach. 1208 */ 1209 int intel_irq_install(struct drm_i915_private *dev_priv) 1210 { 1211 int irq = to_pci_dev(dev_priv->drm.dev)->irq; 1212 int ret; 1213 1214 /* 1215 * We enable some interrupt sources in our postinstall hooks, so mark 1216 * interrupts as enabled _before_ actually enabling them to avoid 1217 * special cases in our ordering checks. 1218 */ 1219 dev_priv->irqs_enabled = true; 1220 1221 intel_irq_reset(dev_priv); 1222 1223 ret = request_irq(irq, intel_irq_handler(dev_priv), 1224 IRQF_SHARED, DRIVER_NAME, dev_priv); 1225 if (ret < 0) { 1226 dev_priv->irqs_enabled = false; 1227 return ret; 1228 } 1229 1230 intel_irq_postinstall(dev_priv); 1231 1232 return ret; 1233 } 1234 1235 /** 1236 * intel_irq_uninstall - finilizes all irq handling 1237 * @dev_priv: i915 device instance 1238 * 1239 * This stops interrupt and hotplug handling and unregisters and frees all 1240 * resources acquired in the init functions. 1241 */ 1242 void intel_irq_uninstall(struct drm_i915_private *dev_priv) 1243 { 1244 int irq = to_pci_dev(dev_priv->drm.dev)->irq; 1245 1246 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->irqs_enabled)) 1247 return; 1248 1249 intel_irq_reset(dev_priv); 1250 1251 free_irq(irq, dev_priv); 1252 1253 intel_hpd_cancel_work(dev_priv); 1254 dev_priv->irqs_enabled = false; 1255 } 1256 1257 /** 1258 * intel_irq_suspend - Suspend interrupts 1259 * @i915: i915 device instance 1260 * 1261 * This function is used to disable interrupts at runtime. 1262 */ 1263 void intel_irq_suspend(struct drm_i915_private *i915) 1264 { 1265 intel_irq_reset(i915); 1266 i915->irqs_enabled = false; 1267 intel_synchronize_irq(i915); 1268 } 1269 1270 /** 1271 * intel_irq_resume - Resume interrupts 1272 * @i915: i915 device instance 1273 * 1274 * This function is used to enable interrupts at runtime. 1275 */ 1276 void intel_irq_resume(struct drm_i915_private *i915) 1277 { 1278 i915->irqs_enabled = true; 1279 intel_irq_reset(i915); 1280 intel_irq_postinstall(i915); 1281 } 1282 1283 bool intel_irqs_enabled(struct drm_i915_private *dev_priv) 1284 { 1285 return dev_priv->irqs_enabled; 1286 } 1287 1288 void intel_synchronize_irq(struct drm_i915_private *i915) 1289 { 1290 synchronize_irq(to_pci_dev(i915->drm.dev)->irq); 1291 } 1292 1293 void intel_synchronize_hardirq(struct drm_i915_private *i915) 1294 { 1295 synchronize_hardirq(to_pci_dev(i915->drm.dev)->irq); 1296 } 1297