1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- 2 */ 3 /* 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 */ 28 29 #include <linux/sysrq.h> 30 #include <linux/slab.h> 31 #include "drmP.h" 32 #include "drm.h" 33 #include "i915_drm.h" 34 #include "i915_drv.h" 35 #include "i915_trace.h" 36 #include "intel_drv.h" 37 38 #define MAX_NOPID ((u32)~0) 39 40 /** 41 * Interrupts that are always left unmasked. 42 * 43 * Since pipe events are edge-triggered from the PIPESTAT register to IIR, 44 * we leave them always unmasked in IMR and then control enabling them through 45 * PIPESTAT alone. 46 */ 47 #define I915_INTERRUPT_ENABLE_FIX \ 48 (I915_ASLE_INTERRUPT | \ 49 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ 50 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ 51 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \ 52 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \ 53 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 54 55 /** Interrupts that we mask and unmask at runtime. */ 56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT) 57 58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ 59 PIPE_VBLANK_INTERRUPT_STATUS) 60 61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ 62 PIPE_VBLANK_INTERRUPT_ENABLE) 63 64 #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ 65 DRM_I915_VBLANK_PIPE_B) 66 67 /* For display hotplug interrupt */ 68 static void 69 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) 70 { 71 if ((dev_priv->irq_mask & mask) != 0) { 72 dev_priv->irq_mask &= ~mask; 73 I915_WRITE(DEIMR, dev_priv->irq_mask); 74 POSTING_READ(DEIMR); 75 } 76 } 77 78 static inline void 79 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) 80 { 81 if ((dev_priv->irq_mask & mask) != mask) { 82 dev_priv->irq_mask |= mask; 83 I915_WRITE(DEIMR, dev_priv->irq_mask); 84 POSTING_READ(DEIMR); 85 } 86 } 87 88 void 89 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) 90 { 91 if ((dev_priv->pipestat[pipe] & mask) != mask) { 92 u32 reg = PIPESTAT(pipe); 93 94 dev_priv->pipestat[pipe] |= mask; 95 /* Enable the interrupt, clear any pending status */ 96 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); 97 POSTING_READ(reg); 98 } 99 } 100 101 void 102 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) 103 { 104 if ((dev_priv->pipestat[pipe] & mask) != 0) { 105 u32 reg = PIPESTAT(pipe); 106 107 dev_priv->pipestat[pipe] &= ~mask; 108 I915_WRITE(reg, dev_priv->pipestat[pipe]); 109 POSTING_READ(reg); 110 } 111 } 112 113 /** 114 * intel_enable_asle - enable ASLE interrupt for OpRegion 115 */ 116 void intel_enable_asle(struct drm_device *dev) 117 { 118 drm_i915_private_t *dev_priv = dev->dev_private; 119 unsigned long irqflags; 120 121 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 122 123 if (HAS_PCH_SPLIT(dev)) 124 ironlake_enable_display_irq(dev_priv, DE_GSE); 125 else { 126 i915_enable_pipestat(dev_priv, 1, 127 PIPE_LEGACY_BLC_EVENT_ENABLE); 128 if (INTEL_INFO(dev)->gen >= 4) 129 i915_enable_pipestat(dev_priv, 0, 130 PIPE_LEGACY_BLC_EVENT_ENABLE); 131 } 132 133 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 134 } 135 136 /** 137 * i915_pipe_enabled - check if a pipe is enabled 138 * @dev: DRM device 139 * @pipe: pipe to check 140 * 141 * Reading certain registers when the pipe is disabled can hang the chip. 142 * Use this routine to make sure the PLL is running and the pipe is active 143 * before reading such registers if unsure. 144 */ 145 static int 146 i915_pipe_enabled(struct drm_device *dev, int pipe) 147 { 148 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 149 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; 150 } 151 152 /* Called from drm generic code, passed a 'crtc', which 153 * we use as a pipe index 154 */ 155 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) 156 { 157 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 158 unsigned long high_frame; 159 unsigned long low_frame; 160 u32 high1, high2, low; 161 162 if (!i915_pipe_enabled(dev, pipe)) { 163 DRM_DEBUG_DRIVER("trying to get vblank count for disabled " 164 "pipe %c\n", pipe_name(pipe)); 165 return 0; 166 } 167 168 high_frame = PIPEFRAME(pipe); 169 low_frame = PIPEFRAMEPIXEL(pipe); 170 171 /* 172 * High & low register fields aren't synchronized, so make sure 173 * we get a low value that's stable across two reads of the high 174 * register. 175 */ 176 do { 177 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; 178 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK; 179 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; 180 } while (high1 != high2); 181 182 high1 >>= PIPE_FRAME_HIGH_SHIFT; 183 low >>= PIPE_FRAME_LOW_SHIFT; 184 return (high1 << 8) | low; 185 } 186 187 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) 188 { 189 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 190 int reg = PIPE_FRMCOUNT_GM45(pipe); 191 192 if (!i915_pipe_enabled(dev, pipe)) { 193 DRM_DEBUG_DRIVER("trying to get vblank count for disabled " 194 "pipe %c\n", pipe_name(pipe)); 195 return 0; 196 } 197 198 return I915_READ(reg); 199 } 200 201 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, 202 int *vpos, int *hpos) 203 { 204 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 205 u32 vbl = 0, position = 0; 206 int vbl_start, vbl_end, htotal, vtotal; 207 bool in_vbl = true; 208 int ret = 0; 209 210 if (!i915_pipe_enabled(dev, pipe)) { 211 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " 212 "pipe %c\n", pipe_name(pipe)); 213 return 0; 214 } 215 216 /* Get vtotal. */ 217 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff); 218 219 if (INTEL_INFO(dev)->gen >= 4) { 220 /* No obvious pixelcount register. Only query vertical 221 * scanout position from Display scan line register. 222 */ 223 position = I915_READ(PIPEDSL(pipe)); 224 225 /* Decode into vertical scanout position. Don't have 226 * horizontal scanout position. 227 */ 228 *vpos = position & 0x1fff; 229 *hpos = 0; 230 } else { 231 /* Have access to pixelcount since start of frame. 232 * We can split this into vertical and horizontal 233 * scanout position. 234 */ 235 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; 236 237 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff); 238 *vpos = position / htotal; 239 *hpos = position - (*vpos * htotal); 240 } 241 242 /* Query vblank area. */ 243 vbl = I915_READ(VBLANK(pipe)); 244 245 /* Test position against vblank region. */ 246 vbl_start = vbl & 0x1fff; 247 vbl_end = (vbl >> 16) & 0x1fff; 248 249 if ((*vpos < vbl_start) || (*vpos > vbl_end)) 250 in_vbl = false; 251 252 /* Inside "upper part" of vblank area? Apply corrective offset: */ 253 if (in_vbl && (*vpos >= vbl_start)) 254 *vpos = *vpos - vtotal; 255 256 /* Readouts valid? */ 257 if (vbl > 0) 258 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; 259 260 /* In vblank? */ 261 if (in_vbl) 262 ret |= DRM_SCANOUTPOS_INVBL; 263 264 return ret; 265 } 266 267 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, 268 int *max_error, 269 struct timeval *vblank_time, 270 unsigned flags) 271 { 272 struct drm_i915_private *dev_priv = dev->dev_private; 273 struct drm_crtc *crtc; 274 275 if (pipe < 0 || pipe >= dev_priv->num_pipe) { 276 DRM_ERROR("Invalid crtc %d\n", pipe); 277 return -EINVAL; 278 } 279 280 /* Get drm_crtc to timestamp: */ 281 crtc = intel_get_crtc_for_pipe(dev, pipe); 282 if (crtc == NULL) { 283 DRM_ERROR("Invalid crtc %d\n", pipe); 284 return -EINVAL; 285 } 286 287 if (!crtc->enabled) { 288 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); 289 return -EBUSY; 290 } 291 292 /* Helper routine in DRM core does all the work: */ 293 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, 294 vblank_time, flags, 295 crtc); 296 } 297 298 /* 299 * Handle hotplug events outside the interrupt handler proper. 300 */ 301 static void i915_hotplug_work_func(struct work_struct *work) 302 { 303 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, 304 hotplug_work); 305 struct drm_device *dev = dev_priv->dev; 306 struct drm_mode_config *mode_config = &dev->mode_config; 307 struct intel_encoder *encoder; 308 309 mutex_lock(&mode_config->mutex); 310 DRM_DEBUG_KMS("running encoder hotplug functions\n"); 311 312 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) 313 if (encoder->hot_plug) 314 encoder->hot_plug(encoder); 315 316 mutex_unlock(&mode_config->mutex); 317 318 /* Just fire off a uevent and let userspace tell us what to do */ 319 drm_helper_hpd_irq_event(dev); 320 } 321 322 static void i915_handle_rps_change(struct drm_device *dev) 323 { 324 drm_i915_private_t *dev_priv = dev->dev_private; 325 u32 busy_up, busy_down, max_avg, min_avg; 326 u8 new_delay = dev_priv->cur_delay; 327 328 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); 329 busy_up = I915_READ(RCPREVBSYTUPAVG); 330 busy_down = I915_READ(RCPREVBSYTDNAVG); 331 max_avg = I915_READ(RCBMAXAVG); 332 min_avg = I915_READ(RCBMINAVG); 333 334 /* Handle RCS change request from hw */ 335 if (busy_up > max_avg) { 336 if (dev_priv->cur_delay != dev_priv->max_delay) 337 new_delay = dev_priv->cur_delay - 1; 338 if (new_delay < dev_priv->max_delay) 339 new_delay = dev_priv->max_delay; 340 } else if (busy_down < min_avg) { 341 if (dev_priv->cur_delay != dev_priv->min_delay) 342 new_delay = dev_priv->cur_delay + 1; 343 if (new_delay > dev_priv->min_delay) 344 new_delay = dev_priv->min_delay; 345 } 346 347 if (ironlake_set_drps(dev, new_delay)) 348 dev_priv->cur_delay = new_delay; 349 350 return; 351 } 352 353 static void notify_ring(struct drm_device *dev, 354 struct intel_ring_buffer *ring) 355 { 356 struct drm_i915_private *dev_priv = dev->dev_private; 357 u32 seqno; 358 359 if (ring->obj == NULL) 360 return; 361 362 seqno = ring->get_seqno(ring); 363 trace_i915_gem_request_complete(ring, seqno); 364 365 ring->irq_seqno = seqno; 366 wake_up_all(&ring->irq_queue); 367 if (i915_enable_hangcheck) { 368 dev_priv->hangcheck_count = 0; 369 mod_timer(&dev_priv->hangcheck_timer, 370 jiffies + 371 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); 372 } 373 } 374 375 static void gen6_pm_rps_work(struct work_struct *work) 376 { 377 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, 378 rps_work); 379 u8 new_delay = dev_priv->cur_delay; 380 u32 pm_iir, pm_imr; 381 382 spin_lock_irq(&dev_priv->rps_lock); 383 pm_iir = dev_priv->pm_iir; 384 dev_priv->pm_iir = 0; 385 pm_imr = I915_READ(GEN6_PMIMR); 386 I915_WRITE(GEN6_PMIMR, 0); 387 spin_unlock_irq(&dev_priv->rps_lock); 388 389 if (!pm_iir) 390 return; 391 392 mutex_lock(&dev_priv->dev->struct_mutex); 393 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { 394 if (dev_priv->cur_delay != dev_priv->max_delay) 395 new_delay = dev_priv->cur_delay + 1; 396 if (new_delay > dev_priv->max_delay) 397 new_delay = dev_priv->max_delay; 398 } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) { 399 gen6_gt_force_wake_get(dev_priv); 400 if (dev_priv->cur_delay != dev_priv->min_delay) 401 new_delay = dev_priv->cur_delay - 1; 402 if (new_delay < dev_priv->min_delay) { 403 new_delay = dev_priv->min_delay; 404 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 405 I915_READ(GEN6_RP_INTERRUPT_LIMITS) | 406 ((new_delay << 16) & 0x3f0000)); 407 } else { 408 /* Make sure we continue to get down interrupts 409 * until we hit the minimum frequency */ 410 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 411 I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000); 412 } 413 gen6_gt_force_wake_put(dev_priv); 414 } 415 416 gen6_set_rps(dev_priv->dev, new_delay); 417 dev_priv->cur_delay = new_delay; 418 419 /* 420 * rps_lock not held here because clearing is non-destructive. There is 421 * an *extremely* unlikely race with gen6_rps_enable() that is prevented 422 * by holding struct_mutex for the duration of the write. 423 */ 424 mutex_unlock(&dev_priv->dev->struct_mutex); 425 } 426 427 static void pch_irq_handler(struct drm_device *dev) 428 { 429 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 430 u32 pch_iir; 431 int pipe; 432 433 pch_iir = I915_READ(SDEIIR); 434 435 if (pch_iir & SDE_AUDIO_POWER_MASK) 436 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", 437 (pch_iir & SDE_AUDIO_POWER_MASK) >> 438 SDE_AUDIO_POWER_SHIFT); 439 440 if (pch_iir & SDE_GMBUS) 441 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n"); 442 443 if (pch_iir & SDE_AUDIO_HDCP_MASK) 444 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); 445 446 if (pch_iir & SDE_AUDIO_TRANS_MASK) 447 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); 448 449 if (pch_iir & SDE_POISON) 450 DRM_ERROR("PCH poison interrupt\n"); 451 452 if (pch_iir & SDE_FDI_MASK) 453 for_each_pipe(pipe) 454 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", 455 pipe_name(pipe), 456 I915_READ(FDI_RX_IIR(pipe))); 457 458 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) 459 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); 460 461 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) 462 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); 463 464 if (pch_iir & SDE_TRANSB_FIFO_UNDER) 465 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n"); 466 if (pch_iir & SDE_TRANSA_FIFO_UNDER) 467 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n"); 468 } 469 470 static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS) 471 { 472 struct drm_device *dev = (struct drm_device *) arg; 473 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 474 int ret = IRQ_NONE; 475 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir; 476 struct drm_i915_master_private *master_priv; 477 478 atomic_inc(&dev_priv->irq_received); 479 480 /* disable master interrupt before clearing iir */ 481 de_ier = I915_READ(DEIER); 482 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); 483 POSTING_READ(DEIER); 484 485 de_iir = I915_READ(DEIIR); 486 gt_iir = I915_READ(GTIIR); 487 pch_iir = I915_READ(SDEIIR); 488 pm_iir = I915_READ(GEN6_PMIIR); 489 490 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0) 491 goto done; 492 493 ret = IRQ_HANDLED; 494 495 if (dev->primary->master) { 496 master_priv = dev->primary->master->driver_priv; 497 if (master_priv->sarea_priv) 498 master_priv->sarea_priv->last_dispatch = 499 READ_BREADCRUMB(dev_priv); 500 } 501 502 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) 503 notify_ring(dev, &dev_priv->ring[RCS]); 504 if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT) 505 notify_ring(dev, &dev_priv->ring[VCS]); 506 if (gt_iir & GT_BLT_USER_INTERRUPT) 507 notify_ring(dev, &dev_priv->ring[BCS]); 508 509 if (de_iir & DE_GSE_IVB) 510 intel_opregion_gse_intr(dev); 511 512 if (de_iir & DE_PLANEA_FLIP_DONE_IVB) { 513 intel_prepare_page_flip(dev, 0); 514 intel_finish_page_flip_plane(dev, 0); 515 } 516 517 if (de_iir & DE_PLANEB_FLIP_DONE_IVB) { 518 intel_prepare_page_flip(dev, 1); 519 intel_finish_page_flip_plane(dev, 1); 520 } 521 522 if (de_iir & DE_PIPEA_VBLANK_IVB) 523 drm_handle_vblank(dev, 0); 524 525 if (de_iir & DE_PIPEB_VBLANK_IVB) 526 drm_handle_vblank(dev, 1); 527 528 /* check event from PCH */ 529 if (de_iir & DE_PCH_EVENT_IVB) { 530 if (pch_iir & SDE_HOTPLUG_MASK_CPT) 531 queue_work(dev_priv->wq, &dev_priv->hotplug_work); 532 pch_irq_handler(dev); 533 } 534 535 if (pm_iir & GEN6_PM_DEFERRED_EVENTS) { 536 unsigned long flags; 537 spin_lock_irqsave(&dev_priv->rps_lock, flags); 538 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n"); 539 dev_priv->pm_iir |= pm_iir; 540 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir); 541 POSTING_READ(GEN6_PMIMR); 542 spin_unlock_irqrestore(&dev_priv->rps_lock, flags); 543 queue_work(dev_priv->wq, &dev_priv->rps_work); 544 } 545 546 /* should clear PCH hotplug event before clear CPU irq */ 547 I915_WRITE(SDEIIR, pch_iir); 548 I915_WRITE(GTIIR, gt_iir); 549 I915_WRITE(DEIIR, de_iir); 550 I915_WRITE(GEN6_PMIIR, pm_iir); 551 552 done: 553 I915_WRITE(DEIER, de_ier); 554 POSTING_READ(DEIER); 555 556 return ret; 557 } 558 559 static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS) 560 { 561 struct drm_device *dev = (struct drm_device *) arg; 562 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 563 int ret = IRQ_NONE; 564 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir; 565 u32 hotplug_mask; 566 struct drm_i915_master_private *master_priv; 567 u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT; 568 569 atomic_inc(&dev_priv->irq_received); 570 571 if (IS_GEN6(dev)) 572 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT; 573 574 /* disable master interrupt before clearing iir */ 575 de_ier = I915_READ(DEIER); 576 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); 577 POSTING_READ(DEIER); 578 579 de_iir = I915_READ(DEIIR); 580 gt_iir = I915_READ(GTIIR); 581 pch_iir = I915_READ(SDEIIR); 582 pm_iir = I915_READ(GEN6_PMIIR); 583 584 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && 585 (!IS_GEN6(dev) || pm_iir == 0)) 586 goto done; 587 588 if (HAS_PCH_CPT(dev)) 589 hotplug_mask = SDE_HOTPLUG_MASK_CPT; 590 else 591 hotplug_mask = SDE_HOTPLUG_MASK; 592 593 ret = IRQ_HANDLED; 594 595 if (dev->primary->master) { 596 master_priv = dev->primary->master->driver_priv; 597 if (master_priv->sarea_priv) 598 master_priv->sarea_priv->last_dispatch = 599 READ_BREADCRUMB(dev_priv); 600 } 601 602 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) 603 notify_ring(dev, &dev_priv->ring[RCS]); 604 if (gt_iir & bsd_usr_interrupt) 605 notify_ring(dev, &dev_priv->ring[VCS]); 606 if (gt_iir & GT_BLT_USER_INTERRUPT) 607 notify_ring(dev, &dev_priv->ring[BCS]); 608 609 if (de_iir & DE_GSE) 610 intel_opregion_gse_intr(dev); 611 612 if (de_iir & DE_PLANEA_FLIP_DONE) { 613 intel_prepare_page_flip(dev, 0); 614 intel_finish_page_flip_plane(dev, 0); 615 } 616 617 if (de_iir & DE_PLANEB_FLIP_DONE) { 618 intel_prepare_page_flip(dev, 1); 619 intel_finish_page_flip_plane(dev, 1); 620 } 621 622 if (de_iir & DE_PIPEA_VBLANK) 623 drm_handle_vblank(dev, 0); 624 625 if (de_iir & DE_PIPEB_VBLANK) 626 drm_handle_vblank(dev, 1); 627 628 /* check event from PCH */ 629 if (de_iir & DE_PCH_EVENT) { 630 if (pch_iir & hotplug_mask) 631 queue_work(dev_priv->wq, &dev_priv->hotplug_work); 632 pch_irq_handler(dev); 633 } 634 635 if (de_iir & DE_PCU_EVENT) { 636 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); 637 i915_handle_rps_change(dev); 638 } 639 640 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) { 641 /* 642 * IIR bits should never already be set because IMR should 643 * prevent an interrupt from being shown in IIR. The warning 644 * displays a case where we've unsafely cleared 645 * dev_priv->pm_iir. Although missing an interrupt of the same 646 * type is not a problem, it displays a problem in the logic. 647 * 648 * The mask bit in IMR is cleared by rps_work. 649 */ 650 unsigned long flags; 651 spin_lock_irqsave(&dev_priv->rps_lock, flags); 652 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n"); 653 dev_priv->pm_iir |= pm_iir; 654 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir); 655 POSTING_READ(GEN6_PMIMR); 656 spin_unlock_irqrestore(&dev_priv->rps_lock, flags); 657 queue_work(dev_priv->wq, &dev_priv->rps_work); 658 } 659 660 /* should clear PCH hotplug event before clear CPU irq */ 661 I915_WRITE(SDEIIR, pch_iir); 662 I915_WRITE(GTIIR, gt_iir); 663 I915_WRITE(DEIIR, de_iir); 664 I915_WRITE(GEN6_PMIIR, pm_iir); 665 666 done: 667 I915_WRITE(DEIER, de_ier); 668 POSTING_READ(DEIER); 669 670 return ret; 671 } 672 673 /** 674 * i915_error_work_func - do process context error handling work 675 * @work: work struct 676 * 677 * Fire an error uevent so userspace can see that a hang or error 678 * was detected. 679 */ 680 static void i915_error_work_func(struct work_struct *work) 681 { 682 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, 683 error_work); 684 struct drm_device *dev = dev_priv->dev; 685 char *error_event[] = { "ERROR=1", NULL }; 686 char *reset_event[] = { "RESET=1", NULL }; 687 char *reset_done_event[] = { "ERROR=0", NULL }; 688 689 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); 690 691 if (atomic_read(&dev_priv->mm.wedged)) { 692 DRM_DEBUG_DRIVER("resetting chip\n"); 693 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); 694 if (!i915_reset(dev, GRDOM_RENDER)) { 695 atomic_set(&dev_priv->mm.wedged, 0); 696 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); 697 } 698 complete_all(&dev_priv->error_completion); 699 } 700 } 701 702 #ifdef CONFIG_DEBUG_FS 703 static struct drm_i915_error_object * 704 i915_error_object_create(struct drm_i915_private *dev_priv, 705 struct drm_i915_gem_object *src) 706 { 707 struct drm_i915_error_object *dst; 708 int page, page_count; 709 u32 reloc_offset; 710 711 if (src == NULL || src->pages == NULL) 712 return NULL; 713 714 page_count = src->base.size / PAGE_SIZE; 715 716 dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC); 717 if (dst == NULL) 718 return NULL; 719 720 reloc_offset = src->gtt_offset; 721 for (page = 0; page < page_count; page++) { 722 unsigned long flags; 723 void __iomem *s; 724 void *d; 725 726 d = kmalloc(PAGE_SIZE, GFP_ATOMIC); 727 if (d == NULL) 728 goto unwind; 729 730 local_irq_save(flags); 731 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, 732 reloc_offset); 733 memcpy_fromio(d, s, PAGE_SIZE); 734 io_mapping_unmap_atomic(s); 735 local_irq_restore(flags); 736 737 dst->pages[page] = d; 738 739 reloc_offset += PAGE_SIZE; 740 } 741 dst->page_count = page_count; 742 dst->gtt_offset = src->gtt_offset; 743 744 return dst; 745 746 unwind: 747 while (page--) 748 kfree(dst->pages[page]); 749 kfree(dst); 750 return NULL; 751 } 752 753 static void 754 i915_error_object_free(struct drm_i915_error_object *obj) 755 { 756 int page; 757 758 if (obj == NULL) 759 return; 760 761 for (page = 0; page < obj->page_count; page++) 762 kfree(obj->pages[page]); 763 764 kfree(obj); 765 } 766 767 static void 768 i915_error_state_free(struct drm_device *dev, 769 struct drm_i915_error_state *error) 770 { 771 int i; 772 773 for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) 774 i915_error_object_free(error->batchbuffer[i]); 775 776 for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++) 777 i915_error_object_free(error->ringbuffer[i]); 778 779 kfree(error->active_bo); 780 kfree(error->overlay); 781 kfree(error); 782 } 783 784 static u32 capture_bo_list(struct drm_i915_error_buffer *err, 785 int count, 786 struct list_head *head) 787 { 788 struct drm_i915_gem_object *obj; 789 int i = 0; 790 791 list_for_each_entry(obj, head, mm_list) { 792 err->size = obj->base.size; 793 err->name = obj->base.name; 794 err->seqno = obj->last_rendering_seqno; 795 err->gtt_offset = obj->gtt_offset; 796 err->read_domains = obj->base.read_domains; 797 err->write_domain = obj->base.write_domain; 798 err->fence_reg = obj->fence_reg; 799 err->pinned = 0; 800 if (obj->pin_count > 0) 801 err->pinned = 1; 802 if (obj->user_pin_count > 0) 803 err->pinned = -1; 804 err->tiling = obj->tiling_mode; 805 err->dirty = obj->dirty; 806 err->purgeable = obj->madv != I915_MADV_WILLNEED; 807 err->ring = obj->ring ? obj->ring->id : 0; 808 err->cache_level = obj->cache_level; 809 810 if (++i == count) 811 break; 812 813 err++; 814 } 815 816 return i; 817 } 818 819 static void i915_gem_record_fences(struct drm_device *dev, 820 struct drm_i915_error_state *error) 821 { 822 struct drm_i915_private *dev_priv = dev->dev_private; 823 int i; 824 825 /* Fences */ 826 switch (INTEL_INFO(dev)->gen) { 827 case 7: 828 case 6: 829 for (i = 0; i < 16; i++) 830 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); 831 break; 832 case 5: 833 case 4: 834 for (i = 0; i < 16; i++) 835 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); 836 break; 837 case 3: 838 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 839 for (i = 0; i < 8; i++) 840 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); 841 case 2: 842 for (i = 0; i < 8; i++) 843 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); 844 break; 845 846 } 847 } 848 849 static struct drm_i915_error_object * 850 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv, 851 struct intel_ring_buffer *ring) 852 { 853 struct drm_i915_gem_object *obj; 854 u32 seqno; 855 856 if (!ring->get_seqno) 857 return NULL; 858 859 seqno = ring->get_seqno(ring); 860 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) { 861 if (obj->ring != ring) 862 continue; 863 864 if (i915_seqno_passed(seqno, obj->last_rendering_seqno)) 865 continue; 866 867 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0) 868 continue; 869 870 /* We need to copy these to an anonymous buffer as the simplest 871 * method to avoid being overwritten by userspace. 872 */ 873 return i915_error_object_create(dev_priv, obj); 874 } 875 876 return NULL; 877 } 878 879 /** 880 * i915_capture_error_state - capture an error record for later analysis 881 * @dev: drm device 882 * 883 * Should be called when an error is detected (either a hang or an error 884 * interrupt) to capture error state from the time of the error. Fills 885 * out a structure which becomes available in debugfs for user level tools 886 * to pick up. 887 */ 888 static void i915_capture_error_state(struct drm_device *dev) 889 { 890 struct drm_i915_private *dev_priv = dev->dev_private; 891 struct drm_i915_gem_object *obj; 892 struct drm_i915_error_state *error; 893 unsigned long flags; 894 int i, pipe; 895 896 spin_lock_irqsave(&dev_priv->error_lock, flags); 897 error = dev_priv->first_error; 898 spin_unlock_irqrestore(&dev_priv->error_lock, flags); 899 if (error) 900 return; 901 902 /* Account for pipe specific data like PIPE*STAT */ 903 error = kmalloc(sizeof(*error), GFP_ATOMIC); 904 if (!error) { 905 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); 906 return; 907 } 908 909 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n", 910 dev->primary->index); 911 912 error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]); 913 error->eir = I915_READ(EIR); 914 error->pgtbl_er = I915_READ(PGTBL_ER); 915 for_each_pipe(pipe) 916 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe)); 917 error->instpm = I915_READ(INSTPM); 918 error->error = 0; 919 if (INTEL_INFO(dev)->gen >= 6) { 920 error->error = I915_READ(ERROR_GEN6); 921 922 error->bcs_acthd = I915_READ(BCS_ACTHD); 923 error->bcs_ipehr = I915_READ(BCS_IPEHR); 924 error->bcs_ipeir = I915_READ(BCS_IPEIR); 925 error->bcs_instdone = I915_READ(BCS_INSTDONE); 926 error->bcs_seqno = 0; 927 if (dev_priv->ring[BCS].get_seqno) 928 error->bcs_seqno = dev_priv->ring[BCS].get_seqno(&dev_priv->ring[BCS]); 929 930 error->vcs_acthd = I915_READ(VCS_ACTHD); 931 error->vcs_ipehr = I915_READ(VCS_IPEHR); 932 error->vcs_ipeir = I915_READ(VCS_IPEIR); 933 error->vcs_instdone = I915_READ(VCS_INSTDONE); 934 error->vcs_seqno = 0; 935 if (dev_priv->ring[VCS].get_seqno) 936 error->vcs_seqno = dev_priv->ring[VCS].get_seqno(&dev_priv->ring[VCS]); 937 } 938 if (INTEL_INFO(dev)->gen >= 4) { 939 error->ipeir = I915_READ(IPEIR_I965); 940 error->ipehr = I915_READ(IPEHR_I965); 941 error->instdone = I915_READ(INSTDONE_I965); 942 error->instps = I915_READ(INSTPS); 943 error->instdone1 = I915_READ(INSTDONE1); 944 error->acthd = I915_READ(ACTHD_I965); 945 error->bbaddr = I915_READ64(BB_ADDR); 946 } else { 947 error->ipeir = I915_READ(IPEIR); 948 error->ipehr = I915_READ(IPEHR); 949 error->instdone = I915_READ(INSTDONE); 950 error->acthd = I915_READ(ACTHD); 951 error->bbaddr = 0; 952 } 953 i915_gem_record_fences(dev, error); 954 955 /* Record the active batch and ring buffers */ 956 for (i = 0; i < I915_NUM_RINGS; i++) { 957 error->batchbuffer[i] = 958 i915_error_first_batchbuffer(dev_priv, 959 &dev_priv->ring[i]); 960 961 error->ringbuffer[i] = 962 i915_error_object_create(dev_priv, 963 dev_priv->ring[i].obj); 964 } 965 966 /* Record buffers on the active and pinned lists. */ 967 error->active_bo = NULL; 968 error->pinned_bo = NULL; 969 970 i = 0; 971 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) 972 i++; 973 error->active_bo_count = i; 974 list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) 975 i++; 976 error->pinned_bo_count = i - error->active_bo_count; 977 978 error->active_bo = NULL; 979 error->pinned_bo = NULL; 980 if (i) { 981 error->active_bo = kmalloc(sizeof(*error->active_bo)*i, 982 GFP_ATOMIC); 983 if (error->active_bo) 984 error->pinned_bo = 985 error->active_bo + error->active_bo_count; 986 } 987 988 if (error->active_bo) 989 error->active_bo_count = 990 capture_bo_list(error->active_bo, 991 error->active_bo_count, 992 &dev_priv->mm.active_list); 993 994 if (error->pinned_bo) 995 error->pinned_bo_count = 996 capture_bo_list(error->pinned_bo, 997 error->pinned_bo_count, 998 &dev_priv->mm.pinned_list); 999 1000 do_gettimeofday(&error->time); 1001 1002 error->overlay = intel_overlay_capture_error_state(dev); 1003 error->display = intel_display_capture_error_state(dev); 1004 1005 spin_lock_irqsave(&dev_priv->error_lock, flags); 1006 if (dev_priv->first_error == NULL) { 1007 dev_priv->first_error = error; 1008 error = NULL; 1009 } 1010 spin_unlock_irqrestore(&dev_priv->error_lock, flags); 1011 1012 if (error) 1013 i915_error_state_free(dev, error); 1014 } 1015 1016 void i915_destroy_error_state(struct drm_device *dev) 1017 { 1018 struct drm_i915_private *dev_priv = dev->dev_private; 1019 struct drm_i915_error_state *error; 1020 1021 spin_lock(&dev_priv->error_lock); 1022 error = dev_priv->first_error; 1023 dev_priv->first_error = NULL; 1024 spin_unlock(&dev_priv->error_lock); 1025 1026 if (error) 1027 i915_error_state_free(dev, error); 1028 } 1029 #else 1030 #define i915_capture_error_state(x) 1031 #endif 1032 1033 static void i915_report_and_clear_eir(struct drm_device *dev) 1034 { 1035 struct drm_i915_private *dev_priv = dev->dev_private; 1036 u32 eir = I915_READ(EIR); 1037 int pipe; 1038 1039 if (!eir) 1040 return; 1041 1042 printk(KERN_ERR "render error detected, EIR: 0x%08x\n", 1043 eir); 1044 1045 if (IS_G4X(dev)) { 1046 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { 1047 u32 ipeir = I915_READ(IPEIR_I965); 1048 1049 printk(KERN_ERR " IPEIR: 0x%08x\n", 1050 I915_READ(IPEIR_I965)); 1051 printk(KERN_ERR " IPEHR: 0x%08x\n", 1052 I915_READ(IPEHR_I965)); 1053 printk(KERN_ERR " INSTDONE: 0x%08x\n", 1054 I915_READ(INSTDONE_I965)); 1055 printk(KERN_ERR " INSTPS: 0x%08x\n", 1056 I915_READ(INSTPS)); 1057 printk(KERN_ERR " INSTDONE1: 0x%08x\n", 1058 I915_READ(INSTDONE1)); 1059 printk(KERN_ERR " ACTHD: 0x%08x\n", 1060 I915_READ(ACTHD_I965)); 1061 I915_WRITE(IPEIR_I965, ipeir); 1062 POSTING_READ(IPEIR_I965); 1063 } 1064 if (eir & GM45_ERROR_PAGE_TABLE) { 1065 u32 pgtbl_err = I915_READ(PGTBL_ER); 1066 printk(KERN_ERR "page table error\n"); 1067 printk(KERN_ERR " PGTBL_ER: 0x%08x\n", 1068 pgtbl_err); 1069 I915_WRITE(PGTBL_ER, pgtbl_err); 1070 POSTING_READ(PGTBL_ER); 1071 } 1072 } 1073 1074 if (!IS_GEN2(dev)) { 1075 if (eir & I915_ERROR_PAGE_TABLE) { 1076 u32 pgtbl_err = I915_READ(PGTBL_ER); 1077 printk(KERN_ERR "page table error\n"); 1078 printk(KERN_ERR " PGTBL_ER: 0x%08x\n", 1079 pgtbl_err); 1080 I915_WRITE(PGTBL_ER, pgtbl_err); 1081 POSTING_READ(PGTBL_ER); 1082 } 1083 } 1084 1085 if (eir & I915_ERROR_MEMORY_REFRESH) { 1086 printk(KERN_ERR "memory refresh error:\n"); 1087 for_each_pipe(pipe) 1088 printk(KERN_ERR "pipe %c stat: 0x%08x\n", 1089 pipe_name(pipe), I915_READ(PIPESTAT(pipe))); 1090 /* pipestat has already been acked */ 1091 } 1092 if (eir & I915_ERROR_INSTRUCTION) { 1093 printk(KERN_ERR "instruction error\n"); 1094 printk(KERN_ERR " INSTPM: 0x%08x\n", 1095 I915_READ(INSTPM)); 1096 if (INTEL_INFO(dev)->gen < 4) { 1097 u32 ipeir = I915_READ(IPEIR); 1098 1099 printk(KERN_ERR " IPEIR: 0x%08x\n", 1100 I915_READ(IPEIR)); 1101 printk(KERN_ERR " IPEHR: 0x%08x\n", 1102 I915_READ(IPEHR)); 1103 printk(KERN_ERR " INSTDONE: 0x%08x\n", 1104 I915_READ(INSTDONE)); 1105 printk(KERN_ERR " ACTHD: 0x%08x\n", 1106 I915_READ(ACTHD)); 1107 I915_WRITE(IPEIR, ipeir); 1108 POSTING_READ(IPEIR); 1109 } else { 1110 u32 ipeir = I915_READ(IPEIR_I965); 1111 1112 printk(KERN_ERR " IPEIR: 0x%08x\n", 1113 I915_READ(IPEIR_I965)); 1114 printk(KERN_ERR " IPEHR: 0x%08x\n", 1115 I915_READ(IPEHR_I965)); 1116 printk(KERN_ERR " INSTDONE: 0x%08x\n", 1117 I915_READ(INSTDONE_I965)); 1118 printk(KERN_ERR " INSTPS: 0x%08x\n", 1119 I915_READ(INSTPS)); 1120 printk(KERN_ERR " INSTDONE1: 0x%08x\n", 1121 I915_READ(INSTDONE1)); 1122 printk(KERN_ERR " ACTHD: 0x%08x\n", 1123 I915_READ(ACTHD_I965)); 1124 I915_WRITE(IPEIR_I965, ipeir); 1125 POSTING_READ(IPEIR_I965); 1126 } 1127 } 1128 1129 I915_WRITE(EIR, eir); 1130 POSTING_READ(EIR); 1131 eir = I915_READ(EIR); 1132 if (eir) { 1133 /* 1134 * some errors might have become stuck, 1135 * mask them. 1136 */ 1137 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); 1138 I915_WRITE(EMR, I915_READ(EMR) | eir); 1139 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 1140 } 1141 } 1142 1143 /** 1144 * i915_handle_error - handle an error interrupt 1145 * @dev: drm device 1146 * 1147 * Do some basic checking of regsiter state at error interrupt time and 1148 * dump it to the syslog. Also call i915_capture_error_state() to make 1149 * sure we get a record and make it available in debugfs. Fire a uevent 1150 * so userspace knows something bad happened (should trigger collection 1151 * of a ring dump etc.). 1152 */ 1153 void i915_handle_error(struct drm_device *dev, bool wedged) 1154 { 1155 struct drm_i915_private *dev_priv = dev->dev_private; 1156 1157 i915_capture_error_state(dev); 1158 i915_report_and_clear_eir(dev); 1159 1160 if (wedged) { 1161 INIT_COMPLETION(dev_priv->error_completion); 1162 atomic_set(&dev_priv->mm.wedged, 1); 1163 1164 /* 1165 * Wakeup waiting processes so they don't hang 1166 */ 1167 wake_up_all(&dev_priv->ring[RCS].irq_queue); 1168 if (HAS_BSD(dev)) 1169 wake_up_all(&dev_priv->ring[VCS].irq_queue); 1170 if (HAS_BLT(dev)) 1171 wake_up_all(&dev_priv->ring[BCS].irq_queue); 1172 } 1173 1174 queue_work(dev_priv->wq, &dev_priv->error_work); 1175 } 1176 1177 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) 1178 { 1179 drm_i915_private_t *dev_priv = dev->dev_private; 1180 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 1181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1182 struct drm_i915_gem_object *obj; 1183 struct intel_unpin_work *work; 1184 unsigned long flags; 1185 bool stall_detected; 1186 1187 /* Ignore early vblank irqs */ 1188 if (intel_crtc == NULL) 1189 return; 1190 1191 spin_lock_irqsave(&dev->event_lock, flags); 1192 work = intel_crtc->unpin_work; 1193 1194 if (work == NULL || work->pending || !work->enable_stall_check) { 1195 /* Either the pending flip IRQ arrived, or we're too early. Don't check */ 1196 spin_unlock_irqrestore(&dev->event_lock, flags); 1197 return; 1198 } 1199 1200 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ 1201 obj = work->pending_flip_obj; 1202 if (INTEL_INFO(dev)->gen >= 4) { 1203 int dspsurf = DSPSURF(intel_crtc->plane); 1204 stall_detected = I915_READ(dspsurf) == obj->gtt_offset; 1205 } else { 1206 int dspaddr = DSPADDR(intel_crtc->plane); 1207 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset + 1208 crtc->y * crtc->fb->pitches[0] + 1209 crtc->x * crtc->fb->bits_per_pixel/8); 1210 } 1211 1212 spin_unlock_irqrestore(&dev->event_lock, flags); 1213 1214 if (stall_detected) { 1215 DRM_DEBUG_DRIVER("Pageflip stall detected\n"); 1216 intel_prepare_page_flip(dev, intel_crtc->plane); 1217 } 1218 } 1219 1220 static irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) 1221 { 1222 struct drm_device *dev = (struct drm_device *) arg; 1223 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1224 struct drm_i915_master_private *master_priv; 1225 u32 iir, new_iir; 1226 u32 pipe_stats[I915_MAX_PIPES]; 1227 u32 vblank_status; 1228 int vblank = 0; 1229 unsigned long irqflags; 1230 int irq_received; 1231 int ret = IRQ_NONE, pipe; 1232 bool blc_event = false; 1233 1234 atomic_inc(&dev_priv->irq_received); 1235 1236 iir = I915_READ(IIR); 1237 1238 if (INTEL_INFO(dev)->gen >= 4) 1239 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS; 1240 else 1241 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS; 1242 1243 for (;;) { 1244 irq_received = iir != 0; 1245 1246 /* Can't rely on pipestat interrupt bit in iir as it might 1247 * have been cleared after the pipestat interrupt was received. 1248 * It doesn't set the bit in iir again, but it still produces 1249 * interrupts (for non-MSI). 1250 */ 1251 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1252 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 1253 i915_handle_error(dev, false); 1254 1255 for_each_pipe(pipe) { 1256 int reg = PIPESTAT(pipe); 1257 pipe_stats[pipe] = I915_READ(reg); 1258 1259 /* 1260 * Clear the PIPE*STAT regs before the IIR 1261 */ 1262 if (pipe_stats[pipe] & 0x8000ffff) { 1263 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 1264 DRM_DEBUG_DRIVER("pipe %c underrun\n", 1265 pipe_name(pipe)); 1266 I915_WRITE(reg, pipe_stats[pipe]); 1267 irq_received = 1; 1268 } 1269 } 1270 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1271 1272 if (!irq_received) 1273 break; 1274 1275 ret = IRQ_HANDLED; 1276 1277 /* Consume port. Then clear IIR or we'll miss events */ 1278 if ((I915_HAS_HOTPLUG(dev)) && 1279 (iir & I915_DISPLAY_PORT_INTERRUPT)) { 1280 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); 1281 1282 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", 1283 hotplug_status); 1284 if (hotplug_status & dev_priv->hotplug_supported_mask) 1285 queue_work(dev_priv->wq, 1286 &dev_priv->hotplug_work); 1287 1288 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 1289 I915_READ(PORT_HOTPLUG_STAT); 1290 } 1291 1292 I915_WRITE(IIR, iir); 1293 new_iir = I915_READ(IIR); /* Flush posted writes */ 1294 1295 if (dev->primary->master) { 1296 master_priv = dev->primary->master->driver_priv; 1297 if (master_priv->sarea_priv) 1298 master_priv->sarea_priv->last_dispatch = 1299 READ_BREADCRUMB(dev_priv); 1300 } 1301 1302 if (iir & I915_USER_INTERRUPT) 1303 notify_ring(dev, &dev_priv->ring[RCS]); 1304 if (iir & I915_BSD_USER_INTERRUPT) 1305 notify_ring(dev, &dev_priv->ring[VCS]); 1306 1307 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) { 1308 intel_prepare_page_flip(dev, 0); 1309 if (dev_priv->flip_pending_is_done) 1310 intel_finish_page_flip_plane(dev, 0); 1311 } 1312 1313 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) { 1314 intel_prepare_page_flip(dev, 1); 1315 if (dev_priv->flip_pending_is_done) 1316 intel_finish_page_flip_plane(dev, 1); 1317 } 1318 1319 for_each_pipe(pipe) { 1320 if (pipe_stats[pipe] & vblank_status && 1321 drm_handle_vblank(dev, pipe)) { 1322 vblank++; 1323 if (!dev_priv->flip_pending_is_done) { 1324 i915_pageflip_stall_check(dev, pipe); 1325 intel_finish_page_flip(dev, pipe); 1326 } 1327 } 1328 1329 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 1330 blc_event = true; 1331 } 1332 1333 1334 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 1335 intel_opregion_asle_intr(dev); 1336 1337 /* With MSI, interrupts are only generated when iir 1338 * transitions from zero to nonzero. If another bit got 1339 * set while we were handling the existing iir bits, then 1340 * we would never get another interrupt. 1341 * 1342 * This is fine on non-MSI as well, as if we hit this path 1343 * we avoid exiting the interrupt handler only to generate 1344 * another one. 1345 * 1346 * Note that for MSI this could cause a stray interrupt report 1347 * if an interrupt landed in the time between writing IIR and 1348 * the posting read. This should be rare enough to never 1349 * trigger the 99% of 100,000 interrupts test for disabling 1350 * stray interrupts. 1351 */ 1352 iir = new_iir; 1353 } 1354 1355 return ret; 1356 } 1357 1358 static int i915_emit_irq(struct drm_device * dev) 1359 { 1360 drm_i915_private_t *dev_priv = dev->dev_private; 1361 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 1362 1363 i915_kernel_lost_context(dev); 1364 1365 DRM_DEBUG_DRIVER("\n"); 1366 1367 dev_priv->counter++; 1368 if (dev_priv->counter > 0x7FFFFFFFUL) 1369 dev_priv->counter = 1; 1370 if (master_priv->sarea_priv) 1371 master_priv->sarea_priv->last_enqueue = dev_priv->counter; 1372 1373 if (BEGIN_LP_RING(4) == 0) { 1374 OUT_RING(MI_STORE_DWORD_INDEX); 1375 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); 1376 OUT_RING(dev_priv->counter); 1377 OUT_RING(MI_USER_INTERRUPT); 1378 ADVANCE_LP_RING(); 1379 } 1380 1381 return dev_priv->counter; 1382 } 1383 1384 static int i915_wait_irq(struct drm_device * dev, int irq_nr) 1385 { 1386 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1387 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 1388 int ret = 0; 1389 struct intel_ring_buffer *ring = LP_RING(dev_priv); 1390 1391 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, 1392 READ_BREADCRUMB(dev_priv)); 1393 1394 if (READ_BREADCRUMB(dev_priv) >= irq_nr) { 1395 if (master_priv->sarea_priv) 1396 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); 1397 return 0; 1398 } 1399 1400 if (master_priv->sarea_priv) 1401 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; 1402 1403 if (ring->irq_get(ring)) { 1404 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ, 1405 READ_BREADCRUMB(dev_priv) >= irq_nr); 1406 ring->irq_put(ring); 1407 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000)) 1408 ret = -EBUSY; 1409 1410 if (ret == -EBUSY) { 1411 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", 1412 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); 1413 } 1414 1415 return ret; 1416 } 1417 1418 /* Needs the lock as it touches the ring. 1419 */ 1420 int i915_irq_emit(struct drm_device *dev, void *data, 1421 struct drm_file *file_priv) 1422 { 1423 drm_i915_private_t *dev_priv = dev->dev_private; 1424 drm_i915_irq_emit_t *emit = data; 1425 int result; 1426 1427 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) { 1428 DRM_ERROR("called with no initialization\n"); 1429 return -EINVAL; 1430 } 1431 1432 RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 1433 1434 mutex_lock(&dev->struct_mutex); 1435 result = i915_emit_irq(dev); 1436 mutex_unlock(&dev->struct_mutex); 1437 1438 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { 1439 DRM_ERROR("copy_to_user\n"); 1440 return -EFAULT; 1441 } 1442 1443 return 0; 1444 } 1445 1446 /* Doesn't need the hardware lock. 1447 */ 1448 int i915_irq_wait(struct drm_device *dev, void *data, 1449 struct drm_file *file_priv) 1450 { 1451 drm_i915_private_t *dev_priv = dev->dev_private; 1452 drm_i915_irq_wait_t *irqwait = data; 1453 1454 if (!dev_priv) { 1455 DRM_ERROR("called with no initialization\n"); 1456 return -EINVAL; 1457 } 1458 1459 return i915_wait_irq(dev, irqwait->irq_seq); 1460 } 1461 1462 /* Called from drm generic code, passed 'crtc' which 1463 * we use as a pipe index 1464 */ 1465 static int i915_enable_vblank(struct drm_device *dev, int pipe) 1466 { 1467 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1468 unsigned long irqflags; 1469 1470 if (!i915_pipe_enabled(dev, pipe)) 1471 return -EINVAL; 1472 1473 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1474 if (INTEL_INFO(dev)->gen >= 4) 1475 i915_enable_pipestat(dev_priv, pipe, 1476 PIPE_START_VBLANK_INTERRUPT_ENABLE); 1477 else 1478 i915_enable_pipestat(dev_priv, pipe, 1479 PIPE_VBLANK_INTERRUPT_ENABLE); 1480 1481 /* maintain vblank delivery even in deep C-states */ 1482 if (dev_priv->info->gen == 3) 1483 I915_WRITE(INSTPM, INSTPM_AGPBUSY_DIS << 16); 1484 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1485 1486 return 0; 1487 } 1488 1489 static int ironlake_enable_vblank(struct drm_device *dev, int pipe) 1490 { 1491 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1492 unsigned long irqflags; 1493 1494 if (!i915_pipe_enabled(dev, pipe)) 1495 return -EINVAL; 1496 1497 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1498 ironlake_enable_display_irq(dev_priv, (pipe == 0) ? 1499 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); 1500 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1501 1502 return 0; 1503 } 1504 1505 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe) 1506 { 1507 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1508 unsigned long irqflags; 1509 1510 if (!i915_pipe_enabled(dev, pipe)) 1511 return -EINVAL; 1512 1513 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1514 ironlake_enable_display_irq(dev_priv, (pipe == 0) ? 1515 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB); 1516 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1517 1518 return 0; 1519 } 1520 1521 /* Called from drm generic code, passed 'crtc' which 1522 * we use as a pipe index 1523 */ 1524 static void i915_disable_vblank(struct drm_device *dev, int pipe) 1525 { 1526 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1527 unsigned long irqflags; 1528 1529 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1530 if (dev_priv->info->gen == 3) 1531 I915_WRITE(INSTPM, 1532 INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS); 1533 1534 i915_disable_pipestat(dev_priv, pipe, 1535 PIPE_VBLANK_INTERRUPT_ENABLE | 1536 PIPE_START_VBLANK_INTERRUPT_ENABLE); 1537 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1538 } 1539 1540 static void ironlake_disable_vblank(struct drm_device *dev, int pipe) 1541 { 1542 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1543 unsigned long irqflags; 1544 1545 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1546 ironlake_disable_display_irq(dev_priv, (pipe == 0) ? 1547 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); 1548 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1549 } 1550 1551 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe) 1552 { 1553 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1554 unsigned long irqflags; 1555 1556 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1557 ironlake_disable_display_irq(dev_priv, (pipe == 0) ? 1558 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB); 1559 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1560 } 1561 1562 /* Set the vblank monitor pipe 1563 */ 1564 int i915_vblank_pipe_set(struct drm_device *dev, void *data, 1565 struct drm_file *file_priv) 1566 { 1567 drm_i915_private_t *dev_priv = dev->dev_private; 1568 1569 if (!dev_priv) { 1570 DRM_ERROR("called with no initialization\n"); 1571 return -EINVAL; 1572 } 1573 1574 return 0; 1575 } 1576 1577 int i915_vblank_pipe_get(struct drm_device *dev, void *data, 1578 struct drm_file *file_priv) 1579 { 1580 drm_i915_private_t *dev_priv = dev->dev_private; 1581 drm_i915_vblank_pipe_t *pipe = data; 1582 1583 if (!dev_priv) { 1584 DRM_ERROR("called with no initialization\n"); 1585 return -EINVAL; 1586 } 1587 1588 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; 1589 1590 return 0; 1591 } 1592 1593 /** 1594 * Schedule buffer swap at given vertical blank. 1595 */ 1596 int i915_vblank_swap(struct drm_device *dev, void *data, 1597 struct drm_file *file_priv) 1598 { 1599 /* The delayed swap mechanism was fundamentally racy, and has been 1600 * removed. The model was that the client requested a delayed flip/swap 1601 * from the kernel, then waited for vblank before continuing to perform 1602 * rendering. The problem was that the kernel might wake the client 1603 * up before it dispatched the vblank swap (since the lock has to be 1604 * held while touching the ringbuffer), in which case the client would 1605 * clear and start the next frame before the swap occurred, and 1606 * flicker would occur in addition to likely missing the vblank. 1607 * 1608 * In the absence of this ioctl, userland falls back to a correct path 1609 * of waiting for a vblank, then dispatching the swap on its own. 1610 * Context switching to userland and back is plenty fast enough for 1611 * meeting the requirements of vblank swapping. 1612 */ 1613 return -EINVAL; 1614 } 1615 1616 static u32 1617 ring_last_seqno(struct intel_ring_buffer *ring) 1618 { 1619 return list_entry(ring->request_list.prev, 1620 struct drm_i915_gem_request, list)->seqno; 1621 } 1622 1623 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err) 1624 { 1625 if (list_empty(&ring->request_list) || 1626 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) { 1627 /* Issue a wake-up to catch stuck h/w. */ 1628 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) { 1629 DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n", 1630 ring->name, 1631 ring->waiting_seqno, 1632 ring->get_seqno(ring)); 1633 wake_up_all(&ring->irq_queue); 1634 *err = true; 1635 } 1636 return true; 1637 } 1638 return false; 1639 } 1640 1641 static bool kick_ring(struct intel_ring_buffer *ring) 1642 { 1643 struct drm_device *dev = ring->dev; 1644 struct drm_i915_private *dev_priv = dev->dev_private; 1645 u32 tmp = I915_READ_CTL(ring); 1646 if (tmp & RING_WAIT) { 1647 DRM_ERROR("Kicking stuck wait on %s\n", 1648 ring->name); 1649 I915_WRITE_CTL(ring, tmp); 1650 return true; 1651 } 1652 return false; 1653 } 1654 1655 /** 1656 * This is called when the chip hasn't reported back with completed 1657 * batchbuffers in a long time. The first time this is called we simply record 1658 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses 1659 * again, we assume the chip is wedged and try to fix it. 1660 */ 1661 void i915_hangcheck_elapsed(unsigned long data) 1662 { 1663 struct drm_device *dev = (struct drm_device *)data; 1664 drm_i915_private_t *dev_priv = dev->dev_private; 1665 uint32_t acthd, instdone, instdone1, acthd_bsd, acthd_blt; 1666 bool err = false; 1667 1668 if (!i915_enable_hangcheck) 1669 return; 1670 1671 /* If all work is done then ACTHD clearly hasn't advanced. */ 1672 if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) && 1673 i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) && 1674 i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) { 1675 dev_priv->hangcheck_count = 0; 1676 if (err) 1677 goto repeat; 1678 return; 1679 } 1680 1681 if (INTEL_INFO(dev)->gen < 4) { 1682 instdone = I915_READ(INSTDONE); 1683 instdone1 = 0; 1684 } else { 1685 instdone = I915_READ(INSTDONE_I965); 1686 instdone1 = I915_READ(INSTDONE1); 1687 } 1688 acthd = intel_ring_get_active_head(&dev_priv->ring[RCS]); 1689 acthd_bsd = HAS_BSD(dev) ? 1690 intel_ring_get_active_head(&dev_priv->ring[VCS]) : 0; 1691 acthd_blt = HAS_BLT(dev) ? 1692 intel_ring_get_active_head(&dev_priv->ring[BCS]) : 0; 1693 1694 if (dev_priv->last_acthd == acthd && 1695 dev_priv->last_acthd_bsd == acthd_bsd && 1696 dev_priv->last_acthd_blt == acthd_blt && 1697 dev_priv->last_instdone == instdone && 1698 dev_priv->last_instdone1 == instdone1) { 1699 if (dev_priv->hangcheck_count++ > 1) { 1700 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); 1701 1702 if (!IS_GEN2(dev)) { 1703 /* Is the chip hanging on a WAIT_FOR_EVENT? 1704 * If so we can simply poke the RB_WAIT bit 1705 * and break the hang. This should work on 1706 * all but the second generation chipsets. 1707 */ 1708 1709 if (kick_ring(&dev_priv->ring[RCS])) 1710 goto repeat; 1711 1712 if (HAS_BSD(dev) && 1713 kick_ring(&dev_priv->ring[VCS])) 1714 goto repeat; 1715 1716 if (HAS_BLT(dev) && 1717 kick_ring(&dev_priv->ring[BCS])) 1718 goto repeat; 1719 } 1720 1721 i915_handle_error(dev, true); 1722 return; 1723 } 1724 } else { 1725 dev_priv->hangcheck_count = 0; 1726 1727 dev_priv->last_acthd = acthd; 1728 dev_priv->last_acthd_bsd = acthd_bsd; 1729 dev_priv->last_acthd_blt = acthd_blt; 1730 dev_priv->last_instdone = instdone; 1731 dev_priv->last_instdone1 = instdone1; 1732 } 1733 1734 repeat: 1735 /* Reset timer case chip hangs without another request being added */ 1736 mod_timer(&dev_priv->hangcheck_timer, 1737 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); 1738 } 1739 1740 /* drm_dma.h hooks 1741 */ 1742 static void ironlake_irq_preinstall(struct drm_device *dev) 1743 { 1744 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1745 1746 atomic_set(&dev_priv->irq_received, 0); 1747 1748 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); 1749 INIT_WORK(&dev_priv->error_work, i915_error_work_func); 1750 if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) 1751 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work); 1752 1753 I915_WRITE(HWSTAM, 0xeffe); 1754 if (IS_GEN6(dev) || IS_GEN7(dev)) { 1755 /* Workaround stalls observed on Sandy Bridge GPUs by 1756 * making the blitter command streamer generate a 1757 * write to the Hardware Status Page for 1758 * MI_USER_INTERRUPT. This appears to serialize the 1759 * previous seqno write out before the interrupt 1760 * happens. 1761 */ 1762 I915_WRITE(GEN6_BLITTER_HWSTAM, ~GEN6_BLITTER_USER_INTERRUPT); 1763 I915_WRITE(GEN6_BSD_HWSTAM, ~GEN6_BSD_USER_INTERRUPT); 1764 } 1765 1766 /* XXX hotplug from PCH */ 1767 1768 I915_WRITE(DEIMR, 0xffffffff); 1769 I915_WRITE(DEIER, 0x0); 1770 POSTING_READ(DEIER); 1771 1772 /* and GT */ 1773 I915_WRITE(GTIMR, 0xffffffff); 1774 I915_WRITE(GTIER, 0x0); 1775 POSTING_READ(GTIER); 1776 1777 /* south display irq */ 1778 I915_WRITE(SDEIMR, 0xffffffff); 1779 I915_WRITE(SDEIER, 0x0); 1780 POSTING_READ(SDEIER); 1781 } 1782 1783 /* 1784 * Enable digital hotplug on the PCH, and configure the DP short pulse 1785 * duration to 2ms (which is the minimum in the Display Port spec) 1786 * 1787 * This register is the same on all known PCH chips. 1788 */ 1789 1790 static void ironlake_enable_pch_hotplug(struct drm_device *dev) 1791 { 1792 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1793 u32 hotplug; 1794 1795 hotplug = I915_READ(PCH_PORT_HOTPLUG); 1796 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); 1797 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; 1798 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; 1799 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; 1800 I915_WRITE(PCH_PORT_HOTPLUG, hotplug); 1801 } 1802 1803 static int ironlake_irq_postinstall(struct drm_device *dev) 1804 { 1805 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1806 /* enable kind of interrupts always enabled */ 1807 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | 1808 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; 1809 u32 render_irqs; 1810 u32 hotplug_mask; 1811 1812 DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue); 1813 if (HAS_BSD(dev)) 1814 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue); 1815 if (HAS_BLT(dev)) 1816 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue); 1817 1818 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; 1819 dev_priv->irq_mask = ~display_mask; 1820 1821 /* should always can generate irq */ 1822 I915_WRITE(DEIIR, I915_READ(DEIIR)); 1823 I915_WRITE(DEIMR, dev_priv->irq_mask); 1824 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK); 1825 POSTING_READ(DEIER); 1826 1827 dev_priv->gt_irq_mask = ~0; 1828 1829 I915_WRITE(GTIIR, I915_READ(GTIIR)); 1830 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 1831 1832 if (IS_GEN6(dev)) 1833 render_irqs = 1834 GT_USER_INTERRUPT | 1835 GT_GEN6_BSD_USER_INTERRUPT | 1836 GT_BLT_USER_INTERRUPT; 1837 else 1838 render_irqs = 1839 GT_USER_INTERRUPT | 1840 GT_PIPE_NOTIFY | 1841 GT_BSD_USER_INTERRUPT; 1842 I915_WRITE(GTIER, render_irqs); 1843 POSTING_READ(GTIER); 1844 1845 if (HAS_PCH_CPT(dev)) { 1846 hotplug_mask = (SDE_CRT_HOTPLUG_CPT | 1847 SDE_PORTB_HOTPLUG_CPT | 1848 SDE_PORTC_HOTPLUG_CPT | 1849 SDE_PORTD_HOTPLUG_CPT); 1850 } else { 1851 hotplug_mask = (SDE_CRT_HOTPLUG | 1852 SDE_PORTB_HOTPLUG | 1853 SDE_PORTC_HOTPLUG | 1854 SDE_PORTD_HOTPLUG | 1855 SDE_AUX_MASK); 1856 } 1857 1858 dev_priv->pch_irq_mask = ~hotplug_mask; 1859 1860 I915_WRITE(SDEIIR, I915_READ(SDEIIR)); 1861 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); 1862 I915_WRITE(SDEIER, hotplug_mask); 1863 POSTING_READ(SDEIER); 1864 1865 ironlake_enable_pch_hotplug(dev); 1866 1867 if (IS_IRONLAKE_M(dev)) { 1868 /* Clear & enable PCU event interrupts */ 1869 I915_WRITE(DEIIR, DE_PCU_EVENT); 1870 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); 1871 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); 1872 } 1873 1874 return 0; 1875 } 1876 1877 static int ivybridge_irq_postinstall(struct drm_device *dev) 1878 { 1879 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1880 /* enable kind of interrupts always enabled */ 1881 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | 1882 DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB | 1883 DE_PLANEB_FLIP_DONE_IVB; 1884 u32 render_irqs; 1885 u32 hotplug_mask; 1886 1887 DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue); 1888 if (HAS_BSD(dev)) 1889 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue); 1890 if (HAS_BLT(dev)) 1891 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue); 1892 1893 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; 1894 dev_priv->irq_mask = ~display_mask; 1895 1896 /* should always can generate irq */ 1897 I915_WRITE(DEIIR, I915_READ(DEIIR)); 1898 I915_WRITE(DEIMR, dev_priv->irq_mask); 1899 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB | 1900 DE_PIPEB_VBLANK_IVB); 1901 POSTING_READ(DEIER); 1902 1903 dev_priv->gt_irq_mask = ~0; 1904 1905 I915_WRITE(GTIIR, I915_READ(GTIIR)); 1906 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 1907 1908 render_irqs = GT_USER_INTERRUPT | GT_GEN6_BSD_USER_INTERRUPT | 1909 GT_BLT_USER_INTERRUPT; 1910 I915_WRITE(GTIER, render_irqs); 1911 POSTING_READ(GTIER); 1912 1913 hotplug_mask = (SDE_CRT_HOTPLUG_CPT | 1914 SDE_PORTB_HOTPLUG_CPT | 1915 SDE_PORTC_HOTPLUG_CPT | 1916 SDE_PORTD_HOTPLUG_CPT); 1917 dev_priv->pch_irq_mask = ~hotplug_mask; 1918 1919 I915_WRITE(SDEIIR, I915_READ(SDEIIR)); 1920 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); 1921 I915_WRITE(SDEIER, hotplug_mask); 1922 POSTING_READ(SDEIER); 1923 1924 ironlake_enable_pch_hotplug(dev); 1925 1926 return 0; 1927 } 1928 1929 static void i915_driver_irq_preinstall(struct drm_device * dev) 1930 { 1931 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1932 int pipe; 1933 1934 atomic_set(&dev_priv->irq_received, 0); 1935 1936 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); 1937 INIT_WORK(&dev_priv->error_work, i915_error_work_func); 1938 1939 if (I915_HAS_HOTPLUG(dev)) { 1940 I915_WRITE(PORT_HOTPLUG_EN, 0); 1941 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 1942 } 1943 1944 I915_WRITE(HWSTAM, 0xeffe); 1945 for_each_pipe(pipe) 1946 I915_WRITE(PIPESTAT(pipe), 0); 1947 I915_WRITE(IMR, 0xffffffff); 1948 I915_WRITE(IER, 0x0); 1949 POSTING_READ(IER); 1950 } 1951 1952 /* 1953 * Must be called after intel_modeset_init or hotplug interrupts won't be 1954 * enabled correctly. 1955 */ 1956 static int i915_driver_irq_postinstall(struct drm_device *dev) 1957 { 1958 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1959 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; 1960 u32 error_mask; 1961 1962 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; 1963 1964 /* Unmask the interrupts that we always want on. */ 1965 dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX; 1966 1967 dev_priv->pipestat[0] = 0; 1968 dev_priv->pipestat[1] = 0; 1969 1970 if (I915_HAS_HOTPLUG(dev)) { 1971 /* Enable in IER... */ 1972 enable_mask |= I915_DISPLAY_PORT_INTERRUPT; 1973 /* and unmask in IMR */ 1974 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; 1975 } 1976 1977 /* 1978 * Enable some error detection, note the instruction error mask 1979 * bit is reserved, so we leave it masked. 1980 */ 1981 if (IS_G4X(dev)) { 1982 error_mask = ~(GM45_ERROR_PAGE_TABLE | 1983 GM45_ERROR_MEM_PRIV | 1984 GM45_ERROR_CP_PRIV | 1985 I915_ERROR_MEMORY_REFRESH); 1986 } else { 1987 error_mask = ~(I915_ERROR_PAGE_TABLE | 1988 I915_ERROR_MEMORY_REFRESH); 1989 } 1990 I915_WRITE(EMR, error_mask); 1991 1992 I915_WRITE(IMR, dev_priv->irq_mask); 1993 I915_WRITE(IER, enable_mask); 1994 POSTING_READ(IER); 1995 1996 if (I915_HAS_HOTPLUG(dev)) { 1997 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); 1998 1999 /* Note HDMI and DP share bits */ 2000 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) 2001 hotplug_en |= HDMIB_HOTPLUG_INT_EN; 2002 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) 2003 hotplug_en |= HDMIC_HOTPLUG_INT_EN; 2004 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) 2005 hotplug_en |= HDMID_HOTPLUG_INT_EN; 2006 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS) 2007 hotplug_en |= SDVOC_HOTPLUG_INT_EN; 2008 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS) 2009 hotplug_en |= SDVOB_HOTPLUG_INT_EN; 2010 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { 2011 hotplug_en |= CRT_HOTPLUG_INT_EN; 2012 2013 /* Programming the CRT detection parameters tends 2014 to generate a spurious hotplug event about three 2015 seconds later. So just do it once. 2016 */ 2017 if (IS_G4X(dev)) 2018 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; 2019 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; 2020 } 2021 2022 /* Ignore TV since it's buggy */ 2023 2024 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 2025 } 2026 2027 intel_opregion_enable_asle(dev); 2028 2029 return 0; 2030 } 2031 2032 static void ironlake_irq_uninstall(struct drm_device *dev) 2033 { 2034 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2035 2036 if (!dev_priv) 2037 return; 2038 2039 dev_priv->vblank_pipe = 0; 2040 2041 I915_WRITE(HWSTAM, 0xffffffff); 2042 2043 I915_WRITE(DEIMR, 0xffffffff); 2044 I915_WRITE(DEIER, 0x0); 2045 I915_WRITE(DEIIR, I915_READ(DEIIR)); 2046 2047 I915_WRITE(GTIMR, 0xffffffff); 2048 I915_WRITE(GTIER, 0x0); 2049 I915_WRITE(GTIIR, I915_READ(GTIIR)); 2050 2051 I915_WRITE(SDEIMR, 0xffffffff); 2052 I915_WRITE(SDEIER, 0x0); 2053 I915_WRITE(SDEIIR, I915_READ(SDEIIR)); 2054 } 2055 2056 static void i915_driver_irq_uninstall(struct drm_device * dev) 2057 { 2058 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2059 int pipe; 2060 2061 if (!dev_priv) 2062 return; 2063 2064 dev_priv->vblank_pipe = 0; 2065 2066 if (I915_HAS_HOTPLUG(dev)) { 2067 I915_WRITE(PORT_HOTPLUG_EN, 0); 2068 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 2069 } 2070 2071 I915_WRITE(HWSTAM, 0xffffffff); 2072 for_each_pipe(pipe) 2073 I915_WRITE(PIPESTAT(pipe), 0); 2074 I915_WRITE(IMR, 0xffffffff); 2075 I915_WRITE(IER, 0x0); 2076 2077 for_each_pipe(pipe) 2078 I915_WRITE(PIPESTAT(pipe), 2079 I915_READ(PIPESTAT(pipe)) & 0x8000ffff); 2080 I915_WRITE(IIR, I915_READ(IIR)); 2081 } 2082 2083 void intel_irq_init(struct drm_device *dev) 2084 { 2085 dev->driver->get_vblank_counter = i915_get_vblank_counter; 2086 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ 2087 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) { 2088 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ 2089 dev->driver->get_vblank_counter = gm45_get_vblank_counter; 2090 } 2091 2092 if (drm_core_check_feature(dev, DRIVER_MODESET)) 2093 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; 2094 else 2095 dev->driver->get_vblank_timestamp = NULL; 2096 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; 2097 2098 if (IS_IVYBRIDGE(dev)) { 2099 /* Share pre & uninstall handlers with ILK/SNB */ 2100 dev->driver->irq_handler = ivybridge_irq_handler; 2101 dev->driver->irq_preinstall = ironlake_irq_preinstall; 2102 dev->driver->irq_postinstall = ivybridge_irq_postinstall; 2103 dev->driver->irq_uninstall = ironlake_irq_uninstall; 2104 dev->driver->enable_vblank = ivybridge_enable_vblank; 2105 dev->driver->disable_vblank = ivybridge_disable_vblank; 2106 } else if (HAS_PCH_SPLIT(dev)) { 2107 dev->driver->irq_handler = ironlake_irq_handler; 2108 dev->driver->irq_preinstall = ironlake_irq_preinstall; 2109 dev->driver->irq_postinstall = ironlake_irq_postinstall; 2110 dev->driver->irq_uninstall = ironlake_irq_uninstall; 2111 dev->driver->enable_vblank = ironlake_enable_vblank; 2112 dev->driver->disable_vblank = ironlake_disable_vblank; 2113 } else { 2114 dev->driver->irq_preinstall = i915_driver_irq_preinstall; 2115 dev->driver->irq_postinstall = i915_driver_irq_postinstall; 2116 dev->driver->irq_uninstall = i915_driver_irq_uninstall; 2117 dev->driver->irq_handler = i915_driver_irq_handler; 2118 dev->driver->enable_vblank = i915_enable_vblank; 2119 dev->driver->disable_vblank = i915_disable_vblank; 2120 } 2121 } 2122