1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- 2 */ 3 /* 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 */ 28 29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 30 31 #include <linux/slab.h> 32 #include <linux/sysrq.h> 33 34 #include <drm/drm_drv.h> 35 36 #include "display/intel_display_irq.h" 37 #include "display/intel_hotplug.h" 38 #include "display/intel_hotplug_irq.h" 39 #include "display/intel_lpe_audio.h" 40 #include "display/intel_psr_regs.h" 41 42 #include "gt/intel_breadcrumbs.h" 43 #include "gt/intel_gt.h" 44 #include "gt/intel_gt_irq.h" 45 #include "gt/intel_gt_pm_irq.h" 46 #include "gt/intel_gt_regs.h" 47 #include "gt/intel_rps.h" 48 49 #include "i915_driver.h" 50 #include "i915_drv.h" 51 #include "i915_irq.h" 52 #include "i915_reg.h" 53 54 /** 55 * DOC: interrupt handling 56 * 57 * These functions provide the basic support for enabling and disabling the 58 * interrupt handling support. There's a lot more functionality in i915_irq.c 59 * and related files, but that will be described in separate chapters. 60 */ 61 62 /* 63 * Interrupt statistic for PMU. Increments the counter only if the 64 * interrupt originated from the GPU so interrupts from a device which 65 * shares the interrupt line are not accounted. 66 */ 67 static inline void pmu_irq_stats(struct drm_i915_private *i915, 68 irqreturn_t res) 69 { 70 if (unlikely(res != IRQ_HANDLED)) 71 return; 72 73 /* 74 * A clever compiler translates that into INC. A not so clever one 75 * should at least prevent store tearing. 76 */ 77 WRITE_ONCE(i915->pmu.irq_count, i915->pmu.irq_count + 1); 78 } 79 80 void gen2_irq_reset(struct intel_uncore *uncore, struct i915_irq_regs regs) 81 { 82 intel_uncore_write(uncore, regs.imr, 0xffffffff); 83 intel_uncore_posting_read(uncore, regs.imr); 84 85 intel_uncore_write(uncore, regs.ier, 0); 86 87 /* IIR can theoretically queue up two events. Be paranoid. */ 88 intel_uncore_write(uncore, regs.iir, 0xffffffff); 89 intel_uncore_posting_read(uncore, regs.iir); 90 intel_uncore_write(uncore, regs.iir, 0xffffffff); 91 intel_uncore_posting_read(uncore, regs.iir); 92 } 93 94 /* 95 * We should clear IMR at preinstall/uninstall, and just check at postinstall. 96 */ 97 void gen2_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg) 98 { 99 u32 val = intel_uncore_read(uncore, reg); 100 101 if (val == 0) 102 return; 103 104 drm_WARN(&uncore->i915->drm, 1, 105 "Interrupt register 0x%x is not zero: 0x%08x\n", 106 i915_mmio_reg_offset(reg), val); 107 intel_uncore_write(uncore, reg, 0xffffffff); 108 intel_uncore_posting_read(uncore, reg); 109 intel_uncore_write(uncore, reg, 0xffffffff); 110 intel_uncore_posting_read(uncore, reg); 111 } 112 113 void gen2_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs, 114 u32 imr_val, u32 ier_val) 115 { 116 gen2_assert_iir_is_zero(uncore, regs.iir); 117 118 intel_uncore_write(uncore, regs.ier, ier_val); 119 intel_uncore_write(uncore, regs.imr, imr_val); 120 intel_uncore_posting_read(uncore, regs.imr); 121 } 122 123 void gen2_error_reset(struct intel_uncore *uncore, struct i915_error_regs regs) 124 { 125 intel_uncore_write(uncore, regs.emr, 0xffffffff); 126 intel_uncore_posting_read(uncore, regs.emr); 127 128 intel_uncore_write(uncore, regs.eir, 0xffffffff); 129 intel_uncore_posting_read(uncore, regs.eir); 130 intel_uncore_write(uncore, regs.eir, 0xffffffff); 131 intel_uncore_posting_read(uncore, regs.eir); 132 } 133 134 void gen2_error_init(struct intel_uncore *uncore, struct i915_error_regs regs, 135 u32 emr_val) 136 { 137 intel_uncore_write(uncore, regs.eir, 0xffffffff); 138 intel_uncore_posting_read(uncore, regs.eir); 139 intel_uncore_write(uncore, regs.eir, 0xffffffff); 140 intel_uncore_posting_read(uncore, regs.eir); 141 142 intel_uncore_write(uncore, regs.emr, emr_val); 143 intel_uncore_posting_read(uncore, regs.emr); 144 } 145 146 /** 147 * ivb_parity_work - Workqueue called when a parity error interrupt 148 * occurred. 149 * @work: workqueue struct 150 * 151 * Doesn't actually do anything except notify userspace. As a consequence of 152 * this event, userspace should try to remap the bad rows since statistically 153 * it is likely the same row is more likely to go bad again. 154 */ 155 static void ivb_parity_work(struct work_struct *work) 156 { 157 struct drm_i915_private *dev_priv = 158 container_of(work, typeof(*dev_priv), l3_parity.error_work); 159 struct intel_gt *gt = to_gt(dev_priv); 160 u32 error_status, row, bank, subbank; 161 char *parity_event[6]; 162 u32 misccpctl; 163 u8 slice = 0; 164 165 /* We must turn off DOP level clock gating to access the L3 registers. 166 * In order to prevent a get/put style interface, acquire struct mutex 167 * any time we access those registers. 168 */ 169 mutex_lock(&dev_priv->drm.struct_mutex); 170 171 /* If we've screwed up tracking, just let the interrupt fire again */ 172 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice)) 173 goto out; 174 175 misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL, 176 GEN7_DOP_CLOCK_GATE_ENABLE, 0); 177 intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL); 178 179 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { 180 i915_reg_t reg; 181 182 slice--; 183 if (drm_WARN_ON_ONCE(&dev_priv->drm, 184 slice >= NUM_L3_SLICES(dev_priv))) 185 break; 186 187 dev_priv->l3_parity.which_slice &= ~(1<<slice); 188 189 reg = GEN7_L3CDERRST1(slice); 190 191 error_status = intel_uncore_read(&dev_priv->uncore, reg); 192 row = GEN7_PARITY_ERROR_ROW(error_status); 193 bank = GEN7_PARITY_ERROR_BANK(error_status); 194 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); 195 196 intel_uncore_write(&dev_priv->uncore, reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); 197 intel_uncore_posting_read(&dev_priv->uncore, reg); 198 199 parity_event[0] = I915_L3_PARITY_UEVENT "=1"; 200 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); 201 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); 202 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); 203 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); 204 parity_event[5] = NULL; 205 206 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj, 207 KOBJ_CHANGE, parity_event); 208 209 drm_dbg(&dev_priv->drm, 210 "Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", 211 slice, row, bank, subbank); 212 213 kfree(parity_event[4]); 214 kfree(parity_event[3]); 215 kfree(parity_event[2]); 216 kfree(parity_event[1]); 217 } 218 219 intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl); 220 221 out: 222 drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice); 223 spin_lock_irq(gt->irq_lock); 224 gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv)); 225 spin_unlock_irq(gt->irq_lock); 226 227 mutex_unlock(&dev_priv->drm.struct_mutex); 228 } 229 230 static irqreturn_t valleyview_irq_handler(int irq, void *arg) 231 { 232 struct drm_i915_private *dev_priv = arg; 233 struct intel_display *display = &dev_priv->display; 234 irqreturn_t ret = IRQ_NONE; 235 236 if (!intel_irqs_enabled(dev_priv)) 237 return IRQ_NONE; 238 239 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 240 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 241 242 do { 243 u32 iir, gt_iir, pm_iir; 244 u32 eir = 0, dpinvgtt = 0; 245 u32 pipe_stats[I915_MAX_PIPES] = {}; 246 u32 hotplug_status = 0; 247 u32 ier = 0; 248 249 gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR); 250 pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR); 251 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR); 252 253 if (gt_iir == 0 && pm_iir == 0 && iir == 0) 254 break; 255 256 ret = IRQ_HANDLED; 257 258 /* 259 * Theory on interrupt generation, based on empirical evidence: 260 * 261 * x = ((VLV_IIR & VLV_IER) || 262 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) && 263 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE))); 264 * 265 * A CPU interrupt will only be raised when 'x' has a 0->1 edge. 266 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to 267 * guarantee the CPU interrupt will be raised again even if we 268 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR 269 * bits this time around. 270 */ 271 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0); 272 ier = intel_uncore_rmw(&dev_priv->uncore, VLV_IER, ~0, 0); 273 274 if (gt_iir) 275 intel_uncore_write(&dev_priv->uncore, GTIIR, gt_iir); 276 if (pm_iir) 277 intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir); 278 279 if (iir & I915_DISPLAY_PORT_INTERRUPT) 280 hotplug_status = i9xx_hpd_irq_ack(display); 281 282 if (iir & I915_MASTER_ERROR_INTERRUPT) 283 vlv_display_error_irq_ack(display, &eir, &dpinvgtt); 284 285 /* Call regardless, as some status bits might not be 286 * signalled in IIR */ 287 i9xx_pipestat_irq_ack(display, iir, pipe_stats); 288 289 if (iir & (I915_LPE_PIPE_A_INTERRUPT | 290 I915_LPE_PIPE_B_INTERRUPT)) 291 intel_lpe_audio_irq_handler(display); 292 293 /* 294 * VLV_IIR is single buffered, and reflects the level 295 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. 296 */ 297 if (iir) 298 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir); 299 300 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier); 301 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); 302 303 if (gt_iir) 304 gen6_gt_irq_handler(to_gt(dev_priv), gt_iir); 305 if (pm_iir) 306 gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir); 307 308 if (hotplug_status) 309 i9xx_hpd_irq_handler(display, hotplug_status); 310 311 if (iir & I915_MASTER_ERROR_INTERRUPT) 312 vlv_display_error_irq_handler(display, eir, dpinvgtt); 313 314 valleyview_pipestat_irq_handler(display, pipe_stats); 315 } while (0); 316 317 pmu_irq_stats(dev_priv, ret); 318 319 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 320 321 return ret; 322 } 323 324 static irqreturn_t cherryview_irq_handler(int irq, void *arg) 325 { 326 struct drm_i915_private *dev_priv = arg; 327 struct intel_display *display = &dev_priv->display; 328 irqreturn_t ret = IRQ_NONE; 329 330 if (!intel_irqs_enabled(dev_priv)) 331 return IRQ_NONE; 332 333 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 334 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 335 336 do { 337 u32 master_ctl, iir; 338 u32 eir = 0, dpinvgtt = 0; 339 u32 pipe_stats[I915_MAX_PIPES] = {}; 340 u32 hotplug_status = 0; 341 u32 ier = 0; 342 343 master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; 344 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR); 345 346 if (master_ctl == 0 && iir == 0) 347 break; 348 349 ret = IRQ_HANDLED; 350 351 /* 352 * Theory on interrupt generation, based on empirical evidence: 353 * 354 * x = ((VLV_IIR & VLV_IER) || 355 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) && 356 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL))); 357 * 358 * A CPU interrupt will only be raised when 'x' has a 0->1 edge. 359 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to 360 * guarantee the CPU interrupt will be raised again even if we 361 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL 362 * bits this time around. 363 */ 364 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0); 365 ier = intel_uncore_rmw(&dev_priv->uncore, VLV_IER, ~0, 0); 366 367 gen8_gt_irq_handler(to_gt(dev_priv), master_ctl); 368 369 if (iir & I915_DISPLAY_PORT_INTERRUPT) 370 hotplug_status = i9xx_hpd_irq_ack(display); 371 372 if (iir & I915_MASTER_ERROR_INTERRUPT) 373 vlv_display_error_irq_ack(display, &eir, &dpinvgtt); 374 375 /* Call regardless, as some status bits might not be 376 * signalled in IIR */ 377 i9xx_pipestat_irq_ack(display, iir, pipe_stats); 378 379 if (iir & (I915_LPE_PIPE_A_INTERRUPT | 380 I915_LPE_PIPE_B_INTERRUPT | 381 I915_LPE_PIPE_C_INTERRUPT)) 382 intel_lpe_audio_irq_handler(display); 383 384 /* 385 * VLV_IIR is single buffered, and reflects the level 386 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. 387 */ 388 if (iir) 389 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir); 390 391 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier); 392 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); 393 394 if (hotplug_status) 395 i9xx_hpd_irq_handler(display, hotplug_status); 396 397 if (iir & I915_MASTER_ERROR_INTERRUPT) 398 vlv_display_error_irq_handler(display, eir, dpinvgtt); 399 400 valleyview_pipestat_irq_handler(display, pipe_stats); 401 } while (0); 402 403 pmu_irq_stats(dev_priv, ret); 404 405 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 406 407 return ret; 408 } 409 410 /* 411 * To handle irqs with the minimum potential races with fresh interrupts, we: 412 * 1 - Disable Master Interrupt Control. 413 * 2 - Find the source(s) of the interrupt. 414 * 3 - Clear the Interrupt Identity bits (IIR). 415 * 4 - Process the interrupt(s) that had bits set in the IIRs. 416 * 5 - Re-enable Master Interrupt Control. 417 */ 418 static irqreturn_t ilk_irq_handler(int irq, void *arg) 419 { 420 struct drm_i915_private *i915 = arg; 421 struct intel_display *display = &i915->display; 422 void __iomem * const regs = intel_uncore_regs(&i915->uncore); 423 u32 de_iir, gt_iir, de_ier, sde_ier = 0; 424 irqreturn_t ret = IRQ_NONE; 425 426 if (unlikely(!intel_irqs_enabled(i915))) 427 return IRQ_NONE; 428 429 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 430 disable_rpm_wakeref_asserts(&i915->runtime_pm); 431 432 /* disable master interrupt before clearing iir */ 433 de_ier = raw_reg_read(regs, DEIER); 434 raw_reg_write(regs, DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); 435 436 /* Disable south interrupts. We'll only write to SDEIIR once, so further 437 * interrupts will will be stored on its back queue, and then we'll be 438 * able to process them after we restore SDEIER (as soon as we restore 439 * it, we'll get an interrupt if SDEIIR still has something to process 440 * due to its back queue). */ 441 if (!HAS_PCH_NOP(i915)) { 442 sde_ier = raw_reg_read(regs, SDEIER); 443 raw_reg_write(regs, SDEIER, 0); 444 } 445 446 /* Find, clear, then process each source of interrupt */ 447 448 gt_iir = raw_reg_read(regs, GTIIR); 449 if (gt_iir) { 450 raw_reg_write(regs, GTIIR, gt_iir); 451 if (GRAPHICS_VER(i915) >= 6) 452 gen6_gt_irq_handler(to_gt(i915), gt_iir); 453 else 454 gen5_gt_irq_handler(to_gt(i915), gt_iir); 455 ret = IRQ_HANDLED; 456 } 457 458 de_iir = raw_reg_read(regs, DEIIR); 459 if (de_iir) { 460 raw_reg_write(regs, DEIIR, de_iir); 461 if (DISPLAY_VER(i915) >= 7) 462 ivb_display_irq_handler(display, de_iir); 463 else 464 ilk_display_irq_handler(display, de_iir); 465 ret = IRQ_HANDLED; 466 } 467 468 if (GRAPHICS_VER(i915) >= 6) { 469 u32 pm_iir = raw_reg_read(regs, GEN6_PMIIR); 470 if (pm_iir) { 471 raw_reg_write(regs, GEN6_PMIIR, pm_iir); 472 gen6_rps_irq_handler(&to_gt(i915)->rps, pm_iir); 473 ret = IRQ_HANDLED; 474 } 475 } 476 477 raw_reg_write(regs, DEIER, de_ier); 478 if (sde_ier) 479 raw_reg_write(regs, SDEIER, sde_ier); 480 481 pmu_irq_stats(i915, ret); 482 483 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 484 enable_rpm_wakeref_asserts(&i915->runtime_pm); 485 486 return ret; 487 } 488 489 static inline u32 gen8_master_intr_disable(void __iomem * const regs) 490 { 491 raw_reg_write(regs, GEN8_MASTER_IRQ, 0); 492 493 /* 494 * Now with master disabled, get a sample of level indications 495 * for this interrupt. Indications will be cleared on related acks. 496 * New indications can and will light up during processing, 497 * and will generate new interrupt after enabling master. 498 */ 499 return raw_reg_read(regs, GEN8_MASTER_IRQ); 500 } 501 502 static inline void gen8_master_intr_enable(void __iomem * const regs) 503 { 504 raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); 505 } 506 507 static irqreturn_t gen8_irq_handler(int irq, void *arg) 508 { 509 struct drm_i915_private *dev_priv = arg; 510 struct intel_display *display = &dev_priv->display; 511 void __iomem * const regs = intel_uncore_regs(&dev_priv->uncore); 512 u32 master_ctl; 513 514 if (!intel_irqs_enabled(dev_priv)) 515 return IRQ_NONE; 516 517 master_ctl = gen8_master_intr_disable(regs); 518 if (!master_ctl) { 519 gen8_master_intr_enable(regs); 520 return IRQ_NONE; 521 } 522 523 /* Find, queue (onto bottom-halves), then clear each source */ 524 gen8_gt_irq_handler(to_gt(dev_priv), master_ctl); 525 526 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 527 if (master_ctl & ~GEN8_GT_IRQS) { 528 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 529 gen8_de_irq_handler(display, master_ctl); 530 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 531 } 532 533 gen8_master_intr_enable(regs); 534 535 pmu_irq_stats(dev_priv, IRQ_HANDLED); 536 537 return IRQ_HANDLED; 538 } 539 540 static inline u32 gen11_master_intr_disable(void __iomem * const regs) 541 { 542 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0); 543 544 /* 545 * Now with master disabled, get a sample of level indications 546 * for this interrupt. Indications will be cleared on related acks. 547 * New indications can and will light up during processing, 548 * and will generate new interrupt after enabling master. 549 */ 550 return raw_reg_read(regs, GEN11_GFX_MSTR_IRQ); 551 } 552 553 static inline void gen11_master_intr_enable(void __iomem * const regs) 554 { 555 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ); 556 } 557 558 static irqreturn_t gen11_irq_handler(int irq, void *arg) 559 { 560 struct drm_i915_private *i915 = arg; 561 struct intel_display *display = &i915->display; 562 void __iomem * const regs = intel_uncore_regs(&i915->uncore); 563 struct intel_gt *gt = to_gt(i915); 564 u32 master_ctl; 565 u32 gu_misc_iir; 566 567 if (!intel_irqs_enabled(i915)) 568 return IRQ_NONE; 569 570 master_ctl = gen11_master_intr_disable(regs); 571 if (!master_ctl) { 572 gen11_master_intr_enable(regs); 573 return IRQ_NONE; 574 } 575 576 /* Find, queue (onto bottom-halves), then clear each source */ 577 gen11_gt_irq_handler(gt, master_ctl); 578 579 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 580 if (master_ctl & GEN11_DISPLAY_IRQ) 581 gen11_display_irq_handler(display); 582 583 gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl); 584 585 gen11_master_intr_enable(regs); 586 587 gen11_gu_misc_irq_handler(display, gu_misc_iir); 588 589 pmu_irq_stats(i915, IRQ_HANDLED); 590 591 return IRQ_HANDLED; 592 } 593 594 static inline u32 dg1_master_intr_disable(void __iomem * const regs) 595 { 596 u32 val; 597 598 /* First disable interrupts */ 599 raw_reg_write(regs, DG1_MSTR_TILE_INTR, 0); 600 601 /* Get the indication levels and ack the master unit */ 602 val = raw_reg_read(regs, DG1_MSTR_TILE_INTR); 603 if (unlikely(!val)) 604 return 0; 605 606 raw_reg_write(regs, DG1_MSTR_TILE_INTR, val); 607 608 return val; 609 } 610 611 static inline void dg1_master_intr_enable(void __iomem * const regs) 612 { 613 raw_reg_write(regs, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ); 614 } 615 616 static irqreturn_t dg1_irq_handler(int irq, void *arg) 617 { 618 struct drm_i915_private * const i915 = arg; 619 struct intel_display *display = &i915->display; 620 struct intel_gt *gt = to_gt(i915); 621 void __iomem * const regs = intel_uncore_regs(gt->uncore); 622 u32 master_tile_ctl, master_ctl; 623 u32 gu_misc_iir; 624 625 if (!intel_irqs_enabled(i915)) 626 return IRQ_NONE; 627 628 master_tile_ctl = dg1_master_intr_disable(regs); 629 if (!master_tile_ctl) { 630 dg1_master_intr_enable(regs); 631 return IRQ_NONE; 632 } 633 634 /* FIXME: we only support tile 0 for now. */ 635 if (master_tile_ctl & DG1_MSTR_TILE(0)) { 636 master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ); 637 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, master_ctl); 638 } else { 639 drm_err(&i915->drm, "Tile not supported: 0x%08x\n", 640 master_tile_ctl); 641 dg1_master_intr_enable(regs); 642 return IRQ_NONE; 643 } 644 645 gen11_gt_irq_handler(gt, master_ctl); 646 647 if (master_ctl & GEN11_DISPLAY_IRQ) 648 gen11_display_irq_handler(display); 649 650 gu_misc_iir = gen11_gu_misc_irq_ack(display, master_ctl); 651 652 dg1_master_intr_enable(regs); 653 654 gen11_gu_misc_irq_handler(display, gu_misc_iir); 655 656 pmu_irq_stats(i915, IRQ_HANDLED); 657 658 return IRQ_HANDLED; 659 } 660 661 static void ibx_irq_reset(struct drm_i915_private *dev_priv) 662 { 663 struct intel_uncore *uncore = &dev_priv->uncore; 664 665 if (HAS_PCH_NOP(dev_priv)) 666 return; 667 668 gen2_irq_reset(uncore, SDE_IRQ_REGS); 669 670 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) 671 intel_uncore_write(&dev_priv->uncore, SERR_INT, 0xffffffff); 672 } 673 674 /* drm_dma.h hooks 675 */ 676 static void ilk_irq_reset(struct drm_i915_private *dev_priv) 677 { 678 struct intel_uncore *uncore = &dev_priv->uncore; 679 680 gen2_irq_reset(uncore, DE_IRQ_REGS); 681 dev_priv->irq_mask = ~0u; 682 683 if (GRAPHICS_VER(dev_priv) == 7) 684 intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff); 685 686 if (IS_HASWELL(dev_priv)) { 687 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff); 688 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff); 689 } 690 691 gen5_gt_irq_reset(to_gt(dev_priv)); 692 693 ibx_irq_reset(dev_priv); 694 } 695 696 static void valleyview_irq_reset(struct drm_i915_private *dev_priv) 697 { 698 struct intel_display *display = &dev_priv->display; 699 700 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0); 701 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER); 702 703 gen5_gt_irq_reset(to_gt(dev_priv)); 704 705 spin_lock_irq(&dev_priv->irq_lock); 706 vlv_display_irq_reset(display); 707 spin_unlock_irq(&dev_priv->irq_lock); 708 } 709 710 static void gen8_irq_reset(struct drm_i915_private *dev_priv) 711 { 712 struct intel_display *display = &dev_priv->display; 713 struct intel_uncore *uncore = &dev_priv->uncore; 714 715 gen8_master_intr_disable(intel_uncore_regs(uncore)); 716 717 gen8_gt_irq_reset(to_gt(dev_priv)); 718 gen8_display_irq_reset(display); 719 gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS); 720 721 if (HAS_PCH_SPLIT(dev_priv)) 722 ibx_irq_reset(dev_priv); 723 724 } 725 726 static void gen11_irq_reset(struct drm_i915_private *dev_priv) 727 { 728 struct intel_display *display = &dev_priv->display; 729 struct intel_gt *gt = to_gt(dev_priv); 730 struct intel_uncore *uncore = gt->uncore; 731 732 gen11_master_intr_disable(intel_uncore_regs(&dev_priv->uncore)); 733 734 gen11_gt_irq_reset(gt); 735 gen11_display_irq_reset(display); 736 737 gen2_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS); 738 gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS); 739 } 740 741 static void dg1_irq_reset(struct drm_i915_private *dev_priv) 742 { 743 struct intel_display *display = &dev_priv->display; 744 struct intel_uncore *uncore = &dev_priv->uncore; 745 struct intel_gt *gt; 746 unsigned int i; 747 748 dg1_master_intr_disable(intel_uncore_regs(&dev_priv->uncore)); 749 750 for_each_gt(gt, dev_priv, i) 751 gen11_gt_irq_reset(gt); 752 753 gen11_display_irq_reset(display); 754 755 gen2_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS); 756 gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS); 757 758 intel_uncore_write(uncore, GEN11_GFX_MSTR_IRQ, ~0); 759 } 760 761 static void cherryview_irq_reset(struct drm_i915_private *dev_priv) 762 { 763 struct intel_display *display = &dev_priv->display; 764 struct intel_uncore *uncore = &dev_priv->uncore; 765 766 intel_uncore_write(uncore, GEN8_MASTER_IRQ, 0); 767 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ); 768 769 gen8_gt_irq_reset(to_gt(dev_priv)); 770 771 gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS); 772 773 spin_lock_irq(&dev_priv->irq_lock); 774 vlv_display_irq_reset(display); 775 spin_unlock_irq(&dev_priv->irq_lock); 776 } 777 778 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv) 779 { 780 struct intel_display *display = &dev_priv->display; 781 782 gen5_gt_irq_postinstall(to_gt(dev_priv)); 783 784 ilk_de_irq_postinstall(display); 785 } 786 787 static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv) 788 { 789 struct intel_display *display = &dev_priv->display; 790 791 gen5_gt_irq_postinstall(to_gt(dev_priv)); 792 793 spin_lock_irq(&dev_priv->irq_lock); 794 vlv_display_irq_postinstall(display); 795 spin_unlock_irq(&dev_priv->irq_lock); 796 797 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); 798 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER); 799 } 800 801 static void gen8_irq_postinstall(struct drm_i915_private *dev_priv) 802 { 803 struct intel_display *display = &dev_priv->display; 804 805 gen8_gt_irq_postinstall(to_gt(dev_priv)); 806 gen8_de_irq_postinstall(display); 807 808 gen8_master_intr_enable(intel_uncore_regs(&dev_priv->uncore)); 809 } 810 811 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv) 812 { 813 struct intel_display *display = &dev_priv->display; 814 struct intel_gt *gt = to_gt(dev_priv); 815 struct intel_uncore *uncore = gt->uncore; 816 u32 gu_misc_masked = GEN11_GU_MISC_GSE; 817 818 gen11_gt_irq_postinstall(gt); 819 gen11_de_irq_postinstall(display); 820 821 gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked); 822 823 gen11_master_intr_enable(intel_uncore_regs(uncore)); 824 intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ); 825 } 826 827 static void dg1_irq_postinstall(struct drm_i915_private *dev_priv) 828 { 829 struct intel_display *display = &dev_priv->display; 830 struct intel_uncore *uncore = &dev_priv->uncore; 831 u32 gu_misc_masked = GEN11_GU_MISC_GSE; 832 struct intel_gt *gt; 833 unsigned int i; 834 835 for_each_gt(gt, dev_priv, i) 836 gen11_gt_irq_postinstall(gt); 837 838 gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked); 839 840 dg1_de_irq_postinstall(display); 841 842 dg1_master_intr_enable(intel_uncore_regs(uncore)); 843 intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR); 844 } 845 846 static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv) 847 { 848 struct intel_display *display = &dev_priv->display; 849 850 gen8_gt_irq_postinstall(to_gt(dev_priv)); 851 852 spin_lock_irq(&dev_priv->irq_lock); 853 vlv_display_irq_postinstall(display); 854 spin_unlock_irq(&dev_priv->irq_lock); 855 856 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); 857 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ); 858 } 859 860 static u32 i9xx_error_mask(struct drm_i915_private *i915) 861 { 862 /* 863 * On gen2/3 FBC generates (seemingly spurious) 864 * display INVALID_GTT/INVALID_GTT_PTE table errors. 865 * 866 * Also gen3 bspec has this to say: 867 * "DISPA_INVALID_GTT_PTE 868 " [DevNapa] : Reserved. This bit does not reflect the page 869 " table error for the display plane A." 870 * 871 * Unfortunately we can't mask off individual PGTBL_ER bits, 872 * so we just have to mask off all page table errors via EMR. 873 */ 874 if (HAS_FBC(i915)) 875 return I915_ERROR_MEMORY_REFRESH; 876 else 877 return I915_ERROR_PAGE_TABLE | 878 I915_ERROR_MEMORY_REFRESH; 879 } 880 881 static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv, 882 u32 *eir, u32 *eir_stuck) 883 { 884 u32 emr; 885 886 *eir = intel_uncore_read(&dev_priv->uncore, EIR); 887 intel_uncore_write(&dev_priv->uncore, EIR, *eir); 888 889 *eir_stuck = intel_uncore_read(&dev_priv->uncore, EIR); 890 if (*eir_stuck == 0) 891 return; 892 893 /* 894 * Toggle all EMR bits to make sure we get an edge 895 * in the ISR master error bit if we don't clear 896 * all the EIR bits. Otherwise the edge triggered 897 * IIR on i965/g4x wouldn't notice that an interrupt 898 * is still pending. Also some EIR bits can't be 899 * cleared except by handling the underlying error 900 * (or by a GPU reset) so we mask any bit that 901 * remains set. 902 */ 903 emr = intel_uncore_read(&dev_priv->uncore, EMR); 904 intel_uncore_write(&dev_priv->uncore, EMR, 0xffffffff); 905 intel_uncore_write(&dev_priv->uncore, EMR, emr | *eir_stuck); 906 } 907 908 static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv, 909 u32 eir, u32 eir_stuck) 910 { 911 drm_dbg(&dev_priv->drm, "Master Error, EIR 0x%08x\n", eir); 912 913 if (eir_stuck) 914 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n", 915 eir_stuck); 916 917 drm_dbg(&dev_priv->drm, "PGTBL_ER: 0x%08x\n", 918 intel_uncore_read(&dev_priv->uncore, PGTBL_ER)); 919 } 920 921 static void i915_irq_reset(struct drm_i915_private *dev_priv) 922 { 923 struct intel_display *display = &dev_priv->display; 924 struct intel_uncore *uncore = &dev_priv->uncore; 925 926 i9xx_display_irq_reset(display); 927 928 gen2_error_reset(uncore, GEN2_ERROR_REGS); 929 gen2_irq_reset(uncore, GEN2_IRQ_REGS); 930 dev_priv->irq_mask = ~0u; 931 } 932 933 static void i915_irq_postinstall(struct drm_i915_private *dev_priv) 934 { 935 struct intel_display *display = &dev_priv->display; 936 struct intel_uncore *uncore = &dev_priv->uncore; 937 u32 enable_mask; 938 939 gen2_error_init(uncore, GEN2_ERROR_REGS, ~i9xx_error_mask(dev_priv)); 940 941 dev_priv->irq_mask = 942 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 943 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 944 I915_MASTER_ERROR_INTERRUPT); 945 946 enable_mask = 947 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 948 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 949 I915_MASTER_ERROR_INTERRUPT | 950 I915_USER_INTERRUPT; 951 952 if (DISPLAY_VER(dev_priv) >= 3) { 953 dev_priv->irq_mask &= ~I915_ASLE_INTERRUPT; 954 enable_mask |= I915_ASLE_INTERRUPT; 955 } 956 957 if (HAS_HOTPLUG(dev_priv)) { 958 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; 959 enable_mask |= I915_DISPLAY_PORT_INTERRUPT; 960 } 961 962 gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->irq_mask, enable_mask); 963 964 /* Interrupt setup is already guaranteed to be single-threaded, this is 965 * just to make the assert_spin_locked check happy. */ 966 spin_lock_irq(&dev_priv->irq_lock); 967 i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); 968 i915_enable_pipestat(display, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); 969 spin_unlock_irq(&dev_priv->irq_lock); 970 971 i915_enable_asle_pipestat(display); 972 } 973 974 static irqreturn_t i915_irq_handler(int irq, void *arg) 975 { 976 struct drm_i915_private *dev_priv = arg; 977 struct intel_display *display = &dev_priv->display; 978 irqreturn_t ret = IRQ_NONE; 979 980 if (!intel_irqs_enabled(dev_priv)) 981 return IRQ_NONE; 982 983 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 984 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 985 986 do { 987 u32 pipe_stats[I915_MAX_PIPES] = {}; 988 u32 eir = 0, eir_stuck = 0; 989 u32 hotplug_status = 0; 990 u32 iir; 991 992 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR); 993 if (iir == 0) 994 break; 995 996 ret = IRQ_HANDLED; 997 998 if (HAS_HOTPLUG(dev_priv) && 999 iir & I915_DISPLAY_PORT_INTERRUPT) 1000 hotplug_status = i9xx_hpd_irq_ack(display); 1001 1002 /* Call regardless, as some status bits might not be 1003 * signalled in IIR */ 1004 i9xx_pipestat_irq_ack(display, iir, pipe_stats); 1005 1006 if (iir & I915_MASTER_ERROR_INTERRUPT) 1007 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck); 1008 1009 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir); 1010 1011 if (iir & I915_USER_INTERRUPT) 1012 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir); 1013 1014 if (iir & I915_MASTER_ERROR_INTERRUPT) 1015 i9xx_error_irq_handler(dev_priv, eir, eir_stuck); 1016 1017 if (hotplug_status) 1018 i9xx_hpd_irq_handler(display, hotplug_status); 1019 1020 i915_pipestat_irq_handler(display, iir, pipe_stats); 1021 } while (0); 1022 1023 pmu_irq_stats(dev_priv, ret); 1024 1025 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1026 1027 return ret; 1028 } 1029 1030 static void i965_irq_reset(struct drm_i915_private *dev_priv) 1031 { 1032 struct intel_display *display = &dev_priv->display; 1033 struct intel_uncore *uncore = &dev_priv->uncore; 1034 1035 i9xx_display_irq_reset(display); 1036 1037 gen2_error_reset(uncore, GEN2_ERROR_REGS); 1038 gen2_irq_reset(uncore, GEN2_IRQ_REGS); 1039 dev_priv->irq_mask = ~0u; 1040 } 1041 1042 static u32 i965_error_mask(struct drm_i915_private *i915) 1043 { 1044 /* 1045 * Enable some error detection, note the instruction error mask 1046 * bit is reserved, so we leave it masked. 1047 * 1048 * i965 FBC no longer generates spurious GTT errors, 1049 * so we can always enable the page table errors. 1050 */ 1051 if (IS_G4X(i915)) 1052 return GM45_ERROR_PAGE_TABLE | 1053 GM45_ERROR_MEM_PRIV | 1054 GM45_ERROR_CP_PRIV | 1055 I915_ERROR_MEMORY_REFRESH; 1056 else 1057 return I915_ERROR_PAGE_TABLE | 1058 I915_ERROR_MEMORY_REFRESH; 1059 } 1060 1061 static void i965_irq_postinstall(struct drm_i915_private *dev_priv) 1062 { 1063 struct intel_display *display = &dev_priv->display; 1064 struct intel_uncore *uncore = &dev_priv->uncore; 1065 u32 enable_mask; 1066 1067 gen2_error_init(uncore, GEN2_ERROR_REGS, ~i965_error_mask(dev_priv)); 1068 1069 dev_priv->irq_mask = 1070 ~(I915_ASLE_INTERRUPT | 1071 I915_DISPLAY_PORT_INTERRUPT | 1072 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 1073 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 1074 I915_MASTER_ERROR_INTERRUPT); 1075 1076 enable_mask = 1077 I915_ASLE_INTERRUPT | 1078 I915_DISPLAY_PORT_INTERRUPT | 1079 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 1080 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 1081 I915_MASTER_ERROR_INTERRUPT | 1082 I915_USER_INTERRUPT; 1083 1084 if (IS_G4X(dev_priv)) 1085 enable_mask |= I915_BSD_USER_INTERRUPT; 1086 1087 gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->irq_mask, enable_mask); 1088 1089 /* Interrupt setup is already guaranteed to be single-threaded, this is 1090 * just to make the assert_spin_locked check happy. */ 1091 spin_lock_irq(&dev_priv->irq_lock); 1092 i915_enable_pipestat(display, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); 1093 i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); 1094 i915_enable_pipestat(display, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); 1095 spin_unlock_irq(&dev_priv->irq_lock); 1096 1097 i915_enable_asle_pipestat(display); 1098 } 1099 1100 static irqreturn_t i965_irq_handler(int irq, void *arg) 1101 { 1102 struct drm_i915_private *dev_priv = arg; 1103 struct intel_display *display = &dev_priv->display; 1104 irqreturn_t ret = IRQ_NONE; 1105 1106 if (!intel_irqs_enabled(dev_priv)) 1107 return IRQ_NONE; 1108 1109 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 1110 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1111 1112 do { 1113 u32 pipe_stats[I915_MAX_PIPES] = {}; 1114 u32 eir = 0, eir_stuck = 0; 1115 u32 hotplug_status = 0; 1116 u32 iir; 1117 1118 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR); 1119 if (iir == 0) 1120 break; 1121 1122 ret = IRQ_HANDLED; 1123 1124 if (iir & I915_DISPLAY_PORT_INTERRUPT) 1125 hotplug_status = i9xx_hpd_irq_ack(display); 1126 1127 /* Call regardless, as some status bits might not be 1128 * signalled in IIR */ 1129 i9xx_pipestat_irq_ack(display, iir, pipe_stats); 1130 1131 if (iir & I915_MASTER_ERROR_INTERRUPT) 1132 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck); 1133 1134 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir); 1135 1136 if (iir & I915_USER_INTERRUPT) 1137 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], 1138 iir); 1139 1140 if (iir & I915_BSD_USER_INTERRUPT) 1141 intel_engine_cs_irq(to_gt(dev_priv)->engine[VCS0], 1142 iir >> 25); 1143 1144 if (iir & I915_MASTER_ERROR_INTERRUPT) 1145 i9xx_error_irq_handler(dev_priv, eir, eir_stuck); 1146 1147 if (hotplug_status) 1148 i9xx_hpd_irq_handler(display, hotplug_status); 1149 1150 i965_pipestat_irq_handler(display, iir, pipe_stats); 1151 } while (0); 1152 1153 pmu_irq_stats(dev_priv, IRQ_HANDLED); 1154 1155 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1156 1157 return ret; 1158 } 1159 1160 /** 1161 * intel_irq_init - initializes irq support 1162 * @dev_priv: i915 device instance 1163 * 1164 * This function initializes all the irq support including work items, timers 1165 * and all the vtables. It does not setup the interrupt itself though. 1166 */ 1167 void intel_irq_init(struct drm_i915_private *dev_priv) 1168 { 1169 int i; 1170 1171 INIT_WORK(&dev_priv->l3_parity.error_work, ivb_parity_work); 1172 for (i = 0; i < MAX_L3_SLICES; ++i) 1173 dev_priv->l3_parity.remap_info[i] = NULL; 1174 1175 /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */ 1176 if (HAS_GT_UC(dev_priv) && GRAPHICS_VER(dev_priv) < 11) 1177 to_gt(dev_priv)->pm_guc_events = GUC_INTR_GUC2HOST << 16; 1178 } 1179 1180 /** 1181 * intel_irq_fini - deinitializes IRQ support 1182 * @i915: i915 device instance 1183 * 1184 * This function deinitializes all the IRQ support. 1185 */ 1186 void intel_irq_fini(struct drm_i915_private *i915) 1187 { 1188 int i; 1189 1190 for (i = 0; i < MAX_L3_SLICES; ++i) 1191 kfree(i915->l3_parity.remap_info[i]); 1192 } 1193 1194 static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv) 1195 { 1196 if (HAS_GMCH(dev_priv)) { 1197 if (IS_CHERRYVIEW(dev_priv)) 1198 return cherryview_irq_handler; 1199 else if (IS_VALLEYVIEW(dev_priv)) 1200 return valleyview_irq_handler; 1201 else if (GRAPHICS_VER(dev_priv) == 4) 1202 return i965_irq_handler; 1203 else 1204 return i915_irq_handler; 1205 } else { 1206 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10)) 1207 return dg1_irq_handler; 1208 else if (GRAPHICS_VER(dev_priv) >= 11) 1209 return gen11_irq_handler; 1210 else if (GRAPHICS_VER(dev_priv) >= 8) 1211 return gen8_irq_handler; 1212 else 1213 return ilk_irq_handler; 1214 } 1215 } 1216 1217 static void intel_irq_reset(struct drm_i915_private *dev_priv) 1218 { 1219 if (HAS_GMCH(dev_priv)) { 1220 if (IS_CHERRYVIEW(dev_priv)) 1221 cherryview_irq_reset(dev_priv); 1222 else if (IS_VALLEYVIEW(dev_priv)) 1223 valleyview_irq_reset(dev_priv); 1224 else if (GRAPHICS_VER(dev_priv) == 4) 1225 i965_irq_reset(dev_priv); 1226 else 1227 i915_irq_reset(dev_priv); 1228 } else { 1229 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10)) 1230 dg1_irq_reset(dev_priv); 1231 else if (GRAPHICS_VER(dev_priv) >= 11) 1232 gen11_irq_reset(dev_priv); 1233 else if (GRAPHICS_VER(dev_priv) >= 8) 1234 gen8_irq_reset(dev_priv); 1235 else 1236 ilk_irq_reset(dev_priv); 1237 } 1238 } 1239 1240 static void intel_irq_postinstall(struct drm_i915_private *dev_priv) 1241 { 1242 if (HAS_GMCH(dev_priv)) { 1243 if (IS_CHERRYVIEW(dev_priv)) 1244 cherryview_irq_postinstall(dev_priv); 1245 else if (IS_VALLEYVIEW(dev_priv)) 1246 valleyview_irq_postinstall(dev_priv); 1247 else if (GRAPHICS_VER(dev_priv) == 4) 1248 i965_irq_postinstall(dev_priv); 1249 else 1250 i915_irq_postinstall(dev_priv); 1251 } else { 1252 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10)) 1253 dg1_irq_postinstall(dev_priv); 1254 else if (GRAPHICS_VER(dev_priv) >= 11) 1255 gen11_irq_postinstall(dev_priv); 1256 else if (GRAPHICS_VER(dev_priv) >= 8) 1257 gen8_irq_postinstall(dev_priv); 1258 else 1259 ilk_irq_postinstall(dev_priv); 1260 } 1261 } 1262 1263 /** 1264 * intel_irq_install - enables the hardware interrupt 1265 * @dev_priv: i915 device instance 1266 * 1267 * This function enables the hardware interrupt handling, but leaves the hotplug 1268 * handling still disabled. It is called after intel_irq_init(). 1269 * 1270 * In the driver load and resume code we need working interrupts in a few places 1271 * but don't want to deal with the hassle of concurrent probe and hotplug 1272 * workers. Hence the split into this two-stage approach. 1273 */ 1274 int intel_irq_install(struct drm_i915_private *dev_priv) 1275 { 1276 int irq = to_pci_dev(dev_priv->drm.dev)->irq; 1277 int ret; 1278 1279 /* 1280 * We enable some interrupt sources in our postinstall hooks, so mark 1281 * interrupts as enabled _before_ actually enabling them to avoid 1282 * special cases in our ordering checks. 1283 */ 1284 dev_priv->irqs_enabled = true; 1285 1286 intel_irq_reset(dev_priv); 1287 1288 ret = request_irq(irq, intel_irq_handler(dev_priv), 1289 IRQF_SHARED, DRIVER_NAME, dev_priv); 1290 if (ret < 0) { 1291 dev_priv->irqs_enabled = false; 1292 return ret; 1293 } 1294 1295 intel_irq_postinstall(dev_priv); 1296 1297 return ret; 1298 } 1299 1300 /** 1301 * intel_irq_uninstall - finalizes all irq handling 1302 * @dev_priv: i915 device instance 1303 * 1304 * This stops interrupt and hotplug handling and unregisters and frees all 1305 * resources acquired in the init functions. 1306 */ 1307 void intel_irq_uninstall(struct drm_i915_private *dev_priv) 1308 { 1309 struct intel_display *display = &dev_priv->display; 1310 int irq = to_pci_dev(dev_priv->drm.dev)->irq; 1311 1312 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->irqs_enabled)) 1313 return; 1314 1315 intel_irq_reset(dev_priv); 1316 1317 free_irq(irq, dev_priv); 1318 1319 intel_hpd_cancel_work(display); 1320 dev_priv->irqs_enabled = false; 1321 } 1322 1323 /** 1324 * intel_irq_suspend - Suspend interrupts 1325 * @i915: i915 device instance 1326 * 1327 * This function is used to disable interrupts at runtime. 1328 */ 1329 void intel_irq_suspend(struct drm_i915_private *i915) 1330 { 1331 intel_irq_reset(i915); 1332 i915->irqs_enabled = false; 1333 intel_synchronize_irq(i915); 1334 } 1335 1336 /** 1337 * intel_irq_resume - Resume interrupts 1338 * @i915: i915 device instance 1339 * 1340 * This function is used to enable interrupts at runtime. 1341 */ 1342 void intel_irq_resume(struct drm_i915_private *i915) 1343 { 1344 i915->irqs_enabled = true; 1345 intel_irq_reset(i915); 1346 intel_irq_postinstall(i915); 1347 } 1348 1349 bool intel_irqs_enabled(struct drm_i915_private *dev_priv) 1350 { 1351 return dev_priv->irqs_enabled; 1352 } 1353 1354 void intel_synchronize_irq(struct drm_i915_private *i915) 1355 { 1356 synchronize_irq(to_pci_dev(i915->drm.dev)->irq); 1357 } 1358 1359 void intel_synchronize_hardirq(struct drm_i915_private *i915) 1360 { 1361 synchronize_hardirq(to_pci_dev(i915->drm.dev)->irq); 1362 } 1363