1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- 2 */ 3 /* 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 */ 28 29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 30 31 #include <linux/circ_buf.h> 32 #include <linux/slab.h> 33 #include <linux/sysrq.h> 34 35 #include <drm/drm_drv.h> 36 #include <drm/drm_irq.h> 37 38 #include "display/intel_display_types.h" 39 #include "display/intel_fifo_underrun.h" 40 #include "display/intel_hotplug.h" 41 #include "display/intel_lpe_audio.h" 42 #include "display/intel_psr.h" 43 44 #include "gt/intel_breadcrumbs.h" 45 #include "gt/intel_gt.h" 46 #include "gt/intel_gt_irq.h" 47 #include "gt/intel_gt_pm_irq.h" 48 #include "gt/intel_rps.h" 49 50 #include "i915_drv.h" 51 #include "i915_irq.h" 52 #include "i915_trace.h" 53 #include "intel_pm.h" 54 55 /** 56 * DOC: interrupt handling 57 * 58 * These functions provide the basic support for enabling and disabling the 59 * interrupt handling support. There's a lot more functionality in i915_irq.c 60 * and related files, but that will be described in separate chapters. 61 */ 62 63 /* 64 * Interrupt statistic for PMU. Increments the counter only if the 65 * interrupt originated from the the GPU so interrupts from a device which 66 * shares the interrupt line are not accounted. 67 */ 68 static inline void pmu_irq_stats(struct drm_i915_private *i915, 69 irqreturn_t res) 70 { 71 if (unlikely(res != IRQ_HANDLED)) 72 return; 73 74 /* 75 * A clever compiler translates that into INC. A not so clever one 76 * should at least prevent store tearing. 77 */ 78 WRITE_ONCE(i915->pmu.irq_count, i915->pmu.irq_count + 1); 79 } 80 81 typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val); 82 typedef u32 (*hotplug_enables_func)(struct drm_i915_private *i915, 83 enum hpd_pin pin); 84 85 static const u32 hpd_ilk[HPD_NUM_PINS] = { 86 [HPD_PORT_A] = DE_DP_A_HOTPLUG, 87 }; 88 89 static const u32 hpd_ivb[HPD_NUM_PINS] = { 90 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB, 91 }; 92 93 static const u32 hpd_bdw[HPD_NUM_PINS] = { 94 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A), 95 }; 96 97 static const u32 hpd_ibx[HPD_NUM_PINS] = { 98 [HPD_CRT] = SDE_CRT_HOTPLUG, 99 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, 100 [HPD_PORT_B] = SDE_PORTB_HOTPLUG, 101 [HPD_PORT_C] = SDE_PORTC_HOTPLUG, 102 [HPD_PORT_D] = SDE_PORTD_HOTPLUG, 103 }; 104 105 static const u32 hpd_cpt[HPD_NUM_PINS] = { 106 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, 107 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, 108 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, 109 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, 110 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT, 111 }; 112 113 static const u32 hpd_spt[HPD_NUM_PINS] = { 114 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT, 115 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, 116 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, 117 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT, 118 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT, 119 }; 120 121 static const u32 hpd_mask_i915[HPD_NUM_PINS] = { 122 [HPD_CRT] = CRT_HOTPLUG_INT_EN, 123 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, 124 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, 125 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, 126 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, 127 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN, 128 }; 129 130 static const u32 hpd_status_g4x[HPD_NUM_PINS] = { 131 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, 132 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, 133 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, 134 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, 135 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, 136 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS, 137 }; 138 139 static const u32 hpd_status_i915[HPD_NUM_PINS] = { 140 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, 141 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, 142 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, 143 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, 144 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, 145 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS, 146 }; 147 148 static const u32 hpd_bxt[HPD_NUM_PINS] = { 149 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A), 150 [HPD_PORT_B] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_B), 151 [HPD_PORT_C] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_C), 152 }; 153 154 static const u32 hpd_gen11[HPD_NUM_PINS] = { 155 [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(HPD_PORT_TC1) | GEN11_TBT_HOTPLUG(HPD_PORT_TC1), 156 [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(HPD_PORT_TC2) | GEN11_TBT_HOTPLUG(HPD_PORT_TC2), 157 [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(HPD_PORT_TC3) | GEN11_TBT_HOTPLUG(HPD_PORT_TC3), 158 [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(HPD_PORT_TC4) | GEN11_TBT_HOTPLUG(HPD_PORT_TC4), 159 [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(HPD_PORT_TC5) | GEN11_TBT_HOTPLUG(HPD_PORT_TC5), 160 [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(HPD_PORT_TC6) | GEN11_TBT_HOTPLUG(HPD_PORT_TC6), 161 }; 162 163 static const u32 hpd_icp[HPD_NUM_PINS] = { 164 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A), 165 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B), 166 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C), 167 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1), 168 [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2), 169 [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3), 170 [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4), 171 [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5), 172 [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6), 173 }; 174 175 static const u32 hpd_sde_dg1[HPD_NUM_PINS] = { 176 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A), 177 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B), 178 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C), 179 [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D), 180 }; 181 182 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) 183 { 184 struct i915_hotplug *hpd = &dev_priv->hotplug; 185 186 if (HAS_GMCH(dev_priv)) { 187 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 188 IS_CHERRYVIEW(dev_priv)) 189 hpd->hpd = hpd_status_g4x; 190 else 191 hpd->hpd = hpd_status_i915; 192 return; 193 } 194 195 if (DISPLAY_VER(dev_priv) >= 11) 196 hpd->hpd = hpd_gen11; 197 else if (IS_GEN9_LP(dev_priv)) 198 hpd->hpd = hpd_bxt; 199 else if (DISPLAY_VER(dev_priv) >= 8) 200 hpd->hpd = hpd_bdw; 201 else if (DISPLAY_VER(dev_priv) >= 7) 202 hpd->hpd = hpd_ivb; 203 else 204 hpd->hpd = hpd_ilk; 205 206 if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) && 207 (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))) 208 return; 209 210 if (HAS_PCH_DG1(dev_priv)) 211 hpd->pch_hpd = hpd_sde_dg1; 212 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 213 hpd->pch_hpd = hpd_icp; 214 else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv)) 215 hpd->pch_hpd = hpd_spt; 216 else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_CPT(dev_priv)) 217 hpd->pch_hpd = hpd_cpt; 218 else if (HAS_PCH_IBX(dev_priv)) 219 hpd->pch_hpd = hpd_ibx; 220 else 221 MISSING_CASE(INTEL_PCH_TYPE(dev_priv)); 222 } 223 224 static void 225 intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) 226 { 227 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 228 229 drm_crtc_handle_vblank(&crtc->base); 230 } 231 232 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, 233 i915_reg_t iir, i915_reg_t ier) 234 { 235 intel_uncore_write(uncore, imr, 0xffffffff); 236 intel_uncore_posting_read(uncore, imr); 237 238 intel_uncore_write(uncore, ier, 0); 239 240 /* IIR can theoretically queue up two events. Be paranoid. */ 241 intel_uncore_write(uncore, iir, 0xffffffff); 242 intel_uncore_posting_read(uncore, iir); 243 intel_uncore_write(uncore, iir, 0xffffffff); 244 intel_uncore_posting_read(uncore, iir); 245 } 246 247 void gen2_irq_reset(struct intel_uncore *uncore) 248 { 249 intel_uncore_write16(uncore, GEN2_IMR, 0xffff); 250 intel_uncore_posting_read16(uncore, GEN2_IMR); 251 252 intel_uncore_write16(uncore, GEN2_IER, 0); 253 254 /* IIR can theoretically queue up two events. Be paranoid. */ 255 intel_uncore_write16(uncore, GEN2_IIR, 0xffff); 256 intel_uncore_posting_read16(uncore, GEN2_IIR); 257 intel_uncore_write16(uncore, GEN2_IIR, 0xffff); 258 intel_uncore_posting_read16(uncore, GEN2_IIR); 259 } 260 261 /* 262 * We should clear IMR at preinstall/uninstall, and just check at postinstall. 263 */ 264 static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg) 265 { 266 u32 val = intel_uncore_read(uncore, reg); 267 268 if (val == 0) 269 return; 270 271 drm_WARN(&uncore->i915->drm, 1, 272 "Interrupt register 0x%x is not zero: 0x%08x\n", 273 i915_mmio_reg_offset(reg), val); 274 intel_uncore_write(uncore, reg, 0xffffffff); 275 intel_uncore_posting_read(uncore, reg); 276 intel_uncore_write(uncore, reg, 0xffffffff); 277 intel_uncore_posting_read(uncore, reg); 278 } 279 280 static void gen2_assert_iir_is_zero(struct intel_uncore *uncore) 281 { 282 u16 val = intel_uncore_read16(uncore, GEN2_IIR); 283 284 if (val == 0) 285 return; 286 287 drm_WARN(&uncore->i915->drm, 1, 288 "Interrupt register 0x%x is not zero: 0x%08x\n", 289 i915_mmio_reg_offset(GEN2_IIR), val); 290 intel_uncore_write16(uncore, GEN2_IIR, 0xffff); 291 intel_uncore_posting_read16(uncore, GEN2_IIR); 292 intel_uncore_write16(uncore, GEN2_IIR, 0xffff); 293 intel_uncore_posting_read16(uncore, GEN2_IIR); 294 } 295 296 void gen3_irq_init(struct intel_uncore *uncore, 297 i915_reg_t imr, u32 imr_val, 298 i915_reg_t ier, u32 ier_val, 299 i915_reg_t iir) 300 { 301 gen3_assert_iir_is_zero(uncore, iir); 302 303 intel_uncore_write(uncore, ier, ier_val); 304 intel_uncore_write(uncore, imr, imr_val); 305 intel_uncore_posting_read(uncore, imr); 306 } 307 308 void gen2_irq_init(struct intel_uncore *uncore, 309 u32 imr_val, u32 ier_val) 310 { 311 gen2_assert_iir_is_zero(uncore); 312 313 intel_uncore_write16(uncore, GEN2_IER, ier_val); 314 intel_uncore_write16(uncore, GEN2_IMR, imr_val); 315 intel_uncore_posting_read16(uncore, GEN2_IMR); 316 } 317 318 /* For display hotplug interrupt */ 319 static inline void 320 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv, 321 u32 mask, 322 u32 bits) 323 { 324 u32 val; 325 326 lockdep_assert_held(&dev_priv->irq_lock); 327 drm_WARN_ON(&dev_priv->drm, bits & ~mask); 328 329 val = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_EN); 330 val &= ~mask; 331 val |= bits; 332 intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_EN, val); 333 } 334 335 /** 336 * i915_hotplug_interrupt_update - update hotplug interrupt enable 337 * @dev_priv: driver private 338 * @mask: bits to update 339 * @bits: bits to enable 340 * NOTE: the HPD enable bits are modified both inside and outside 341 * of an interrupt context. To avoid that read-modify-write cycles 342 * interfer, these bits are protected by a spinlock. Since this 343 * function is usually not called from a context where the lock is 344 * held already, this function acquires the lock itself. A non-locking 345 * version is also available. 346 */ 347 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, 348 u32 mask, 349 u32 bits) 350 { 351 spin_lock_irq(&dev_priv->irq_lock); 352 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits); 353 spin_unlock_irq(&dev_priv->irq_lock); 354 } 355 356 /** 357 * ilk_update_display_irq - update DEIMR 358 * @dev_priv: driver private 359 * @interrupt_mask: mask of interrupt bits to update 360 * @enabled_irq_mask: mask of interrupt bits to enable 361 */ 362 void ilk_update_display_irq(struct drm_i915_private *dev_priv, 363 u32 interrupt_mask, 364 u32 enabled_irq_mask) 365 { 366 u32 new_val; 367 368 lockdep_assert_held(&dev_priv->irq_lock); 369 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); 370 371 new_val = dev_priv->irq_mask; 372 new_val &= ~interrupt_mask; 373 new_val |= (~enabled_irq_mask & interrupt_mask); 374 375 if (new_val != dev_priv->irq_mask && 376 !drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) { 377 dev_priv->irq_mask = new_val; 378 intel_uncore_write(&dev_priv->uncore, DEIMR, dev_priv->irq_mask); 379 intel_uncore_posting_read(&dev_priv->uncore, DEIMR); 380 } 381 } 382 383 /** 384 * bdw_update_port_irq - update DE port interrupt 385 * @dev_priv: driver private 386 * @interrupt_mask: mask of interrupt bits to update 387 * @enabled_irq_mask: mask of interrupt bits to enable 388 */ 389 static void bdw_update_port_irq(struct drm_i915_private *dev_priv, 390 u32 interrupt_mask, 391 u32 enabled_irq_mask) 392 { 393 u32 new_val; 394 u32 old_val; 395 396 lockdep_assert_held(&dev_priv->irq_lock); 397 398 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); 399 400 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) 401 return; 402 403 old_val = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IMR); 404 405 new_val = old_val; 406 new_val &= ~interrupt_mask; 407 new_val |= (~enabled_irq_mask & interrupt_mask); 408 409 if (new_val != old_val) { 410 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IMR, new_val); 411 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PORT_IMR); 412 } 413 } 414 415 /** 416 * bdw_update_pipe_irq - update DE pipe interrupt 417 * @dev_priv: driver private 418 * @pipe: pipe whose interrupt to update 419 * @interrupt_mask: mask of interrupt bits to update 420 * @enabled_irq_mask: mask of interrupt bits to enable 421 */ 422 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, 423 enum pipe pipe, 424 u32 interrupt_mask, 425 u32 enabled_irq_mask) 426 { 427 u32 new_val; 428 429 lockdep_assert_held(&dev_priv->irq_lock); 430 431 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); 432 433 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) 434 return; 435 436 new_val = dev_priv->de_irq_mask[pipe]; 437 new_val &= ~interrupt_mask; 438 new_val |= (~enabled_irq_mask & interrupt_mask); 439 440 if (new_val != dev_priv->de_irq_mask[pipe]) { 441 dev_priv->de_irq_mask[pipe] = new_val; 442 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); 443 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe)); 444 } 445 } 446 447 /** 448 * ibx_display_interrupt_update - update SDEIMR 449 * @dev_priv: driver private 450 * @interrupt_mask: mask of interrupt bits to update 451 * @enabled_irq_mask: mask of interrupt bits to enable 452 */ 453 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, 454 u32 interrupt_mask, 455 u32 enabled_irq_mask) 456 { 457 u32 sdeimr = intel_uncore_read(&dev_priv->uncore, SDEIMR); 458 sdeimr &= ~interrupt_mask; 459 sdeimr |= (~enabled_irq_mask & interrupt_mask); 460 461 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); 462 463 lockdep_assert_held(&dev_priv->irq_lock); 464 465 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) 466 return; 467 468 intel_uncore_write(&dev_priv->uncore, SDEIMR, sdeimr); 469 intel_uncore_posting_read(&dev_priv->uncore, SDEIMR); 470 } 471 472 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv, 473 enum pipe pipe) 474 { 475 u32 status_mask = dev_priv->pipestat_irq_mask[pipe]; 476 u32 enable_mask = status_mask << 16; 477 478 lockdep_assert_held(&dev_priv->irq_lock); 479 480 if (DISPLAY_VER(dev_priv) < 5) 481 goto out; 482 483 /* 484 * On pipe A we don't support the PSR interrupt yet, 485 * on pipe B and C the same bit MBZ. 486 */ 487 if (drm_WARN_ON_ONCE(&dev_priv->drm, 488 status_mask & PIPE_A_PSR_STATUS_VLV)) 489 return 0; 490 /* 491 * On pipe B and C we don't support the PSR interrupt yet, on pipe 492 * A the same bit is for perf counters which we don't use either. 493 */ 494 if (drm_WARN_ON_ONCE(&dev_priv->drm, 495 status_mask & PIPE_B_PSR_STATUS_VLV)) 496 return 0; 497 498 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | 499 SPRITE0_FLIP_DONE_INT_EN_VLV | 500 SPRITE1_FLIP_DONE_INT_EN_VLV); 501 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) 502 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; 503 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) 504 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; 505 506 out: 507 drm_WARN_ONCE(&dev_priv->drm, 508 enable_mask & ~PIPESTAT_INT_ENABLE_MASK || 509 status_mask & ~PIPESTAT_INT_STATUS_MASK, 510 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", 511 pipe_name(pipe), enable_mask, status_mask); 512 513 return enable_mask; 514 } 515 516 void i915_enable_pipestat(struct drm_i915_private *dev_priv, 517 enum pipe pipe, u32 status_mask) 518 { 519 i915_reg_t reg = PIPESTAT(pipe); 520 u32 enable_mask; 521 522 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK, 523 "pipe %c: status_mask=0x%x\n", 524 pipe_name(pipe), status_mask); 525 526 lockdep_assert_held(&dev_priv->irq_lock); 527 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)); 528 529 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask) 530 return; 531 532 dev_priv->pipestat_irq_mask[pipe] |= status_mask; 533 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); 534 535 intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask); 536 intel_uncore_posting_read(&dev_priv->uncore, reg); 537 } 538 539 void i915_disable_pipestat(struct drm_i915_private *dev_priv, 540 enum pipe pipe, u32 status_mask) 541 { 542 i915_reg_t reg = PIPESTAT(pipe); 543 u32 enable_mask; 544 545 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK, 546 "pipe %c: status_mask=0x%x\n", 547 pipe_name(pipe), status_mask); 548 549 lockdep_assert_held(&dev_priv->irq_lock); 550 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)); 551 552 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0) 553 return; 554 555 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; 556 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); 557 558 intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask); 559 intel_uncore_posting_read(&dev_priv->uncore, reg); 560 } 561 562 static bool i915_has_asle(struct drm_i915_private *dev_priv) 563 { 564 if (!dev_priv->opregion.asle) 565 return false; 566 567 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 568 } 569 570 /** 571 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion 572 * @dev_priv: i915 device private 573 */ 574 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv) 575 { 576 if (!i915_has_asle(dev_priv)) 577 return; 578 579 spin_lock_irq(&dev_priv->irq_lock); 580 581 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); 582 if (DISPLAY_VER(dev_priv) >= 4) 583 i915_enable_pipestat(dev_priv, PIPE_A, 584 PIPE_LEGACY_BLC_EVENT_STATUS); 585 586 spin_unlock_irq(&dev_priv->irq_lock); 587 } 588 589 /* 590 * This timing diagram depicts the video signal in and 591 * around the vertical blanking period. 592 * 593 * Assumptions about the fictitious mode used in this example: 594 * vblank_start >= 3 595 * vsync_start = vblank_start + 1 596 * vsync_end = vblank_start + 2 597 * vtotal = vblank_start + 3 598 * 599 * start of vblank: 600 * latch double buffered registers 601 * increment frame counter (ctg+) 602 * generate start of vblank interrupt (gen4+) 603 * | 604 * | frame start: 605 * | generate frame start interrupt (aka. vblank interrupt) (gmch) 606 * | may be shifted forward 1-3 extra lines via PIPECONF 607 * | | 608 * | | start of vsync: 609 * | | generate vsync interrupt 610 * | | | 611 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx 612 * . \hs/ . \hs/ \hs/ \hs/ . \hs/ 613 * ----va---> <-----------------vb--------------------> <--------va------------- 614 * | | <----vs-----> | 615 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2) 616 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+) 617 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi) 618 * | | | 619 * last visible pixel first visible pixel 620 * | increment frame counter (gen3/4) 621 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4) 622 * 623 * x = horizontal active 624 * _ = horizontal blanking 625 * hs = horizontal sync 626 * va = vertical active 627 * vb = vertical blanking 628 * vs = vertical sync 629 * vbs = vblank_start (number) 630 * 631 * Summary: 632 * - most events happen at the start of horizontal sync 633 * - frame start happens at the start of horizontal blank, 1-4 lines 634 * (depending on PIPECONF settings) after the start of vblank 635 * - gen3/4 pixel and frame counter are synchronized with the start 636 * of horizontal active on the first line of vertical active 637 */ 638 639 /* Called from drm generic code, passed a 'crtc', which 640 * we use as a pipe index 641 */ 642 u32 i915_get_vblank_counter(struct drm_crtc *crtc) 643 { 644 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 645 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)]; 646 const struct drm_display_mode *mode = &vblank->hwmode; 647 enum pipe pipe = to_intel_crtc(crtc)->pipe; 648 i915_reg_t high_frame, low_frame; 649 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal; 650 unsigned long irqflags; 651 652 /* 653 * On i965gm TV output the frame counter only works up to 654 * the point when we enable the TV encoder. After that the 655 * frame counter ceases to work and reads zero. We need a 656 * vblank wait before enabling the TV encoder and so we 657 * have to enable vblank interrupts while the frame counter 658 * is still in a working state. However the core vblank code 659 * does not like us returning non-zero frame counter values 660 * when we've told it that we don't have a working frame 661 * counter. Thus we must stop non-zero values leaking out. 662 */ 663 if (!vblank->max_vblank_count) 664 return 0; 665 666 htotal = mode->crtc_htotal; 667 hsync_start = mode->crtc_hsync_start; 668 vbl_start = mode->crtc_vblank_start; 669 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 670 vbl_start = DIV_ROUND_UP(vbl_start, 2); 671 672 /* Convert to pixel count */ 673 vbl_start *= htotal; 674 675 /* Start of vblank event occurs at start of hsync */ 676 vbl_start -= htotal - hsync_start; 677 678 high_frame = PIPEFRAME(pipe); 679 low_frame = PIPEFRAMEPIXEL(pipe); 680 681 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 682 683 /* 684 * High & low register fields aren't synchronized, so make sure 685 * we get a low value that's stable across two reads of the high 686 * register. 687 */ 688 do { 689 high1 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK; 690 low = intel_de_read_fw(dev_priv, low_frame); 691 high2 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK; 692 } while (high1 != high2); 693 694 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 695 696 high1 >>= PIPE_FRAME_HIGH_SHIFT; 697 pixel = low & PIPE_PIXEL_MASK; 698 low >>= PIPE_FRAME_LOW_SHIFT; 699 700 /* 701 * The frame counter increments at beginning of active. 702 * Cook up a vblank counter by also checking the pixel 703 * counter against vblank start. 704 */ 705 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; 706 } 707 708 u32 g4x_get_vblank_counter(struct drm_crtc *crtc) 709 { 710 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 711 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)]; 712 enum pipe pipe = to_intel_crtc(crtc)->pipe; 713 714 if (!vblank->max_vblank_count) 715 return 0; 716 717 return intel_uncore_read(&dev_priv->uncore, PIPE_FRMCOUNT_G4X(pipe)); 718 } 719 720 static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc) 721 { 722 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 723 struct drm_vblank_crtc *vblank = 724 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; 725 const struct drm_display_mode *mode = &vblank->hwmode; 726 u32 htotal = mode->crtc_htotal; 727 u32 clock = mode->crtc_clock; 728 u32 scan_prev_time, scan_curr_time, scan_post_time; 729 730 /* 731 * To avoid the race condition where we might cross into the 732 * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR 733 * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR 734 * during the same frame. 735 */ 736 do { 737 /* 738 * This field provides read back of the display 739 * pipe frame time stamp. The time stamp value 740 * is sampled at every start of vertical blank. 741 */ 742 scan_prev_time = intel_de_read_fw(dev_priv, 743 PIPE_FRMTMSTMP(crtc->pipe)); 744 745 /* 746 * The TIMESTAMP_CTR register has the current 747 * time stamp value. 748 */ 749 scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR); 750 751 scan_post_time = intel_de_read_fw(dev_priv, 752 PIPE_FRMTMSTMP(crtc->pipe)); 753 } while (scan_post_time != scan_prev_time); 754 755 return div_u64(mul_u32_u32(scan_curr_time - scan_prev_time, 756 clock), 1000 * htotal); 757 } 758 759 /* 760 * On certain encoders on certain platforms, pipe 761 * scanline register will not work to get the scanline, 762 * since the timings are driven from the PORT or issues 763 * with scanline register updates. 764 * This function will use Framestamp and current 765 * timestamp registers to calculate the scanline. 766 */ 767 static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc) 768 { 769 struct drm_vblank_crtc *vblank = 770 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; 771 const struct drm_display_mode *mode = &vblank->hwmode; 772 u32 vblank_start = mode->crtc_vblank_start; 773 u32 vtotal = mode->crtc_vtotal; 774 u32 scanline; 775 776 scanline = intel_crtc_scanlines_since_frame_timestamp(crtc); 777 scanline = min(scanline, vtotal - 1); 778 scanline = (scanline + vblank_start) % vtotal; 779 780 return scanline; 781 } 782 783 /* 784 * intel_de_read_fw(), only for fast reads of display block, no need for 785 * forcewake etc. 786 */ 787 static int __intel_get_crtc_scanline(struct intel_crtc *crtc) 788 { 789 struct drm_device *dev = crtc->base.dev; 790 struct drm_i915_private *dev_priv = to_i915(dev); 791 const struct drm_display_mode *mode; 792 struct drm_vblank_crtc *vblank; 793 enum pipe pipe = crtc->pipe; 794 int position, vtotal; 795 796 if (!crtc->active) 797 return 0; 798 799 vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; 800 mode = &vblank->hwmode; 801 802 if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP) 803 return __intel_get_crtc_scanline_from_timestamp(crtc); 804 805 vtotal = mode->crtc_vtotal; 806 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 807 vtotal /= 2; 808 809 if (IS_DISPLAY_VER(dev_priv, 2)) 810 position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; 811 else 812 position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; 813 814 /* 815 * On HSW, the DSL reg (0x70000) appears to return 0 if we 816 * read it just before the start of vblank. So try it again 817 * so we don't accidentally end up spanning a vblank frame 818 * increment, causing the pipe_update_end() code to squak at us. 819 * 820 * The nature of this problem means we can't simply check the ISR 821 * bit and return the vblank start value; nor can we use the scanline 822 * debug register in the transcoder as it appears to have the same 823 * problem. We may need to extend this to include other platforms, 824 * but so far testing only shows the problem on HSW. 825 */ 826 if (HAS_DDI(dev_priv) && !position) { 827 int i, temp; 828 829 for (i = 0; i < 100; i++) { 830 udelay(1); 831 temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; 832 if (temp != position) { 833 position = temp; 834 break; 835 } 836 } 837 } 838 839 /* 840 * See update_scanline_offset() for the details on the 841 * scanline_offset adjustment. 842 */ 843 return (position + crtc->scanline_offset) % vtotal; 844 } 845 846 static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc, 847 bool in_vblank_irq, 848 int *vpos, int *hpos, 849 ktime_t *stime, ktime_t *etime, 850 const struct drm_display_mode *mode) 851 { 852 struct drm_device *dev = _crtc->dev; 853 struct drm_i915_private *dev_priv = to_i915(dev); 854 struct intel_crtc *crtc = to_intel_crtc(_crtc); 855 enum pipe pipe = crtc->pipe; 856 int position; 857 int vbl_start, vbl_end, hsync_start, htotal, vtotal; 858 unsigned long irqflags; 859 bool use_scanline_counter = DISPLAY_VER(dev_priv) >= 5 || 860 IS_G4X(dev_priv) || IS_DISPLAY_VER(dev_priv, 2) || 861 crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER; 862 863 if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) { 864 drm_dbg(&dev_priv->drm, 865 "trying to get scanoutpos for disabled " 866 "pipe %c\n", pipe_name(pipe)); 867 return false; 868 } 869 870 htotal = mode->crtc_htotal; 871 hsync_start = mode->crtc_hsync_start; 872 vtotal = mode->crtc_vtotal; 873 vbl_start = mode->crtc_vblank_start; 874 vbl_end = mode->crtc_vblank_end; 875 876 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 877 vbl_start = DIV_ROUND_UP(vbl_start, 2); 878 vbl_end /= 2; 879 vtotal /= 2; 880 } 881 882 /* 883 * Lock uncore.lock, as we will do multiple timing critical raw 884 * register reads, potentially with preemption disabled, so the 885 * following code must not block on uncore.lock. 886 */ 887 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 888 889 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 890 891 /* Get optional system timestamp before query. */ 892 if (stime) 893 *stime = ktime_get(); 894 895 if (crtc->mode_flags & I915_MODE_FLAG_VRR) { 896 int scanlines = intel_crtc_scanlines_since_frame_timestamp(crtc); 897 898 position = __intel_get_crtc_scanline(crtc); 899 900 /* 901 * Already exiting vblank? If so, shift our position 902 * so it looks like we're already apporaching the full 903 * vblank end. This should make the generated timestamp 904 * more or less match when the active portion will start. 905 */ 906 if (position >= vbl_start && scanlines < position) 907 position = min(crtc->vmax_vblank_start + scanlines, vtotal - 1); 908 } else if (use_scanline_counter) { 909 /* No obvious pixelcount register. Only query vertical 910 * scanout position from Display scan line register. 911 */ 912 position = __intel_get_crtc_scanline(crtc); 913 } else { 914 /* Have access to pixelcount since start of frame. 915 * We can split this into vertical and horizontal 916 * scanout position. 917 */ 918 position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; 919 920 /* convert to pixel counts */ 921 vbl_start *= htotal; 922 vbl_end *= htotal; 923 vtotal *= htotal; 924 925 /* 926 * In interlaced modes, the pixel counter counts all pixels, 927 * so one field will have htotal more pixels. In order to avoid 928 * the reported position from jumping backwards when the pixel 929 * counter is beyond the length of the shorter field, just 930 * clamp the position the length of the shorter field. This 931 * matches how the scanline counter based position works since 932 * the scanline counter doesn't count the two half lines. 933 */ 934 if (position >= vtotal) 935 position = vtotal - 1; 936 937 /* 938 * Start of vblank interrupt is triggered at start of hsync, 939 * just prior to the first active line of vblank. However we 940 * consider lines to start at the leading edge of horizontal 941 * active. So, should we get here before we've crossed into 942 * the horizontal active of the first line in vblank, we would 943 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that, 944 * always add htotal-hsync_start to the current pixel position. 945 */ 946 position = (position + htotal - hsync_start) % vtotal; 947 } 948 949 /* Get optional system timestamp after query. */ 950 if (etime) 951 *etime = ktime_get(); 952 953 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 954 955 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 956 957 /* 958 * While in vblank, position will be negative 959 * counting up towards 0 at vbl_end. And outside 960 * vblank, position will be positive counting 961 * up since vbl_end. 962 */ 963 if (position >= vbl_start) 964 position -= vbl_end; 965 else 966 position += vtotal - vbl_end; 967 968 if (use_scanline_counter) { 969 *vpos = position; 970 *hpos = 0; 971 } else { 972 *vpos = position / htotal; 973 *hpos = position - (*vpos * htotal); 974 } 975 976 return true; 977 } 978 979 bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error, 980 ktime_t *vblank_time, bool in_vblank_irq) 981 { 982 return drm_crtc_vblank_helper_get_vblank_timestamp_internal( 983 crtc, max_error, vblank_time, in_vblank_irq, 984 i915_get_crtc_scanoutpos); 985 } 986 987 int intel_get_crtc_scanline(struct intel_crtc *crtc) 988 { 989 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 990 unsigned long irqflags; 991 int position; 992 993 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 994 position = __intel_get_crtc_scanline(crtc); 995 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 996 997 return position; 998 } 999 1000 /** 1001 * ivb_parity_work - Workqueue called when a parity error interrupt 1002 * occurred. 1003 * @work: workqueue struct 1004 * 1005 * Doesn't actually do anything except notify userspace. As a consequence of 1006 * this event, userspace should try to remap the bad rows since statistically 1007 * it is likely the same row is more likely to go bad again. 1008 */ 1009 static void ivb_parity_work(struct work_struct *work) 1010 { 1011 struct drm_i915_private *dev_priv = 1012 container_of(work, typeof(*dev_priv), l3_parity.error_work); 1013 struct intel_gt *gt = &dev_priv->gt; 1014 u32 error_status, row, bank, subbank; 1015 char *parity_event[6]; 1016 u32 misccpctl; 1017 u8 slice = 0; 1018 1019 /* We must turn off DOP level clock gating to access the L3 registers. 1020 * In order to prevent a get/put style interface, acquire struct mutex 1021 * any time we access those registers. 1022 */ 1023 mutex_lock(&dev_priv->drm.struct_mutex); 1024 1025 /* If we've screwed up tracking, just let the interrupt fire again */ 1026 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice)) 1027 goto out; 1028 1029 misccpctl = intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL); 1030 intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); 1031 intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL); 1032 1033 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { 1034 i915_reg_t reg; 1035 1036 slice--; 1037 if (drm_WARN_ON_ONCE(&dev_priv->drm, 1038 slice >= NUM_L3_SLICES(dev_priv))) 1039 break; 1040 1041 dev_priv->l3_parity.which_slice &= ~(1<<slice); 1042 1043 reg = GEN7_L3CDERRST1(slice); 1044 1045 error_status = intel_uncore_read(&dev_priv->uncore, reg); 1046 row = GEN7_PARITY_ERROR_ROW(error_status); 1047 bank = GEN7_PARITY_ERROR_BANK(error_status); 1048 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); 1049 1050 intel_uncore_write(&dev_priv->uncore, reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); 1051 intel_uncore_posting_read(&dev_priv->uncore, reg); 1052 1053 parity_event[0] = I915_L3_PARITY_UEVENT "=1"; 1054 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); 1055 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); 1056 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); 1057 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); 1058 parity_event[5] = NULL; 1059 1060 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj, 1061 KOBJ_CHANGE, parity_event); 1062 1063 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", 1064 slice, row, bank, subbank); 1065 1066 kfree(parity_event[4]); 1067 kfree(parity_event[3]); 1068 kfree(parity_event[2]); 1069 kfree(parity_event[1]); 1070 } 1071 1072 intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl); 1073 1074 out: 1075 drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice); 1076 spin_lock_irq(>->irq_lock); 1077 gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv)); 1078 spin_unlock_irq(>->irq_lock); 1079 1080 mutex_unlock(&dev_priv->drm.struct_mutex); 1081 } 1082 1083 static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 1084 { 1085 switch (pin) { 1086 case HPD_PORT_TC1: 1087 case HPD_PORT_TC2: 1088 case HPD_PORT_TC3: 1089 case HPD_PORT_TC4: 1090 case HPD_PORT_TC5: 1091 case HPD_PORT_TC6: 1092 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(pin); 1093 default: 1094 return false; 1095 } 1096 } 1097 1098 static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 1099 { 1100 switch (pin) { 1101 case HPD_PORT_A: 1102 return val & PORTA_HOTPLUG_LONG_DETECT; 1103 case HPD_PORT_B: 1104 return val & PORTB_HOTPLUG_LONG_DETECT; 1105 case HPD_PORT_C: 1106 return val & PORTC_HOTPLUG_LONG_DETECT; 1107 default: 1108 return false; 1109 } 1110 } 1111 1112 static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 1113 { 1114 switch (pin) { 1115 case HPD_PORT_A: 1116 case HPD_PORT_B: 1117 case HPD_PORT_C: 1118 case HPD_PORT_D: 1119 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(pin); 1120 default: 1121 return false; 1122 } 1123 } 1124 1125 static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 1126 { 1127 switch (pin) { 1128 case HPD_PORT_TC1: 1129 case HPD_PORT_TC2: 1130 case HPD_PORT_TC3: 1131 case HPD_PORT_TC4: 1132 case HPD_PORT_TC5: 1133 case HPD_PORT_TC6: 1134 return val & ICP_TC_HPD_LONG_DETECT(pin); 1135 default: 1136 return false; 1137 } 1138 } 1139 1140 static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val) 1141 { 1142 switch (pin) { 1143 case HPD_PORT_E: 1144 return val & PORTE_HOTPLUG_LONG_DETECT; 1145 default: 1146 return false; 1147 } 1148 } 1149 1150 static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 1151 { 1152 switch (pin) { 1153 case HPD_PORT_A: 1154 return val & PORTA_HOTPLUG_LONG_DETECT; 1155 case HPD_PORT_B: 1156 return val & PORTB_HOTPLUG_LONG_DETECT; 1157 case HPD_PORT_C: 1158 return val & PORTC_HOTPLUG_LONG_DETECT; 1159 case HPD_PORT_D: 1160 return val & PORTD_HOTPLUG_LONG_DETECT; 1161 default: 1162 return false; 1163 } 1164 } 1165 1166 static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 1167 { 1168 switch (pin) { 1169 case HPD_PORT_A: 1170 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT; 1171 default: 1172 return false; 1173 } 1174 } 1175 1176 static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 1177 { 1178 switch (pin) { 1179 case HPD_PORT_B: 1180 return val & PORTB_HOTPLUG_LONG_DETECT; 1181 case HPD_PORT_C: 1182 return val & PORTC_HOTPLUG_LONG_DETECT; 1183 case HPD_PORT_D: 1184 return val & PORTD_HOTPLUG_LONG_DETECT; 1185 default: 1186 return false; 1187 } 1188 } 1189 1190 static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 1191 { 1192 switch (pin) { 1193 case HPD_PORT_B: 1194 return val & PORTB_HOTPLUG_INT_LONG_PULSE; 1195 case HPD_PORT_C: 1196 return val & PORTC_HOTPLUG_INT_LONG_PULSE; 1197 case HPD_PORT_D: 1198 return val & PORTD_HOTPLUG_INT_LONG_PULSE; 1199 default: 1200 return false; 1201 } 1202 } 1203 1204 /* 1205 * Get a bit mask of pins that have triggered, and which ones may be long. 1206 * This can be called multiple times with the same masks to accumulate 1207 * hotplug detection results from several registers. 1208 * 1209 * Note that the caller is expected to zero out the masks initially. 1210 */ 1211 static void intel_get_hpd_pins(struct drm_i915_private *dev_priv, 1212 u32 *pin_mask, u32 *long_mask, 1213 u32 hotplug_trigger, u32 dig_hotplug_reg, 1214 const u32 hpd[HPD_NUM_PINS], 1215 bool long_pulse_detect(enum hpd_pin pin, u32 val)) 1216 { 1217 enum hpd_pin pin; 1218 1219 BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS); 1220 1221 for_each_hpd_pin(pin) { 1222 if ((hpd[pin] & hotplug_trigger) == 0) 1223 continue; 1224 1225 *pin_mask |= BIT(pin); 1226 1227 if (long_pulse_detect(pin, dig_hotplug_reg)) 1228 *long_mask |= BIT(pin); 1229 } 1230 1231 drm_dbg(&dev_priv->drm, 1232 "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n", 1233 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask); 1234 1235 } 1236 1237 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv, 1238 const u32 hpd[HPD_NUM_PINS]) 1239 { 1240 struct intel_encoder *encoder; 1241 u32 enabled_irqs = 0; 1242 1243 for_each_intel_encoder(&dev_priv->drm, encoder) 1244 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) 1245 enabled_irqs |= hpd[encoder->hpd_pin]; 1246 1247 return enabled_irqs; 1248 } 1249 1250 static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv, 1251 const u32 hpd[HPD_NUM_PINS]) 1252 { 1253 struct intel_encoder *encoder; 1254 u32 hotplug_irqs = 0; 1255 1256 for_each_intel_encoder(&dev_priv->drm, encoder) 1257 hotplug_irqs |= hpd[encoder->hpd_pin]; 1258 1259 return hotplug_irqs; 1260 } 1261 1262 static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915, 1263 hotplug_enables_func hotplug_enables) 1264 { 1265 struct intel_encoder *encoder; 1266 u32 hotplug = 0; 1267 1268 for_each_intel_encoder(&i915->drm, encoder) 1269 hotplug |= hotplug_enables(i915, encoder->hpd_pin); 1270 1271 return hotplug; 1272 } 1273 1274 static void gmbus_irq_handler(struct drm_i915_private *dev_priv) 1275 { 1276 wake_up_all(&dev_priv->gmbus_wait_queue); 1277 } 1278 1279 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv) 1280 { 1281 wake_up_all(&dev_priv->gmbus_wait_queue); 1282 } 1283 1284 #if defined(CONFIG_DEBUG_FS) 1285 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, 1286 enum pipe pipe, 1287 u32 crc0, u32 crc1, 1288 u32 crc2, u32 crc3, 1289 u32 crc4) 1290 { 1291 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 1292 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc; 1293 u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 }; 1294 1295 trace_intel_pipe_crc(crtc, crcs); 1296 1297 spin_lock(&pipe_crc->lock); 1298 /* 1299 * For some not yet identified reason, the first CRC is 1300 * bonkers. So let's just wait for the next vblank and read 1301 * out the buggy result. 1302 * 1303 * On GEN8+ sometimes the second CRC is bonkers as well, so 1304 * don't trust that one either. 1305 */ 1306 if (pipe_crc->skipped <= 0 || 1307 (DISPLAY_VER(dev_priv) >= 8 && pipe_crc->skipped == 1)) { 1308 pipe_crc->skipped++; 1309 spin_unlock(&pipe_crc->lock); 1310 return; 1311 } 1312 spin_unlock(&pipe_crc->lock); 1313 1314 drm_crtc_add_crc_entry(&crtc->base, true, 1315 drm_crtc_accurate_vblank_count(&crtc->base), 1316 crcs); 1317 } 1318 #else 1319 static inline void 1320 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, 1321 enum pipe pipe, 1322 u32 crc0, u32 crc1, 1323 u32 crc2, u32 crc3, 1324 u32 crc4) {} 1325 #endif 1326 1327 static void flip_done_handler(struct drm_i915_private *i915, 1328 enum pipe pipe) 1329 { 1330 struct intel_crtc *crtc = intel_get_crtc_for_pipe(i915, pipe); 1331 struct drm_crtc_state *crtc_state = crtc->base.state; 1332 struct drm_pending_vblank_event *e = crtc_state->event; 1333 struct drm_device *dev = &i915->drm; 1334 unsigned long irqflags; 1335 1336 spin_lock_irqsave(&dev->event_lock, irqflags); 1337 1338 crtc_state->event = NULL; 1339 1340 drm_crtc_send_vblank_event(&crtc->base, e); 1341 1342 spin_unlock_irqrestore(&dev->event_lock, irqflags); 1343 } 1344 1345 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, 1346 enum pipe pipe) 1347 { 1348 display_pipe_crc_irq_handler(dev_priv, pipe, 1349 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), 1350 0, 0, 0, 0); 1351 } 1352 1353 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, 1354 enum pipe pipe) 1355 { 1356 display_pipe_crc_irq_handler(dev_priv, pipe, 1357 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), 1358 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)), 1359 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)), 1360 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)), 1361 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe))); 1362 } 1363 1364 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, 1365 enum pipe pipe) 1366 { 1367 u32 res1, res2; 1368 1369 if (DISPLAY_VER(dev_priv) >= 3) 1370 res1 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES1_I915(pipe)); 1371 else 1372 res1 = 0; 1373 1374 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) 1375 res2 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES2_G4X(pipe)); 1376 else 1377 res2 = 0; 1378 1379 display_pipe_crc_irq_handler(dev_priv, pipe, 1380 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RED(pipe)), 1381 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_GREEN(pipe)), 1382 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_BLUE(pipe)), 1383 res1, res2); 1384 } 1385 1386 static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv) 1387 { 1388 enum pipe pipe; 1389 1390 for_each_pipe(dev_priv, pipe) { 1391 intel_uncore_write(&dev_priv->uncore, PIPESTAT(pipe), 1392 PIPESTAT_INT_STATUS_MASK | 1393 PIPE_FIFO_UNDERRUN_STATUS); 1394 1395 dev_priv->pipestat_irq_mask[pipe] = 0; 1396 } 1397 } 1398 1399 static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv, 1400 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) 1401 { 1402 enum pipe pipe; 1403 1404 spin_lock(&dev_priv->irq_lock); 1405 1406 if (!dev_priv->display_irqs_enabled) { 1407 spin_unlock(&dev_priv->irq_lock); 1408 return; 1409 } 1410 1411 for_each_pipe(dev_priv, pipe) { 1412 i915_reg_t reg; 1413 u32 status_mask, enable_mask, iir_bit = 0; 1414 1415 /* 1416 * PIPESTAT bits get signalled even when the interrupt is 1417 * disabled with the mask bits, and some of the status bits do 1418 * not generate interrupts at all (like the underrun bit). Hence 1419 * we need to be careful that we only handle what we want to 1420 * handle. 1421 */ 1422 1423 /* fifo underruns are filterered in the underrun handler. */ 1424 status_mask = PIPE_FIFO_UNDERRUN_STATUS; 1425 1426 switch (pipe) { 1427 default: 1428 case PIPE_A: 1429 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; 1430 break; 1431 case PIPE_B: 1432 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; 1433 break; 1434 case PIPE_C: 1435 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; 1436 break; 1437 } 1438 if (iir & iir_bit) 1439 status_mask |= dev_priv->pipestat_irq_mask[pipe]; 1440 1441 if (!status_mask) 1442 continue; 1443 1444 reg = PIPESTAT(pipe); 1445 pipe_stats[pipe] = intel_uncore_read(&dev_priv->uncore, reg) & status_mask; 1446 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); 1447 1448 /* 1449 * Clear the PIPE*STAT regs before the IIR 1450 * 1451 * Toggle the enable bits to make sure we get an 1452 * edge in the ISR pipe event bit if we don't clear 1453 * all the enabled status bits. Otherwise the edge 1454 * triggered IIR on i965/g4x wouldn't notice that 1455 * an interrupt is still pending. 1456 */ 1457 if (pipe_stats[pipe]) { 1458 intel_uncore_write(&dev_priv->uncore, reg, pipe_stats[pipe]); 1459 intel_uncore_write(&dev_priv->uncore, reg, enable_mask); 1460 } 1461 } 1462 spin_unlock(&dev_priv->irq_lock); 1463 } 1464 1465 static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv, 1466 u16 iir, u32 pipe_stats[I915_MAX_PIPES]) 1467 { 1468 enum pipe pipe; 1469 1470 for_each_pipe(dev_priv, pipe) { 1471 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) 1472 intel_handle_vblank(dev_priv, pipe); 1473 1474 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 1475 i9xx_pipe_crc_irq_handler(dev_priv, pipe); 1476 1477 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 1478 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 1479 } 1480 } 1481 1482 static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv, 1483 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) 1484 { 1485 bool blc_event = false; 1486 enum pipe pipe; 1487 1488 for_each_pipe(dev_priv, pipe) { 1489 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) 1490 intel_handle_vblank(dev_priv, pipe); 1491 1492 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 1493 blc_event = true; 1494 1495 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 1496 i9xx_pipe_crc_irq_handler(dev_priv, pipe); 1497 1498 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 1499 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 1500 } 1501 1502 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 1503 intel_opregion_asle_intr(dev_priv); 1504 } 1505 1506 static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv, 1507 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) 1508 { 1509 bool blc_event = false; 1510 enum pipe pipe; 1511 1512 for_each_pipe(dev_priv, pipe) { 1513 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) 1514 intel_handle_vblank(dev_priv, pipe); 1515 1516 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 1517 blc_event = true; 1518 1519 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 1520 i9xx_pipe_crc_irq_handler(dev_priv, pipe); 1521 1522 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 1523 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 1524 } 1525 1526 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 1527 intel_opregion_asle_intr(dev_priv); 1528 1529 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) 1530 gmbus_irq_handler(dev_priv); 1531 } 1532 1533 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv, 1534 u32 pipe_stats[I915_MAX_PIPES]) 1535 { 1536 enum pipe pipe; 1537 1538 for_each_pipe(dev_priv, pipe) { 1539 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) 1540 intel_handle_vblank(dev_priv, pipe); 1541 1542 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) 1543 flip_done_handler(dev_priv, pipe); 1544 1545 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 1546 i9xx_pipe_crc_irq_handler(dev_priv, pipe); 1547 1548 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 1549 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 1550 } 1551 1552 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) 1553 gmbus_irq_handler(dev_priv); 1554 } 1555 1556 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv) 1557 { 1558 u32 hotplug_status = 0, hotplug_status_mask; 1559 int i; 1560 1561 if (IS_G4X(dev_priv) || 1562 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1563 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X | 1564 DP_AUX_CHANNEL_MASK_INT_STATUS_G4X; 1565 else 1566 hotplug_status_mask = HOTPLUG_INT_STATUS_I915; 1567 1568 /* 1569 * We absolutely have to clear all the pending interrupt 1570 * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port 1571 * interrupt bit won't have an edge, and the i965/g4x 1572 * edge triggered IIR will not notice that an interrupt 1573 * is still pending. We can't use PORT_HOTPLUG_EN to 1574 * guarantee the edge as the act of toggling the enable 1575 * bits can itself generate a new hotplug interrupt :( 1576 */ 1577 for (i = 0; i < 10; i++) { 1578 u32 tmp = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT) & hotplug_status_mask; 1579 1580 if (tmp == 0) 1581 return hotplug_status; 1582 1583 hotplug_status |= tmp; 1584 intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, hotplug_status); 1585 } 1586 1587 drm_WARN_ONCE(&dev_priv->drm, 1, 1588 "PORT_HOTPLUG_STAT did not clear (0x%08x)\n", 1589 intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT)); 1590 1591 return hotplug_status; 1592 } 1593 1594 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv, 1595 u32 hotplug_status) 1596 { 1597 u32 pin_mask = 0, long_mask = 0; 1598 u32 hotplug_trigger; 1599 1600 if (IS_G4X(dev_priv) || 1601 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1602 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; 1603 else 1604 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; 1605 1606 if (hotplug_trigger) { 1607 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 1608 hotplug_trigger, hotplug_trigger, 1609 dev_priv->hotplug.hpd, 1610 i9xx_port_hotplug_long_detect); 1611 1612 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); 1613 } 1614 1615 if ((IS_G4X(dev_priv) || 1616 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 1617 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) 1618 dp_aux_irq_handler(dev_priv); 1619 } 1620 1621 static irqreturn_t valleyview_irq_handler(int irq, void *arg) 1622 { 1623 struct drm_i915_private *dev_priv = arg; 1624 irqreturn_t ret = IRQ_NONE; 1625 1626 if (!intel_irqs_enabled(dev_priv)) 1627 return IRQ_NONE; 1628 1629 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 1630 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1631 1632 do { 1633 u32 iir, gt_iir, pm_iir; 1634 u32 pipe_stats[I915_MAX_PIPES] = {}; 1635 u32 hotplug_status = 0; 1636 u32 ier = 0; 1637 1638 gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR); 1639 pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR); 1640 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR); 1641 1642 if (gt_iir == 0 && pm_iir == 0 && iir == 0) 1643 break; 1644 1645 ret = IRQ_HANDLED; 1646 1647 /* 1648 * Theory on interrupt generation, based on empirical evidence: 1649 * 1650 * x = ((VLV_IIR & VLV_IER) || 1651 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) && 1652 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE))); 1653 * 1654 * A CPU interrupt will only be raised when 'x' has a 0->1 edge. 1655 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to 1656 * guarantee the CPU interrupt will be raised again even if we 1657 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR 1658 * bits this time around. 1659 */ 1660 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0); 1661 ier = intel_uncore_read(&dev_priv->uncore, VLV_IER); 1662 intel_uncore_write(&dev_priv->uncore, VLV_IER, 0); 1663 1664 if (gt_iir) 1665 intel_uncore_write(&dev_priv->uncore, GTIIR, gt_iir); 1666 if (pm_iir) 1667 intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir); 1668 1669 if (iir & I915_DISPLAY_PORT_INTERRUPT) 1670 hotplug_status = i9xx_hpd_irq_ack(dev_priv); 1671 1672 /* Call regardless, as some status bits might not be 1673 * signalled in iir */ 1674 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); 1675 1676 if (iir & (I915_LPE_PIPE_A_INTERRUPT | 1677 I915_LPE_PIPE_B_INTERRUPT)) 1678 intel_lpe_audio_irq_handler(dev_priv); 1679 1680 /* 1681 * VLV_IIR is single buffered, and reflects the level 1682 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. 1683 */ 1684 if (iir) 1685 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir); 1686 1687 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier); 1688 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); 1689 1690 if (gt_iir) 1691 gen6_gt_irq_handler(&dev_priv->gt, gt_iir); 1692 if (pm_iir) 1693 gen6_rps_irq_handler(&dev_priv->gt.rps, pm_iir); 1694 1695 if (hotplug_status) 1696 i9xx_hpd_irq_handler(dev_priv, hotplug_status); 1697 1698 valleyview_pipestat_irq_handler(dev_priv, pipe_stats); 1699 } while (0); 1700 1701 pmu_irq_stats(dev_priv, ret); 1702 1703 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1704 1705 return ret; 1706 } 1707 1708 static irqreturn_t cherryview_irq_handler(int irq, void *arg) 1709 { 1710 struct drm_i915_private *dev_priv = arg; 1711 irqreturn_t ret = IRQ_NONE; 1712 1713 if (!intel_irqs_enabled(dev_priv)) 1714 return IRQ_NONE; 1715 1716 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 1717 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1718 1719 do { 1720 u32 master_ctl, iir; 1721 u32 pipe_stats[I915_MAX_PIPES] = {}; 1722 u32 hotplug_status = 0; 1723 u32 ier = 0; 1724 1725 master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; 1726 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR); 1727 1728 if (master_ctl == 0 && iir == 0) 1729 break; 1730 1731 ret = IRQ_HANDLED; 1732 1733 /* 1734 * Theory on interrupt generation, based on empirical evidence: 1735 * 1736 * x = ((VLV_IIR & VLV_IER) || 1737 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) && 1738 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL))); 1739 * 1740 * A CPU interrupt will only be raised when 'x' has a 0->1 edge. 1741 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to 1742 * guarantee the CPU interrupt will be raised again even if we 1743 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL 1744 * bits this time around. 1745 */ 1746 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0); 1747 ier = intel_uncore_read(&dev_priv->uncore, VLV_IER); 1748 intel_uncore_write(&dev_priv->uncore, VLV_IER, 0); 1749 1750 gen8_gt_irq_handler(&dev_priv->gt, master_ctl); 1751 1752 if (iir & I915_DISPLAY_PORT_INTERRUPT) 1753 hotplug_status = i9xx_hpd_irq_ack(dev_priv); 1754 1755 /* Call regardless, as some status bits might not be 1756 * signalled in iir */ 1757 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); 1758 1759 if (iir & (I915_LPE_PIPE_A_INTERRUPT | 1760 I915_LPE_PIPE_B_INTERRUPT | 1761 I915_LPE_PIPE_C_INTERRUPT)) 1762 intel_lpe_audio_irq_handler(dev_priv); 1763 1764 /* 1765 * VLV_IIR is single buffered, and reflects the level 1766 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. 1767 */ 1768 if (iir) 1769 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir); 1770 1771 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier); 1772 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); 1773 1774 if (hotplug_status) 1775 i9xx_hpd_irq_handler(dev_priv, hotplug_status); 1776 1777 valleyview_pipestat_irq_handler(dev_priv, pipe_stats); 1778 } while (0); 1779 1780 pmu_irq_stats(dev_priv, ret); 1781 1782 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1783 1784 return ret; 1785 } 1786 1787 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv, 1788 u32 hotplug_trigger) 1789 { 1790 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; 1791 1792 /* 1793 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU 1794 * unless we touch the hotplug register, even if hotplug_trigger is 1795 * zero. Not acking leads to "The master control interrupt lied (SDE)!" 1796 * errors. 1797 */ 1798 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); 1799 if (!hotplug_trigger) { 1800 u32 mask = PORTA_HOTPLUG_STATUS_MASK | 1801 PORTD_HOTPLUG_STATUS_MASK | 1802 PORTC_HOTPLUG_STATUS_MASK | 1803 PORTB_HOTPLUG_STATUS_MASK; 1804 dig_hotplug_reg &= ~mask; 1805 } 1806 1807 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg); 1808 if (!hotplug_trigger) 1809 return; 1810 1811 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 1812 hotplug_trigger, dig_hotplug_reg, 1813 dev_priv->hotplug.pch_hpd, 1814 pch_port_hotplug_long_detect); 1815 1816 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); 1817 } 1818 1819 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) 1820 { 1821 enum pipe pipe; 1822 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; 1823 1824 ibx_hpd_irq_handler(dev_priv, hotplug_trigger); 1825 1826 if (pch_iir & SDE_AUDIO_POWER_MASK) { 1827 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> 1828 SDE_AUDIO_POWER_SHIFT); 1829 drm_dbg(&dev_priv->drm, "PCH audio power change on port %d\n", 1830 port_name(port)); 1831 } 1832 1833 if (pch_iir & SDE_AUX_MASK) 1834 dp_aux_irq_handler(dev_priv); 1835 1836 if (pch_iir & SDE_GMBUS) 1837 gmbus_irq_handler(dev_priv); 1838 1839 if (pch_iir & SDE_AUDIO_HDCP_MASK) 1840 drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n"); 1841 1842 if (pch_iir & SDE_AUDIO_TRANS_MASK) 1843 drm_dbg(&dev_priv->drm, "PCH transcoder audio interrupt\n"); 1844 1845 if (pch_iir & SDE_POISON) 1846 drm_err(&dev_priv->drm, "PCH poison interrupt\n"); 1847 1848 if (pch_iir & SDE_FDI_MASK) { 1849 for_each_pipe(dev_priv, pipe) 1850 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", 1851 pipe_name(pipe), 1852 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe))); 1853 } 1854 1855 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) 1856 drm_dbg(&dev_priv->drm, "PCH transcoder CRC done interrupt\n"); 1857 1858 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) 1859 drm_dbg(&dev_priv->drm, 1860 "PCH transcoder CRC error interrupt\n"); 1861 1862 if (pch_iir & SDE_TRANSA_FIFO_UNDER) 1863 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); 1864 1865 if (pch_iir & SDE_TRANSB_FIFO_UNDER) 1866 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); 1867 } 1868 1869 static void ivb_err_int_handler(struct drm_i915_private *dev_priv) 1870 { 1871 u32 err_int = intel_uncore_read(&dev_priv->uncore, GEN7_ERR_INT); 1872 enum pipe pipe; 1873 1874 if (err_int & ERR_INT_POISON) 1875 drm_err(&dev_priv->drm, "Poison interrupt\n"); 1876 1877 for_each_pipe(dev_priv, pipe) { 1878 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) 1879 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 1880 1881 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { 1882 if (IS_IVYBRIDGE(dev_priv)) 1883 ivb_pipe_crc_irq_handler(dev_priv, pipe); 1884 else 1885 hsw_pipe_crc_irq_handler(dev_priv, pipe); 1886 } 1887 } 1888 1889 intel_uncore_write(&dev_priv->uncore, GEN7_ERR_INT, err_int); 1890 } 1891 1892 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv) 1893 { 1894 u32 serr_int = intel_uncore_read(&dev_priv->uncore, SERR_INT); 1895 enum pipe pipe; 1896 1897 if (serr_int & SERR_INT_POISON) 1898 drm_err(&dev_priv->drm, "PCH poison interrupt\n"); 1899 1900 for_each_pipe(dev_priv, pipe) 1901 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe)) 1902 intel_pch_fifo_underrun_irq_handler(dev_priv, pipe); 1903 1904 intel_uncore_write(&dev_priv->uncore, SERR_INT, serr_int); 1905 } 1906 1907 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) 1908 { 1909 enum pipe pipe; 1910 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; 1911 1912 ibx_hpd_irq_handler(dev_priv, hotplug_trigger); 1913 1914 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { 1915 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> 1916 SDE_AUDIO_POWER_SHIFT_CPT); 1917 drm_dbg(&dev_priv->drm, "PCH audio power change on port %c\n", 1918 port_name(port)); 1919 } 1920 1921 if (pch_iir & SDE_AUX_MASK_CPT) 1922 dp_aux_irq_handler(dev_priv); 1923 1924 if (pch_iir & SDE_GMBUS_CPT) 1925 gmbus_irq_handler(dev_priv); 1926 1927 if (pch_iir & SDE_AUDIO_CP_REQ_CPT) 1928 drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n"); 1929 1930 if (pch_iir & SDE_AUDIO_CP_CHG_CPT) 1931 drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n"); 1932 1933 if (pch_iir & SDE_FDI_MASK_CPT) { 1934 for_each_pipe(dev_priv, pipe) 1935 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", 1936 pipe_name(pipe), 1937 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe))); 1938 } 1939 1940 if (pch_iir & SDE_ERROR_CPT) 1941 cpt_serr_int_handler(dev_priv); 1942 } 1943 1944 static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) 1945 { 1946 u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP; 1947 u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP; 1948 u32 pin_mask = 0, long_mask = 0; 1949 1950 if (ddi_hotplug_trigger) { 1951 u32 dig_hotplug_reg; 1952 1953 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_DDI); 1954 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_DDI, dig_hotplug_reg); 1955 1956 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 1957 ddi_hotplug_trigger, dig_hotplug_reg, 1958 dev_priv->hotplug.pch_hpd, 1959 icp_ddi_port_hotplug_long_detect); 1960 } 1961 1962 if (tc_hotplug_trigger) { 1963 u32 dig_hotplug_reg; 1964 1965 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_TC); 1966 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_TC, dig_hotplug_reg); 1967 1968 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 1969 tc_hotplug_trigger, dig_hotplug_reg, 1970 dev_priv->hotplug.pch_hpd, 1971 icp_tc_port_hotplug_long_detect); 1972 } 1973 1974 if (pin_mask) 1975 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); 1976 1977 if (pch_iir & SDE_GMBUS_ICP) 1978 gmbus_irq_handler(dev_priv); 1979 } 1980 1981 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) 1982 { 1983 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT & 1984 ~SDE_PORTE_HOTPLUG_SPT; 1985 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT; 1986 u32 pin_mask = 0, long_mask = 0; 1987 1988 if (hotplug_trigger) { 1989 u32 dig_hotplug_reg; 1990 1991 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); 1992 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg); 1993 1994 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 1995 hotplug_trigger, dig_hotplug_reg, 1996 dev_priv->hotplug.pch_hpd, 1997 spt_port_hotplug_long_detect); 1998 } 1999 2000 if (hotplug2_trigger) { 2001 u32 dig_hotplug_reg; 2002 2003 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG2); 2004 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG2, dig_hotplug_reg); 2005 2006 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 2007 hotplug2_trigger, dig_hotplug_reg, 2008 dev_priv->hotplug.pch_hpd, 2009 spt_port_hotplug2_long_detect); 2010 } 2011 2012 if (pin_mask) 2013 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); 2014 2015 if (pch_iir & SDE_GMBUS_CPT) 2016 gmbus_irq_handler(dev_priv); 2017 } 2018 2019 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, 2020 u32 hotplug_trigger) 2021 { 2022 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; 2023 2024 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL); 2025 intel_uncore_write(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg); 2026 2027 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 2028 hotplug_trigger, dig_hotplug_reg, 2029 dev_priv->hotplug.hpd, 2030 ilk_port_hotplug_long_detect); 2031 2032 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); 2033 } 2034 2035 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv, 2036 u32 de_iir) 2037 { 2038 enum pipe pipe; 2039 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG; 2040 2041 if (hotplug_trigger) 2042 ilk_hpd_irq_handler(dev_priv, hotplug_trigger); 2043 2044 if (de_iir & DE_AUX_CHANNEL_A) 2045 dp_aux_irq_handler(dev_priv); 2046 2047 if (de_iir & DE_GSE) 2048 intel_opregion_asle_intr(dev_priv); 2049 2050 if (de_iir & DE_POISON) 2051 drm_err(&dev_priv->drm, "Poison interrupt\n"); 2052 2053 for_each_pipe(dev_priv, pipe) { 2054 if (de_iir & DE_PIPE_VBLANK(pipe)) 2055 intel_handle_vblank(dev_priv, pipe); 2056 2057 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) 2058 flip_done_handler(dev_priv, pipe); 2059 2060 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) 2061 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 2062 2063 if (de_iir & DE_PIPE_CRC_DONE(pipe)) 2064 i9xx_pipe_crc_irq_handler(dev_priv, pipe); 2065 } 2066 2067 /* check event from PCH */ 2068 if (de_iir & DE_PCH_EVENT) { 2069 u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR); 2070 2071 if (HAS_PCH_CPT(dev_priv)) 2072 cpt_irq_handler(dev_priv, pch_iir); 2073 else 2074 ibx_irq_handler(dev_priv, pch_iir); 2075 2076 /* should clear PCH hotplug event before clear CPU irq */ 2077 intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir); 2078 } 2079 2080 if (IS_DISPLAY_VER(dev_priv, 5) && de_iir & DE_PCU_EVENT) 2081 gen5_rps_irq_handler(&dev_priv->gt.rps); 2082 } 2083 2084 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv, 2085 u32 de_iir) 2086 { 2087 enum pipe pipe; 2088 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB; 2089 2090 if (hotplug_trigger) 2091 ilk_hpd_irq_handler(dev_priv, hotplug_trigger); 2092 2093 if (de_iir & DE_ERR_INT_IVB) 2094 ivb_err_int_handler(dev_priv); 2095 2096 if (de_iir & DE_EDP_PSR_INT_HSW) { 2097 struct intel_encoder *encoder; 2098 2099 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2100 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2101 2102 u32 psr_iir = intel_uncore_read(&dev_priv->uncore, 2103 EDP_PSR_IIR); 2104 2105 intel_psr_irq_handler(intel_dp, psr_iir); 2106 intel_uncore_write(&dev_priv->uncore, 2107 EDP_PSR_IIR, psr_iir); 2108 break; 2109 } 2110 } 2111 2112 if (de_iir & DE_AUX_CHANNEL_A_IVB) 2113 dp_aux_irq_handler(dev_priv); 2114 2115 if (de_iir & DE_GSE_IVB) 2116 intel_opregion_asle_intr(dev_priv); 2117 2118 for_each_pipe(dev_priv, pipe) { 2119 if (de_iir & DE_PIPE_VBLANK_IVB(pipe)) 2120 intel_handle_vblank(dev_priv, pipe); 2121 2122 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) 2123 flip_done_handler(dev_priv, pipe); 2124 } 2125 2126 /* check event from PCH */ 2127 if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) { 2128 u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR); 2129 2130 cpt_irq_handler(dev_priv, pch_iir); 2131 2132 /* clear PCH hotplug event before clear CPU irq */ 2133 intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir); 2134 } 2135 } 2136 2137 /* 2138 * To handle irqs with the minimum potential races with fresh interrupts, we: 2139 * 1 - Disable Master Interrupt Control. 2140 * 2 - Find the source(s) of the interrupt. 2141 * 3 - Clear the Interrupt Identity bits (IIR). 2142 * 4 - Process the interrupt(s) that had bits set in the IIRs. 2143 * 5 - Re-enable Master Interrupt Control. 2144 */ 2145 static irqreturn_t ilk_irq_handler(int irq, void *arg) 2146 { 2147 struct drm_i915_private *i915 = arg; 2148 void __iomem * const regs = i915->uncore.regs; 2149 u32 de_iir, gt_iir, de_ier, sde_ier = 0; 2150 irqreturn_t ret = IRQ_NONE; 2151 2152 if (unlikely(!intel_irqs_enabled(i915))) 2153 return IRQ_NONE; 2154 2155 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 2156 disable_rpm_wakeref_asserts(&i915->runtime_pm); 2157 2158 /* disable master interrupt before clearing iir */ 2159 de_ier = raw_reg_read(regs, DEIER); 2160 raw_reg_write(regs, DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); 2161 2162 /* Disable south interrupts. We'll only write to SDEIIR once, so further 2163 * interrupts will will be stored on its back queue, and then we'll be 2164 * able to process them after we restore SDEIER (as soon as we restore 2165 * it, we'll get an interrupt if SDEIIR still has something to process 2166 * due to its back queue). */ 2167 if (!HAS_PCH_NOP(i915)) { 2168 sde_ier = raw_reg_read(regs, SDEIER); 2169 raw_reg_write(regs, SDEIER, 0); 2170 } 2171 2172 /* Find, clear, then process each source of interrupt */ 2173 2174 gt_iir = raw_reg_read(regs, GTIIR); 2175 if (gt_iir) { 2176 raw_reg_write(regs, GTIIR, gt_iir); 2177 if (INTEL_GEN(i915) >= 6) 2178 gen6_gt_irq_handler(&i915->gt, gt_iir); 2179 else 2180 gen5_gt_irq_handler(&i915->gt, gt_iir); 2181 ret = IRQ_HANDLED; 2182 } 2183 2184 de_iir = raw_reg_read(regs, DEIIR); 2185 if (de_iir) { 2186 raw_reg_write(regs, DEIIR, de_iir); 2187 if (DISPLAY_VER(i915) >= 7) 2188 ivb_display_irq_handler(i915, de_iir); 2189 else 2190 ilk_display_irq_handler(i915, de_iir); 2191 ret = IRQ_HANDLED; 2192 } 2193 2194 if (INTEL_GEN(i915) >= 6) { 2195 u32 pm_iir = raw_reg_read(regs, GEN6_PMIIR); 2196 if (pm_iir) { 2197 raw_reg_write(regs, GEN6_PMIIR, pm_iir); 2198 gen6_rps_irq_handler(&i915->gt.rps, pm_iir); 2199 ret = IRQ_HANDLED; 2200 } 2201 } 2202 2203 raw_reg_write(regs, DEIER, de_ier); 2204 if (sde_ier) 2205 raw_reg_write(regs, SDEIER, sde_ier); 2206 2207 pmu_irq_stats(i915, ret); 2208 2209 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 2210 enable_rpm_wakeref_asserts(&i915->runtime_pm); 2211 2212 return ret; 2213 } 2214 2215 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, 2216 u32 hotplug_trigger) 2217 { 2218 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; 2219 2220 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); 2221 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg); 2222 2223 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 2224 hotplug_trigger, dig_hotplug_reg, 2225 dev_priv->hotplug.hpd, 2226 bxt_port_hotplug_long_detect); 2227 2228 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); 2229 } 2230 2231 static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir) 2232 { 2233 u32 pin_mask = 0, long_mask = 0; 2234 u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK; 2235 u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK; 2236 2237 if (trigger_tc) { 2238 u32 dig_hotplug_reg; 2239 2240 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL); 2241 intel_uncore_write(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg); 2242 2243 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 2244 trigger_tc, dig_hotplug_reg, 2245 dev_priv->hotplug.hpd, 2246 gen11_port_hotplug_long_detect); 2247 } 2248 2249 if (trigger_tbt) { 2250 u32 dig_hotplug_reg; 2251 2252 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL); 2253 intel_uncore_write(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg); 2254 2255 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 2256 trigger_tbt, dig_hotplug_reg, 2257 dev_priv->hotplug.hpd, 2258 gen11_port_hotplug_long_detect); 2259 } 2260 2261 if (pin_mask) 2262 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); 2263 else 2264 drm_err(&dev_priv->drm, 2265 "Unexpected DE HPD interrupt 0x%08x\n", iir); 2266 } 2267 2268 static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv) 2269 { 2270 u32 mask; 2271 2272 if (DISPLAY_VER(dev_priv) >= 12) 2273 return TGL_DE_PORT_AUX_DDIA | 2274 TGL_DE_PORT_AUX_DDIB | 2275 TGL_DE_PORT_AUX_DDIC | 2276 TGL_DE_PORT_AUX_USBC1 | 2277 TGL_DE_PORT_AUX_USBC2 | 2278 TGL_DE_PORT_AUX_USBC3 | 2279 TGL_DE_PORT_AUX_USBC4 | 2280 TGL_DE_PORT_AUX_USBC5 | 2281 TGL_DE_PORT_AUX_USBC6; 2282 2283 2284 mask = GEN8_AUX_CHANNEL_A; 2285 if (DISPLAY_VER(dev_priv) >= 9) 2286 mask |= GEN9_AUX_CHANNEL_B | 2287 GEN9_AUX_CHANNEL_C | 2288 GEN9_AUX_CHANNEL_D; 2289 2290 if (IS_CNL_WITH_PORT_F(dev_priv) || IS_DISPLAY_VER(dev_priv, 11)) 2291 mask |= CNL_AUX_CHANNEL_F; 2292 2293 if (IS_DISPLAY_VER(dev_priv, 11)) 2294 mask |= ICL_AUX_CHANNEL_E; 2295 2296 return mask; 2297 } 2298 2299 static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv) 2300 { 2301 if (HAS_D12_PLANE_MINIMIZATION(dev_priv)) 2302 return RKL_DE_PIPE_IRQ_FAULT_ERRORS; 2303 else if (DISPLAY_VER(dev_priv) >= 11) 2304 return GEN11_DE_PIPE_IRQ_FAULT_ERRORS; 2305 else if (DISPLAY_VER(dev_priv) >= 9) 2306 return GEN9_DE_PIPE_IRQ_FAULT_ERRORS; 2307 else 2308 return GEN8_DE_PIPE_IRQ_FAULT_ERRORS; 2309 } 2310 2311 static void 2312 gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir) 2313 { 2314 bool found = false; 2315 2316 if (iir & GEN8_DE_MISC_GSE) { 2317 intel_opregion_asle_intr(dev_priv); 2318 found = true; 2319 } 2320 2321 if (iir & GEN8_DE_EDP_PSR) { 2322 struct intel_encoder *encoder; 2323 u32 psr_iir; 2324 i915_reg_t iir_reg; 2325 2326 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2327 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2328 2329 if (DISPLAY_VER(dev_priv) >= 12) 2330 iir_reg = TRANS_PSR_IIR(intel_dp->psr.transcoder); 2331 else 2332 iir_reg = EDP_PSR_IIR; 2333 2334 psr_iir = intel_uncore_read(&dev_priv->uncore, iir_reg); 2335 intel_uncore_write(&dev_priv->uncore, iir_reg, psr_iir); 2336 2337 if (psr_iir) 2338 found = true; 2339 2340 intel_psr_irq_handler(intel_dp, psr_iir); 2341 2342 /* prior GEN12 only have one EDP PSR */ 2343 if (DISPLAY_VER(dev_priv) < 12) 2344 break; 2345 } 2346 } 2347 2348 if (!found) 2349 drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n"); 2350 } 2351 2352 static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv, 2353 u32 te_trigger) 2354 { 2355 enum pipe pipe = INVALID_PIPE; 2356 enum transcoder dsi_trans; 2357 enum port port; 2358 u32 val, tmp; 2359 2360 /* 2361 * Incase of dual link, TE comes from DSI_1 2362 * this is to check if dual link is enabled 2363 */ 2364 val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0)); 2365 val &= PORT_SYNC_MODE_ENABLE; 2366 2367 /* 2368 * if dual link is enabled, then read DSI_0 2369 * transcoder registers 2370 */ 2371 port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ? 2372 PORT_A : PORT_B; 2373 dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1; 2374 2375 /* Check if DSI configured in command mode */ 2376 val = intel_uncore_read(&dev_priv->uncore, DSI_TRANS_FUNC_CONF(dsi_trans)); 2377 val = val & OP_MODE_MASK; 2378 2379 if (val != CMD_MODE_NO_GATE && val != CMD_MODE_TE_GATE) { 2380 drm_err(&dev_priv->drm, "DSI trancoder not configured in command mode\n"); 2381 return; 2382 } 2383 2384 /* Get PIPE for handling VBLANK event */ 2385 val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL(dsi_trans)); 2386 switch (val & TRANS_DDI_EDP_INPUT_MASK) { 2387 case TRANS_DDI_EDP_INPUT_A_ON: 2388 pipe = PIPE_A; 2389 break; 2390 case TRANS_DDI_EDP_INPUT_B_ONOFF: 2391 pipe = PIPE_B; 2392 break; 2393 case TRANS_DDI_EDP_INPUT_C_ONOFF: 2394 pipe = PIPE_C; 2395 break; 2396 default: 2397 drm_err(&dev_priv->drm, "Invalid PIPE\n"); 2398 return; 2399 } 2400 2401 intel_handle_vblank(dev_priv, pipe); 2402 2403 /* clear TE in dsi IIR */ 2404 port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A; 2405 tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_IDENT_REG(port)); 2406 intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp); 2407 } 2408 2409 static u32 gen8_de_pipe_flip_done_mask(struct drm_i915_private *i915) 2410 { 2411 if (DISPLAY_VER(i915) >= 9) 2412 return GEN9_PIPE_PLANE1_FLIP_DONE; 2413 else 2414 return GEN8_PIPE_PRIMARY_FLIP_DONE; 2415 } 2416 2417 static irqreturn_t 2418 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) 2419 { 2420 irqreturn_t ret = IRQ_NONE; 2421 u32 iir; 2422 enum pipe pipe; 2423 2424 if (master_ctl & GEN8_DE_MISC_IRQ) { 2425 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IIR); 2426 if (iir) { 2427 intel_uncore_write(&dev_priv->uncore, GEN8_DE_MISC_IIR, iir); 2428 ret = IRQ_HANDLED; 2429 gen8_de_misc_irq_handler(dev_priv, iir); 2430 } else { 2431 drm_err(&dev_priv->drm, 2432 "The master control interrupt lied (DE MISC)!\n"); 2433 } 2434 } 2435 2436 if (DISPLAY_VER(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) { 2437 iir = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IIR); 2438 if (iir) { 2439 intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IIR, iir); 2440 ret = IRQ_HANDLED; 2441 gen11_hpd_irq_handler(dev_priv, iir); 2442 } else { 2443 drm_err(&dev_priv->drm, 2444 "The master control interrupt lied, (DE HPD)!\n"); 2445 } 2446 } 2447 2448 if (master_ctl & GEN8_DE_PORT_IRQ) { 2449 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IIR); 2450 if (iir) { 2451 bool found = false; 2452 2453 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IIR, iir); 2454 ret = IRQ_HANDLED; 2455 2456 if (iir & gen8_de_port_aux_mask(dev_priv)) { 2457 dp_aux_irq_handler(dev_priv); 2458 found = true; 2459 } 2460 2461 if (IS_GEN9_LP(dev_priv)) { 2462 u32 hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK; 2463 2464 if (hotplug_trigger) { 2465 bxt_hpd_irq_handler(dev_priv, hotplug_trigger); 2466 found = true; 2467 } 2468 } else if (IS_BROADWELL(dev_priv)) { 2469 u32 hotplug_trigger = iir & BDW_DE_PORT_HOTPLUG_MASK; 2470 2471 if (hotplug_trigger) { 2472 ilk_hpd_irq_handler(dev_priv, hotplug_trigger); 2473 found = true; 2474 } 2475 } 2476 2477 if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) { 2478 gmbus_irq_handler(dev_priv); 2479 found = true; 2480 } 2481 2482 if (DISPLAY_VER(dev_priv) >= 11) { 2483 u32 te_trigger = iir & (DSI0_TE | DSI1_TE); 2484 2485 if (te_trigger) { 2486 gen11_dsi_te_interrupt_handler(dev_priv, te_trigger); 2487 found = true; 2488 } 2489 } 2490 2491 if (!found) 2492 drm_err(&dev_priv->drm, 2493 "Unexpected DE Port interrupt\n"); 2494 } 2495 else 2496 drm_err(&dev_priv->drm, 2497 "The master control interrupt lied (DE PORT)!\n"); 2498 } 2499 2500 for_each_pipe(dev_priv, pipe) { 2501 u32 fault_errors; 2502 2503 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) 2504 continue; 2505 2506 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe)); 2507 if (!iir) { 2508 drm_err(&dev_priv->drm, 2509 "The master control interrupt lied (DE PIPE)!\n"); 2510 continue; 2511 } 2512 2513 ret = IRQ_HANDLED; 2514 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir); 2515 2516 if (iir & GEN8_PIPE_VBLANK) 2517 intel_handle_vblank(dev_priv, pipe); 2518 2519 if (iir & gen8_de_pipe_flip_done_mask(dev_priv)) 2520 flip_done_handler(dev_priv, pipe); 2521 2522 if (iir & GEN8_PIPE_CDCLK_CRC_DONE) 2523 hsw_pipe_crc_irq_handler(dev_priv, pipe); 2524 2525 if (iir & GEN8_PIPE_FIFO_UNDERRUN) 2526 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 2527 2528 fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv); 2529 if (fault_errors) 2530 drm_err(&dev_priv->drm, 2531 "Fault errors on pipe %c: 0x%08x\n", 2532 pipe_name(pipe), 2533 fault_errors); 2534 } 2535 2536 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) && 2537 master_ctl & GEN8_DE_PCH_IRQ) { 2538 /* 2539 * FIXME(BDW): Assume for now that the new interrupt handling 2540 * scheme also closed the SDE interrupt handling race we've seen 2541 * on older pch-split platforms. But this needs testing. 2542 */ 2543 iir = intel_uncore_read(&dev_priv->uncore, SDEIIR); 2544 if (iir) { 2545 intel_uncore_write(&dev_priv->uncore, SDEIIR, iir); 2546 ret = IRQ_HANDLED; 2547 2548 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 2549 icp_irq_handler(dev_priv, iir); 2550 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT) 2551 spt_irq_handler(dev_priv, iir); 2552 else 2553 cpt_irq_handler(dev_priv, iir); 2554 } else { 2555 /* 2556 * Like on previous PCH there seems to be something 2557 * fishy going on with forwarding PCH interrupts. 2558 */ 2559 drm_dbg(&dev_priv->drm, 2560 "The master control interrupt lied (SDE)!\n"); 2561 } 2562 } 2563 2564 return ret; 2565 } 2566 2567 static inline u32 gen8_master_intr_disable(void __iomem * const regs) 2568 { 2569 raw_reg_write(regs, GEN8_MASTER_IRQ, 0); 2570 2571 /* 2572 * Now with master disabled, get a sample of level indications 2573 * for this interrupt. Indications will be cleared on related acks. 2574 * New indications can and will light up during processing, 2575 * and will generate new interrupt after enabling master. 2576 */ 2577 return raw_reg_read(regs, GEN8_MASTER_IRQ); 2578 } 2579 2580 static inline void gen8_master_intr_enable(void __iomem * const regs) 2581 { 2582 raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); 2583 } 2584 2585 static irqreturn_t gen8_irq_handler(int irq, void *arg) 2586 { 2587 struct drm_i915_private *dev_priv = arg; 2588 void __iomem * const regs = dev_priv->uncore.regs; 2589 u32 master_ctl; 2590 2591 if (!intel_irqs_enabled(dev_priv)) 2592 return IRQ_NONE; 2593 2594 master_ctl = gen8_master_intr_disable(regs); 2595 if (!master_ctl) { 2596 gen8_master_intr_enable(regs); 2597 return IRQ_NONE; 2598 } 2599 2600 /* Find, queue (onto bottom-halves), then clear each source */ 2601 gen8_gt_irq_handler(&dev_priv->gt, master_ctl); 2602 2603 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 2604 if (master_ctl & ~GEN8_GT_IRQS) { 2605 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 2606 gen8_de_irq_handler(dev_priv, master_ctl); 2607 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 2608 } 2609 2610 gen8_master_intr_enable(regs); 2611 2612 pmu_irq_stats(dev_priv, IRQ_HANDLED); 2613 2614 return IRQ_HANDLED; 2615 } 2616 2617 static u32 2618 gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32 master_ctl) 2619 { 2620 void __iomem * const regs = gt->uncore->regs; 2621 u32 iir; 2622 2623 if (!(master_ctl & GEN11_GU_MISC_IRQ)) 2624 return 0; 2625 2626 iir = raw_reg_read(regs, GEN11_GU_MISC_IIR); 2627 if (likely(iir)) 2628 raw_reg_write(regs, GEN11_GU_MISC_IIR, iir); 2629 2630 return iir; 2631 } 2632 2633 static void 2634 gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir) 2635 { 2636 if (iir & GEN11_GU_MISC_GSE) 2637 intel_opregion_asle_intr(gt->i915); 2638 } 2639 2640 static inline u32 gen11_master_intr_disable(void __iomem * const regs) 2641 { 2642 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0); 2643 2644 /* 2645 * Now with master disabled, get a sample of level indications 2646 * for this interrupt. Indications will be cleared on related acks. 2647 * New indications can and will light up during processing, 2648 * and will generate new interrupt after enabling master. 2649 */ 2650 return raw_reg_read(regs, GEN11_GFX_MSTR_IRQ); 2651 } 2652 2653 static inline void gen11_master_intr_enable(void __iomem * const regs) 2654 { 2655 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ); 2656 } 2657 2658 static void 2659 gen11_display_irq_handler(struct drm_i915_private *i915) 2660 { 2661 void __iomem * const regs = i915->uncore.regs; 2662 const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL); 2663 2664 disable_rpm_wakeref_asserts(&i915->runtime_pm); 2665 /* 2666 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ 2667 * for the display related bits. 2668 */ 2669 raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0); 2670 gen8_de_irq_handler(i915, disp_ctl); 2671 raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 2672 GEN11_DISPLAY_IRQ_ENABLE); 2673 2674 enable_rpm_wakeref_asserts(&i915->runtime_pm); 2675 } 2676 2677 static __always_inline irqreturn_t 2678 __gen11_irq_handler(struct drm_i915_private * const i915, 2679 u32 (*intr_disable)(void __iomem * const regs), 2680 void (*intr_enable)(void __iomem * const regs)) 2681 { 2682 void __iomem * const regs = i915->uncore.regs; 2683 struct intel_gt *gt = &i915->gt; 2684 u32 master_ctl; 2685 u32 gu_misc_iir; 2686 2687 if (!intel_irqs_enabled(i915)) 2688 return IRQ_NONE; 2689 2690 master_ctl = intr_disable(regs); 2691 if (!master_ctl) { 2692 intr_enable(regs); 2693 return IRQ_NONE; 2694 } 2695 2696 /* Find, queue (onto bottom-halves), then clear each source */ 2697 gen11_gt_irq_handler(gt, master_ctl); 2698 2699 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 2700 if (master_ctl & GEN11_DISPLAY_IRQ) 2701 gen11_display_irq_handler(i915); 2702 2703 gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl); 2704 2705 intr_enable(regs); 2706 2707 gen11_gu_misc_irq_handler(gt, gu_misc_iir); 2708 2709 pmu_irq_stats(i915, IRQ_HANDLED); 2710 2711 return IRQ_HANDLED; 2712 } 2713 2714 static irqreturn_t gen11_irq_handler(int irq, void *arg) 2715 { 2716 return __gen11_irq_handler(arg, 2717 gen11_master_intr_disable, 2718 gen11_master_intr_enable); 2719 } 2720 2721 static u32 dg1_master_intr_disable_and_ack(void __iomem * const regs) 2722 { 2723 u32 val; 2724 2725 /* First disable interrupts */ 2726 raw_reg_write(regs, DG1_MSTR_UNIT_INTR, 0); 2727 2728 /* Get the indication levels and ack the master unit */ 2729 val = raw_reg_read(regs, DG1_MSTR_UNIT_INTR); 2730 if (unlikely(!val)) 2731 return 0; 2732 2733 raw_reg_write(regs, DG1_MSTR_UNIT_INTR, val); 2734 2735 /* 2736 * Now with master disabled, get a sample of level indications 2737 * for this interrupt and ack them right away - we keep GEN11_MASTER_IRQ 2738 * out as this bit doesn't exist anymore for DG1 2739 */ 2740 val = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ) & ~GEN11_MASTER_IRQ; 2741 if (unlikely(!val)) 2742 return 0; 2743 2744 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, val); 2745 2746 return val; 2747 } 2748 2749 static inline void dg1_master_intr_enable(void __iomem * const regs) 2750 { 2751 raw_reg_write(regs, DG1_MSTR_UNIT_INTR, DG1_MSTR_IRQ); 2752 } 2753 2754 static irqreturn_t dg1_irq_handler(int irq, void *arg) 2755 { 2756 return __gen11_irq_handler(arg, 2757 dg1_master_intr_disable_and_ack, 2758 dg1_master_intr_enable); 2759 } 2760 2761 /* Called from drm generic code, passed 'crtc' which 2762 * we use as a pipe index 2763 */ 2764 int i8xx_enable_vblank(struct drm_crtc *crtc) 2765 { 2766 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 2767 enum pipe pipe = to_intel_crtc(crtc)->pipe; 2768 unsigned long irqflags; 2769 2770 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2771 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); 2772 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2773 2774 return 0; 2775 } 2776 2777 int i915gm_enable_vblank(struct drm_crtc *crtc) 2778 { 2779 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 2780 2781 /* 2782 * Vblank interrupts fail to wake the device up from C2+. 2783 * Disabling render clock gating during C-states avoids 2784 * the problem. There is a small power cost so we do this 2785 * only when vblank interrupts are actually enabled. 2786 */ 2787 if (dev_priv->vblank_enabled++ == 0) 2788 intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); 2789 2790 return i8xx_enable_vblank(crtc); 2791 } 2792 2793 int i965_enable_vblank(struct drm_crtc *crtc) 2794 { 2795 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 2796 enum pipe pipe = to_intel_crtc(crtc)->pipe; 2797 unsigned long irqflags; 2798 2799 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2800 i915_enable_pipestat(dev_priv, pipe, 2801 PIPE_START_VBLANK_INTERRUPT_STATUS); 2802 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2803 2804 return 0; 2805 } 2806 2807 int ilk_enable_vblank(struct drm_crtc *crtc) 2808 { 2809 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 2810 enum pipe pipe = to_intel_crtc(crtc)->pipe; 2811 unsigned long irqflags; 2812 u32 bit = DISPLAY_VER(dev_priv) >= 7 ? 2813 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); 2814 2815 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2816 ilk_enable_display_irq(dev_priv, bit); 2817 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2818 2819 /* Even though there is no DMC, frame counter can get stuck when 2820 * PSR is active as no frames are generated. 2821 */ 2822 if (HAS_PSR(dev_priv)) 2823 drm_crtc_vblank_restore(crtc); 2824 2825 return 0; 2826 } 2827 2828 static bool gen11_dsi_configure_te(struct intel_crtc *intel_crtc, 2829 bool enable) 2830 { 2831 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); 2832 enum port port; 2833 u32 tmp; 2834 2835 if (!(intel_crtc->mode_flags & 2836 (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0))) 2837 return false; 2838 2839 /* for dual link cases we consider TE from slave */ 2840 if (intel_crtc->mode_flags & I915_MODE_FLAG_DSI_USE_TE1) 2841 port = PORT_B; 2842 else 2843 port = PORT_A; 2844 2845 tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_MASK_REG(port)); 2846 if (enable) 2847 tmp &= ~DSI_TE_EVENT; 2848 else 2849 tmp |= DSI_TE_EVENT; 2850 2851 intel_uncore_write(&dev_priv->uncore, DSI_INTR_MASK_REG(port), tmp); 2852 2853 tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_IDENT_REG(port)); 2854 intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp); 2855 2856 return true; 2857 } 2858 2859 int bdw_enable_vblank(struct drm_crtc *crtc) 2860 { 2861 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 2862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2863 enum pipe pipe = intel_crtc->pipe; 2864 unsigned long irqflags; 2865 2866 if (gen11_dsi_configure_te(intel_crtc, true)) 2867 return 0; 2868 2869 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2870 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); 2871 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2872 2873 /* Even if there is no DMC, frame counter can get stuck when 2874 * PSR is active as no frames are generated, so check only for PSR. 2875 */ 2876 if (HAS_PSR(dev_priv)) 2877 drm_crtc_vblank_restore(crtc); 2878 2879 return 0; 2880 } 2881 2882 /* Called from drm generic code, passed 'crtc' which 2883 * we use as a pipe index 2884 */ 2885 void i8xx_disable_vblank(struct drm_crtc *crtc) 2886 { 2887 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 2888 enum pipe pipe = to_intel_crtc(crtc)->pipe; 2889 unsigned long irqflags; 2890 2891 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2892 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); 2893 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2894 } 2895 2896 void i915gm_disable_vblank(struct drm_crtc *crtc) 2897 { 2898 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 2899 2900 i8xx_disable_vblank(crtc); 2901 2902 if (--dev_priv->vblank_enabled == 0) 2903 intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); 2904 } 2905 2906 void i965_disable_vblank(struct drm_crtc *crtc) 2907 { 2908 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 2909 enum pipe pipe = to_intel_crtc(crtc)->pipe; 2910 unsigned long irqflags; 2911 2912 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2913 i915_disable_pipestat(dev_priv, pipe, 2914 PIPE_START_VBLANK_INTERRUPT_STATUS); 2915 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2916 } 2917 2918 void ilk_disable_vblank(struct drm_crtc *crtc) 2919 { 2920 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 2921 enum pipe pipe = to_intel_crtc(crtc)->pipe; 2922 unsigned long irqflags; 2923 u32 bit = DISPLAY_VER(dev_priv) >= 7 ? 2924 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); 2925 2926 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2927 ilk_disable_display_irq(dev_priv, bit); 2928 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2929 } 2930 2931 void bdw_disable_vblank(struct drm_crtc *crtc) 2932 { 2933 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 2934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2935 enum pipe pipe = intel_crtc->pipe; 2936 unsigned long irqflags; 2937 2938 if (gen11_dsi_configure_te(intel_crtc, false)) 2939 return; 2940 2941 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2942 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); 2943 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2944 } 2945 2946 static void ibx_irq_reset(struct drm_i915_private *dev_priv) 2947 { 2948 struct intel_uncore *uncore = &dev_priv->uncore; 2949 2950 if (HAS_PCH_NOP(dev_priv)) 2951 return; 2952 2953 GEN3_IRQ_RESET(uncore, SDE); 2954 2955 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) 2956 intel_uncore_write(&dev_priv->uncore, SERR_INT, 0xffffffff); 2957 } 2958 2959 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) 2960 { 2961 struct intel_uncore *uncore = &dev_priv->uncore; 2962 2963 if (IS_CHERRYVIEW(dev_priv)) 2964 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV); 2965 else 2966 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK); 2967 2968 i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0); 2969 intel_uncore_write(uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT)); 2970 2971 i9xx_pipestat_irq_reset(dev_priv); 2972 2973 GEN3_IRQ_RESET(uncore, VLV_); 2974 dev_priv->irq_mask = ~0u; 2975 } 2976 2977 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) 2978 { 2979 struct intel_uncore *uncore = &dev_priv->uncore; 2980 2981 u32 pipestat_mask; 2982 u32 enable_mask; 2983 enum pipe pipe; 2984 2985 pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS; 2986 2987 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); 2988 for_each_pipe(dev_priv, pipe) 2989 i915_enable_pipestat(dev_priv, pipe, pipestat_mask); 2990 2991 enable_mask = I915_DISPLAY_PORT_INTERRUPT | 2992 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 2993 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 2994 I915_LPE_PIPE_A_INTERRUPT | 2995 I915_LPE_PIPE_B_INTERRUPT; 2996 2997 if (IS_CHERRYVIEW(dev_priv)) 2998 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT | 2999 I915_LPE_PIPE_C_INTERRUPT; 3000 3001 drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u); 3002 3003 dev_priv->irq_mask = ~enable_mask; 3004 3005 GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask); 3006 } 3007 3008 /* drm_dma.h hooks 3009 */ 3010 static void ilk_irq_reset(struct drm_i915_private *dev_priv) 3011 { 3012 struct intel_uncore *uncore = &dev_priv->uncore; 3013 3014 GEN3_IRQ_RESET(uncore, DE); 3015 dev_priv->irq_mask = ~0u; 3016 3017 if (IS_GEN(dev_priv, 7)) 3018 intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff); 3019 3020 if (IS_HASWELL(dev_priv)) { 3021 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff); 3022 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff); 3023 } 3024 3025 gen5_gt_irq_reset(&dev_priv->gt); 3026 3027 ibx_irq_reset(dev_priv); 3028 } 3029 3030 static void valleyview_irq_reset(struct drm_i915_private *dev_priv) 3031 { 3032 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0); 3033 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER); 3034 3035 gen5_gt_irq_reset(&dev_priv->gt); 3036 3037 spin_lock_irq(&dev_priv->irq_lock); 3038 if (dev_priv->display_irqs_enabled) 3039 vlv_display_irq_reset(dev_priv); 3040 spin_unlock_irq(&dev_priv->irq_lock); 3041 } 3042 3043 static void cnp_display_clock_wa(struct drm_i915_private *dev_priv) 3044 { 3045 struct intel_uncore *uncore = &dev_priv->uncore; 3046 3047 /* 3048 * Wa_14010685332:cnp/cmp,tgp,adp 3049 * TODO: Clarify which platforms this applies to 3050 * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as 3051 * on earlier platforms and whether the workaround is also needed for runtime suspend/resume 3052 */ 3053 if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP || 3054 (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) { 3055 intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 3056 SBCLK_RUN_REFCLK_DIS); 3057 intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0); 3058 } 3059 } 3060 3061 static void gen8_irq_reset(struct drm_i915_private *dev_priv) 3062 { 3063 struct intel_uncore *uncore = &dev_priv->uncore; 3064 enum pipe pipe; 3065 3066 gen8_master_intr_disable(dev_priv->uncore.regs); 3067 3068 gen8_gt_irq_reset(&dev_priv->gt); 3069 3070 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff); 3071 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff); 3072 3073 for_each_pipe(dev_priv, pipe) 3074 if (intel_display_power_is_enabled(dev_priv, 3075 POWER_DOMAIN_PIPE(pipe))) 3076 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); 3077 3078 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_); 3079 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_); 3080 GEN3_IRQ_RESET(uncore, GEN8_PCU_); 3081 3082 if (HAS_PCH_SPLIT(dev_priv)) 3083 ibx_irq_reset(dev_priv); 3084 3085 cnp_display_clock_wa(dev_priv); 3086 } 3087 3088 static void gen11_display_irq_reset(struct drm_i915_private *dev_priv) 3089 { 3090 struct intel_uncore *uncore = &dev_priv->uncore; 3091 enum pipe pipe; 3092 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3093 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3094 3095 intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0); 3096 3097 if (DISPLAY_VER(dev_priv) >= 12) { 3098 enum transcoder trans; 3099 3100 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) { 3101 enum intel_display_power_domain domain; 3102 3103 domain = POWER_DOMAIN_TRANSCODER(trans); 3104 if (!intel_display_power_is_enabled(dev_priv, domain)) 3105 continue; 3106 3107 intel_uncore_write(uncore, TRANS_PSR_IMR(trans), 0xffffffff); 3108 intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff); 3109 } 3110 } else { 3111 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff); 3112 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff); 3113 } 3114 3115 for_each_pipe(dev_priv, pipe) 3116 if (intel_display_power_is_enabled(dev_priv, 3117 POWER_DOMAIN_PIPE(pipe))) 3118 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); 3119 3120 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_); 3121 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_); 3122 GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_); 3123 3124 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 3125 GEN3_IRQ_RESET(uncore, SDE); 3126 3127 cnp_display_clock_wa(dev_priv); 3128 } 3129 3130 static void gen11_irq_reset(struct drm_i915_private *dev_priv) 3131 { 3132 struct intel_uncore *uncore = &dev_priv->uncore; 3133 3134 if (HAS_MASTER_UNIT_IRQ(dev_priv)) 3135 dg1_master_intr_disable_and_ack(dev_priv->uncore.regs); 3136 else 3137 gen11_master_intr_disable(dev_priv->uncore.regs); 3138 3139 gen11_gt_irq_reset(&dev_priv->gt); 3140 gen11_display_irq_reset(dev_priv); 3141 3142 GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_); 3143 GEN3_IRQ_RESET(uncore, GEN8_PCU_); 3144 } 3145 3146 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, 3147 u8 pipe_mask) 3148 { 3149 struct intel_uncore *uncore = &dev_priv->uncore; 3150 u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN | 3151 gen8_de_pipe_flip_done_mask(dev_priv); 3152 enum pipe pipe; 3153 3154 spin_lock_irq(&dev_priv->irq_lock); 3155 3156 if (!intel_irqs_enabled(dev_priv)) { 3157 spin_unlock_irq(&dev_priv->irq_lock); 3158 return; 3159 } 3160 3161 for_each_pipe_masked(dev_priv, pipe, pipe_mask) 3162 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe, 3163 dev_priv->de_irq_mask[pipe], 3164 ~dev_priv->de_irq_mask[pipe] | extra_ier); 3165 3166 spin_unlock_irq(&dev_priv->irq_lock); 3167 } 3168 3169 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, 3170 u8 pipe_mask) 3171 { 3172 struct intel_uncore *uncore = &dev_priv->uncore; 3173 enum pipe pipe; 3174 3175 spin_lock_irq(&dev_priv->irq_lock); 3176 3177 if (!intel_irqs_enabled(dev_priv)) { 3178 spin_unlock_irq(&dev_priv->irq_lock); 3179 return; 3180 } 3181 3182 for_each_pipe_masked(dev_priv, pipe, pipe_mask) 3183 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); 3184 3185 spin_unlock_irq(&dev_priv->irq_lock); 3186 3187 /* make sure we're done processing display irqs */ 3188 intel_synchronize_irq(dev_priv); 3189 } 3190 3191 static void cherryview_irq_reset(struct drm_i915_private *dev_priv) 3192 { 3193 struct intel_uncore *uncore = &dev_priv->uncore; 3194 3195 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0); 3196 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ); 3197 3198 gen8_gt_irq_reset(&dev_priv->gt); 3199 3200 GEN3_IRQ_RESET(uncore, GEN8_PCU_); 3201 3202 spin_lock_irq(&dev_priv->irq_lock); 3203 if (dev_priv->display_irqs_enabled) 3204 vlv_display_irq_reset(dev_priv); 3205 spin_unlock_irq(&dev_priv->irq_lock); 3206 } 3207 3208 static u32 ibx_hotplug_enables(struct drm_i915_private *i915, 3209 enum hpd_pin pin) 3210 { 3211 switch (pin) { 3212 case HPD_PORT_A: 3213 /* 3214 * When CPU and PCH are on the same package, port A 3215 * HPD must be enabled in both north and south. 3216 */ 3217 return HAS_PCH_LPT_LP(i915) ? 3218 PORTA_HOTPLUG_ENABLE : 0; 3219 case HPD_PORT_B: 3220 return PORTB_HOTPLUG_ENABLE | 3221 PORTB_PULSE_DURATION_2ms; 3222 case HPD_PORT_C: 3223 return PORTC_HOTPLUG_ENABLE | 3224 PORTC_PULSE_DURATION_2ms; 3225 case HPD_PORT_D: 3226 return PORTD_HOTPLUG_ENABLE | 3227 PORTD_PULSE_DURATION_2ms; 3228 default: 3229 return 0; 3230 } 3231 } 3232 3233 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv) 3234 { 3235 u32 hotplug; 3236 3237 /* 3238 * Enable digital hotplug on the PCH, and configure the DP short pulse 3239 * duration to 2ms (which is the minimum in the Display Port spec). 3240 * The pulse duration bits are reserved on LPT+. 3241 */ 3242 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); 3243 hotplug &= ~(PORTA_HOTPLUG_ENABLE | 3244 PORTB_HOTPLUG_ENABLE | 3245 PORTC_HOTPLUG_ENABLE | 3246 PORTD_HOTPLUG_ENABLE | 3247 PORTB_PULSE_DURATION_MASK | 3248 PORTC_PULSE_DURATION_MASK | 3249 PORTD_PULSE_DURATION_MASK); 3250 hotplug |= intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables); 3251 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug); 3252 } 3253 3254 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv) 3255 { 3256 u32 hotplug_irqs, enabled_irqs; 3257 3258 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd); 3259 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd); 3260 3261 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); 3262 3263 ibx_hpd_detection_setup(dev_priv); 3264 } 3265 3266 static u32 icp_ddi_hotplug_enables(struct drm_i915_private *i915, 3267 enum hpd_pin pin) 3268 { 3269 switch (pin) { 3270 case HPD_PORT_A: 3271 case HPD_PORT_B: 3272 case HPD_PORT_C: 3273 case HPD_PORT_D: 3274 return SHOTPLUG_CTL_DDI_HPD_ENABLE(pin); 3275 default: 3276 return 0; 3277 } 3278 } 3279 3280 static u32 icp_tc_hotplug_enables(struct drm_i915_private *i915, 3281 enum hpd_pin pin) 3282 { 3283 switch (pin) { 3284 case HPD_PORT_TC1: 3285 case HPD_PORT_TC2: 3286 case HPD_PORT_TC3: 3287 case HPD_PORT_TC4: 3288 case HPD_PORT_TC5: 3289 case HPD_PORT_TC6: 3290 return ICP_TC_HPD_ENABLE(pin); 3291 default: 3292 return 0; 3293 } 3294 } 3295 3296 static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv) 3297 { 3298 u32 hotplug; 3299 3300 hotplug = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_DDI); 3301 hotplug &= ~(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A) | 3302 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | 3303 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) | 3304 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_D)); 3305 hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_ddi_hotplug_enables); 3306 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_DDI, hotplug); 3307 } 3308 3309 static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv) 3310 { 3311 u32 hotplug; 3312 3313 hotplug = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_TC); 3314 hotplug &= ~(ICP_TC_HPD_ENABLE(HPD_PORT_TC1) | 3315 ICP_TC_HPD_ENABLE(HPD_PORT_TC2) | 3316 ICP_TC_HPD_ENABLE(HPD_PORT_TC3) | 3317 ICP_TC_HPD_ENABLE(HPD_PORT_TC4) | 3318 ICP_TC_HPD_ENABLE(HPD_PORT_TC5) | 3319 ICP_TC_HPD_ENABLE(HPD_PORT_TC6)); 3320 hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_tc_hotplug_enables); 3321 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_TC, hotplug); 3322 } 3323 3324 static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv) 3325 { 3326 u32 hotplug_irqs, enabled_irqs; 3327 3328 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd); 3329 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd); 3330 3331 if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP) 3332 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); 3333 3334 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); 3335 3336 icp_ddi_hpd_detection_setup(dev_priv); 3337 icp_tc_hpd_detection_setup(dev_priv); 3338 } 3339 3340 static u32 gen11_hotplug_enables(struct drm_i915_private *i915, 3341 enum hpd_pin pin) 3342 { 3343 switch (pin) { 3344 case HPD_PORT_TC1: 3345 case HPD_PORT_TC2: 3346 case HPD_PORT_TC3: 3347 case HPD_PORT_TC4: 3348 case HPD_PORT_TC5: 3349 case HPD_PORT_TC6: 3350 return GEN11_HOTPLUG_CTL_ENABLE(pin); 3351 default: 3352 return 0; 3353 } 3354 } 3355 3356 static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv) 3357 { 3358 u32 val; 3359 3360 val = intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN1); 3361 val |= (INVERT_DDIA_HPD | 3362 INVERT_DDIB_HPD | 3363 INVERT_DDIC_HPD | 3364 INVERT_DDID_HPD); 3365 intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN1, val); 3366 3367 icp_hpd_irq_setup(dev_priv); 3368 } 3369 3370 static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv) 3371 { 3372 u32 hotplug; 3373 3374 hotplug = intel_uncore_read(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL); 3375 hotplug &= ~(GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) | 3376 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) | 3377 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) | 3378 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) | 3379 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) | 3380 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6)); 3381 hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables); 3382 intel_uncore_write(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, hotplug); 3383 } 3384 3385 static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv) 3386 { 3387 u32 hotplug; 3388 3389 hotplug = intel_uncore_read(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL); 3390 hotplug &= ~(GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) | 3391 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) | 3392 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) | 3393 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) | 3394 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) | 3395 GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6)); 3396 hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables); 3397 intel_uncore_write(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, hotplug); 3398 } 3399 3400 static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv) 3401 { 3402 u32 hotplug_irqs, enabled_irqs; 3403 u32 val; 3404 3405 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd); 3406 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd); 3407 3408 val = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IMR); 3409 val &= ~hotplug_irqs; 3410 val |= ~enabled_irqs & hotplug_irqs; 3411 intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IMR, val); 3412 intel_uncore_posting_read(&dev_priv->uncore, GEN11_DE_HPD_IMR); 3413 3414 gen11_tc_hpd_detection_setup(dev_priv); 3415 gen11_tbt_hpd_detection_setup(dev_priv); 3416 3417 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 3418 icp_hpd_irq_setup(dev_priv); 3419 } 3420 3421 static u32 spt_hotplug_enables(struct drm_i915_private *i915, 3422 enum hpd_pin pin) 3423 { 3424 switch (pin) { 3425 case HPD_PORT_A: 3426 return PORTA_HOTPLUG_ENABLE; 3427 case HPD_PORT_B: 3428 return PORTB_HOTPLUG_ENABLE; 3429 case HPD_PORT_C: 3430 return PORTC_HOTPLUG_ENABLE; 3431 case HPD_PORT_D: 3432 return PORTD_HOTPLUG_ENABLE; 3433 default: 3434 return 0; 3435 } 3436 } 3437 3438 static u32 spt_hotplug2_enables(struct drm_i915_private *i915, 3439 enum hpd_pin pin) 3440 { 3441 switch (pin) { 3442 case HPD_PORT_E: 3443 return PORTE_HOTPLUG_ENABLE; 3444 default: 3445 return 0; 3446 } 3447 } 3448 3449 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv) 3450 { 3451 u32 val, hotplug; 3452 3453 /* Display WA #1179 WaHardHangonHotPlug: cnp */ 3454 if (HAS_PCH_CNP(dev_priv)) { 3455 val = intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN1); 3456 val &= ~CHASSIS_CLK_REQ_DURATION_MASK; 3457 val |= CHASSIS_CLK_REQ_DURATION(0xf); 3458 intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN1, val); 3459 } 3460 3461 /* Enable digital hotplug on the PCH */ 3462 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); 3463 hotplug &= ~(PORTA_HOTPLUG_ENABLE | 3464 PORTB_HOTPLUG_ENABLE | 3465 PORTC_HOTPLUG_ENABLE | 3466 PORTD_HOTPLUG_ENABLE); 3467 hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug_enables); 3468 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug); 3469 3470 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG2); 3471 hotplug &= ~PORTE_HOTPLUG_ENABLE; 3472 hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug2_enables); 3473 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG2, hotplug); 3474 } 3475 3476 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv) 3477 { 3478 u32 hotplug_irqs, enabled_irqs; 3479 3480 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) 3481 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); 3482 3483 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd); 3484 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd); 3485 3486 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); 3487 3488 spt_hpd_detection_setup(dev_priv); 3489 } 3490 3491 static u32 ilk_hotplug_enables(struct drm_i915_private *i915, 3492 enum hpd_pin pin) 3493 { 3494 switch (pin) { 3495 case HPD_PORT_A: 3496 return DIGITAL_PORTA_HOTPLUG_ENABLE | 3497 DIGITAL_PORTA_PULSE_DURATION_2ms; 3498 default: 3499 return 0; 3500 } 3501 } 3502 3503 static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv) 3504 { 3505 u32 hotplug; 3506 3507 /* 3508 * Enable digital hotplug on the CPU, and configure the DP short pulse 3509 * duration to 2ms (which is the minimum in the Display Port spec) 3510 * The pulse duration bits are reserved on HSW+. 3511 */ 3512 hotplug = intel_uncore_read(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL); 3513 hotplug &= ~(DIGITAL_PORTA_HOTPLUG_ENABLE | 3514 DIGITAL_PORTA_PULSE_DURATION_MASK); 3515 hotplug |= intel_hpd_hotplug_enables(dev_priv, ilk_hotplug_enables); 3516 intel_uncore_write(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, hotplug); 3517 } 3518 3519 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv) 3520 { 3521 u32 hotplug_irqs, enabled_irqs; 3522 3523 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd); 3524 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd); 3525 3526 if (DISPLAY_VER(dev_priv) >= 8) 3527 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); 3528 else 3529 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); 3530 3531 ilk_hpd_detection_setup(dev_priv); 3532 3533 ibx_hpd_irq_setup(dev_priv); 3534 } 3535 3536 static u32 bxt_hotplug_enables(struct drm_i915_private *i915, 3537 enum hpd_pin pin) 3538 { 3539 u32 hotplug; 3540 3541 switch (pin) { 3542 case HPD_PORT_A: 3543 hotplug = PORTA_HOTPLUG_ENABLE; 3544 if (intel_bios_is_port_hpd_inverted(i915, PORT_A)) 3545 hotplug |= BXT_DDIA_HPD_INVERT; 3546 return hotplug; 3547 case HPD_PORT_B: 3548 hotplug = PORTB_HOTPLUG_ENABLE; 3549 if (intel_bios_is_port_hpd_inverted(i915, PORT_B)) 3550 hotplug |= BXT_DDIB_HPD_INVERT; 3551 return hotplug; 3552 case HPD_PORT_C: 3553 hotplug = PORTC_HOTPLUG_ENABLE; 3554 if (intel_bios_is_port_hpd_inverted(i915, PORT_C)) 3555 hotplug |= BXT_DDIC_HPD_INVERT; 3556 return hotplug; 3557 default: 3558 return 0; 3559 } 3560 } 3561 3562 static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv) 3563 { 3564 u32 hotplug; 3565 3566 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); 3567 hotplug &= ~(PORTA_HOTPLUG_ENABLE | 3568 PORTB_HOTPLUG_ENABLE | 3569 PORTC_HOTPLUG_ENABLE | 3570 BXT_DDIA_HPD_INVERT | 3571 BXT_DDIB_HPD_INVERT | 3572 BXT_DDIC_HPD_INVERT); 3573 hotplug |= intel_hpd_hotplug_enables(dev_priv, bxt_hotplug_enables); 3574 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug); 3575 } 3576 3577 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv) 3578 { 3579 u32 hotplug_irqs, enabled_irqs; 3580 3581 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd); 3582 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd); 3583 3584 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); 3585 3586 bxt_hpd_detection_setup(dev_priv); 3587 } 3588 3589 /* 3590 * SDEIER is also touched by the interrupt handler to work around missed PCH 3591 * interrupts. Hence we can't update it after the interrupt handler is enabled - 3592 * instead we unconditionally enable all PCH interrupt sources here, but then 3593 * only unmask them as needed with SDEIMR. 3594 * 3595 * Note that we currently do this after installing the interrupt handler, 3596 * but before we enable the master interrupt. That should be sufficient 3597 * to avoid races with the irq handler, assuming we have MSI. Shared legacy 3598 * interrupts could still race. 3599 */ 3600 static void ibx_irq_postinstall(struct drm_i915_private *dev_priv) 3601 { 3602 struct intel_uncore *uncore = &dev_priv->uncore; 3603 u32 mask; 3604 3605 if (HAS_PCH_NOP(dev_priv)) 3606 return; 3607 3608 if (HAS_PCH_IBX(dev_priv)) 3609 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; 3610 else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) 3611 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; 3612 else 3613 mask = SDE_GMBUS_CPT; 3614 3615 GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff); 3616 } 3617 3618 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv) 3619 { 3620 struct intel_uncore *uncore = &dev_priv->uncore; 3621 u32 display_mask, extra_mask; 3622 3623 if (INTEL_GEN(dev_priv) >= 7) { 3624 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | 3625 DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB); 3626 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | 3627 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB | 3628 DE_PLANE_FLIP_DONE_IVB(PLANE_C) | 3629 DE_PLANE_FLIP_DONE_IVB(PLANE_B) | 3630 DE_PLANE_FLIP_DONE_IVB(PLANE_A) | 3631 DE_DP_A_HOTPLUG_IVB); 3632 } else { 3633 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | 3634 DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE | 3635 DE_PIPEA_CRC_DONE | DE_POISON); 3636 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | 3637 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN | 3638 DE_PLANE_FLIP_DONE(PLANE_A) | 3639 DE_PLANE_FLIP_DONE(PLANE_B) | 3640 DE_DP_A_HOTPLUG); 3641 } 3642 3643 if (IS_HASWELL(dev_priv)) { 3644 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR); 3645 display_mask |= DE_EDP_PSR_INT_HSW; 3646 } 3647 3648 if (IS_IRONLAKE_M(dev_priv)) 3649 extra_mask |= DE_PCU_EVENT; 3650 3651 dev_priv->irq_mask = ~display_mask; 3652 3653 ibx_irq_postinstall(dev_priv); 3654 3655 gen5_gt_irq_postinstall(&dev_priv->gt); 3656 3657 GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask, 3658 display_mask | extra_mask); 3659 } 3660 3661 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) 3662 { 3663 lockdep_assert_held(&dev_priv->irq_lock); 3664 3665 if (dev_priv->display_irqs_enabled) 3666 return; 3667 3668 dev_priv->display_irqs_enabled = true; 3669 3670 if (intel_irqs_enabled(dev_priv)) { 3671 vlv_display_irq_reset(dev_priv); 3672 vlv_display_irq_postinstall(dev_priv); 3673 } 3674 } 3675 3676 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) 3677 { 3678 lockdep_assert_held(&dev_priv->irq_lock); 3679 3680 if (!dev_priv->display_irqs_enabled) 3681 return; 3682 3683 dev_priv->display_irqs_enabled = false; 3684 3685 if (intel_irqs_enabled(dev_priv)) 3686 vlv_display_irq_reset(dev_priv); 3687 } 3688 3689 3690 static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv) 3691 { 3692 gen5_gt_irq_postinstall(&dev_priv->gt); 3693 3694 spin_lock_irq(&dev_priv->irq_lock); 3695 if (dev_priv->display_irqs_enabled) 3696 vlv_display_irq_postinstall(dev_priv); 3697 spin_unlock_irq(&dev_priv->irq_lock); 3698 3699 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); 3700 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER); 3701 } 3702 3703 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) 3704 { 3705 struct intel_uncore *uncore = &dev_priv->uncore; 3706 3707 u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) | 3708 GEN8_PIPE_CDCLK_CRC_DONE; 3709 u32 de_pipe_enables; 3710 u32 de_port_masked = gen8_de_port_aux_mask(dev_priv); 3711 u32 de_port_enables; 3712 u32 de_misc_masked = GEN8_DE_EDP_PSR; 3713 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3714 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3715 enum pipe pipe; 3716 3717 if (DISPLAY_VER(dev_priv) <= 10) 3718 de_misc_masked |= GEN8_DE_MISC_GSE; 3719 3720 if (IS_GEN9_LP(dev_priv)) 3721 de_port_masked |= BXT_DE_PORT_GMBUS; 3722 3723 if (DISPLAY_VER(dev_priv) >= 11) { 3724 enum port port; 3725 3726 if (intel_bios_is_dsi_present(dev_priv, &port)) 3727 de_port_masked |= DSI0_TE | DSI1_TE; 3728 } 3729 3730 de_pipe_enables = de_pipe_masked | 3731 GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN | 3732 gen8_de_pipe_flip_done_mask(dev_priv); 3733 3734 de_port_enables = de_port_masked; 3735 if (IS_GEN9_LP(dev_priv)) 3736 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; 3737 else if (IS_BROADWELL(dev_priv)) 3738 de_port_enables |= BDW_DE_PORT_HOTPLUG_MASK; 3739 3740 if (DISPLAY_VER(dev_priv) >= 12) { 3741 enum transcoder trans; 3742 3743 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) { 3744 enum intel_display_power_domain domain; 3745 3746 domain = POWER_DOMAIN_TRANSCODER(trans); 3747 if (!intel_display_power_is_enabled(dev_priv, domain)) 3748 continue; 3749 3750 gen3_assert_iir_is_zero(uncore, TRANS_PSR_IIR(trans)); 3751 } 3752 } else { 3753 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR); 3754 } 3755 3756 for_each_pipe(dev_priv, pipe) { 3757 dev_priv->de_irq_mask[pipe] = ~de_pipe_masked; 3758 3759 if (intel_display_power_is_enabled(dev_priv, 3760 POWER_DOMAIN_PIPE(pipe))) 3761 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe, 3762 dev_priv->de_irq_mask[pipe], 3763 de_pipe_enables); 3764 } 3765 3766 GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables); 3767 GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked); 3768 3769 if (DISPLAY_VER(dev_priv) >= 11) { 3770 u32 de_hpd_masked = 0; 3771 u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK | 3772 GEN11_DE_TBT_HOTPLUG_MASK; 3773 3774 GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked, 3775 de_hpd_enables); 3776 } 3777 } 3778 3779 static void icp_irq_postinstall(struct drm_i915_private *dev_priv) 3780 { 3781 struct intel_uncore *uncore = &dev_priv->uncore; 3782 u32 mask = SDE_GMBUS_ICP; 3783 3784 GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff); 3785 } 3786 3787 static void gen8_irq_postinstall(struct drm_i915_private *dev_priv) 3788 { 3789 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 3790 icp_irq_postinstall(dev_priv); 3791 else if (HAS_PCH_SPLIT(dev_priv)) 3792 ibx_irq_postinstall(dev_priv); 3793 3794 gen8_gt_irq_postinstall(&dev_priv->gt); 3795 gen8_de_irq_postinstall(dev_priv); 3796 3797 gen8_master_intr_enable(dev_priv->uncore.regs); 3798 } 3799 3800 3801 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv) 3802 { 3803 struct intel_uncore *uncore = &dev_priv->uncore; 3804 u32 gu_misc_masked = GEN11_GU_MISC_GSE; 3805 3806 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 3807 icp_irq_postinstall(dev_priv); 3808 3809 gen11_gt_irq_postinstall(&dev_priv->gt); 3810 gen8_de_irq_postinstall(dev_priv); 3811 3812 GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked); 3813 3814 intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE); 3815 3816 if (HAS_MASTER_UNIT_IRQ(dev_priv)) { 3817 dg1_master_intr_enable(uncore->regs); 3818 intel_uncore_posting_read(&dev_priv->uncore, DG1_MSTR_UNIT_INTR); 3819 } else { 3820 gen11_master_intr_enable(uncore->regs); 3821 intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ); 3822 } 3823 } 3824 3825 static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv) 3826 { 3827 gen8_gt_irq_postinstall(&dev_priv->gt); 3828 3829 spin_lock_irq(&dev_priv->irq_lock); 3830 if (dev_priv->display_irqs_enabled) 3831 vlv_display_irq_postinstall(dev_priv); 3832 spin_unlock_irq(&dev_priv->irq_lock); 3833 3834 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); 3835 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ); 3836 } 3837 3838 static void i8xx_irq_reset(struct drm_i915_private *dev_priv) 3839 { 3840 struct intel_uncore *uncore = &dev_priv->uncore; 3841 3842 i9xx_pipestat_irq_reset(dev_priv); 3843 3844 GEN2_IRQ_RESET(uncore); 3845 dev_priv->irq_mask = ~0u; 3846 } 3847 3848 static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv) 3849 { 3850 struct intel_uncore *uncore = &dev_priv->uncore; 3851 u16 enable_mask; 3852 3853 intel_uncore_write16(uncore, 3854 EMR, 3855 ~(I915_ERROR_PAGE_TABLE | 3856 I915_ERROR_MEMORY_REFRESH)); 3857 3858 /* Unmask the interrupts that we always want on. */ 3859 dev_priv->irq_mask = 3860 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 3861 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 3862 I915_MASTER_ERROR_INTERRUPT); 3863 3864 enable_mask = 3865 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 3866 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 3867 I915_MASTER_ERROR_INTERRUPT | 3868 I915_USER_INTERRUPT; 3869 3870 GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask); 3871 3872 /* Interrupt setup is already guaranteed to be single-threaded, this is 3873 * just to make the assert_spin_locked check happy. */ 3874 spin_lock_irq(&dev_priv->irq_lock); 3875 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); 3876 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); 3877 spin_unlock_irq(&dev_priv->irq_lock); 3878 } 3879 3880 static void i8xx_error_irq_ack(struct drm_i915_private *i915, 3881 u16 *eir, u16 *eir_stuck) 3882 { 3883 struct intel_uncore *uncore = &i915->uncore; 3884 u16 emr; 3885 3886 *eir = intel_uncore_read16(uncore, EIR); 3887 3888 if (*eir) 3889 intel_uncore_write16(uncore, EIR, *eir); 3890 3891 *eir_stuck = intel_uncore_read16(uncore, EIR); 3892 if (*eir_stuck == 0) 3893 return; 3894 3895 /* 3896 * Toggle all EMR bits to make sure we get an edge 3897 * in the ISR master error bit if we don't clear 3898 * all the EIR bits. Otherwise the edge triggered 3899 * IIR on i965/g4x wouldn't notice that an interrupt 3900 * is still pending. Also some EIR bits can't be 3901 * cleared except by handling the underlying error 3902 * (or by a GPU reset) so we mask any bit that 3903 * remains set. 3904 */ 3905 emr = intel_uncore_read16(uncore, EMR); 3906 intel_uncore_write16(uncore, EMR, 0xffff); 3907 intel_uncore_write16(uncore, EMR, emr | *eir_stuck); 3908 } 3909 3910 static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv, 3911 u16 eir, u16 eir_stuck) 3912 { 3913 DRM_DEBUG("Master Error: EIR 0x%04x\n", eir); 3914 3915 if (eir_stuck) 3916 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%04x, masked\n", 3917 eir_stuck); 3918 } 3919 3920 static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv, 3921 u32 *eir, u32 *eir_stuck) 3922 { 3923 u32 emr; 3924 3925 *eir = intel_uncore_read(&dev_priv->uncore, EIR); 3926 3927 intel_uncore_write(&dev_priv->uncore, EIR, *eir); 3928 3929 *eir_stuck = intel_uncore_read(&dev_priv->uncore, EIR); 3930 if (*eir_stuck == 0) 3931 return; 3932 3933 /* 3934 * Toggle all EMR bits to make sure we get an edge 3935 * in the ISR master error bit if we don't clear 3936 * all the EIR bits. Otherwise the edge triggered 3937 * IIR on i965/g4x wouldn't notice that an interrupt 3938 * is still pending. Also some EIR bits can't be 3939 * cleared except by handling the underlying error 3940 * (or by a GPU reset) so we mask any bit that 3941 * remains set. 3942 */ 3943 emr = intel_uncore_read(&dev_priv->uncore, EMR); 3944 intel_uncore_write(&dev_priv->uncore, EMR, 0xffffffff); 3945 intel_uncore_write(&dev_priv->uncore, EMR, emr | *eir_stuck); 3946 } 3947 3948 static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv, 3949 u32 eir, u32 eir_stuck) 3950 { 3951 DRM_DEBUG("Master Error, EIR 0x%08x\n", eir); 3952 3953 if (eir_stuck) 3954 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n", 3955 eir_stuck); 3956 } 3957 3958 static irqreturn_t i8xx_irq_handler(int irq, void *arg) 3959 { 3960 struct drm_i915_private *dev_priv = arg; 3961 irqreturn_t ret = IRQ_NONE; 3962 3963 if (!intel_irqs_enabled(dev_priv)) 3964 return IRQ_NONE; 3965 3966 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 3967 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 3968 3969 do { 3970 u32 pipe_stats[I915_MAX_PIPES] = {}; 3971 u16 eir = 0, eir_stuck = 0; 3972 u16 iir; 3973 3974 iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR); 3975 if (iir == 0) 3976 break; 3977 3978 ret = IRQ_HANDLED; 3979 3980 /* Call regardless, as some status bits might not be 3981 * signalled in iir */ 3982 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); 3983 3984 if (iir & I915_MASTER_ERROR_INTERRUPT) 3985 i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck); 3986 3987 intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir); 3988 3989 if (iir & I915_USER_INTERRUPT) 3990 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]); 3991 3992 if (iir & I915_MASTER_ERROR_INTERRUPT) 3993 i8xx_error_irq_handler(dev_priv, eir, eir_stuck); 3994 3995 i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats); 3996 } while (0); 3997 3998 pmu_irq_stats(dev_priv, ret); 3999 4000 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 4001 4002 return ret; 4003 } 4004 4005 static void i915_irq_reset(struct drm_i915_private *dev_priv) 4006 { 4007 struct intel_uncore *uncore = &dev_priv->uncore; 4008 4009 if (I915_HAS_HOTPLUG(dev_priv)) { 4010 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); 4011 intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT)); 4012 } 4013 4014 i9xx_pipestat_irq_reset(dev_priv); 4015 4016 GEN3_IRQ_RESET(uncore, GEN2_); 4017 dev_priv->irq_mask = ~0u; 4018 } 4019 4020 static void i915_irq_postinstall(struct drm_i915_private *dev_priv) 4021 { 4022 struct intel_uncore *uncore = &dev_priv->uncore; 4023 u32 enable_mask; 4024 4025 intel_uncore_write(&dev_priv->uncore, EMR, ~(I915_ERROR_PAGE_TABLE | 4026 I915_ERROR_MEMORY_REFRESH)); 4027 4028 /* Unmask the interrupts that we always want on. */ 4029 dev_priv->irq_mask = 4030 ~(I915_ASLE_INTERRUPT | 4031 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 4032 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 4033 I915_MASTER_ERROR_INTERRUPT); 4034 4035 enable_mask = 4036 I915_ASLE_INTERRUPT | 4037 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 4038 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 4039 I915_MASTER_ERROR_INTERRUPT | 4040 I915_USER_INTERRUPT; 4041 4042 if (I915_HAS_HOTPLUG(dev_priv)) { 4043 /* Enable in IER... */ 4044 enable_mask |= I915_DISPLAY_PORT_INTERRUPT; 4045 /* and unmask in IMR */ 4046 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; 4047 } 4048 4049 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask); 4050 4051 /* Interrupt setup is already guaranteed to be single-threaded, this is 4052 * just to make the assert_spin_locked check happy. */ 4053 spin_lock_irq(&dev_priv->irq_lock); 4054 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); 4055 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); 4056 spin_unlock_irq(&dev_priv->irq_lock); 4057 4058 i915_enable_asle_pipestat(dev_priv); 4059 } 4060 4061 static irqreturn_t i915_irq_handler(int irq, void *arg) 4062 { 4063 struct drm_i915_private *dev_priv = arg; 4064 irqreturn_t ret = IRQ_NONE; 4065 4066 if (!intel_irqs_enabled(dev_priv)) 4067 return IRQ_NONE; 4068 4069 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 4070 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 4071 4072 do { 4073 u32 pipe_stats[I915_MAX_PIPES] = {}; 4074 u32 eir = 0, eir_stuck = 0; 4075 u32 hotplug_status = 0; 4076 u32 iir; 4077 4078 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR); 4079 if (iir == 0) 4080 break; 4081 4082 ret = IRQ_HANDLED; 4083 4084 if (I915_HAS_HOTPLUG(dev_priv) && 4085 iir & I915_DISPLAY_PORT_INTERRUPT) 4086 hotplug_status = i9xx_hpd_irq_ack(dev_priv); 4087 4088 /* Call regardless, as some status bits might not be 4089 * signalled in iir */ 4090 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); 4091 4092 if (iir & I915_MASTER_ERROR_INTERRUPT) 4093 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck); 4094 4095 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir); 4096 4097 if (iir & I915_USER_INTERRUPT) 4098 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]); 4099 4100 if (iir & I915_MASTER_ERROR_INTERRUPT) 4101 i9xx_error_irq_handler(dev_priv, eir, eir_stuck); 4102 4103 if (hotplug_status) 4104 i9xx_hpd_irq_handler(dev_priv, hotplug_status); 4105 4106 i915_pipestat_irq_handler(dev_priv, iir, pipe_stats); 4107 } while (0); 4108 4109 pmu_irq_stats(dev_priv, ret); 4110 4111 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 4112 4113 return ret; 4114 } 4115 4116 static void i965_irq_reset(struct drm_i915_private *dev_priv) 4117 { 4118 struct intel_uncore *uncore = &dev_priv->uncore; 4119 4120 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); 4121 intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT)); 4122 4123 i9xx_pipestat_irq_reset(dev_priv); 4124 4125 GEN3_IRQ_RESET(uncore, GEN2_); 4126 dev_priv->irq_mask = ~0u; 4127 } 4128 4129 static void i965_irq_postinstall(struct drm_i915_private *dev_priv) 4130 { 4131 struct intel_uncore *uncore = &dev_priv->uncore; 4132 u32 enable_mask; 4133 u32 error_mask; 4134 4135 /* 4136 * Enable some error detection, note the instruction error mask 4137 * bit is reserved, so we leave it masked. 4138 */ 4139 if (IS_G4X(dev_priv)) { 4140 error_mask = ~(GM45_ERROR_PAGE_TABLE | 4141 GM45_ERROR_MEM_PRIV | 4142 GM45_ERROR_CP_PRIV | 4143 I915_ERROR_MEMORY_REFRESH); 4144 } else { 4145 error_mask = ~(I915_ERROR_PAGE_TABLE | 4146 I915_ERROR_MEMORY_REFRESH); 4147 } 4148 intel_uncore_write(&dev_priv->uncore, EMR, error_mask); 4149 4150 /* Unmask the interrupts that we always want on. */ 4151 dev_priv->irq_mask = 4152 ~(I915_ASLE_INTERRUPT | 4153 I915_DISPLAY_PORT_INTERRUPT | 4154 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 4155 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 4156 I915_MASTER_ERROR_INTERRUPT); 4157 4158 enable_mask = 4159 I915_ASLE_INTERRUPT | 4160 I915_DISPLAY_PORT_INTERRUPT | 4161 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 4162 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 4163 I915_MASTER_ERROR_INTERRUPT | 4164 I915_USER_INTERRUPT; 4165 4166 if (IS_G4X(dev_priv)) 4167 enable_mask |= I915_BSD_USER_INTERRUPT; 4168 4169 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask); 4170 4171 /* Interrupt setup is already guaranteed to be single-threaded, this is 4172 * just to make the assert_spin_locked check happy. */ 4173 spin_lock_irq(&dev_priv->irq_lock); 4174 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); 4175 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); 4176 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); 4177 spin_unlock_irq(&dev_priv->irq_lock); 4178 4179 i915_enable_asle_pipestat(dev_priv); 4180 } 4181 4182 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv) 4183 { 4184 u32 hotplug_en; 4185 4186 lockdep_assert_held(&dev_priv->irq_lock); 4187 4188 /* Note HDMI and DP share hotplug bits */ 4189 /* enable bits are the same for all generations */ 4190 hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915); 4191 /* Programming the CRT detection parameters tends 4192 to generate a spurious hotplug event about three 4193 seconds later. So just do it once. 4194 */ 4195 if (IS_G4X(dev_priv)) 4196 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; 4197 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; 4198 4199 /* Ignore TV since it's buggy */ 4200 i915_hotplug_interrupt_update_locked(dev_priv, 4201 HOTPLUG_INT_EN_MASK | 4202 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK | 4203 CRT_HOTPLUG_ACTIVATION_PERIOD_64, 4204 hotplug_en); 4205 } 4206 4207 static irqreturn_t i965_irq_handler(int irq, void *arg) 4208 { 4209 struct drm_i915_private *dev_priv = arg; 4210 irqreturn_t ret = IRQ_NONE; 4211 4212 if (!intel_irqs_enabled(dev_priv)) 4213 return IRQ_NONE; 4214 4215 /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 4216 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 4217 4218 do { 4219 u32 pipe_stats[I915_MAX_PIPES] = {}; 4220 u32 eir = 0, eir_stuck = 0; 4221 u32 hotplug_status = 0; 4222 u32 iir; 4223 4224 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR); 4225 if (iir == 0) 4226 break; 4227 4228 ret = IRQ_HANDLED; 4229 4230 if (iir & I915_DISPLAY_PORT_INTERRUPT) 4231 hotplug_status = i9xx_hpd_irq_ack(dev_priv); 4232 4233 /* Call regardless, as some status bits might not be 4234 * signalled in iir */ 4235 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); 4236 4237 if (iir & I915_MASTER_ERROR_INTERRUPT) 4238 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck); 4239 4240 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir); 4241 4242 if (iir & I915_USER_INTERRUPT) 4243 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]); 4244 4245 if (iir & I915_BSD_USER_INTERRUPT) 4246 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[VCS0]); 4247 4248 if (iir & I915_MASTER_ERROR_INTERRUPT) 4249 i9xx_error_irq_handler(dev_priv, eir, eir_stuck); 4250 4251 if (hotplug_status) 4252 i9xx_hpd_irq_handler(dev_priv, hotplug_status); 4253 4254 i965_pipestat_irq_handler(dev_priv, iir, pipe_stats); 4255 } while (0); 4256 4257 pmu_irq_stats(dev_priv, IRQ_HANDLED); 4258 4259 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 4260 4261 return ret; 4262 } 4263 4264 /** 4265 * intel_irq_init - initializes irq support 4266 * @dev_priv: i915 device instance 4267 * 4268 * This function initializes all the irq support including work items, timers 4269 * and all the vtables. It does not setup the interrupt itself though. 4270 */ 4271 void intel_irq_init(struct drm_i915_private *dev_priv) 4272 { 4273 struct drm_device *dev = &dev_priv->drm; 4274 int i; 4275 4276 INIT_WORK(&dev_priv->l3_parity.error_work, ivb_parity_work); 4277 for (i = 0; i < MAX_L3_SLICES; ++i) 4278 dev_priv->l3_parity.remap_info[i] = NULL; 4279 4280 /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */ 4281 if (HAS_GT_UC(dev_priv) && INTEL_GEN(dev_priv) < 11) 4282 dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16; 4283 4284 if (!HAS_DISPLAY(dev_priv)) 4285 return; 4286 4287 intel_hpd_init_pins(dev_priv); 4288 4289 intel_hpd_init_work(dev_priv); 4290 4291 dev->vblank_disable_immediate = true; 4292 4293 /* Most platforms treat the display irq block as an always-on 4294 * power domain. vlv/chv can disable it at runtime and need 4295 * special care to avoid writing any of the display block registers 4296 * outside of the power domain. We defer setting up the display irqs 4297 * in this case to the runtime pm. 4298 */ 4299 dev_priv->display_irqs_enabled = true; 4300 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 4301 dev_priv->display_irqs_enabled = false; 4302 4303 dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD; 4304 /* If we have MST support, we want to avoid doing short HPD IRQ storm 4305 * detection, as short HPD storms will occur as a natural part of 4306 * sideband messaging with MST. 4307 * On older platforms however, IRQ storms can occur with both long and 4308 * short pulses, as seen on some G4x systems. 4309 */ 4310 dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv); 4311 4312 if (HAS_GMCH(dev_priv)) { 4313 if (I915_HAS_HOTPLUG(dev_priv)) 4314 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; 4315 } else { 4316 if (HAS_PCH_DG1(dev_priv)) 4317 dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup; 4318 else if (DISPLAY_VER(dev_priv) >= 11) 4319 dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup; 4320 else if (IS_GEN9_LP(dev_priv)) 4321 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup; 4322 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 4323 dev_priv->display.hpd_irq_setup = icp_hpd_irq_setup; 4324 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT) 4325 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup; 4326 else 4327 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; 4328 } 4329 } 4330 4331 /** 4332 * intel_irq_fini - deinitializes IRQ support 4333 * @i915: i915 device instance 4334 * 4335 * This function deinitializes all the IRQ support. 4336 */ 4337 void intel_irq_fini(struct drm_i915_private *i915) 4338 { 4339 int i; 4340 4341 for (i = 0; i < MAX_L3_SLICES; ++i) 4342 kfree(i915->l3_parity.remap_info[i]); 4343 } 4344 4345 static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv) 4346 { 4347 if (HAS_GMCH(dev_priv)) { 4348 if (IS_CHERRYVIEW(dev_priv)) 4349 return cherryview_irq_handler; 4350 else if (IS_VALLEYVIEW(dev_priv)) 4351 return valleyview_irq_handler; 4352 else if (IS_GEN(dev_priv, 4)) 4353 return i965_irq_handler; 4354 else if (IS_GEN(dev_priv, 3)) 4355 return i915_irq_handler; 4356 else 4357 return i8xx_irq_handler; 4358 } else { 4359 if (HAS_MASTER_UNIT_IRQ(dev_priv)) 4360 return dg1_irq_handler; 4361 if (INTEL_GEN(dev_priv) >= 11) 4362 return gen11_irq_handler; 4363 else if (INTEL_GEN(dev_priv) >= 8) 4364 return gen8_irq_handler; 4365 else 4366 return ilk_irq_handler; 4367 } 4368 } 4369 4370 static void intel_irq_reset(struct drm_i915_private *dev_priv) 4371 { 4372 if (HAS_GMCH(dev_priv)) { 4373 if (IS_CHERRYVIEW(dev_priv)) 4374 cherryview_irq_reset(dev_priv); 4375 else if (IS_VALLEYVIEW(dev_priv)) 4376 valleyview_irq_reset(dev_priv); 4377 else if (IS_GEN(dev_priv, 4)) 4378 i965_irq_reset(dev_priv); 4379 else if (IS_GEN(dev_priv, 3)) 4380 i915_irq_reset(dev_priv); 4381 else 4382 i8xx_irq_reset(dev_priv); 4383 } else { 4384 if (INTEL_GEN(dev_priv) >= 11) 4385 gen11_irq_reset(dev_priv); 4386 else if (INTEL_GEN(dev_priv) >= 8) 4387 gen8_irq_reset(dev_priv); 4388 else 4389 ilk_irq_reset(dev_priv); 4390 } 4391 } 4392 4393 static void intel_irq_postinstall(struct drm_i915_private *dev_priv) 4394 { 4395 if (HAS_GMCH(dev_priv)) { 4396 if (IS_CHERRYVIEW(dev_priv)) 4397 cherryview_irq_postinstall(dev_priv); 4398 else if (IS_VALLEYVIEW(dev_priv)) 4399 valleyview_irq_postinstall(dev_priv); 4400 else if (IS_GEN(dev_priv, 4)) 4401 i965_irq_postinstall(dev_priv); 4402 else if (IS_GEN(dev_priv, 3)) 4403 i915_irq_postinstall(dev_priv); 4404 else 4405 i8xx_irq_postinstall(dev_priv); 4406 } else { 4407 if (INTEL_GEN(dev_priv) >= 11) 4408 gen11_irq_postinstall(dev_priv); 4409 else if (INTEL_GEN(dev_priv) >= 8) 4410 gen8_irq_postinstall(dev_priv); 4411 else 4412 ilk_irq_postinstall(dev_priv); 4413 } 4414 } 4415 4416 /** 4417 * intel_irq_install - enables the hardware interrupt 4418 * @dev_priv: i915 device instance 4419 * 4420 * This function enables the hardware interrupt handling, but leaves the hotplug 4421 * handling still disabled. It is called after intel_irq_init(). 4422 * 4423 * In the driver load and resume code we need working interrupts in a few places 4424 * but don't want to deal with the hassle of concurrent probe and hotplug 4425 * workers. Hence the split into this two-stage approach. 4426 */ 4427 int intel_irq_install(struct drm_i915_private *dev_priv) 4428 { 4429 int irq = to_pci_dev(dev_priv->drm.dev)->irq; 4430 int ret; 4431 4432 /* 4433 * We enable some interrupt sources in our postinstall hooks, so mark 4434 * interrupts as enabled _before_ actually enabling them to avoid 4435 * special cases in our ordering checks. 4436 */ 4437 dev_priv->runtime_pm.irqs_enabled = true; 4438 4439 dev_priv->drm.irq_enabled = true; 4440 4441 intel_irq_reset(dev_priv); 4442 4443 ret = request_irq(irq, intel_irq_handler(dev_priv), 4444 IRQF_SHARED, DRIVER_NAME, dev_priv); 4445 if (ret < 0) { 4446 dev_priv->drm.irq_enabled = false; 4447 return ret; 4448 } 4449 4450 intel_irq_postinstall(dev_priv); 4451 4452 return ret; 4453 } 4454 4455 /** 4456 * intel_irq_uninstall - finilizes all irq handling 4457 * @dev_priv: i915 device instance 4458 * 4459 * This stops interrupt and hotplug handling and unregisters and frees all 4460 * resources acquired in the init functions. 4461 */ 4462 void intel_irq_uninstall(struct drm_i915_private *dev_priv) 4463 { 4464 int irq = to_pci_dev(dev_priv->drm.dev)->irq; 4465 4466 /* 4467 * FIXME we can get called twice during driver probe 4468 * error handling as well as during driver remove due to 4469 * intel_modeset_driver_remove() calling us out of sequence. 4470 * Would be nice if it didn't do that... 4471 */ 4472 if (!dev_priv->drm.irq_enabled) 4473 return; 4474 4475 dev_priv->drm.irq_enabled = false; 4476 4477 intel_irq_reset(dev_priv); 4478 4479 free_irq(irq, dev_priv); 4480 4481 intel_hpd_cancel_work(dev_priv); 4482 dev_priv->runtime_pm.irqs_enabled = false; 4483 } 4484 4485 /** 4486 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling 4487 * @dev_priv: i915 device instance 4488 * 4489 * This function is used to disable interrupts at runtime, both in the runtime 4490 * pm and the system suspend/resume code. 4491 */ 4492 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) 4493 { 4494 intel_irq_reset(dev_priv); 4495 dev_priv->runtime_pm.irqs_enabled = false; 4496 intel_synchronize_irq(dev_priv); 4497 } 4498 4499 /** 4500 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling 4501 * @dev_priv: i915 device instance 4502 * 4503 * This function is used to enable interrupts at runtime, both in the runtime 4504 * pm and the system suspend/resume code. 4505 */ 4506 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) 4507 { 4508 dev_priv->runtime_pm.irqs_enabled = true; 4509 intel_irq_reset(dev_priv); 4510 intel_irq_postinstall(dev_priv); 4511 } 4512 4513 bool intel_irqs_enabled(struct drm_i915_private *dev_priv) 4514 { 4515 /* 4516 * We only use drm_irq_uninstall() at unload and VT switch, so 4517 * this is the only thing we need to check. 4518 */ 4519 return dev_priv->runtime_pm.irqs_enabled; 4520 } 4521 4522 void intel_synchronize_irq(struct drm_i915_private *i915) 4523 { 4524 synchronize_irq(to_pci_dev(i915->drm.dev)->irq); 4525 } 4526