1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include <linux/hwmon.h> 7 #include <linux/hwmon-sysfs.h> 8 #include <linux/jiffies.h> 9 #include <linux/types.h> 10 #include <linux/units.h> 11 12 #include <drm/intel/intel_pcode_regs.h> 13 14 #include "i915_drv.h" 15 #include "i915_hwmon.h" 16 #include "i915_reg.h" 17 #include "intel_mchbar_regs.h" 18 #include "intel_pcode.h" 19 #include "gt/intel_gt.h" 20 #include "gt/intel_gt_regs.h" 21 22 /* 23 * SF_* - scale factors for particular quantities according to hwmon spec. 24 * - voltage - millivolts 25 * - power - microwatts 26 * - curr - milliamperes 27 * - energy - microjoules 28 * - time - milliseconds 29 */ 30 #define SF_VOLTAGE 1000 31 #define SF_POWER 1000000 32 #define SF_CURR 1000 33 #define SF_ENERGY 1000000 34 #define SF_TIME 1000 35 36 struct hwm_reg { 37 i915_reg_t gt_perf_status; 38 i915_reg_t pkg_temp; 39 i915_reg_t pkg_power_sku_unit; 40 i915_reg_t pkg_power_sku; 41 i915_reg_t pkg_rapl_limit; 42 i915_reg_t energy_status_all; 43 i915_reg_t energy_status_tile; 44 i915_reg_t fan_speed; 45 }; 46 47 struct hwm_energy_info { 48 u32 reg_val_prev; 49 long accum_energy; /* Accumulated energy for energy1_input */ 50 }; 51 52 struct hwm_fan_info { 53 u32 reg_val_prev; 54 u64 time_prev; 55 }; 56 57 struct hwm_drvdata { 58 struct i915_hwmon *hwmon; 59 struct intel_uncore *uncore; 60 struct device *hwmon_dev; 61 struct hwm_energy_info ei; /* Energy info for energy1_input */ 62 struct hwm_fan_info fi; /* Fan info for fan1_input */ 63 char name[12]; 64 int gt_n; 65 bool reset_in_progress; 66 wait_queue_head_t waitq; 67 }; 68 69 struct i915_hwmon { 70 struct hwm_drvdata ddat; 71 struct hwm_drvdata ddat_gt[I915_MAX_GT]; 72 struct mutex hwmon_lock; /* counter overflow logic and rmw */ 73 struct hwm_reg rg; 74 int scl_shift_power; 75 int scl_shift_energy; 76 int scl_shift_time; 77 }; 78 79 static void 80 hwm_locked_with_pm_intel_uncore_rmw(struct hwm_drvdata *ddat, 81 i915_reg_t reg, u32 clear, u32 set) 82 { 83 struct i915_hwmon *hwmon = ddat->hwmon; 84 struct intel_uncore *uncore = ddat->uncore; 85 intel_wakeref_t wakeref; 86 87 with_intel_runtime_pm(uncore->rpm, wakeref) { 88 mutex_lock(&hwmon->hwmon_lock); 89 90 intel_uncore_rmw(uncore, reg, clear, set); 91 92 mutex_unlock(&hwmon->hwmon_lock); 93 } 94 } 95 96 /* 97 * This function's return type of u64 allows for the case where the scaling 98 * of the field taken from the 32-bit register value might cause a result to 99 * exceed 32 bits. 100 */ 101 static u64 102 hwm_field_read_and_scale(struct hwm_drvdata *ddat, i915_reg_t rgadr, 103 u32 field_msk, int nshift, u32 scale_factor) 104 { 105 struct intel_uncore *uncore = ddat->uncore; 106 intel_wakeref_t wakeref; 107 u32 reg_value; 108 109 with_intel_runtime_pm(uncore->rpm, wakeref) 110 reg_value = intel_uncore_read(uncore, rgadr); 111 112 reg_value = REG_FIELD_GET(field_msk, reg_value); 113 114 return mul_u64_u32_shr(reg_value, scale_factor, nshift); 115 } 116 117 /* 118 * hwm_energy - Obtain energy value 119 * 120 * The underlying energy hardware register is 32-bits and is subject to 121 * overflow. How long before overflow? For example, with an example 122 * scaling bit shift of 14 bits (see register *PACKAGE_POWER_SKU_UNIT) and 123 * a power draw of 1000 watts, the 32-bit counter will overflow in 124 * approximately 4.36 minutes. 125 * 126 * Examples: 127 * 1 watt: (2^32 >> 14) / 1 W / (60 * 60 * 24) secs/day -> 3 days 128 * 1000 watts: (2^32 >> 14) / 1000 W / 60 secs/min -> 4.36 minutes 129 * 130 * The function significantly increases overflow duration (from 4.36 131 * minutes) by accumulating the energy register into a 'long' as allowed by 132 * the hwmon API. Using x86_64 128 bit arithmetic (see mul_u64_u32_shr()), 133 * a 'long' of 63 bits, SF_ENERGY of 1e6 (~20 bits) and 134 * hwmon->scl_shift_energy of 14 bits we have 57 (63 - 20 + 14) bits before 135 * energy1_input overflows. This at 1000 W is an overflow duration of 278 years. 136 */ 137 static void 138 hwm_energy(struct hwm_drvdata *ddat, long *energy) 139 { 140 struct intel_uncore *uncore = ddat->uncore; 141 struct i915_hwmon *hwmon = ddat->hwmon; 142 struct hwm_energy_info *ei = &ddat->ei; 143 intel_wakeref_t wakeref; 144 i915_reg_t rgaddr; 145 u32 reg_val; 146 147 if (ddat->gt_n >= 0) 148 rgaddr = hwmon->rg.energy_status_tile; 149 else 150 rgaddr = hwmon->rg.energy_status_all; 151 152 with_intel_runtime_pm(uncore->rpm, wakeref) { 153 mutex_lock(&hwmon->hwmon_lock); 154 155 reg_val = intel_uncore_read(uncore, rgaddr); 156 157 if (reg_val >= ei->reg_val_prev) 158 ei->accum_energy += reg_val - ei->reg_val_prev; 159 else 160 ei->accum_energy += UINT_MAX - ei->reg_val_prev + reg_val; 161 ei->reg_val_prev = reg_val; 162 163 *energy = mul_u64_u32_shr(ei->accum_energy, SF_ENERGY, 164 hwmon->scl_shift_energy); 165 mutex_unlock(&hwmon->hwmon_lock); 166 } 167 } 168 169 static ssize_t 170 hwm_power1_max_interval_show(struct device *dev, struct device_attribute *attr, 171 char *buf) 172 { 173 struct hwm_drvdata *ddat = dev_get_drvdata(dev); 174 struct i915_hwmon *hwmon = ddat->hwmon; 175 intel_wakeref_t wakeref; 176 u32 r, x, y, x_w = 2; /* 2 bits */ 177 u64 tau4, out; 178 179 with_intel_runtime_pm(ddat->uncore->rpm, wakeref) 180 r = intel_uncore_read(ddat->uncore, hwmon->rg.pkg_rapl_limit); 181 182 x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r); 183 y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r); 184 /* 185 * tau = 1.x * power(2,y), x = bits(23:22), y = bits(21:17) 186 * = (4 | x) << (y - 2) 187 * where (y - 2) ensures a 1.x fixed point representation of 1.x 188 * However because y can be < 2, we compute 189 * tau4 = (4 | x) << y 190 * but add 2 when doing the final right shift to account for units 191 */ 192 tau4 = (u64)((1 << x_w) | x) << y; 193 /* val in hwmon interface units (millisec) */ 194 out = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w); 195 196 return sysfs_emit(buf, "%llu\n", out); 197 } 198 199 static ssize_t 200 hwm_power1_max_interval_store(struct device *dev, 201 struct device_attribute *attr, 202 const char *buf, size_t count) 203 { 204 struct hwm_drvdata *ddat = dev_get_drvdata(dev); 205 struct i915_hwmon *hwmon = ddat->hwmon; 206 u32 x, y, rxy, x_w = 2; /* 2 bits */ 207 u64 tau4, r, max_win; 208 unsigned long val; 209 int ret; 210 211 ret = kstrtoul(buf, 0, &val); 212 if (ret) 213 return ret; 214 215 /* 216 * Max HW supported tau in '1.x * power(2,y)' format, x = 0, y = 0x12 217 * The hwmon->scl_shift_time default of 0xa results in a max tau of 256 seconds 218 */ 219 #define PKG_MAX_WIN_DEFAULT 0x12ull 220 221 /* 222 * val must be < max in hwmon interface units. The steps below are 223 * explained in i915_power1_max_interval_show() 224 */ 225 r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT); 226 x = REG_FIELD_GET(PKG_MAX_WIN_X, r); 227 y = REG_FIELD_GET(PKG_MAX_WIN_Y, r); 228 tau4 = (u64)((1 << x_w) | x) << y; 229 max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w); 230 231 if (val > max_win) 232 return -EINVAL; 233 234 /* val in hw units */ 235 val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME); 236 /* Convert to 1.x * power(2,y) */ 237 if (!val) { 238 /* Avoid ilog2(0) */ 239 y = 0; 240 x = 0; 241 } else { 242 y = ilog2(val); 243 /* x = (val - (1 << y)) >> (y - 2); */ 244 x = (val - (1ul << y)) << x_w >> y; 245 } 246 247 rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) | REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y); 248 249 hwm_locked_with_pm_intel_uncore_rmw(ddat, hwmon->rg.pkg_rapl_limit, 250 PKG_PWR_LIM_1_TIME, rxy); 251 return count; 252 } 253 254 static SENSOR_DEVICE_ATTR(power1_max_interval, 0664, 255 hwm_power1_max_interval_show, 256 hwm_power1_max_interval_store, 0); 257 258 static struct attribute *hwm_attributes[] = { 259 &sensor_dev_attr_power1_max_interval.dev_attr.attr, 260 NULL 261 }; 262 263 static umode_t hwm_attributes_visible(struct kobject *kobj, 264 struct attribute *attr, int index) 265 { 266 struct device *dev = kobj_to_dev(kobj); 267 struct hwm_drvdata *ddat = dev_get_drvdata(dev); 268 struct i915_hwmon *hwmon = ddat->hwmon; 269 270 if (attr == &sensor_dev_attr_power1_max_interval.dev_attr.attr) 271 return i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit) ? attr->mode : 0; 272 273 return 0; 274 } 275 276 static const struct attribute_group hwm_attrgroup = { 277 .attrs = hwm_attributes, 278 .is_visible = hwm_attributes_visible, 279 }; 280 281 static const struct attribute_group *hwm_groups[] = { 282 &hwm_attrgroup, 283 NULL 284 }; 285 286 static const struct hwmon_channel_info * const hwm_info[] = { 287 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT), 288 HWMON_CHANNEL_INFO(in, HWMON_I_INPUT), 289 HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT), 290 HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT), 291 HWMON_CHANNEL_INFO(curr, HWMON_C_CRIT), 292 HWMON_CHANNEL_INFO(fan, HWMON_F_INPUT), 293 NULL 294 }; 295 296 static const struct hwmon_channel_info * const hwm_gt_info[] = { 297 HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT), 298 NULL 299 }; 300 301 /* I1 is exposed as power_crit or as curr_crit depending on bit 31 */ 302 static int hwm_pcode_read_i1(struct drm_i915_private *i915, u32 *uval) 303 { 304 /* Avoid ILLEGAL_SUBCOMMAND "mailbox access failed" warning in snb_pcode_read */ 305 if (IS_DG1(i915) || IS_DG2(i915)) 306 return -ENXIO; 307 308 return snb_pcode_read_p(&i915->uncore, PCODE_POWER_SETUP, 309 POWER_SETUP_SUBCOMMAND_READ_I1, 0, uval); 310 } 311 312 static int hwm_pcode_write_i1(struct drm_i915_private *i915, u32 uval) 313 { 314 return snb_pcode_write_p(&i915->uncore, PCODE_POWER_SETUP, 315 POWER_SETUP_SUBCOMMAND_WRITE_I1, 0, uval); 316 } 317 318 static umode_t 319 hwm_temp_is_visible(const struct hwm_drvdata *ddat, u32 attr) 320 { 321 struct i915_hwmon *hwmon = ddat->hwmon; 322 323 if (attr == hwmon_temp_input && i915_mmio_reg_valid(hwmon->rg.pkg_temp)) 324 return 0444; 325 326 return 0; 327 } 328 329 static int 330 hwm_temp_read(struct hwm_drvdata *ddat, u32 attr, long *val) 331 { 332 struct i915_hwmon *hwmon = ddat->hwmon; 333 intel_wakeref_t wakeref; 334 u32 reg_val; 335 336 switch (attr) { 337 case hwmon_temp_input: 338 with_intel_runtime_pm(ddat->uncore->rpm, wakeref) 339 reg_val = intel_uncore_read(ddat->uncore, hwmon->rg.pkg_temp); 340 341 /* HW register value is in degrees Celsius, convert to millidegrees. */ 342 *val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE; 343 return 0; 344 default: 345 return -EOPNOTSUPP; 346 } 347 } 348 349 static umode_t 350 hwm_in_is_visible(const struct hwm_drvdata *ddat, u32 attr) 351 { 352 struct drm_i915_private *i915 = ddat->uncore->i915; 353 354 switch (attr) { 355 case hwmon_in_input: 356 return IS_DG1(i915) || IS_DG2(i915) ? 0444 : 0; 357 default: 358 return 0; 359 } 360 } 361 362 static int 363 hwm_in_read(struct hwm_drvdata *ddat, u32 attr, long *val) 364 { 365 struct i915_hwmon *hwmon = ddat->hwmon; 366 intel_wakeref_t wakeref; 367 u32 reg_value; 368 369 switch (attr) { 370 case hwmon_in_input: 371 with_intel_runtime_pm(ddat->uncore->rpm, wakeref) 372 reg_value = intel_uncore_read(ddat->uncore, hwmon->rg.gt_perf_status); 373 /* HW register value in units of 2.5 millivolt */ 374 *val = DIV_ROUND_CLOSEST(REG_FIELD_GET(GEN12_VOLTAGE_MASK, reg_value) * 25, 10); 375 return 0; 376 default: 377 return -EOPNOTSUPP; 378 } 379 } 380 381 static umode_t 382 hwm_power_is_visible(const struct hwm_drvdata *ddat, u32 attr, int chan) 383 { 384 struct drm_i915_private *i915 = ddat->uncore->i915; 385 struct i915_hwmon *hwmon = ddat->hwmon; 386 u32 uval; 387 388 switch (attr) { 389 case hwmon_power_max: 390 return i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit) ? 0664 : 0; 391 case hwmon_power_rated_max: 392 return i915_mmio_reg_valid(hwmon->rg.pkg_power_sku) ? 0444 : 0; 393 case hwmon_power_crit: 394 return (hwm_pcode_read_i1(i915, &uval) || 395 !(uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644; 396 default: 397 return 0; 398 } 399 } 400 401 #define PL1_DISABLE 0 402 403 /* 404 * HW allows arbitrary PL1 limits to be set but silently clamps these values to 405 * "typical but not guaranteed" min/max values in rg.pkg_power_sku. Follow the 406 * same pattern for sysfs, allow arbitrary PL1 limits to be set but display 407 * clamped values when read. Write/read I1 also follows the same pattern. 408 */ 409 static int 410 hwm_power_max_read(struct hwm_drvdata *ddat, long *val) 411 { 412 struct i915_hwmon *hwmon = ddat->hwmon; 413 intel_wakeref_t wakeref; 414 u64 r, min, max; 415 416 /* Check if PL1 limit is disabled */ 417 with_intel_runtime_pm(ddat->uncore->rpm, wakeref) 418 r = intel_uncore_read(ddat->uncore, hwmon->rg.pkg_rapl_limit); 419 if (!(r & PKG_PWR_LIM_1_EN)) { 420 *val = PL1_DISABLE; 421 return 0; 422 } 423 424 *val = hwm_field_read_and_scale(ddat, 425 hwmon->rg.pkg_rapl_limit, 426 PKG_PWR_LIM_1, 427 hwmon->scl_shift_power, 428 SF_POWER); 429 430 with_intel_runtime_pm(ddat->uncore->rpm, wakeref) 431 r = intel_uncore_read64(ddat->uncore, hwmon->rg.pkg_power_sku); 432 min = REG_FIELD_GET(PKG_MIN_PWR, r); 433 min = mul_u64_u32_shr(min, SF_POWER, hwmon->scl_shift_power); 434 max = REG_FIELD_GET(PKG_MAX_PWR, r); 435 max = mul_u64_u32_shr(max, SF_POWER, hwmon->scl_shift_power); 436 437 if (min && max) 438 *val = clamp_t(u64, *val, min, max); 439 440 return 0; 441 } 442 443 static int 444 hwm_power_max_write(struct hwm_drvdata *ddat, long val) 445 { 446 struct i915_hwmon *hwmon = ddat->hwmon; 447 intel_wakeref_t wakeref; 448 DEFINE_WAIT(wait); 449 int ret = 0; 450 u32 nval; 451 452 /* Block waiting for GuC reset to complete when needed */ 453 for (;;) { 454 wakeref = intel_runtime_pm_get(ddat->uncore->rpm); 455 mutex_lock(&hwmon->hwmon_lock); 456 457 prepare_to_wait(&ddat->waitq, &wait, TASK_INTERRUPTIBLE); 458 459 if (!hwmon->ddat.reset_in_progress) 460 break; 461 462 if (signal_pending(current)) { 463 ret = -EINTR; 464 break; 465 } 466 467 mutex_unlock(&hwmon->hwmon_lock); 468 intel_runtime_pm_put(ddat->uncore->rpm, wakeref); 469 470 schedule(); 471 } 472 finish_wait(&ddat->waitq, &wait); 473 if (ret) 474 goto exit; 475 476 /* Disable PL1 limit and verify, because the limit cannot be disabled on all platforms */ 477 if (val == PL1_DISABLE) { 478 intel_uncore_rmw(ddat->uncore, hwmon->rg.pkg_rapl_limit, 479 PKG_PWR_LIM_1_EN, 0); 480 nval = intel_uncore_read(ddat->uncore, hwmon->rg.pkg_rapl_limit); 481 482 if (nval & PKG_PWR_LIM_1_EN) 483 ret = -ENODEV; 484 goto exit; 485 } 486 487 /* Computation in 64-bits to avoid overflow. Round to nearest. */ 488 nval = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_power, SF_POWER); 489 nval = PKG_PWR_LIM_1_EN | REG_FIELD_PREP(PKG_PWR_LIM_1, nval); 490 491 intel_uncore_rmw(ddat->uncore, hwmon->rg.pkg_rapl_limit, 492 PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, nval); 493 exit: 494 mutex_unlock(&hwmon->hwmon_lock); 495 intel_runtime_pm_put(ddat->uncore->rpm, wakeref); 496 return ret; 497 } 498 499 static int 500 hwm_power_read(struct hwm_drvdata *ddat, u32 attr, int chan, long *val) 501 { 502 struct i915_hwmon *hwmon = ddat->hwmon; 503 int ret; 504 u32 uval; 505 506 switch (attr) { 507 case hwmon_power_max: 508 return hwm_power_max_read(ddat, val); 509 case hwmon_power_rated_max: 510 *val = hwm_field_read_and_scale(ddat, 511 hwmon->rg.pkg_power_sku, 512 PKG_PKG_TDP, 513 hwmon->scl_shift_power, 514 SF_POWER); 515 return 0; 516 case hwmon_power_crit: 517 ret = hwm_pcode_read_i1(ddat->uncore->i915, &uval); 518 if (ret) 519 return ret; 520 if (!(uval & POWER_SETUP_I1_WATTS)) 521 return -ENODEV; 522 *val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval), 523 SF_POWER, POWER_SETUP_I1_SHIFT); 524 return 0; 525 default: 526 return -EOPNOTSUPP; 527 } 528 } 529 530 static int 531 hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int chan, long val) 532 { 533 u32 uval; 534 535 switch (attr) { 536 case hwmon_power_max: 537 return hwm_power_max_write(ddat, val); 538 case hwmon_power_crit: 539 uval = DIV_ROUND_CLOSEST_ULL(val << POWER_SETUP_I1_SHIFT, SF_POWER); 540 return hwm_pcode_write_i1(ddat->uncore->i915, uval); 541 default: 542 return -EOPNOTSUPP; 543 } 544 } 545 546 void i915_hwmon_power_max_disable(struct drm_i915_private *i915, bool *old) 547 { 548 struct i915_hwmon *hwmon = i915->hwmon; 549 u32 r; 550 551 if (!hwmon || !i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit)) 552 return; 553 554 mutex_lock(&hwmon->hwmon_lock); 555 556 hwmon->ddat.reset_in_progress = true; 557 r = intel_uncore_rmw(hwmon->ddat.uncore, hwmon->rg.pkg_rapl_limit, 558 PKG_PWR_LIM_1_EN, 0); 559 *old = !!(r & PKG_PWR_LIM_1_EN); 560 561 mutex_unlock(&hwmon->hwmon_lock); 562 } 563 564 void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old) 565 { 566 struct i915_hwmon *hwmon = i915->hwmon; 567 568 if (!hwmon || !i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit)) 569 return; 570 571 mutex_lock(&hwmon->hwmon_lock); 572 573 intel_uncore_rmw(hwmon->ddat.uncore, hwmon->rg.pkg_rapl_limit, 574 PKG_PWR_LIM_1_EN, old ? PKG_PWR_LIM_1_EN : 0); 575 hwmon->ddat.reset_in_progress = false; 576 wake_up_all(&hwmon->ddat.waitq); 577 578 mutex_unlock(&hwmon->hwmon_lock); 579 } 580 581 static umode_t 582 hwm_energy_is_visible(const struct hwm_drvdata *ddat, u32 attr) 583 { 584 struct i915_hwmon *hwmon = ddat->hwmon; 585 i915_reg_t rgaddr; 586 587 switch (attr) { 588 case hwmon_energy_input: 589 if (ddat->gt_n >= 0) 590 rgaddr = hwmon->rg.energy_status_tile; 591 else 592 rgaddr = hwmon->rg.energy_status_all; 593 return i915_mmio_reg_valid(rgaddr) ? 0444 : 0; 594 default: 595 return 0; 596 } 597 } 598 599 static int 600 hwm_energy_read(struct hwm_drvdata *ddat, u32 attr, long *val) 601 { 602 switch (attr) { 603 case hwmon_energy_input: 604 hwm_energy(ddat, val); 605 return 0; 606 default: 607 return -EOPNOTSUPP; 608 } 609 } 610 611 static umode_t 612 hwm_curr_is_visible(const struct hwm_drvdata *ddat, u32 attr) 613 { 614 struct drm_i915_private *i915 = ddat->uncore->i915; 615 u32 uval; 616 617 switch (attr) { 618 case hwmon_curr_crit: 619 return (hwm_pcode_read_i1(i915, &uval) || 620 (uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644; 621 default: 622 return 0; 623 } 624 } 625 626 static int 627 hwm_curr_read(struct hwm_drvdata *ddat, u32 attr, long *val) 628 { 629 int ret; 630 u32 uval; 631 632 switch (attr) { 633 case hwmon_curr_crit: 634 ret = hwm_pcode_read_i1(ddat->uncore->i915, &uval); 635 if (ret) 636 return ret; 637 if (uval & POWER_SETUP_I1_WATTS) 638 return -ENODEV; 639 *val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval), 640 SF_CURR, POWER_SETUP_I1_SHIFT); 641 return 0; 642 default: 643 return -EOPNOTSUPP; 644 } 645 } 646 647 static int 648 hwm_curr_write(struct hwm_drvdata *ddat, u32 attr, long val) 649 { 650 u32 uval; 651 652 switch (attr) { 653 case hwmon_curr_crit: 654 uval = DIV_ROUND_CLOSEST_ULL(val << POWER_SETUP_I1_SHIFT, SF_CURR); 655 return hwm_pcode_write_i1(ddat->uncore->i915, uval); 656 default: 657 return -EOPNOTSUPP; 658 } 659 } 660 661 static umode_t 662 hwm_fan_is_visible(const struct hwm_drvdata *ddat, u32 attr) 663 { 664 struct i915_hwmon *hwmon = ddat->hwmon; 665 666 if (attr == hwmon_fan_input && i915_mmio_reg_valid(hwmon->rg.fan_speed)) 667 return 0444; 668 669 return 0; 670 } 671 672 static int 673 hwm_fan_input_read(struct hwm_drvdata *ddat, long *val) 674 { 675 struct i915_hwmon *hwmon = ddat->hwmon; 676 struct hwm_fan_info *fi = &ddat->fi; 677 u64 rotations, time_now, time; 678 intel_wakeref_t wakeref; 679 u32 reg_val; 680 int ret = 0; 681 682 wakeref = intel_runtime_pm_get(ddat->uncore->rpm); 683 mutex_lock(&hwmon->hwmon_lock); 684 685 reg_val = intel_uncore_read(ddat->uncore, hwmon->rg.fan_speed); 686 time_now = get_jiffies_64(); 687 688 /* 689 * HW register value is accumulated count of pulses from 690 * PWM fan with the scale of 2 pulses per rotation. 691 */ 692 rotations = (reg_val - fi->reg_val_prev) / 2; 693 694 time = jiffies_delta_to_msecs(time_now - fi->time_prev); 695 if (unlikely(!time)) { 696 ret = -EAGAIN; 697 goto exit; 698 } 699 700 /* 701 * Calculate fan speed in RPM by time averaging two subsequent 702 * readings in minutes. 703 * RPM = number of rotations * msecs per minute / time in msecs 704 */ 705 *val = DIV_ROUND_UP_ULL(rotations * (MSEC_PER_SEC * 60), time); 706 707 fi->reg_val_prev = reg_val; 708 fi->time_prev = time_now; 709 exit: 710 mutex_unlock(&hwmon->hwmon_lock); 711 intel_runtime_pm_put(ddat->uncore->rpm, wakeref); 712 return ret; 713 } 714 715 static int 716 hwm_fan_read(struct hwm_drvdata *ddat, u32 attr, long *val) 717 { 718 if (attr == hwmon_fan_input) 719 return hwm_fan_input_read(ddat, val); 720 721 return -EOPNOTSUPP; 722 } 723 724 static umode_t 725 hwm_is_visible(const void *drvdata, enum hwmon_sensor_types type, 726 u32 attr, int channel) 727 { 728 struct hwm_drvdata *ddat = (struct hwm_drvdata *)drvdata; 729 730 switch (type) { 731 case hwmon_temp: 732 return hwm_temp_is_visible(ddat, attr); 733 case hwmon_in: 734 return hwm_in_is_visible(ddat, attr); 735 case hwmon_power: 736 return hwm_power_is_visible(ddat, attr, channel); 737 case hwmon_energy: 738 return hwm_energy_is_visible(ddat, attr); 739 case hwmon_curr: 740 return hwm_curr_is_visible(ddat, attr); 741 case hwmon_fan: 742 return hwm_fan_is_visible(ddat, attr); 743 default: 744 return 0; 745 } 746 } 747 748 static int 749 hwm_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, 750 int channel, long *val) 751 { 752 struct hwm_drvdata *ddat = dev_get_drvdata(dev); 753 754 switch (type) { 755 case hwmon_temp: 756 return hwm_temp_read(ddat, attr, val); 757 case hwmon_in: 758 return hwm_in_read(ddat, attr, val); 759 case hwmon_power: 760 return hwm_power_read(ddat, attr, channel, val); 761 case hwmon_energy: 762 return hwm_energy_read(ddat, attr, val); 763 case hwmon_curr: 764 return hwm_curr_read(ddat, attr, val); 765 case hwmon_fan: 766 return hwm_fan_read(ddat, attr, val); 767 default: 768 return -EOPNOTSUPP; 769 } 770 } 771 772 static int 773 hwm_write(struct device *dev, enum hwmon_sensor_types type, u32 attr, 774 int channel, long val) 775 { 776 struct hwm_drvdata *ddat = dev_get_drvdata(dev); 777 778 switch (type) { 779 case hwmon_power: 780 return hwm_power_write(ddat, attr, channel, val); 781 case hwmon_curr: 782 return hwm_curr_write(ddat, attr, val); 783 default: 784 return -EOPNOTSUPP; 785 } 786 } 787 788 static const struct hwmon_ops hwm_ops = { 789 .is_visible = hwm_is_visible, 790 .read = hwm_read, 791 .write = hwm_write, 792 }; 793 794 static const struct hwmon_chip_info hwm_chip_info = { 795 .ops = &hwm_ops, 796 .info = hwm_info, 797 }; 798 799 static umode_t 800 hwm_gt_is_visible(const void *drvdata, enum hwmon_sensor_types type, 801 u32 attr, int channel) 802 { 803 struct hwm_drvdata *ddat = (struct hwm_drvdata *)drvdata; 804 805 switch (type) { 806 case hwmon_energy: 807 return hwm_energy_is_visible(ddat, attr); 808 default: 809 return 0; 810 } 811 } 812 813 static int 814 hwm_gt_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, 815 int channel, long *val) 816 { 817 struct hwm_drvdata *ddat = dev_get_drvdata(dev); 818 819 switch (type) { 820 case hwmon_energy: 821 return hwm_energy_read(ddat, attr, val); 822 default: 823 return -EOPNOTSUPP; 824 } 825 } 826 827 static const struct hwmon_ops hwm_gt_ops = { 828 .is_visible = hwm_gt_is_visible, 829 .read = hwm_gt_read, 830 }; 831 832 static const struct hwmon_chip_info hwm_gt_chip_info = { 833 .ops = &hwm_gt_ops, 834 .info = hwm_gt_info, 835 }; 836 837 static void 838 hwm_get_preregistration_info(struct drm_i915_private *i915) 839 { 840 struct i915_hwmon *hwmon = i915->hwmon; 841 struct intel_uncore *uncore = &i915->uncore; 842 struct hwm_drvdata *ddat = &hwmon->ddat; 843 intel_wakeref_t wakeref; 844 u32 val_sku_unit = 0; 845 struct intel_gt *gt; 846 long energy; 847 int i; 848 849 /* Available for all Gen12+/dGfx */ 850 hwmon->rg.gt_perf_status = GEN12_RPSTAT1; 851 852 if (IS_DG1(i915) || IS_DG2(i915)) { 853 hwmon->rg.pkg_temp = PCU_PACKAGE_TEMPERATURE; 854 hwmon->rg.pkg_power_sku_unit = PCU_PACKAGE_POWER_SKU_UNIT; 855 hwmon->rg.pkg_power_sku = PCU_PACKAGE_POWER_SKU; 856 hwmon->rg.pkg_rapl_limit = PCU_PACKAGE_RAPL_LIMIT; 857 hwmon->rg.energy_status_all = PCU_PACKAGE_ENERGY_STATUS; 858 hwmon->rg.energy_status_tile = INVALID_MMIO_REG; 859 hwmon->rg.fan_speed = PCU_PWM_FAN_SPEED; 860 } else { 861 hwmon->rg.pkg_temp = INVALID_MMIO_REG; 862 hwmon->rg.pkg_power_sku_unit = INVALID_MMIO_REG; 863 hwmon->rg.pkg_power_sku = INVALID_MMIO_REG; 864 hwmon->rg.pkg_rapl_limit = INVALID_MMIO_REG; 865 hwmon->rg.energy_status_all = INVALID_MMIO_REG; 866 hwmon->rg.energy_status_tile = INVALID_MMIO_REG; 867 hwmon->rg.fan_speed = INVALID_MMIO_REG; 868 } 869 870 with_intel_runtime_pm(uncore->rpm, wakeref) { 871 /* 872 * The contents of register hwmon->rg.pkg_power_sku_unit do not change, 873 * so read it once and store the shift values. 874 */ 875 if (i915_mmio_reg_valid(hwmon->rg.pkg_power_sku_unit)) 876 val_sku_unit = intel_uncore_read(uncore, 877 hwmon->rg.pkg_power_sku_unit); 878 879 /* 880 * Store the initial fan register value, so that we can use it for 881 * initial fan speed calculation. 882 */ 883 if (i915_mmio_reg_valid(hwmon->rg.fan_speed)) { 884 ddat->fi.reg_val_prev = intel_uncore_read(uncore, 885 hwmon->rg.fan_speed); 886 ddat->fi.time_prev = get_jiffies_64(); 887 } 888 } 889 890 hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit); 891 hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit); 892 hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT, val_sku_unit); 893 894 /* 895 * Initialize 'struct hwm_energy_info', i.e. set fields to the 896 * first value of the energy register read 897 */ 898 if (i915_mmio_reg_valid(hwmon->rg.energy_status_all)) 899 hwm_energy(ddat, &energy); 900 if (i915_mmio_reg_valid(hwmon->rg.energy_status_tile)) { 901 for_each_gt(gt, i915, i) 902 hwm_energy(&hwmon->ddat_gt[i], &energy); 903 } 904 } 905 906 void i915_hwmon_register(struct drm_i915_private *i915) 907 { 908 struct device *dev = i915->drm.dev; 909 struct i915_hwmon *hwmon; 910 struct device *hwmon_dev; 911 struct hwm_drvdata *ddat; 912 struct hwm_drvdata *ddat_gt; 913 struct intel_gt *gt; 914 int i; 915 916 /* hwmon is available only for dGfx */ 917 if (!IS_DGFX(i915)) 918 return; 919 920 hwmon = kzalloc_obj(*hwmon); 921 if (!hwmon) 922 return; 923 924 i915->hwmon = hwmon; 925 mutex_init(&hwmon->hwmon_lock); 926 ddat = &hwmon->ddat; 927 928 ddat->hwmon = hwmon; 929 ddat->uncore = &i915->uncore; 930 snprintf(ddat->name, sizeof(ddat->name), "i915"); 931 ddat->gt_n = -1; 932 init_waitqueue_head(&ddat->waitq); 933 934 for_each_gt(gt, i915, i) { 935 ddat_gt = hwmon->ddat_gt + i; 936 937 ddat_gt->hwmon = hwmon; 938 ddat_gt->uncore = gt->uncore; 939 snprintf(ddat_gt->name, sizeof(ddat_gt->name), "i915_gt%u", i); 940 ddat_gt->gt_n = i; 941 } 942 943 hwm_get_preregistration_info(i915); 944 945 /* hwmon_dev points to device hwmon<i> */ 946 hwmon_dev = hwmon_device_register_with_info(dev, ddat->name, 947 ddat, 948 &hwm_chip_info, 949 hwm_groups); 950 if (IS_ERR(hwmon_dev)) 951 goto err; 952 953 ddat->hwmon_dev = hwmon_dev; 954 955 for_each_gt(gt, i915, i) { 956 ddat_gt = hwmon->ddat_gt + i; 957 /* 958 * Create per-gt directories only if a per-gt attribute is 959 * visible. Currently this is only energy 960 */ 961 if (!hwm_gt_is_visible(ddat_gt, hwmon_energy, hwmon_energy_input, 0)) 962 continue; 963 964 hwmon_dev = hwmon_device_register_with_info(dev, ddat_gt->name, 965 ddat_gt, 966 &hwm_gt_chip_info, 967 NULL); 968 if (!IS_ERR(hwmon_dev)) 969 ddat_gt->hwmon_dev = hwmon_dev; 970 } 971 return; 972 err: 973 i915_hwmon_unregister(i915); 974 } 975 976 void i915_hwmon_unregister(struct drm_i915_private *i915) 977 { 978 struct i915_hwmon *hwmon = i915->hwmon; 979 struct intel_gt *gt; 980 int i; 981 982 if (!hwmon) 983 return; 984 985 for_each_gt(gt, i915, i) 986 if (hwmon->ddat_gt[i].hwmon_dev) 987 hwmon_device_unregister(hwmon->ddat_gt[i].hwmon_dev); 988 989 if (hwmon->ddat.hwmon_dev) 990 hwmon_device_unregister(hwmon->ddat.hwmon_dev); 991 992 mutex_destroy(&hwmon->hwmon_lock); 993 994 kfree(i915->hwmon); 995 i915->hwmon = NULL; 996 } 997