xref: /linux/drivers/gpu/drm/i915/i915_gpu_error.h (revision cbaf84e73811ed0ff7ff6d7f52b73fd7ed082d65)
1 /*
2  * SPDX-License-Identifier: MIT
3  *
4  * Copyright © 2008-2018 Intel Corporation
5  */
6 
7 #ifndef _I915_GPU_ERROR_H_
8 #define _I915_GPU_ERROR_H_
9 
10 #include <linux/atomic.h>
11 #include <linux/kref.h>
12 #include <linux/ktime.h>
13 #include <linux/sched.h>
14 
15 #include <drm/drm_mm.h>
16 
17 #include "display/intel_display_device.h"
18 #include "display/intel_display_params.h"
19 #include "gt/intel_engine.h"
20 #include "gt/intel_gt_types.h"
21 #include "gt/uc/intel_uc_fw.h"
22 
23 #include "intel_device_info.h"
24 
25 #include "i915_gem.h"
26 #include "i915_gem_gtt.h"
27 #include "i915_params.h"
28 #include "i915_scheduler.h"
29 
30 struct drm_i915_private;
31 struct i915_vma_compress;
32 struct intel_engine_capture_vma;
33 struct intel_overlay_error_state;
34 
35 struct i915_vma_coredump {
36 	struct i915_vma_coredump *next;
37 
38 	char name[20];
39 
40 	u64 gtt_offset;
41 	u64 gtt_size;
42 	u32 gtt_page_sizes;
43 
44 	int unused;
45 	struct list_head page_list;
46 };
47 
48 struct i915_request_coredump {
49 	unsigned long flags;
50 	pid_t pid;
51 	u32 context;
52 	u32 seqno;
53 	u32 head;
54 	u32 tail;
55 	struct i915_sched_attr sched_attr;
56 };
57 
58 struct __guc_capture_parsed_output;
59 
60 struct intel_engine_coredump {
61 	const struct intel_engine_cs *engine;
62 
63 	bool hung;
64 	bool simulated;
65 	u32 reset_count;
66 
67 	/* position of active request inside the ring */
68 	u32 rq_head, rq_post, rq_tail;
69 
70 	/* Register state */
71 	u32 ccid;
72 	u32 start;
73 	u32 tail;
74 	u32 head;
75 	u32 ctl;
76 	u32 mode;
77 	u32 hws;
78 	u32 ipeir;
79 	u32 ipehr;
80 	u32 esr;
81 	u32 bbstate;
82 	u32 instpm;
83 	u32 instps;
84 	u64 bbaddr;
85 	u64 acthd;
86 	u32 fault_reg;
87 	u64 faddr;
88 	u32 rc_psmi; /* sleep state */
89 	u32 nopid;
90 	u32 excc;
91 	u32 cmd_cctl;
92 	u32 cscmdop;
93 	u32 ctx_sr_ctl;
94 	u32 dma_faddr_hi;
95 	u32 dma_faddr_lo;
96 	struct intel_instdone instdone;
97 
98 	/* GuC matched capture-lists info */
99 	struct intel_guc_state_capture *guc_capture;
100 	struct __guc_capture_parsed_output *guc_capture_node;
101 
102 	struct i915_gem_context_coredump {
103 		char comm[TASK_COMM_LEN];
104 
105 		u64 total_runtime;
106 		u64 avg_runtime;
107 
108 		pid_t pid;
109 		int active;
110 		int guilty;
111 		struct i915_sched_attr sched_attr;
112 		u32 hwsp_seqno;
113 	} context;
114 
115 	struct i915_vma_coredump *vma;
116 
117 	struct i915_request_coredump execlist[EXECLIST_MAX_PORTS];
118 	unsigned int num_ports;
119 
120 	struct {
121 		u32 gfx_mode;
122 		union {
123 			u64 pdp[4];
124 			u32 pp_dir_base;
125 		};
126 	} vm_info;
127 
128 	struct intel_engine_coredump *next;
129 };
130 
131 struct intel_ctb_coredump {
132 	u32 raw_head, head;
133 	u32 raw_tail, tail;
134 	u32 raw_status;
135 	u32 desc_offset;
136 	u32 cmds_offset;
137 	u32 size;
138 };
139 
140 struct intel_gt_coredump {
141 	const struct intel_gt *_gt;
142 	bool awake;
143 	bool simulated;
144 
145 	struct intel_gt_info info;
146 
147 	/* Generic register state */
148 	u32 eir;
149 	u32 pgtbl_er;
150 	u32 ier;
151 	u32 gtier[6], ngtier;
152 	u32 forcewake;
153 	u32 error; /* gen6+ */
154 	u32 err_int; /* gen7 */
155 	u32 fault_data0; /* gen8, gen9 */
156 	u32 fault_data1; /* gen8, gen9 */
157 	u32 done_reg;
158 	u32 gac_eco;
159 	u32 gam_ecochk;
160 	u32 gab_ctl;
161 	u32 gfx_mode;
162 	u32 gtt_cache;
163 	u32 aux_err; /* gen12 */
164 	u32 gam_done; /* gen12 */
165 	u32 clock_frequency;
166 	u32 clock_period_ns;
167 
168 	/* Display related */
169 	u32 derrmr;
170 	u32 sfc_done[I915_MAX_SFC]; /* gen12 */
171 
172 	u32 nfence;
173 	u64 fence[I915_MAX_NUM_FENCES];
174 
175 	struct intel_engine_coredump *engine;
176 
177 	struct intel_uc_coredump {
178 		struct intel_uc_fw guc_fw;
179 		struct intel_uc_fw huc_fw;
180 		struct guc_info {
181 			struct intel_ctb_coredump ctb[2];
182 			struct i915_vma_coredump *vma_ctb;
183 			struct i915_vma_coredump *vma_log;
184 			u32 timestamp;
185 			u16 last_fence;
186 			bool is_guc_capture;
187 		} guc;
188 	} *uc;
189 
190 	struct intel_gt_coredump *next;
191 };
192 
193 struct i915_gpu_coredump {
194 	struct kref ref;
195 	ktime_t time;
196 	ktime_t boottime;
197 	ktime_t uptime;
198 	unsigned long capture;
199 
200 	struct drm_i915_private *i915;
201 
202 	struct intel_gt_coredump *gt;
203 
204 	char error_msg[128];
205 	bool simulated;
206 	bool wakelock;
207 	bool suspended;
208 	int iommu;
209 	u32 reset_count;
210 	u32 suspend_count;
211 
212 	struct intel_device_info device_info;
213 	struct intel_runtime_info runtime_info;
214 	struct intel_display_device_info display_device_info;
215 	struct intel_display_runtime_info display_runtime_info;
216 	struct intel_driver_caps driver_caps;
217 	struct i915_params params;
218 	struct intel_display_params display_params;
219 
220 	struct intel_overlay_error_state *overlay;
221 
222 	struct scatterlist *sgl, *fit;
223 };
224 
225 struct i915_gpu_error {
226 	/* For reset and error_state handling. */
227 	spinlock_t lock;
228 	/* Protected by the above dev->gpu_error.lock. */
229 	struct i915_gpu_coredump *first_error;
230 
231 	atomic_t pending_fb_pin;
232 
233 	/** Number of times the device has been reset (global) */
234 	atomic_t reset_count;
235 
236 	/** Number of times an engine has been reset */
237 	atomic_t reset_engine_count[I915_NUM_ENGINES];
238 };
239 
240 struct drm_i915_error_state_buf {
241 	struct drm_i915_private *i915;
242 	struct scatterlist *sgl, *cur, *end;
243 
244 	char *buf;
245 	size_t bytes;
246 	size_t size;
247 	loff_t iter;
248 
249 	int err;
250 };
251 
252 static inline u32 i915_reset_count(struct i915_gpu_error *error)
253 {
254 	return atomic_read(&error->reset_count);
255 }
256 
257 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
258 					  const struct intel_engine_cs *engine)
259 {
260 	return atomic_read(&error->reset_engine_count[engine->uabi_class]);
261 }
262 
263 #define CORE_DUMP_FLAG_NONE           0x0
264 #define CORE_DUMP_FLAG_IS_GUC_CAPTURE BIT(0)
265 
266 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) && IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
267 void intel_klog_error_capture(struct intel_gt *gt,
268 			      intel_engine_mask_t engine_mask);
269 #else
270 static inline void intel_klog_error_capture(struct intel_gt *gt,
271 					    intel_engine_mask_t engine_mask)
272 {
273 }
274 #endif
275 
276 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
277 
278 __printf(2, 3)
279 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
280 void intel_gpu_error_print_vma(struct drm_i915_error_state_buf *m,
281 			       const struct intel_engine_cs *engine,
282 			       const struct i915_vma_coredump *vma);
283 struct i915_vma_coredump *
284 intel_gpu_error_find_batch(const struct intel_engine_coredump *ee);
285 
286 struct i915_gpu_coredump *i915_gpu_coredump(struct intel_gt *gt,
287 					    intel_engine_mask_t engine_mask, u32 dump_flags);
288 void i915_capture_error_state(struct intel_gt *gt,
289 			      intel_engine_mask_t engine_mask, u32 dump_flags);
290 
291 struct i915_gpu_coredump *
292 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp);
293 
294 struct intel_gt_coredump *
295 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags);
296 
297 struct intel_engine_coredump *
298 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags);
299 
300 struct intel_engine_capture_vma *
301 intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
302 				  struct i915_request *rq,
303 				  gfp_t gfp);
304 
305 void intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
306 				   struct intel_engine_capture_vma *capture,
307 				   struct i915_vma_compress *compress);
308 
309 struct i915_vma_compress *
310 i915_vma_capture_prepare(struct intel_gt_coredump *gt);
311 
312 void i915_vma_capture_finish(struct intel_gt_coredump *gt,
313 			     struct i915_vma_compress *compress);
314 
315 void i915_error_state_store(struct i915_gpu_coredump *error);
316 
317 static inline struct i915_gpu_coredump *
318 i915_gpu_coredump_get(struct i915_gpu_coredump *gpu)
319 {
320 	kref_get(&gpu->ref);
321 	return gpu;
322 }
323 
324 ssize_t
325 i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error,
326 				 char *buf, loff_t offset, size_t count);
327 
328 void __i915_gpu_coredump_free(struct kref *kref);
329 static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu)
330 {
331 	if (gpu)
332 		kref_put(&gpu->ref, __i915_gpu_coredump_free);
333 }
334 
335 struct i915_gpu_coredump *i915_first_error_state(struct drm_i915_private *i915);
336 void i915_reset_error_state(struct drm_i915_private *i915);
337 void i915_disable_error_state(struct drm_i915_private *i915, int err);
338 
339 #else
340 
341 __printf(2, 3)
342 static inline void
343 i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
344 {
345 }
346 
347 static inline void
348 i915_capture_error_state(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags)
349 {
350 }
351 
352 static inline struct i915_gpu_coredump *
353 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp)
354 {
355 	return NULL;
356 }
357 
358 static inline struct intel_gt_coredump *
359 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags)
360 {
361 	return NULL;
362 }
363 
364 static inline struct intel_engine_coredump *
365 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags)
366 {
367 	return NULL;
368 }
369 
370 static inline struct intel_engine_capture_vma *
371 intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
372 				  struct i915_request *rq,
373 				  gfp_t gfp)
374 {
375 	return NULL;
376 }
377 
378 static inline void
379 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
380 			      struct intel_engine_capture_vma *capture,
381 			      struct i915_vma_compress *compress)
382 {
383 }
384 
385 static inline struct i915_vma_compress *
386 i915_vma_capture_prepare(struct intel_gt_coredump *gt)
387 {
388 	return NULL;
389 }
390 
391 static inline void
392 i915_vma_capture_finish(struct intel_gt_coredump *gt,
393 			struct i915_vma_compress *compress)
394 {
395 }
396 
397 static inline void
398 i915_error_state_store(struct i915_gpu_coredump *error)
399 {
400 }
401 
402 static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu)
403 {
404 }
405 
406 static inline struct i915_gpu_coredump *
407 i915_first_error_state(struct drm_i915_private *i915)
408 {
409 	return ERR_PTR(-ENODEV);
410 }
411 
412 static inline void i915_reset_error_state(struct drm_i915_private *i915)
413 {
414 }
415 
416 static inline void i915_disable_error_state(struct drm_i915_private *i915,
417 					    int err)
418 {
419 }
420 
421 #endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */
422 
423 #endif /* _I915_GPU_ERROR_H_ */
424