1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright © 2008-2018 Intel Corporation 5 */ 6 7 #ifndef _I915_GPU_ERROR_H_ 8 #define _I915_GPU_ERROR_H_ 9 10 #include <linux/atomic.h> 11 #include <linux/kref.h> 12 #include <linux/ktime.h> 13 #include <linux/sched.h> 14 15 #include <drm/drm_mm.h> 16 17 #include "gt/intel_engine.h" 18 #include "gt/intel_engine_types.h" 19 #include "gt/intel_gt_types.h" 20 #include "gt/uc/intel_uc_fw.h" 21 22 #include "intel_device_info.h" 23 24 #include "i915_gem.h" 25 #include "i915_gem_gtt.h" 26 #include "i915_params.h" 27 #include "i915_scheduler.h" 28 29 struct drm_i915_private; 30 struct i915_vma_compress; 31 struct intel_engine_capture_vma; 32 struct intel_display_snapshot; 33 34 struct i915_vma_coredump { 35 struct i915_vma_coredump *next; 36 37 char name[20]; 38 39 u64 gtt_offset; 40 u64 gtt_size; 41 u32 gtt_page_sizes; 42 43 int unused; 44 struct list_head page_list; 45 }; 46 47 struct i915_request_coredump { 48 unsigned long flags; 49 pid_t pid; 50 u32 context; 51 u32 seqno; 52 u32 head; 53 u32 tail; 54 struct i915_sched_attr sched_attr; 55 }; 56 57 struct __guc_capture_parsed_output; 58 59 struct intel_engine_coredump { 60 const struct intel_engine_cs *engine; 61 62 bool hung; 63 bool simulated; 64 u32 reset_count; 65 66 /* position of active request inside the ring */ 67 u32 rq_head, rq_post, rq_tail; 68 69 /* Register state */ 70 u32 ccid; 71 u32 start; 72 u32 tail; 73 u32 head; 74 u32 ctl; 75 u32 mode; 76 u32 hws; 77 u32 ipeir; 78 u32 ipehr; 79 u32 esr; 80 u32 bbstate; 81 u32 instpm; 82 u32 instps; 83 u64 bbaddr; 84 u64 acthd; 85 u32 fault_reg; 86 u64 faddr; 87 u32 rc_psmi; /* sleep state */ 88 u32 nopid; 89 u32 excc; 90 u32 cmd_cctl; 91 u32 cscmdop; 92 u32 ctx_sr_ctl; 93 u32 dma_faddr_hi; 94 u32 dma_faddr_lo; 95 struct intel_instdone instdone; 96 97 /* GuC matched capture-lists info */ 98 struct intel_guc_state_capture *guc_capture; 99 struct __guc_capture_parsed_output *guc_capture_node; 100 101 struct i915_gem_context_coredump { 102 char comm[TASK_COMM_LEN]; 103 104 u64 total_runtime; 105 u64 avg_runtime; 106 107 pid_t pid; 108 int active; 109 int guilty; 110 struct i915_sched_attr sched_attr; 111 u32 hwsp_seqno; 112 } context; 113 114 struct i915_vma_coredump *vma; 115 116 struct i915_request_coredump execlist[EXECLIST_MAX_PORTS]; 117 unsigned int num_ports; 118 119 struct { 120 u32 gfx_mode; 121 union { 122 u64 pdp[4]; 123 u32 pp_dir_base; 124 }; 125 } vm_info; 126 127 struct intel_engine_coredump *next; 128 }; 129 130 struct intel_ctb_coredump { 131 u32 raw_head, head; 132 u32 raw_tail, tail; 133 u32 raw_status; 134 u32 desc_offset; 135 u32 cmds_offset; 136 u32 size; 137 }; 138 139 struct intel_gt_coredump { 140 const struct intel_gt *_gt; 141 bool awake; 142 bool simulated; 143 144 struct intel_gt_info info; 145 146 /* Generic register state */ 147 u32 eir; 148 u32 pgtbl_er; 149 u32 gtier[6], ngtier; 150 u32 forcewake; 151 u32 error; /* gen6+ */ 152 u32 err_int; /* gen7 */ 153 u32 fault_data0; /* gen8, gen9 */ 154 u32 fault_data1; /* gen8, gen9 */ 155 u32 done_reg; 156 u32 gac_eco; 157 u32 gam_ecochk; 158 u32 gab_ctl; 159 u32 gfx_mode; 160 u32 gtt_cache; 161 u32 aux_err; /* gen12 */ 162 u32 gam_done; /* gen12 */ 163 u32 clock_frequency; 164 u32 clock_period_ns; 165 166 u32 sfc_done[I915_MAX_SFC]; /* gen12 */ 167 168 u32 nfence; 169 u64 fence[I915_MAX_NUM_FENCES]; 170 171 struct intel_engine_coredump *engine; 172 173 struct intel_uc_coredump { 174 struct intel_uc_fw guc_fw; 175 struct intel_uc_fw huc_fw; 176 struct guc_info { 177 struct intel_ctb_coredump ctb[2]; 178 struct i915_vma_coredump *vma_ctb; 179 struct i915_vma_coredump *vma_log; 180 u32 timestamp; 181 u16 last_fence; 182 bool is_guc_capture; 183 } guc; 184 } *uc; 185 186 struct intel_gt_coredump *next; 187 }; 188 189 struct i915_gpu_coredump { 190 struct kref ref; 191 ktime_t time; 192 ktime_t boottime; 193 ktime_t uptime; 194 unsigned long capture; 195 196 struct drm_i915_private *i915; 197 198 struct intel_gt_coredump *gt; 199 200 char error_msg[128]; 201 bool simulated; 202 bool wakelock; 203 bool suspended; 204 int iommu; 205 u32 reset_count; 206 u32 suspend_count; 207 208 struct intel_device_info device_info; 209 struct intel_runtime_info runtime_info; 210 struct intel_driver_caps driver_caps; 211 struct i915_params params; 212 213 struct scatterlist *sgl, *fit; 214 215 struct intel_display_snapshot *display_snapshot; 216 }; 217 218 struct i915_gpu_error { 219 /* For reset and error_state handling. */ 220 spinlock_t lock; 221 /* Protected by the above dev->gpu_error.lock. */ 222 struct i915_gpu_coredump *first_error; 223 224 /** Number of times the device has been reset (global) */ 225 atomic_t reset_count; 226 227 /** Number of times an engine has been reset */ 228 atomic_t reset_engine_count[MAX_ENGINE_CLASS]; 229 }; 230 231 struct drm_i915_error_state_buf { 232 struct drm_i915_private *i915; 233 struct scatterlist *sgl, *cur, *end; 234 235 char *buf; 236 size_t bytes; 237 size_t size; 238 loff_t iter; 239 240 int err; 241 }; 242 243 static inline u32 i915_reset_count(struct i915_gpu_error *error) 244 { 245 return atomic_read(&error->reset_count); 246 } 247 248 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error, 249 const struct intel_engine_cs *engine) 250 { 251 return atomic_read(&error->reset_engine_count[engine->class]); 252 } 253 254 static inline void 255 i915_increase_reset_engine_count(struct i915_gpu_error *error, 256 const struct intel_engine_cs *engine) 257 { 258 atomic_inc(&error->reset_engine_count[engine->class]); 259 } 260 261 #define CORE_DUMP_FLAG_NONE 0x0 262 #define CORE_DUMP_FLAG_IS_GUC_CAPTURE BIT(0) 263 264 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) && IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) 265 void intel_klog_error_capture(struct intel_gt *gt, 266 intel_engine_mask_t engine_mask); 267 #else 268 static inline void intel_klog_error_capture(struct intel_gt *gt, 269 intel_engine_mask_t engine_mask) 270 { 271 } 272 #endif 273 274 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 275 276 __printf(2, 3) 277 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); 278 279 void i915_capture_error_state(struct intel_gt *gt, 280 intel_engine_mask_t engine_mask, u32 dump_flags); 281 282 struct i915_gpu_coredump * 283 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp); 284 285 struct intel_gt_coredump * 286 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags); 287 288 struct intel_engine_coredump * 289 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags); 290 291 struct intel_engine_capture_vma * 292 intel_engine_coredump_add_request(struct intel_engine_coredump *ee, 293 struct i915_request *rq, 294 gfp_t gfp); 295 296 void intel_engine_coredump_add_vma(struct intel_engine_coredump *ee, 297 struct intel_engine_capture_vma *capture, 298 struct i915_vma_compress *compress); 299 300 struct i915_vma_compress * 301 i915_vma_capture_prepare(struct intel_gt_coredump *gt); 302 303 void i915_vma_capture_finish(struct intel_gt_coredump *gt, 304 struct i915_vma_compress *compress); 305 306 void i915_error_state_store(struct i915_gpu_coredump *error); 307 308 static inline struct i915_gpu_coredump * 309 i915_gpu_coredump_get(struct i915_gpu_coredump *gpu) 310 { 311 kref_get(&gpu->ref); 312 return gpu; 313 } 314 315 ssize_t 316 i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error, 317 char *buf, loff_t offset, size_t count); 318 319 void __i915_gpu_coredump_free(struct kref *kref); 320 static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu) 321 { 322 if (gpu) 323 kref_put(&gpu->ref, __i915_gpu_coredump_free); 324 } 325 326 void i915_reset_error_state(struct drm_i915_private *i915); 327 void i915_disable_error_state(struct drm_i915_private *i915, int err); 328 329 void i915_gpu_error_debugfs_register(struct drm_i915_private *i915); 330 void i915_gpu_error_sysfs_setup(struct drm_i915_private *i915); 331 void i915_gpu_error_sysfs_teardown(struct drm_i915_private *i915); 332 333 #else 334 335 __printf(2, 3) 336 static inline void 337 i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 338 { 339 } 340 341 static inline void 342 i915_capture_error_state(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags) 343 { 344 } 345 346 static inline struct i915_gpu_coredump * 347 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp) 348 { 349 return NULL; 350 } 351 352 static inline struct intel_gt_coredump * 353 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags) 354 { 355 return NULL; 356 } 357 358 static inline struct intel_engine_coredump * 359 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags) 360 { 361 return NULL; 362 } 363 364 static inline struct intel_engine_capture_vma * 365 intel_engine_coredump_add_request(struct intel_engine_coredump *ee, 366 struct i915_request *rq, 367 gfp_t gfp) 368 { 369 return NULL; 370 } 371 372 static inline void 373 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee, 374 struct intel_engine_capture_vma *capture, 375 struct i915_vma_compress *compress) 376 { 377 } 378 379 static inline struct i915_vma_compress * 380 i915_vma_capture_prepare(struct intel_gt_coredump *gt) 381 { 382 return NULL; 383 } 384 385 static inline void 386 i915_vma_capture_finish(struct intel_gt_coredump *gt, 387 struct i915_vma_compress *compress) 388 { 389 } 390 391 static inline void 392 i915_error_state_store(struct i915_gpu_coredump *error) 393 { 394 } 395 396 static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu) 397 { 398 } 399 400 static inline void i915_reset_error_state(struct drm_i915_private *i915) 401 { 402 } 403 404 static inline void i915_disable_error_state(struct drm_i915_private *i915, 405 int err) 406 { 407 } 408 409 static inline void i915_gpu_error_debugfs_register(struct drm_i915_private *i915) 410 { 411 } 412 413 static inline void i915_gpu_error_sysfs_setup(struct drm_i915_private *i915) 414 { 415 } 416 417 static inline void i915_gpu_error_sysfs_teardown(struct drm_i915_private *i915) 418 { 419 } 420 421 #endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */ 422 423 #endif /* _I915_GPU_ERROR_H_ */ 424