1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright � 2008-2018 Intel Corporation 5 */ 6 7 #ifndef _I915_GPU_ERROR_H_ 8 #define _I915_GPU_ERROR_H_ 9 10 #include <linux/atomic.h> 11 #include <linux/kref.h> 12 #include <linux/ktime.h> 13 #include <linux/sched.h> 14 15 #include <drm/drm_mm.h> 16 17 #include "gt/intel_engine.h" 18 #include "gt/uc/intel_uc_fw.h" 19 20 #include "intel_device_info.h" 21 22 #include "i915_gem.h" 23 #include "i915_gem_gtt.h" 24 #include "i915_params.h" 25 #include "i915_scheduler.h" 26 27 struct drm_i915_private; 28 struct intel_overlay_error_state; 29 struct intel_display_error_state; 30 31 struct i915_gpu_state { 32 struct kref ref; 33 ktime_t time; 34 ktime_t boottime; 35 ktime_t uptime; 36 unsigned long capture; 37 38 struct drm_i915_private *i915; 39 40 char error_msg[128]; 41 bool simulated; 42 bool awake; 43 bool wakelock; 44 bool suspended; 45 int iommu; 46 u32 reset_count; 47 u32 suspend_count; 48 struct intel_device_info device_info; 49 struct intel_runtime_info runtime_info; 50 struct intel_driver_caps driver_caps; 51 struct i915_params params; 52 53 struct i915_error_uc { 54 struct intel_uc_fw guc_fw; 55 struct intel_uc_fw huc_fw; 56 struct drm_i915_error_object *guc_log; 57 } uc; 58 59 /* Generic register state */ 60 u32 eir; 61 u32 pgtbl_er; 62 u32 ier; 63 u32 gtier[6], ngtier; 64 u32 ccid; 65 u32 derrmr; 66 u32 forcewake; 67 u32 error; /* gen6+ */ 68 u32 err_int; /* gen7 */ 69 u32 fault_data0; /* gen8, gen9 */ 70 u32 fault_data1; /* gen8, gen9 */ 71 u32 done_reg; 72 u32 gac_eco; 73 u32 gam_ecochk; 74 u32 gab_ctl; 75 u32 gfx_mode; 76 u32 gtt_cache; 77 u32 aux_err; /* gen12 */ 78 u32 sfc_done[GEN12_SFC_DONE_MAX]; /* gen12 */ 79 u32 gam_done; /* gen12 */ 80 81 u32 nfence; 82 u64 fence[I915_MAX_NUM_FENCES]; 83 struct intel_overlay_error_state *overlay; 84 struct intel_display_error_state *display; 85 86 struct drm_i915_error_engine { 87 const struct intel_engine_cs *engine; 88 89 /* Software tracked state */ 90 bool idle; 91 int num_requests; 92 u32 reset_count; 93 94 /* position of active request inside the ring */ 95 u32 rq_head, rq_post, rq_tail; 96 97 /* our own tracking of ring head and tail */ 98 u32 cpu_ring_head; 99 u32 cpu_ring_tail; 100 101 /* Register state */ 102 u32 start; 103 u32 tail; 104 u32 head; 105 u32 ctl; 106 u32 mode; 107 u32 hws; 108 u32 ipeir; 109 u32 ipehr; 110 u32 bbstate; 111 u32 instpm; 112 u32 instps; 113 u64 bbaddr; 114 u64 acthd; 115 u32 fault_reg; 116 u64 faddr; 117 u32 rc_psmi; /* sleep state */ 118 struct intel_instdone instdone; 119 120 struct drm_i915_error_context { 121 char comm[TASK_COMM_LEN]; 122 pid_t pid; 123 int active; 124 int guilty; 125 struct i915_sched_attr sched_attr; 126 } context; 127 128 struct drm_i915_error_object { 129 u64 gtt_offset; 130 u64 gtt_size; 131 u32 gtt_page_sizes; 132 int num_pages; 133 int page_count; 134 int unused; 135 u32 *pages[0]; 136 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; 137 138 struct drm_i915_error_object **user_bo; 139 long user_bo_count; 140 141 struct drm_i915_error_object *wa_ctx; 142 struct drm_i915_error_object *default_state; 143 144 struct drm_i915_error_request { 145 unsigned long flags; 146 long jiffies; 147 pid_t pid; 148 u32 context; 149 u32 seqno; 150 u32 start; 151 u32 head; 152 u32 tail; 153 struct i915_sched_attr sched_attr; 154 } *requests, execlist[EXECLIST_MAX_PORTS]; 155 unsigned int num_ports; 156 157 struct { 158 u32 gfx_mode; 159 union { 160 u64 pdp[4]; 161 u32 pp_dir_base; 162 }; 163 } vm_info; 164 165 struct drm_i915_error_engine *next; 166 } *engine; 167 168 struct scatterlist *sgl, *fit; 169 }; 170 171 struct i915_gpu_error { 172 /* For reset and error_state handling. */ 173 spinlock_t lock; 174 /* Protected by the above dev->gpu_error.lock. */ 175 struct i915_gpu_state *first_error; 176 177 atomic_t pending_fb_pin; 178 179 /** Number of times the device has been reset (global) */ 180 atomic_t reset_count; 181 182 /** Number of times an engine has been reset */ 183 atomic_t reset_engine_count[I915_NUM_ENGINES]; 184 }; 185 186 struct drm_i915_error_state_buf { 187 struct drm_i915_private *i915; 188 struct scatterlist *sgl, *cur, *end; 189 190 char *buf; 191 size_t bytes; 192 size_t size; 193 loff_t iter; 194 195 int err; 196 }; 197 198 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 199 200 __printf(2, 3) 201 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); 202 203 struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915); 204 void i915_capture_error_state(struct drm_i915_private *dev_priv, 205 intel_engine_mask_t engine_mask, 206 const char *error_msg); 207 208 static inline struct i915_gpu_state * 209 i915_gpu_state_get(struct i915_gpu_state *gpu) 210 { 211 kref_get(&gpu->ref); 212 return gpu; 213 } 214 215 ssize_t i915_gpu_state_copy_to_buffer(struct i915_gpu_state *error, 216 char *buf, loff_t offset, size_t count); 217 218 void __i915_gpu_state_free(struct kref *kref); 219 static inline void i915_gpu_state_put(struct i915_gpu_state *gpu) 220 { 221 if (gpu) 222 kref_put(&gpu->ref, __i915_gpu_state_free); 223 } 224 225 struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915); 226 void i915_reset_error_state(struct drm_i915_private *i915); 227 void i915_disable_error_state(struct drm_i915_private *i915, int err); 228 229 #else 230 231 static inline void i915_capture_error_state(struct drm_i915_private *dev_priv, 232 u32 engine_mask, 233 const char *error_msg) 234 { 235 } 236 237 static inline struct i915_gpu_state * 238 i915_first_error_state(struct drm_i915_private *i915) 239 { 240 return ERR_PTR(-ENODEV); 241 } 242 243 static inline void i915_reset_error_state(struct drm_i915_private *i915) 244 { 245 } 246 247 static inline void i915_disable_error_state(struct drm_i915_private *i915, 248 int err) 249 { 250 } 251 252 #endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */ 253 254 #endif /* _I915_GPU_ERROR_H_ */ 255