1 /* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30 #include <linux/ascii85.h> 31 #include <linux/debugfs.h> 32 #include <linux/highmem.h> 33 #include <linux/nmi.h> 34 #include <linux/pagevec.h> 35 #include <linux/scatterlist.h> 36 #include <linux/string_helpers.h> 37 #include <linux/utsname.h> 38 #include <linux/zlib.h> 39 40 #include <drm/drm_cache.h> 41 #include <drm/drm_print.h> 42 43 #include "display/intel_display_snapshot.h" 44 45 #include "gem/i915_gem_context.h" 46 #include "gem/i915_gem_lmem.h" 47 #include "gt/intel_engine_regs.h" 48 #include "gt/intel_gt.h" 49 #include "gt/intel_gt_mcr.h" 50 #include "gt/intel_gt_pm.h" 51 #include "gt/intel_gt_regs.h" 52 #include "gt/uc/intel_guc_capture.h" 53 54 #include "i915_driver.h" 55 #include "i915_drv.h" 56 #include "i915_gpu_error.h" 57 #include "i915_memcpy.h" 58 #include "i915_reg.h" 59 #include "i915_scatterlist.h" 60 #include "i915_sysfs.h" 61 #include "i915_utils.h" 62 63 #define ALLOW_FAIL (__GFP_KSWAPD_RECLAIM | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) 64 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN) 65 66 static void __sg_set_buf(struct scatterlist *sg, 67 void *addr, unsigned int len, loff_t it) 68 { 69 sg->page_link = (unsigned long)virt_to_page(addr); 70 sg->offset = offset_in_page(addr); 71 sg->length = len; 72 sg->dma_address = it; 73 } 74 75 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len) 76 { 77 if (!len) 78 return false; 79 80 if (e->bytes + len + 1 <= e->size) 81 return true; 82 83 if (e->bytes) { 84 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter); 85 e->iter += e->bytes; 86 e->buf = NULL; 87 e->bytes = 0; 88 } 89 90 if (e->cur == e->end) { 91 struct scatterlist *sgl; 92 93 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL); 94 if (!sgl) { 95 e->err = -ENOMEM; 96 return false; 97 } 98 99 if (e->cur) { 100 e->cur->offset = 0; 101 e->cur->length = 0; 102 e->cur->page_link = 103 (unsigned long)sgl | SG_CHAIN; 104 } else { 105 e->sgl = sgl; 106 } 107 108 e->cur = sgl; 109 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1; 110 } 111 112 e->size = ALIGN(len + 1, SZ_64K); 113 e->buf = kmalloc(e->size, ALLOW_FAIL); 114 if (!e->buf) { 115 e->size = PAGE_ALIGN(len + 1); 116 e->buf = kmalloc(e->size, GFP_KERNEL); 117 } 118 if (!e->buf) { 119 e->err = -ENOMEM; 120 return false; 121 } 122 123 return true; 124 } 125 126 __printf(2, 0) 127 static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 128 const char *fmt, va_list args) 129 { 130 va_list ap; 131 int len; 132 133 if (e->err) 134 return; 135 136 va_copy(ap, args); 137 len = vsnprintf(NULL, 0, fmt, ap); 138 va_end(ap); 139 if (len <= 0) { 140 e->err = len; 141 return; 142 } 143 144 if (!__i915_error_grow(e, len)) 145 return; 146 147 GEM_BUG_ON(e->bytes >= e->size); 148 len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args); 149 if (len < 0) { 150 e->err = len; 151 return; 152 } 153 e->bytes += len; 154 } 155 156 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str) 157 { 158 unsigned len; 159 160 if (e->err || !str) 161 return; 162 163 len = strlen(str); 164 if (!__i915_error_grow(e, len)) 165 return; 166 167 GEM_BUG_ON(e->bytes + len > e->size); 168 memcpy(e->buf + e->bytes, str, len); 169 e->bytes += len; 170 } 171 172 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 173 #define err_puts(e, s) i915_error_puts(e, s) 174 175 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf) 176 { 177 i915_error_vprintf(p->arg, vaf->fmt, *vaf->va); 178 } 179 180 static inline struct drm_printer 181 i915_error_printer(struct drm_i915_error_state_buf *e) 182 { 183 struct drm_printer p = { 184 .printfn = __i915_printfn_error, 185 .arg = e, 186 }; 187 return p; 188 } 189 190 /* single threaded page allocator with a reserved stash for emergencies */ 191 static void pool_fini(struct folio_batch *fbatch) 192 { 193 folio_batch_release(fbatch); 194 } 195 196 static int pool_refill(struct folio_batch *fbatch, gfp_t gfp) 197 { 198 while (folio_batch_space(fbatch)) { 199 struct folio *folio; 200 201 folio = folio_alloc(gfp, 0); 202 if (!folio) 203 return -ENOMEM; 204 205 folio_batch_add(fbatch, folio); 206 } 207 208 return 0; 209 } 210 211 static int pool_init(struct folio_batch *fbatch, gfp_t gfp) 212 { 213 int err; 214 215 folio_batch_init(fbatch); 216 217 err = pool_refill(fbatch, gfp); 218 if (err) 219 pool_fini(fbatch); 220 221 return err; 222 } 223 224 static void *pool_alloc(struct folio_batch *fbatch, gfp_t gfp) 225 { 226 struct folio *folio; 227 228 folio = folio_alloc(gfp, 0); 229 if (!folio && folio_batch_count(fbatch)) 230 folio = fbatch->folios[--fbatch->nr]; 231 232 return folio ? folio_address(folio) : NULL; 233 } 234 235 static void pool_free(struct folio_batch *fbatch, void *addr) 236 { 237 struct folio *folio = virt_to_folio(addr); 238 239 if (folio_batch_space(fbatch)) 240 folio_batch_add(fbatch, folio); 241 else 242 folio_put(folio); 243 } 244 245 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR 246 247 struct i915_vma_compress { 248 struct folio_batch pool; 249 struct z_stream_s zstream; 250 void *tmp; 251 }; 252 253 static bool compress_init(struct i915_vma_compress *c) 254 { 255 struct z_stream_s *zstream = &c->zstream; 256 257 if (pool_init(&c->pool, ALLOW_FAIL)) 258 return false; 259 260 zstream->workspace = 261 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL), 262 ALLOW_FAIL); 263 if (!zstream->workspace) { 264 pool_fini(&c->pool); 265 return false; 266 } 267 268 c->tmp = NULL; 269 if (i915_has_memcpy_from_wc()) 270 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL); 271 272 return true; 273 } 274 275 static bool compress_start(struct i915_vma_compress *c) 276 { 277 struct z_stream_s *zstream = &c->zstream; 278 void *workspace = zstream->workspace; 279 280 memset(zstream, 0, sizeof(*zstream)); 281 zstream->workspace = workspace; 282 283 return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK; 284 } 285 286 static void *compress_next_page(struct i915_vma_compress *c, 287 struct i915_vma_coredump *dst) 288 { 289 void *page_addr; 290 struct page *page; 291 292 page_addr = pool_alloc(&c->pool, ALLOW_FAIL); 293 if (!page_addr) 294 return ERR_PTR(-ENOMEM); 295 296 page = virt_to_page(page_addr); 297 list_add_tail(&page->lru, &dst->page_list); 298 return page_addr; 299 } 300 301 static int compress_page(struct i915_vma_compress *c, 302 void *src, 303 struct i915_vma_coredump *dst, 304 bool wc) 305 { 306 struct z_stream_s *zstream = &c->zstream; 307 308 zstream->next_in = src; 309 if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE)) 310 zstream->next_in = c->tmp; 311 zstream->avail_in = PAGE_SIZE; 312 313 do { 314 if (zstream->avail_out == 0) { 315 zstream->next_out = compress_next_page(c, dst); 316 if (IS_ERR(zstream->next_out)) 317 return PTR_ERR(zstream->next_out); 318 319 zstream->avail_out = PAGE_SIZE; 320 } 321 322 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK) 323 return -EIO; 324 325 cond_resched(); 326 } while (zstream->avail_in); 327 328 /* Fallback to uncompressed if we increase size? */ 329 if (0 && zstream->total_out > zstream->total_in) 330 return -E2BIG; 331 332 return 0; 333 } 334 335 static int compress_flush(struct i915_vma_compress *c, 336 struct i915_vma_coredump *dst) 337 { 338 struct z_stream_s *zstream = &c->zstream; 339 340 do { 341 switch (zlib_deflate(zstream, Z_FINISH)) { 342 case Z_OK: /* more space requested */ 343 zstream->next_out = compress_next_page(c, dst); 344 if (IS_ERR(zstream->next_out)) 345 return PTR_ERR(zstream->next_out); 346 347 zstream->avail_out = PAGE_SIZE; 348 break; 349 350 case Z_STREAM_END: 351 goto end; 352 353 default: /* any error */ 354 return -EIO; 355 } 356 } while (1); 357 358 end: 359 memset(zstream->next_out, 0, zstream->avail_out); 360 dst->unused = zstream->avail_out; 361 return 0; 362 } 363 364 static void compress_finish(struct i915_vma_compress *c) 365 { 366 zlib_deflateEnd(&c->zstream); 367 } 368 369 static void compress_fini(struct i915_vma_compress *c) 370 { 371 kfree(c->zstream.workspace); 372 if (c->tmp) 373 pool_free(&c->pool, c->tmp); 374 pool_fini(&c->pool); 375 } 376 377 static void err_compression_marker(struct drm_i915_error_state_buf *m) 378 { 379 err_puts(m, ":"); 380 } 381 382 #else 383 384 struct i915_vma_compress { 385 struct folio_batch pool; 386 }; 387 388 static bool compress_init(struct i915_vma_compress *c) 389 { 390 return pool_init(&c->pool, ALLOW_FAIL) == 0; 391 } 392 393 static bool compress_start(struct i915_vma_compress *c) 394 { 395 return true; 396 } 397 398 static int compress_page(struct i915_vma_compress *c, 399 void *src, 400 struct i915_vma_coredump *dst, 401 bool wc) 402 { 403 void *ptr; 404 405 ptr = pool_alloc(&c->pool, ALLOW_FAIL); 406 if (!ptr) 407 return -ENOMEM; 408 409 if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE))) 410 memcpy(ptr, src, PAGE_SIZE); 411 list_add_tail(&virt_to_page(ptr)->lru, &dst->page_list); 412 cond_resched(); 413 414 return 0; 415 } 416 417 static int compress_flush(struct i915_vma_compress *c, 418 struct i915_vma_coredump *dst) 419 { 420 return 0; 421 } 422 423 static void compress_finish(struct i915_vma_compress *c) 424 { 425 } 426 427 static void compress_fini(struct i915_vma_compress *c) 428 { 429 pool_fini(&c->pool); 430 } 431 432 static void err_compression_marker(struct drm_i915_error_state_buf *m) 433 { 434 err_puts(m, "~"); 435 } 436 437 #endif 438 439 static void error_print_instdone(struct drm_i915_error_state_buf *m, 440 const struct intel_engine_coredump *ee) 441 { 442 int slice; 443 int subslice; 444 int iter; 445 446 err_printf(m, " INSTDONE: 0x%08x\n", 447 ee->instdone.instdone); 448 449 if (ee->engine->class != RENDER_CLASS || GRAPHICS_VER(m->i915) <= 3) 450 return; 451 452 err_printf(m, " SC_INSTDONE: 0x%08x\n", 453 ee->instdone.slice_common); 454 455 if (GRAPHICS_VER(m->i915) <= 6) 456 return; 457 458 for_each_ss_steering(iter, ee->engine->gt, slice, subslice) 459 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", 460 slice, subslice, 461 ee->instdone.sampler[slice][subslice]); 462 463 for_each_ss_steering(iter, ee->engine->gt, slice, subslice) 464 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", 465 slice, subslice, 466 ee->instdone.row[slice][subslice]); 467 468 if (GRAPHICS_VER(m->i915) < 12) 469 return; 470 471 if (GRAPHICS_VER_FULL(m->i915) >= IP_VER(12, 55)) { 472 for_each_ss_steering(iter, ee->engine->gt, slice, subslice) 473 err_printf(m, " GEOM_SVGUNIT_INSTDONE[%d][%d]: 0x%08x\n", 474 slice, subslice, 475 ee->instdone.geom_svg[slice][subslice]); 476 } 477 478 err_printf(m, " SC_INSTDONE_EXTRA: 0x%08x\n", 479 ee->instdone.slice_common_extra[0]); 480 err_printf(m, " SC_INSTDONE_EXTRA2: 0x%08x\n", 481 ee->instdone.slice_common_extra[1]); 482 } 483 484 static void error_print_request(struct drm_i915_error_state_buf *m, 485 const char *prefix, 486 const struct i915_request_coredump *erq) 487 { 488 if (!erq->seqno) 489 return; 490 491 err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, head %08x, tail %08x\n", 492 prefix, erq->pid, erq->context, erq->seqno, 493 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, 494 &erq->flags) ? "!" : "", 495 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, 496 &erq->flags) ? "+" : "", 497 erq->sched_attr.priority, 498 erq->head, erq->tail); 499 } 500 501 static void error_print_context(struct drm_i915_error_state_buf *m, 502 const char *header, 503 const struct i915_gem_context_coredump *ctx) 504 { 505 err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n", 506 header, ctx->comm, ctx->pid, ctx->sched_attr.priority, 507 ctx->guilty, ctx->active, 508 ctx->total_runtime, ctx->avg_runtime); 509 err_printf(m, " context timeline seqno %u\n", ctx->hwsp_seqno); 510 } 511 512 static struct i915_vma_coredump * 513 __find_vma(struct i915_vma_coredump *vma, const char *name) 514 { 515 while (vma) { 516 if (strcmp(vma->name, name) == 0) 517 return vma; 518 vma = vma->next; 519 } 520 521 return NULL; 522 } 523 524 static struct i915_vma_coredump * 525 intel_gpu_error_find_batch(const struct intel_engine_coredump *ee) 526 { 527 return __find_vma(ee->vma, "batch"); 528 } 529 530 static void error_print_engine(struct drm_i915_error_state_buf *m, 531 const struct intel_engine_coredump *ee) 532 { 533 struct i915_vma_coredump *batch; 534 int n; 535 536 err_printf(m, "%s command stream:\n", ee->engine->name); 537 err_printf(m, " CCID: 0x%08x\n", ee->ccid); 538 err_printf(m, " START: 0x%08x\n", ee->start); 539 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head); 540 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n", 541 ee->tail, ee->rq_post, ee->rq_tail); 542 err_printf(m, " CTL: 0x%08x\n", ee->ctl); 543 err_printf(m, " MODE: 0x%08x\n", ee->mode); 544 err_printf(m, " HWS: 0x%08x\n", ee->hws); 545 err_printf(m, " ACTHD: 0x%08x %08x\n", 546 (u32)(ee->acthd>>32), (u32)ee->acthd); 547 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir); 548 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr); 549 err_printf(m, " ESR: 0x%08x\n", ee->esr); 550 551 error_print_instdone(m, ee); 552 553 batch = intel_gpu_error_find_batch(ee); 554 if (batch) { 555 u64 start = batch->gtt_offset; 556 u64 end = start + batch->gtt_size; 557 558 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n", 559 upper_32_bits(start), lower_32_bits(start), 560 upper_32_bits(end), lower_32_bits(end)); 561 } 562 if (GRAPHICS_VER(m->i915) >= 4) { 563 err_printf(m, " BBADDR: 0x%08x_%08x\n", 564 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr); 565 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate); 566 err_printf(m, " INSTPS: 0x%08x\n", ee->instps); 567 } 568 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm); 569 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr), 570 lower_32_bits(ee->faddr)); 571 if (GRAPHICS_VER(m->i915) >= 6) { 572 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi); 573 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg); 574 } 575 if (GRAPHICS_VER(m->i915) >= 11) { 576 err_printf(m, " NOPID: 0x%08x\n", ee->nopid); 577 err_printf(m, " EXCC: 0x%08x\n", ee->excc); 578 err_printf(m, " CMD_CCTL: 0x%08x\n", ee->cmd_cctl); 579 err_printf(m, " CSCMDOP: 0x%08x\n", ee->cscmdop); 580 err_printf(m, " CTX_SR_CTL: 0x%08x\n", ee->ctx_sr_ctl); 581 err_printf(m, " DMA_FADDR_HI: 0x%08x\n", ee->dma_faddr_hi); 582 err_printf(m, " DMA_FADDR_LO: 0x%08x\n", ee->dma_faddr_lo); 583 } 584 if (HAS_PPGTT(m->i915)) { 585 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode); 586 587 if (GRAPHICS_VER(m->i915) >= 8) { 588 int i; 589 for (i = 0; i < 4; i++) 590 err_printf(m, " PDP%d: 0x%016llx\n", 591 i, ee->vm_info.pdp[i]); 592 } else { 593 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 594 ee->vm_info.pp_dir_base); 595 } 596 } 597 598 for (n = 0; n < ee->num_ports; n++) { 599 err_printf(m, " ELSP[%d]:", n); 600 error_print_request(m, " ", &ee->execlist[n]); 601 } 602 } 603 604 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 605 { 606 va_list args; 607 608 va_start(args, f); 609 i915_error_vprintf(e, f, args); 610 va_end(args); 611 } 612 613 static void intel_gpu_error_print_vma(struct drm_i915_error_state_buf *m, 614 const struct intel_engine_cs *engine, 615 const struct i915_vma_coredump *vma) 616 { 617 char out[ASCII85_BUFSZ]; 618 struct page *page; 619 620 if (!vma) 621 return; 622 623 err_printf(m, "%s --- %s = 0x%08x %08x\n", 624 engine ? engine->name : "global", vma->name, 625 upper_32_bits(vma->gtt_offset), 626 lower_32_bits(vma->gtt_offset)); 627 628 if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K) 629 err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes); 630 631 err_compression_marker(m); 632 list_for_each_entry(page, &vma->page_list, lru) { 633 int i, len; 634 const u32 *addr = page_address(page); 635 636 len = PAGE_SIZE; 637 if (page == list_last_entry(&vma->page_list, typeof(*page), lru)) 638 len -= vma->unused; 639 len = ascii85_encode_len(len); 640 641 for (i = 0; i < len; i++) 642 err_puts(m, ascii85_encode(addr[i], out)); 643 } 644 err_puts(m, "\n"); 645 } 646 647 static void err_print_capabilities(struct drm_i915_error_state_buf *m, 648 struct i915_gpu_coredump *error) 649 { 650 struct drm_printer p = i915_error_printer(m); 651 652 intel_device_info_print(&error->device_info, &error->runtime_info, &p); 653 intel_driver_caps_print(&error->driver_caps, &p); 654 } 655 656 static void err_print_params(struct drm_i915_error_state_buf *m, 657 const struct i915_params *params) 658 { 659 struct drm_printer p = i915_error_printer(m); 660 661 i915_params_dump(params, &p); 662 } 663 664 static void err_print_pciid(struct drm_i915_error_state_buf *m, 665 struct drm_i915_private *i915) 666 { 667 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 668 669 err_printf(m, "PCI ID: 0x%04x\n", pdev->device); 670 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision); 671 err_printf(m, "PCI Subsystem: %04x:%04x\n", 672 pdev->subsystem_vendor, 673 pdev->subsystem_device); 674 } 675 676 static void err_print_guc_ctb(struct drm_i915_error_state_buf *m, 677 const char *name, 678 const struct intel_ctb_coredump *ctb) 679 { 680 if (!ctb->size) 681 return; 682 683 err_printf(m, "GuC %s CTB: raw: 0x%08X, 0x%08X/%08X, cached: 0x%08X/%08X, desc = 0x%08X, buf = 0x%08X x 0x%08X\n", 684 name, ctb->raw_status, ctb->raw_head, ctb->raw_tail, 685 ctb->head, ctb->tail, ctb->desc_offset, ctb->cmds_offset, ctb->size); 686 } 687 688 static void err_print_uc(struct drm_i915_error_state_buf *m, 689 const struct intel_uc_coredump *error_uc) 690 { 691 struct drm_printer p = i915_error_printer(m); 692 693 intel_uc_fw_dump(&error_uc->guc_fw, &p); 694 intel_uc_fw_dump(&error_uc->huc_fw, &p); 695 err_printf(m, "GuC timestamp: 0x%08x\n", error_uc->guc.timestamp); 696 intel_gpu_error_print_vma(m, NULL, error_uc->guc.vma_log); 697 err_printf(m, "GuC CTB fence: %d\n", error_uc->guc.last_fence); 698 err_print_guc_ctb(m, "Send", error_uc->guc.ctb + 0); 699 err_print_guc_ctb(m, "Recv", error_uc->guc.ctb + 1); 700 intel_gpu_error_print_vma(m, NULL, error_uc->guc.vma_ctb); 701 } 702 703 static void err_free_sgl(struct scatterlist *sgl) 704 { 705 while (sgl) { 706 struct scatterlist *sg; 707 708 for (sg = sgl; !sg_is_chain(sg); sg++) { 709 kfree(sg_virt(sg)); 710 if (sg_is_last(sg)) 711 break; 712 } 713 714 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg); 715 free_page((unsigned long)sgl); 716 sgl = sg; 717 } 718 } 719 720 static void err_print_gt_info(struct drm_i915_error_state_buf *m, 721 struct intel_gt_coredump *gt) 722 { 723 struct drm_printer p = i915_error_printer(m); 724 725 intel_gt_info_print(>->info, &p); 726 intel_sseu_print_topology(gt->_gt->i915, >->info.sseu, &p); 727 } 728 729 static void err_print_gt_display(struct drm_i915_error_state_buf *m, 730 struct intel_gt_coredump *gt) 731 { 732 err_printf(m, "IER: 0x%08x\n", gt->ier); 733 err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr); 734 } 735 736 static void err_print_gt_global_nonguc(struct drm_i915_error_state_buf *m, 737 struct intel_gt_coredump *gt) 738 { 739 int i; 740 741 err_printf(m, "GT awake: %s\n", str_yes_no(gt->awake)); 742 err_printf(m, "CS timestamp frequency: %u Hz, %d ns\n", 743 gt->clock_frequency, gt->clock_period_ns); 744 err_printf(m, "EIR: 0x%08x\n", gt->eir); 745 err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er); 746 747 for (i = 0; i < gt->ngtier; i++) 748 err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]); 749 } 750 751 static void err_print_gt_global(struct drm_i915_error_state_buf *m, 752 struct intel_gt_coredump *gt) 753 { 754 err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake); 755 756 if (IS_GRAPHICS_VER(m->i915, 6, 11)) { 757 err_printf(m, "ERROR: 0x%08x\n", gt->error); 758 err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg); 759 } 760 761 if (GRAPHICS_VER(m->i915) >= 8) 762 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", 763 gt->fault_data1, gt->fault_data0); 764 765 if (GRAPHICS_VER(m->i915) == 7) 766 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int); 767 768 if (IS_GRAPHICS_VER(m->i915, 8, 11)) 769 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache); 770 771 if (GRAPHICS_VER(m->i915) == 12) 772 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err); 773 774 if (GRAPHICS_VER(m->i915) >= 12) { 775 int i; 776 777 for (i = 0; i < I915_MAX_SFC; i++) { 778 /* 779 * SFC_DONE resides in the VD forcewake domain, so it 780 * only exists if the corresponding VCS engine is 781 * present. 782 */ 783 if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || 784 !HAS_ENGINE(gt->_gt, _VCS(i * 2))) 785 continue; 786 787 err_printf(m, " SFC_DONE[%d]: 0x%08x\n", i, 788 gt->sfc_done[i]); 789 } 790 791 err_printf(m, " GAM_DONE: 0x%08x\n", gt->gam_done); 792 } 793 } 794 795 static void err_print_gt_fences(struct drm_i915_error_state_buf *m, 796 struct intel_gt_coredump *gt) 797 { 798 int i; 799 800 for (i = 0; i < gt->nfence; i++) 801 err_printf(m, " fence[%d] = %08llx\n", i, gt->fence[i]); 802 } 803 804 static void err_print_gt_engines(struct drm_i915_error_state_buf *m, 805 struct intel_gt_coredump *gt) 806 { 807 const struct intel_engine_coredump *ee; 808 809 for (ee = gt->engine; ee; ee = ee->next) { 810 const struct i915_vma_coredump *vma; 811 812 if (gt->uc && gt->uc->guc.is_guc_capture) { 813 if (ee->guc_capture_node) 814 intel_guc_capture_print_engine_node(m, ee); 815 else 816 err_printf(m, " Missing GuC capture node for %s\n", 817 ee->engine->name); 818 } else { 819 error_print_engine(m, ee); 820 } 821 822 err_printf(m, " hung: %u\n", ee->hung); 823 err_printf(m, " engine reset count: %u\n", ee->reset_count); 824 error_print_context(m, " Active context: ", &ee->context); 825 826 for (vma = ee->vma; vma; vma = vma->next) 827 intel_gpu_error_print_vma(m, ee->engine, vma); 828 } 829 830 } 831 832 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, 833 struct i915_gpu_coredump *error) 834 { 835 struct drm_printer p = i915_error_printer(m); 836 const struct intel_engine_coredump *ee; 837 struct timespec64 ts; 838 839 if (*error->error_msg) 840 err_printf(m, "%s\n", error->error_msg); 841 err_printf(m, "Kernel: %s %s\n", 842 init_utsname()->release, 843 init_utsname()->machine); 844 ts = ktime_to_timespec64(error->time); 845 err_printf(m, "Time: %lld s %ld us\n", 846 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 847 ts = ktime_to_timespec64(error->boottime); 848 err_printf(m, "Boottime: %lld s %ld us\n", 849 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 850 ts = ktime_to_timespec64(error->uptime); 851 err_printf(m, "Uptime: %lld s %ld us\n", 852 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 853 err_printf(m, "Capture: %lu jiffies; %d ms ago\n", 854 error->capture, jiffies_to_msecs(jiffies - error->capture)); 855 856 for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next) 857 err_printf(m, "Active process (on ring %s): %s [%d]\n", 858 ee->engine->name, 859 ee->context.comm, 860 ee->context.pid); 861 862 err_printf(m, "Reset count: %u\n", error->reset_count); 863 err_printf(m, "Suspend count: %u\n", error->suspend_count); 864 err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform)); 865 err_printf(m, "Subplatform: 0x%x\n", 866 intel_subplatform(&error->runtime_info, 867 error->device_info.platform)); 868 err_print_pciid(m, m->i915); 869 870 err_printf(m, "IOMMU enabled?: %d\n", error->iommu); 871 872 err_printf(m, "RPM wakelock: %s\n", str_yes_no(error->wakelock)); 873 err_printf(m, "PM suspended: %s\n", str_yes_no(error->suspended)); 874 875 if (error->gt) { 876 bool print_guc_capture = false; 877 878 if (error->gt->uc && error->gt->uc->guc.is_guc_capture) 879 print_guc_capture = true; 880 881 err_print_gt_display(m, error->gt); 882 err_print_gt_global_nonguc(m, error->gt); 883 err_print_gt_fences(m, error->gt); 884 885 /* 886 * GuC dumped global, eng-class and eng-instance registers together 887 * as part of engine state dump so we print in err_print_gt_engines 888 */ 889 if (!print_guc_capture) 890 err_print_gt_global(m, error->gt); 891 892 err_print_gt_engines(m, error->gt); 893 894 if (error->gt->uc) 895 err_print_uc(m, error->gt->uc); 896 897 err_print_gt_info(m, error->gt); 898 } 899 900 err_print_capabilities(m, error); 901 err_print_params(m, &error->params); 902 903 intel_display_snapshot_print(error->display_snapshot, &p); 904 } 905 906 static int err_print_to_sgl(struct i915_gpu_coredump *error) 907 { 908 struct drm_i915_error_state_buf m; 909 910 if (IS_ERR(error)) 911 return PTR_ERR(error); 912 913 if (READ_ONCE(error->sgl)) 914 return 0; 915 916 memset(&m, 0, sizeof(m)); 917 m.i915 = error->i915; 918 919 __err_print_to_sgl(&m, error); 920 921 if (m.buf) { 922 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter); 923 m.bytes = 0; 924 m.buf = NULL; 925 } 926 if (m.cur) { 927 GEM_BUG_ON(m.end < m.cur); 928 sg_mark_end(m.cur - 1); 929 } 930 GEM_BUG_ON(m.sgl && !m.cur); 931 932 if (m.err) { 933 err_free_sgl(m.sgl); 934 return m.err; 935 } 936 937 if (cmpxchg(&error->sgl, NULL, m.sgl)) 938 err_free_sgl(m.sgl); 939 940 return 0; 941 } 942 943 ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error, 944 char *buf, loff_t off, size_t rem) 945 { 946 struct scatterlist *sg; 947 size_t count; 948 loff_t pos; 949 int err; 950 951 if (!error || !rem) 952 return 0; 953 954 err = err_print_to_sgl(error); 955 if (err) 956 return err; 957 958 sg = READ_ONCE(error->fit); 959 if (!sg || off < sg->dma_address) 960 sg = error->sgl; 961 if (!sg) 962 return 0; 963 964 pos = sg->dma_address; 965 count = 0; 966 do { 967 size_t len, start; 968 969 if (sg_is_chain(sg)) { 970 sg = sg_chain_ptr(sg); 971 GEM_BUG_ON(sg_is_chain(sg)); 972 } 973 974 len = sg->length; 975 if (pos + len <= off) { 976 pos += len; 977 continue; 978 } 979 980 start = sg->offset; 981 if (pos < off) { 982 GEM_BUG_ON(off - pos > len); 983 len -= off - pos; 984 start += off - pos; 985 pos = off; 986 } 987 988 len = min(len, rem); 989 GEM_BUG_ON(!len || len > sg->length); 990 991 memcpy(buf, page_address(sg_page(sg)) + start, len); 992 993 count += len; 994 pos += len; 995 996 buf += len; 997 rem -= len; 998 if (!rem) { 999 WRITE_ONCE(error->fit, sg); 1000 break; 1001 } 1002 } while (!sg_is_last(sg++)); 1003 1004 return count; 1005 } 1006 1007 static void i915_vma_coredump_free(struct i915_vma_coredump *vma) 1008 { 1009 while (vma) { 1010 struct i915_vma_coredump *next = vma->next; 1011 struct page *page, *n; 1012 1013 list_for_each_entry_safe(page, n, &vma->page_list, lru) { 1014 list_del_init(&page->lru); 1015 __free_page(page); 1016 } 1017 1018 kfree(vma); 1019 vma = next; 1020 } 1021 } 1022 1023 static void cleanup_params(struct i915_gpu_coredump *error) 1024 { 1025 i915_params_free(&error->params); 1026 } 1027 1028 static void cleanup_uc(struct intel_uc_coredump *uc) 1029 { 1030 kfree(uc->guc_fw.file_selected.path); 1031 kfree(uc->huc_fw.file_selected.path); 1032 kfree(uc->guc_fw.file_wanted.path); 1033 kfree(uc->huc_fw.file_wanted.path); 1034 i915_vma_coredump_free(uc->guc.vma_log); 1035 i915_vma_coredump_free(uc->guc.vma_ctb); 1036 1037 kfree(uc); 1038 } 1039 1040 static void cleanup_gt(struct intel_gt_coredump *gt) 1041 { 1042 while (gt->engine) { 1043 struct intel_engine_coredump *ee = gt->engine; 1044 1045 gt->engine = ee->next; 1046 1047 i915_vma_coredump_free(ee->vma); 1048 intel_guc_capture_free_node(ee); 1049 kfree(ee); 1050 } 1051 1052 if (gt->uc) 1053 cleanup_uc(gt->uc); 1054 1055 kfree(gt); 1056 } 1057 1058 void __i915_gpu_coredump_free(struct kref *error_ref) 1059 { 1060 struct i915_gpu_coredump *error = 1061 container_of(error_ref, typeof(*error), ref); 1062 1063 while (error->gt) { 1064 struct intel_gt_coredump *gt = error->gt; 1065 1066 error->gt = gt->next; 1067 cleanup_gt(gt); 1068 } 1069 1070 intel_display_snapshot_free(error->display_snapshot); 1071 1072 cleanup_params(error); 1073 1074 err_free_sgl(error->sgl); 1075 kfree(error); 1076 } 1077 1078 static struct i915_vma_coredump * 1079 i915_vma_coredump_create(const struct intel_gt *gt, 1080 const struct i915_vma_resource *vma_res, 1081 struct i915_vma_compress *compress, 1082 const char *name) 1083 1084 { 1085 struct i915_ggtt *ggtt = gt->ggtt; 1086 const u64 slot = ggtt->error_capture.start; 1087 struct i915_vma_coredump *dst; 1088 struct sgt_iter iter; 1089 int ret; 1090 1091 might_sleep(); 1092 1093 if (!vma_res || !vma_res->bi.pages || !compress) 1094 return NULL; 1095 1096 dst = kmalloc(sizeof(*dst), ALLOW_FAIL); 1097 if (!dst) 1098 return NULL; 1099 1100 if (!compress_start(compress)) { 1101 kfree(dst); 1102 return NULL; 1103 } 1104 1105 INIT_LIST_HEAD(&dst->page_list); 1106 strscpy(dst->name, name); 1107 dst->next = NULL; 1108 1109 dst->gtt_offset = vma_res->start; 1110 dst->gtt_size = vma_res->node_size; 1111 dst->gtt_page_sizes = vma_res->page_sizes_gtt; 1112 dst->unused = 0; 1113 1114 ret = -EINVAL; 1115 if (drm_mm_node_allocated(&ggtt->error_capture)) { 1116 void __iomem *s; 1117 dma_addr_t dma; 1118 1119 for_each_sgt_daddr(dma, iter, vma_res->bi.pages) { 1120 mutex_lock(&ggtt->error_mutex); 1121 if (ggtt->vm.raw_insert_page) 1122 ggtt->vm.raw_insert_page(&ggtt->vm, dma, slot, 1123 i915_gem_get_pat_index(gt->i915, 1124 I915_CACHE_NONE), 1125 0); 1126 else 1127 ggtt->vm.insert_page(&ggtt->vm, dma, slot, 1128 i915_gem_get_pat_index(gt->i915, 1129 I915_CACHE_NONE), 1130 0); 1131 mb(); 1132 1133 s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE); 1134 ret = compress_page(compress, 1135 (void __force *)s, dst, 1136 true); 1137 io_mapping_unmap(s); 1138 1139 mb(); 1140 ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE); 1141 mutex_unlock(&ggtt->error_mutex); 1142 if (ret) 1143 break; 1144 } 1145 } else if (vma_res->bi.lmem) { 1146 struct intel_memory_region *mem = vma_res->mr; 1147 dma_addr_t dma; 1148 1149 for_each_sgt_daddr(dma, iter, vma_res->bi.pages) { 1150 dma_addr_t offset = dma - mem->region.start; 1151 void __iomem *s; 1152 1153 if (offset + PAGE_SIZE > resource_size(&mem->io)) { 1154 ret = -EINVAL; 1155 break; 1156 } 1157 1158 s = io_mapping_map_wc(&mem->iomap, offset, PAGE_SIZE); 1159 ret = compress_page(compress, 1160 (void __force *)s, dst, 1161 true); 1162 io_mapping_unmap(s); 1163 if (ret) 1164 break; 1165 } 1166 } else { 1167 struct page *page; 1168 1169 for_each_sgt_page(page, iter, vma_res->bi.pages) { 1170 void *s; 1171 1172 drm_clflush_pages(&page, 1); 1173 1174 s = kmap_local_page(page); 1175 ret = compress_page(compress, s, dst, false); 1176 kunmap_local(s); 1177 1178 drm_clflush_pages(&page, 1); 1179 1180 if (ret) 1181 break; 1182 } 1183 } 1184 1185 if (ret || compress_flush(compress, dst)) { 1186 struct page *page, *n; 1187 1188 list_for_each_entry_safe_reverse(page, n, &dst->page_list, lru) { 1189 list_del_init(&page->lru); 1190 pool_free(&compress->pool, page_address(page)); 1191 } 1192 1193 kfree(dst); 1194 dst = NULL; 1195 } 1196 compress_finish(compress); 1197 1198 return dst; 1199 } 1200 1201 static void gt_record_fences(struct intel_gt_coredump *gt) 1202 { 1203 struct i915_ggtt *ggtt = gt->_gt->ggtt; 1204 struct intel_uncore *uncore = gt->_gt->uncore; 1205 int i; 1206 1207 if (GRAPHICS_VER(uncore->i915) >= 6) { 1208 for (i = 0; i < ggtt->num_fences; i++) 1209 gt->fence[i] = 1210 intel_uncore_read64(uncore, 1211 FENCE_REG_GEN6_LO(i)); 1212 } else if (GRAPHICS_VER(uncore->i915) >= 4) { 1213 for (i = 0; i < ggtt->num_fences; i++) 1214 gt->fence[i] = 1215 intel_uncore_read64(uncore, 1216 FENCE_REG_965_LO(i)); 1217 } else { 1218 for (i = 0; i < ggtt->num_fences; i++) 1219 gt->fence[i] = 1220 intel_uncore_read(uncore, FENCE_REG(i)); 1221 } 1222 gt->nfence = i; 1223 } 1224 1225 static void engine_record_registers(struct intel_engine_coredump *ee) 1226 { 1227 const struct intel_engine_cs *engine = ee->engine; 1228 struct drm_i915_private *i915 = engine->i915; 1229 1230 if (GRAPHICS_VER(i915) >= 6) { 1231 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL); 1232 1233 /* 1234 * For the media GT, this ring fault register is not replicated, 1235 * so don't do multicast/replicated register read/write 1236 * operation on it. 1237 */ 1238 if (MEDIA_VER(i915) >= 13 && engine->gt->type == GT_MEDIA) 1239 ee->fault_reg = intel_uncore_read(engine->uncore, 1240 XELPMP_RING_FAULT_REG); 1241 else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) 1242 ee->fault_reg = intel_gt_mcr_read_any(engine->gt, 1243 XEHP_RING_FAULT_REG); 1244 else if (GRAPHICS_VER(i915) >= 12) 1245 ee->fault_reg = intel_uncore_read(engine->uncore, 1246 GEN12_RING_FAULT_REG); 1247 else if (GRAPHICS_VER(i915) >= 8) 1248 ee->fault_reg = intel_uncore_read(engine->uncore, 1249 GEN8_RING_FAULT_REG); 1250 else 1251 ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine); 1252 } 1253 1254 if (GRAPHICS_VER(i915) >= 4) { 1255 ee->esr = ENGINE_READ(engine, RING_ESR); 1256 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD); 1257 ee->ipeir = ENGINE_READ(engine, RING_IPEIR); 1258 ee->ipehr = ENGINE_READ(engine, RING_IPEHR); 1259 ee->instps = ENGINE_READ(engine, RING_INSTPS); 1260 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR); 1261 ee->ccid = ENGINE_READ(engine, CCID); 1262 if (GRAPHICS_VER(i915) >= 8) { 1263 ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32; 1264 ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32; 1265 } 1266 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE); 1267 } else { 1268 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX); 1269 ee->ipeir = ENGINE_READ(engine, IPEIR); 1270 ee->ipehr = ENGINE_READ(engine, IPEHR); 1271 } 1272 1273 if (GRAPHICS_VER(i915) >= 11) { 1274 ee->cmd_cctl = ENGINE_READ(engine, RING_CMD_CCTL); 1275 ee->cscmdop = ENGINE_READ(engine, RING_CSCMDOP); 1276 ee->ctx_sr_ctl = ENGINE_READ(engine, RING_CTX_SR_CTL); 1277 ee->dma_faddr_hi = ENGINE_READ(engine, RING_DMA_FADD_UDW); 1278 ee->dma_faddr_lo = ENGINE_READ(engine, RING_DMA_FADD); 1279 ee->nopid = ENGINE_READ(engine, RING_NOPID); 1280 ee->excc = ENGINE_READ(engine, RING_EXCC); 1281 } 1282 1283 intel_engine_get_instdone(engine, &ee->instdone); 1284 1285 ee->instpm = ENGINE_READ(engine, RING_INSTPM); 1286 ee->acthd = intel_engine_get_active_head(engine); 1287 ee->start = ENGINE_READ(engine, RING_START); 1288 ee->head = ENGINE_READ(engine, RING_HEAD); 1289 ee->tail = ENGINE_READ(engine, RING_TAIL); 1290 ee->ctl = ENGINE_READ(engine, RING_CTL); 1291 if (GRAPHICS_VER(i915) > 2) 1292 ee->mode = ENGINE_READ(engine, RING_MI_MODE); 1293 1294 if (!HWS_NEEDS_PHYSICAL(i915)) { 1295 i915_reg_t mmio; 1296 1297 if (GRAPHICS_VER(i915) == 7) { 1298 switch (engine->id) { 1299 default: 1300 MISSING_CASE(engine->id); 1301 fallthrough; 1302 case RCS0: 1303 mmio = RENDER_HWS_PGA_GEN7; 1304 break; 1305 case BCS0: 1306 mmio = BLT_HWS_PGA_GEN7; 1307 break; 1308 case VCS0: 1309 mmio = BSD_HWS_PGA_GEN7; 1310 break; 1311 case VECS0: 1312 mmio = VEBOX_HWS_PGA_GEN7; 1313 break; 1314 } 1315 } else if (GRAPHICS_VER(engine->i915) == 6) { 1316 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); 1317 } else { 1318 /* XXX: gen8 returns to sanity */ 1319 mmio = RING_HWS_PGA(engine->mmio_base); 1320 } 1321 1322 ee->hws = intel_uncore_read(engine->uncore, mmio); 1323 } 1324 1325 ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine); 1326 1327 if (HAS_PPGTT(i915)) { 1328 int i; 1329 1330 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7); 1331 1332 if (GRAPHICS_VER(i915) == 6) { 1333 ee->vm_info.pp_dir_base = 1334 ENGINE_READ(engine, RING_PP_DIR_BASE_READ); 1335 } else if (GRAPHICS_VER(i915) == 7) { 1336 ee->vm_info.pp_dir_base = 1337 ENGINE_READ(engine, RING_PP_DIR_BASE); 1338 } else if (GRAPHICS_VER(i915) >= 8) { 1339 u32 base = engine->mmio_base; 1340 1341 for (i = 0; i < 4; i++) { 1342 ee->vm_info.pdp[i] = 1343 intel_uncore_read(engine->uncore, 1344 GEN8_RING_PDP_UDW(base, i)); 1345 ee->vm_info.pdp[i] <<= 32; 1346 ee->vm_info.pdp[i] |= 1347 intel_uncore_read(engine->uncore, 1348 GEN8_RING_PDP_LDW(base, i)); 1349 } 1350 } 1351 } 1352 } 1353 1354 static void record_request(const struct i915_request *request, 1355 struct i915_request_coredump *erq) 1356 { 1357 erq->flags = request->fence.flags; 1358 erq->context = request->fence.context; 1359 erq->seqno = request->fence.seqno; 1360 erq->sched_attr = request->sched.attr; 1361 erq->head = request->head; 1362 erq->tail = request->tail; 1363 1364 erq->pid = 0; 1365 rcu_read_lock(); 1366 if (!intel_context_is_closed(request->context)) { 1367 const struct i915_gem_context *ctx; 1368 1369 ctx = rcu_dereference(request->context->gem_context); 1370 if (ctx) 1371 erq->pid = pid_nr(ctx->pid); 1372 } 1373 rcu_read_unlock(); 1374 } 1375 1376 static void engine_record_execlists(struct intel_engine_coredump *ee) 1377 { 1378 const struct intel_engine_execlists * const el = &ee->engine->execlists; 1379 struct i915_request * const *port = el->active; 1380 unsigned int n = 0; 1381 1382 while (*port) 1383 record_request(*port++, &ee->execlist[n++]); 1384 1385 ee->num_ports = n; 1386 } 1387 1388 static bool record_context(struct i915_gem_context_coredump *e, 1389 struct intel_context *ce) 1390 { 1391 struct i915_gem_context *ctx; 1392 struct task_struct *task; 1393 bool simulated; 1394 1395 rcu_read_lock(); 1396 ctx = rcu_dereference(ce->gem_context); 1397 if (ctx && !kref_get_unless_zero(&ctx->ref)) 1398 ctx = NULL; 1399 rcu_read_unlock(); 1400 if (!ctx) 1401 return true; 1402 1403 rcu_read_lock(); 1404 task = pid_task(ctx->pid, PIDTYPE_PID); 1405 if (task) { 1406 strscpy(e->comm, task->comm); 1407 e->pid = task->pid; 1408 } 1409 rcu_read_unlock(); 1410 1411 e->sched_attr = ctx->sched; 1412 e->guilty = atomic_read(&ctx->guilty_count); 1413 e->active = atomic_read(&ctx->active_count); 1414 e->hwsp_seqno = (ce->timeline && ce->timeline->hwsp_seqno) ? 1415 *ce->timeline->hwsp_seqno : ~0U; 1416 1417 e->total_runtime = intel_context_get_total_runtime_ns(ce); 1418 e->avg_runtime = intel_context_get_avg_runtime_ns(ce); 1419 1420 simulated = i915_gem_context_no_error_capture(ctx); 1421 1422 i915_gem_context_put(ctx); 1423 return simulated; 1424 } 1425 1426 struct intel_engine_capture_vma { 1427 struct intel_engine_capture_vma *next; 1428 struct i915_vma_resource *vma_res; 1429 char name[16]; 1430 bool lockdep_cookie; 1431 }; 1432 1433 static struct intel_engine_capture_vma * 1434 capture_vma_snapshot(struct intel_engine_capture_vma *next, 1435 struct i915_vma_resource *vma_res, 1436 gfp_t gfp, const char *name) 1437 { 1438 struct intel_engine_capture_vma *c; 1439 1440 if (!vma_res) 1441 return next; 1442 1443 c = kmalloc(sizeof(*c), gfp); 1444 if (!c) 1445 return next; 1446 1447 if (!i915_vma_resource_hold(vma_res, &c->lockdep_cookie)) { 1448 kfree(c); 1449 return next; 1450 } 1451 1452 strscpy(c->name, name); 1453 c->vma_res = i915_vma_resource_get(vma_res); 1454 1455 c->next = next; 1456 return c; 1457 } 1458 1459 static struct intel_engine_capture_vma * 1460 capture_vma(struct intel_engine_capture_vma *next, 1461 struct i915_vma *vma, 1462 const char *name, 1463 gfp_t gfp) 1464 { 1465 if (!vma) 1466 return next; 1467 1468 /* 1469 * If the vma isn't pinned, then the vma should be snapshotted 1470 * to a struct i915_vma_snapshot at command submission time. 1471 * Not here. 1472 */ 1473 if (GEM_WARN_ON(!i915_vma_is_pinned(vma))) 1474 return next; 1475 1476 next = capture_vma_snapshot(next, vma->resource, gfp, name); 1477 1478 return next; 1479 } 1480 1481 static struct intel_engine_capture_vma * 1482 capture_user(struct intel_engine_capture_vma *capture, 1483 const struct i915_request *rq, 1484 gfp_t gfp) 1485 { 1486 struct i915_capture_list *c; 1487 1488 for (c = rq->capture_list; c; c = c->next) 1489 capture = capture_vma_snapshot(capture, c->vma_res, gfp, 1490 "user"); 1491 1492 return capture; 1493 } 1494 1495 static void add_vma(struct intel_engine_coredump *ee, 1496 struct i915_vma_coredump *vma) 1497 { 1498 if (vma) { 1499 vma->next = ee->vma; 1500 ee->vma = vma; 1501 } 1502 } 1503 1504 static struct i915_vma_coredump * 1505 create_vma_coredump(const struct intel_gt *gt, struct i915_vma *vma, 1506 const char *name, struct i915_vma_compress *compress) 1507 { 1508 struct i915_vma_coredump *ret = NULL; 1509 struct i915_vma_resource *vma_res; 1510 bool lockdep_cookie; 1511 1512 if (!vma) 1513 return NULL; 1514 1515 vma_res = vma->resource; 1516 1517 if (i915_vma_resource_hold(vma_res, &lockdep_cookie)) { 1518 ret = i915_vma_coredump_create(gt, vma_res, compress, name); 1519 i915_vma_resource_unhold(vma_res, lockdep_cookie); 1520 } 1521 1522 return ret; 1523 } 1524 1525 static void add_vma_coredump(struct intel_engine_coredump *ee, 1526 const struct intel_gt *gt, 1527 struct i915_vma *vma, 1528 const char *name, 1529 struct i915_vma_compress *compress) 1530 { 1531 add_vma(ee, create_vma_coredump(gt, vma, name, compress)); 1532 } 1533 1534 struct intel_engine_coredump * 1535 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags) 1536 { 1537 struct intel_engine_coredump *ee; 1538 1539 ee = kzalloc(sizeof(*ee), gfp); 1540 if (!ee) 1541 return NULL; 1542 1543 ee->engine = engine; 1544 1545 if (!(dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)) { 1546 engine_record_registers(ee); 1547 engine_record_execlists(ee); 1548 } 1549 1550 return ee; 1551 } 1552 1553 static struct intel_engine_capture_vma * 1554 engine_coredump_add_context(struct intel_engine_coredump *ee, 1555 struct intel_context *ce, 1556 gfp_t gfp) 1557 { 1558 struct intel_engine_capture_vma *vma = NULL; 1559 1560 ee->simulated |= record_context(&ee->context, ce); 1561 if (ee->simulated) 1562 return NULL; 1563 1564 /* 1565 * We need to copy these to an anonymous buffer 1566 * as the simplest method to avoid being overwritten 1567 * by userspace. 1568 */ 1569 vma = capture_vma(vma, ce->ring->vma, "ring", gfp); 1570 vma = capture_vma(vma, ce->state, "HW context", gfp); 1571 1572 return vma; 1573 } 1574 1575 struct intel_engine_capture_vma * 1576 intel_engine_coredump_add_request(struct intel_engine_coredump *ee, 1577 struct i915_request *rq, 1578 gfp_t gfp) 1579 { 1580 struct intel_engine_capture_vma *vma; 1581 1582 vma = engine_coredump_add_context(ee, rq->context, gfp); 1583 if (!vma) 1584 return NULL; 1585 1586 /* 1587 * We need to copy these to an anonymous buffer 1588 * as the simplest method to avoid being overwritten 1589 * by userspace. 1590 */ 1591 vma = capture_vma_snapshot(vma, rq->batch_res, gfp, "batch"); 1592 vma = capture_user(vma, rq, gfp); 1593 1594 ee->rq_head = rq->head; 1595 ee->rq_post = rq->postfix; 1596 ee->rq_tail = rq->tail; 1597 1598 return vma; 1599 } 1600 1601 void 1602 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee, 1603 struct intel_engine_capture_vma *capture, 1604 struct i915_vma_compress *compress) 1605 { 1606 const struct intel_engine_cs *engine = ee->engine; 1607 1608 while (capture) { 1609 struct intel_engine_capture_vma *this = capture; 1610 struct i915_vma_resource *vma_res = this->vma_res; 1611 1612 add_vma(ee, 1613 i915_vma_coredump_create(engine->gt, vma_res, 1614 compress, this->name)); 1615 1616 i915_vma_resource_unhold(vma_res, this->lockdep_cookie); 1617 i915_vma_resource_put(vma_res); 1618 1619 capture = this->next; 1620 kfree(this); 1621 } 1622 1623 add_vma_coredump(ee, engine->gt, engine->status_page.vma, 1624 "HW Status", compress); 1625 1626 add_vma_coredump(ee, engine->gt, engine->wa_ctx.vma, 1627 "WA context", compress); 1628 } 1629 1630 static struct intel_engine_coredump * 1631 capture_engine(struct intel_engine_cs *engine, 1632 struct i915_vma_compress *compress, 1633 u32 dump_flags) 1634 { 1635 struct intel_engine_capture_vma *capture = NULL; 1636 struct intel_engine_coredump *ee; 1637 struct intel_context *ce = NULL; 1638 struct i915_request *rq = NULL; 1639 1640 ee = intel_engine_coredump_alloc(engine, ALLOW_FAIL, dump_flags); 1641 if (!ee) 1642 return NULL; 1643 1644 intel_engine_get_hung_entity(engine, &ce, &rq); 1645 if (rq && !i915_request_started(rq)) { 1646 /* 1647 * We want to know also what is the guc_id of the context, 1648 * but if we don't have the context reference, then skip 1649 * printing it. 1650 */ 1651 if (ce) 1652 drm_info(&engine->gt->i915->drm, 1653 "Got hung context on %s with active request %lld:%lld [0x%04X] not yet started\n", 1654 engine->name, rq->fence.context, rq->fence.seqno, ce->guc_id.id); 1655 else 1656 drm_info(&engine->gt->i915->drm, 1657 "Got hung context on %s with active request %lld:%lld not yet started\n", 1658 engine->name, rq->fence.context, rq->fence.seqno); 1659 } 1660 1661 if (rq) { 1662 capture = intel_engine_coredump_add_request(ee, rq, ATOMIC_MAYFAIL); 1663 i915_request_put(rq); 1664 } else if (ce) { 1665 capture = engine_coredump_add_context(ee, ce, ATOMIC_MAYFAIL); 1666 } 1667 1668 if (capture) { 1669 intel_engine_coredump_add_vma(ee, capture, compress); 1670 1671 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE) 1672 intel_guc_capture_get_matching_node(engine->gt, ee, ce); 1673 } else { 1674 kfree(ee); 1675 ee = NULL; 1676 } 1677 1678 return ee; 1679 } 1680 1681 static void 1682 gt_record_engines(struct intel_gt_coredump *gt, 1683 intel_engine_mask_t engine_mask, 1684 struct i915_vma_compress *compress, 1685 u32 dump_flags) 1686 { 1687 struct intel_engine_cs *engine; 1688 enum intel_engine_id id; 1689 1690 for_each_engine(engine, gt->_gt, id) { 1691 struct intel_engine_coredump *ee; 1692 1693 /* Refill our page pool before entering atomic section */ 1694 pool_refill(&compress->pool, ALLOW_FAIL); 1695 1696 ee = capture_engine(engine, compress, dump_flags); 1697 if (!ee) 1698 continue; 1699 1700 ee->hung = engine->mask & engine_mask; 1701 1702 gt->simulated |= ee->simulated; 1703 if (ee->simulated) { 1704 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE) 1705 intel_guc_capture_free_node(ee); 1706 kfree(ee); 1707 continue; 1708 } 1709 1710 ee->next = gt->engine; 1711 gt->engine = ee; 1712 } 1713 } 1714 1715 static void gt_record_guc_ctb(struct intel_ctb_coredump *saved, 1716 const struct intel_guc_ct_buffer *ctb, 1717 const void *blob_ptr, struct intel_guc *guc) 1718 { 1719 if (!ctb || !ctb->desc) 1720 return; 1721 1722 saved->raw_status = ctb->desc->status; 1723 saved->raw_head = ctb->desc->head; 1724 saved->raw_tail = ctb->desc->tail; 1725 saved->head = ctb->head; 1726 saved->tail = ctb->tail; 1727 saved->size = ctb->size; 1728 saved->desc_offset = ((void *)ctb->desc) - blob_ptr; 1729 saved->cmds_offset = ((void *)ctb->cmds) - blob_ptr; 1730 } 1731 1732 static struct intel_uc_coredump * 1733 gt_record_uc(struct intel_gt_coredump *gt, 1734 struct i915_vma_compress *compress) 1735 { 1736 const struct intel_uc *uc = >->_gt->uc; 1737 struct intel_uc_coredump *error_uc; 1738 1739 error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL); 1740 if (!error_uc) 1741 return NULL; 1742 1743 memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw)); 1744 memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw)); 1745 1746 error_uc->guc_fw.file_selected.path = kstrdup(uc->guc.fw.file_selected.path, ALLOW_FAIL); 1747 error_uc->huc_fw.file_selected.path = kstrdup(uc->huc.fw.file_selected.path, ALLOW_FAIL); 1748 error_uc->guc_fw.file_wanted.path = kstrdup(uc->guc.fw.file_wanted.path, ALLOW_FAIL); 1749 error_uc->huc_fw.file_wanted.path = kstrdup(uc->huc.fw.file_wanted.path, ALLOW_FAIL); 1750 1751 /* 1752 * Save the GuC log and include a timestamp reference for converting the 1753 * log times to system times (in conjunction with the error->boottime and 1754 * gt->clock_frequency fields saved elsewhere). 1755 */ 1756 error_uc->guc.timestamp = intel_uncore_read(gt->_gt->uncore, GUCPMTIMESTAMP); 1757 error_uc->guc.vma_log = create_vma_coredump(gt->_gt, uc->guc.log.vma, 1758 "GuC log buffer", compress); 1759 error_uc->guc.vma_ctb = create_vma_coredump(gt->_gt, uc->guc.ct.vma, 1760 "GuC CT buffer", compress); 1761 error_uc->guc.last_fence = uc->guc.ct.requests.last_fence; 1762 gt_record_guc_ctb(error_uc->guc.ctb + 0, &uc->guc.ct.ctbs.send, 1763 uc->guc.ct.ctbs.send.desc, (struct intel_guc *)&uc->guc); 1764 gt_record_guc_ctb(error_uc->guc.ctb + 1, &uc->guc.ct.ctbs.recv, 1765 uc->guc.ct.ctbs.send.desc, (struct intel_guc *)&uc->guc); 1766 1767 return error_uc; 1768 } 1769 1770 /* Capture display registers. */ 1771 static void gt_record_display_regs(struct intel_gt_coredump *gt) 1772 { 1773 struct intel_uncore *uncore = gt->_gt->uncore; 1774 struct drm_i915_private *i915 = uncore->i915; 1775 1776 if (DISPLAY_VER(i915) >= 6 && DISPLAY_VER(i915) < 20) 1777 gt->derrmr = intel_uncore_read(uncore, DERRMR); 1778 1779 if (GRAPHICS_VER(i915) >= 8) 1780 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); 1781 else if (IS_VALLEYVIEW(i915)) 1782 gt->ier = intel_uncore_read(uncore, VLV_IER); 1783 else if (HAS_PCH_SPLIT(i915)) 1784 gt->ier = intel_uncore_read(uncore, DEIER); 1785 else if (GRAPHICS_VER(i915) == 2) 1786 gt->ier = intel_uncore_read16(uncore, GEN2_IER); 1787 else 1788 gt->ier = intel_uncore_read(uncore, GEN2_IER); 1789 } 1790 1791 /* Capture all other registers that GuC doesn't capture. */ 1792 static void gt_record_global_nonguc_regs(struct intel_gt_coredump *gt) 1793 { 1794 struct intel_uncore *uncore = gt->_gt->uncore; 1795 struct drm_i915_private *i915 = uncore->i915; 1796 int i; 1797 1798 if (IS_VALLEYVIEW(i915)) { 1799 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1800 gt->ngtier = 1; 1801 } else if (GRAPHICS_VER(i915) >= 11) { 1802 gt->gtier[0] = 1803 intel_uncore_read(uncore, 1804 GEN11_RENDER_COPY_INTR_ENABLE); 1805 gt->gtier[1] = 1806 intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE); 1807 gt->gtier[2] = 1808 intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE); 1809 gt->gtier[3] = 1810 intel_uncore_read(uncore, 1811 GEN11_GPM_WGBOXPERF_INTR_ENABLE); 1812 gt->gtier[4] = 1813 intel_uncore_read(uncore, 1814 GEN11_CRYPTO_RSVD_INTR_ENABLE); 1815 gt->gtier[5] = 1816 intel_uncore_read(uncore, 1817 GEN11_GUNIT_CSME_INTR_ENABLE); 1818 gt->ngtier = 6; 1819 } else if (GRAPHICS_VER(i915) >= 8) { 1820 for (i = 0; i < 4; i++) 1821 gt->gtier[i] = 1822 intel_uncore_read(uncore, GEN8_GT_IER(i)); 1823 gt->ngtier = 4; 1824 } else if (HAS_PCH_SPLIT(i915)) { 1825 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1826 gt->ngtier = 1; 1827 } 1828 1829 gt->eir = intel_uncore_read(uncore, EIR); 1830 gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER); 1831 } 1832 1833 /* 1834 * Capture all registers that relate to workload submission. 1835 * NOTE: In GuC submission, when GuC resets an engine, it can dump these for us 1836 */ 1837 static void gt_record_global_regs(struct intel_gt_coredump *gt) 1838 { 1839 struct intel_uncore *uncore = gt->_gt->uncore; 1840 struct drm_i915_private *i915 = uncore->i915; 1841 int i; 1842 1843 /* 1844 * General organization 1845 * 1. Registers specific to a single generation 1846 * 2. Registers which belong to multiple generations 1847 * 3. Feature specific registers. 1848 * 4. Everything else 1849 * Please try to follow the order. 1850 */ 1851 1852 /* 1: Registers specific to a single generation */ 1853 if (IS_VALLEYVIEW(i915)) 1854 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV); 1855 1856 if (GRAPHICS_VER(i915) == 7) 1857 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT); 1858 1859 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) { 1860 gt->fault_data0 = intel_gt_mcr_read_any((struct intel_gt *)gt->_gt, 1861 XEHP_FAULT_TLB_DATA0); 1862 gt->fault_data1 = intel_gt_mcr_read_any((struct intel_gt *)gt->_gt, 1863 XEHP_FAULT_TLB_DATA1); 1864 } else if (GRAPHICS_VER(i915) >= 12) { 1865 gt->fault_data0 = intel_uncore_read(uncore, 1866 GEN12_FAULT_TLB_DATA0); 1867 gt->fault_data1 = intel_uncore_read(uncore, 1868 GEN12_FAULT_TLB_DATA1); 1869 } else if (GRAPHICS_VER(i915) >= 8) { 1870 gt->fault_data0 = intel_uncore_read(uncore, 1871 GEN8_FAULT_TLB_DATA0); 1872 gt->fault_data1 = intel_uncore_read(uncore, 1873 GEN8_FAULT_TLB_DATA1); 1874 } 1875 1876 if (GRAPHICS_VER(i915) == 6) { 1877 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE); 1878 gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL); 1879 gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE); 1880 } 1881 1882 /* 2: Registers which belong to multiple generations */ 1883 if (GRAPHICS_VER(i915) >= 7) 1884 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT); 1885 1886 if (GRAPHICS_VER(i915) >= 6) { 1887 if (GRAPHICS_VER(i915) < 12) { 1888 gt->error = intel_uncore_read(uncore, ERROR_GEN6); 1889 gt->done_reg = intel_uncore_read(uncore, DONE_REG); 1890 } 1891 } 1892 1893 /* 3: Feature specific registers */ 1894 if (IS_GRAPHICS_VER(i915, 6, 7)) { 1895 gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK); 1896 gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS); 1897 } 1898 1899 if (IS_GRAPHICS_VER(i915, 8, 11)) 1900 gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN); 1901 1902 if (GRAPHICS_VER(i915) == 12) 1903 gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG); 1904 1905 if (GRAPHICS_VER(i915) >= 12) { 1906 for (i = 0; i < I915_MAX_SFC; i++) { 1907 /* 1908 * SFC_DONE resides in the VD forcewake domain, so it 1909 * only exists if the corresponding VCS engine is 1910 * present. 1911 */ 1912 if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || 1913 !HAS_ENGINE(gt->_gt, _VCS(i * 2))) 1914 continue; 1915 1916 gt->sfc_done[i] = 1917 intel_uncore_read(uncore, GEN12_SFC_DONE(i)); 1918 } 1919 1920 gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE); 1921 } 1922 } 1923 1924 static void gt_record_info(struct intel_gt_coredump *gt) 1925 { 1926 memcpy(>->info, >->_gt->info, sizeof(struct intel_gt_info)); 1927 gt->clock_frequency = gt->_gt->clock_frequency; 1928 gt->clock_period_ns = gt->_gt->clock_period_ns; 1929 } 1930 1931 /* 1932 * Generate a semi-unique error code. The code is not meant to have meaning, The 1933 * code's only purpose is to try to prevent false duplicated bug reports by 1934 * grossly estimating a GPU error state. 1935 * 1936 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 1937 * the hang if we could strip the GTT offset information from it. 1938 * 1939 * It's only a small step better than a random number in its current form. 1940 */ 1941 static u32 generate_ecode(const struct intel_engine_coredump *ee) 1942 { 1943 /* 1944 * IPEHR would be an ideal way to detect errors, as it's the gross 1945 * measure of "the command that hung." However, has some very common 1946 * synchronization commands which almost always appear in the case 1947 * strictly a client bug. Use instdone to differentiate those some. 1948 */ 1949 return ee ? ee->ipehr ^ ee->instdone.instdone : 0; 1950 } 1951 1952 static const char *error_msg(struct i915_gpu_coredump *error) 1953 { 1954 struct intel_engine_coredump *first = NULL; 1955 unsigned int hung_classes = 0; 1956 struct intel_gt_coredump *gt; 1957 int len; 1958 1959 for (gt = error->gt; gt; gt = gt->next) { 1960 struct intel_engine_coredump *cs; 1961 1962 for (cs = gt->engine; cs; cs = cs->next) { 1963 if (cs->hung) { 1964 hung_classes |= BIT(cs->engine->uabi_class); 1965 if (!first) 1966 first = cs; 1967 } 1968 } 1969 } 1970 1971 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1972 "GPU HANG: ecode %d:%x:%08x", 1973 GRAPHICS_VER(error->i915), hung_classes, 1974 generate_ecode(first)); 1975 if (first && first->context.pid) { 1976 /* Just show the first executing process, more is confusing */ 1977 len += scnprintf(error->error_msg + len, 1978 sizeof(error->error_msg) - len, 1979 ", in %s [%d]", 1980 first->context.comm, first->context.pid); 1981 } 1982 1983 return error->error_msg; 1984 } 1985 1986 static void capture_gen(struct i915_gpu_coredump *error) 1987 { 1988 struct drm_i915_private *i915 = error->i915; 1989 1990 error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count); 1991 error->suspended = pm_runtime_suspended(i915->drm.dev); 1992 1993 error->iommu = i915_vtd_active(i915); 1994 error->reset_count = i915_reset_count(&i915->gpu_error); 1995 error->suspend_count = i915->suspend_count; 1996 1997 i915_params_copy(&error->params, &i915->params); 1998 memcpy(&error->device_info, 1999 INTEL_INFO(i915), 2000 sizeof(error->device_info)); 2001 memcpy(&error->runtime_info, 2002 RUNTIME_INFO(i915), 2003 sizeof(error->runtime_info)); 2004 error->driver_caps = i915->caps; 2005 } 2006 2007 struct i915_gpu_coredump * 2008 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp) 2009 { 2010 struct i915_gpu_coredump *error; 2011 2012 if (!i915->params.error_capture) 2013 return NULL; 2014 2015 error = kzalloc(sizeof(*error), gfp); 2016 if (!error) 2017 return NULL; 2018 2019 kref_init(&error->ref); 2020 error->i915 = i915; 2021 2022 error->time = ktime_get_real(); 2023 error->boottime = ktime_get_boottime(); 2024 error->uptime = ktime_sub(ktime_get(), to_gt(i915)->last_init_time); 2025 error->capture = jiffies; 2026 2027 capture_gen(error); 2028 2029 return error; 2030 } 2031 2032 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x)) 2033 2034 struct intel_gt_coredump * 2035 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags) 2036 { 2037 struct intel_gt_coredump *gc; 2038 2039 gc = kzalloc(sizeof(*gc), gfp); 2040 if (!gc) 2041 return NULL; 2042 2043 gc->_gt = gt; 2044 gc->awake = intel_gt_pm_is_awake(gt); 2045 2046 gt_record_display_regs(gc); 2047 gt_record_global_nonguc_regs(gc); 2048 2049 /* 2050 * GuC dumps global, eng-class and eng-instance registers 2051 * (that can change as part of engine state during execution) 2052 * before an engine is reset due to a hung context. 2053 * GuC captures and reports all three groups of registers 2054 * together as a single set before the engine is reset. 2055 * Thus, if GuC triggered the context reset we retrieve 2056 * the register values as part of gt_record_engines. 2057 */ 2058 if (!(dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)) 2059 gt_record_global_regs(gc); 2060 2061 gt_record_fences(gc); 2062 2063 return gc; 2064 } 2065 2066 struct i915_vma_compress * 2067 i915_vma_capture_prepare(struct intel_gt_coredump *gt) 2068 { 2069 struct i915_vma_compress *compress; 2070 2071 compress = kmalloc(sizeof(*compress), ALLOW_FAIL); 2072 if (!compress) 2073 return NULL; 2074 2075 if (!compress_init(compress)) { 2076 kfree(compress); 2077 return NULL; 2078 } 2079 2080 return compress; 2081 } 2082 2083 void i915_vma_capture_finish(struct intel_gt_coredump *gt, 2084 struct i915_vma_compress *compress) 2085 { 2086 if (!compress) 2087 return; 2088 2089 compress_fini(compress); 2090 kfree(compress); 2091 } 2092 2093 static struct i915_gpu_coredump * 2094 __i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags) 2095 { 2096 struct drm_i915_private *i915 = gt->i915; 2097 struct intel_display *display = &i915->display; 2098 struct i915_gpu_coredump *error; 2099 2100 /* Check if GPU capture has been disabled */ 2101 error = READ_ONCE(i915->gpu_error.first_error); 2102 if (IS_ERR(error)) 2103 return error; 2104 2105 error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL); 2106 if (!error) 2107 return ERR_PTR(-ENOMEM); 2108 2109 error->gt = intel_gt_coredump_alloc(gt, ALLOW_FAIL, dump_flags); 2110 if (error->gt) { 2111 struct i915_vma_compress *compress; 2112 2113 compress = i915_vma_capture_prepare(error->gt); 2114 if (!compress) { 2115 kfree(error->gt); 2116 kfree(error); 2117 return ERR_PTR(-ENOMEM); 2118 } 2119 2120 if (INTEL_INFO(i915)->has_gt_uc) { 2121 error->gt->uc = gt_record_uc(error->gt, compress); 2122 if (error->gt->uc) { 2123 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE) 2124 error->gt->uc->guc.is_guc_capture = true; 2125 else 2126 GEM_BUG_ON(error->gt->uc->guc.is_guc_capture); 2127 } 2128 } 2129 2130 gt_record_info(error->gt); 2131 gt_record_engines(error->gt, engine_mask, compress, dump_flags); 2132 2133 2134 i915_vma_capture_finish(error->gt, compress); 2135 2136 error->simulated |= error->gt->simulated; 2137 } 2138 2139 error->display_snapshot = intel_display_snapshot_capture(display); 2140 2141 return error; 2142 } 2143 2144 static struct i915_gpu_coredump * 2145 i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags) 2146 { 2147 static DEFINE_MUTEX(capture_mutex); 2148 int ret = mutex_lock_interruptible(&capture_mutex); 2149 struct i915_gpu_coredump *dump; 2150 2151 if (ret) 2152 return ERR_PTR(ret); 2153 2154 dump = __i915_gpu_coredump(gt, engine_mask, dump_flags); 2155 mutex_unlock(&capture_mutex); 2156 2157 return dump; 2158 } 2159 2160 void i915_error_state_store(struct i915_gpu_coredump *error) 2161 { 2162 struct drm_i915_private *i915; 2163 static bool warned; 2164 2165 if (IS_ERR_OR_NULL(error)) 2166 return; 2167 2168 i915 = error->i915; 2169 drm_info(&i915->drm, "%s\n", error_msg(error)); 2170 2171 if (error->simulated || 2172 cmpxchg(&i915->gpu_error.first_error, NULL, error)) 2173 return; 2174 2175 i915_gpu_coredump_get(error); 2176 2177 if (!xchg(&warned, true) && 2178 ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) { 2179 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 2180 pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n"); 2181 pr_info("Please see https://drm.pages.freedesktop.org/intel-docs/how-to-file-i915-bugs.html for details.\n"); 2182 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 2183 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n"); 2184 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n", 2185 i915->drm.primary->index); 2186 } 2187 } 2188 2189 /** 2190 * i915_capture_error_state - capture an error record for later analysis 2191 * @gt: intel_gt which originated the hang 2192 * @engine_mask: hung engines 2193 * @dump_flags: dump flags 2194 * 2195 * Should be called when an error is detected (either a hang or an error 2196 * interrupt) to capture error state from the time of the error. Fills 2197 * out a structure which becomes available in debugfs for user level tools 2198 * to pick up. 2199 */ 2200 void i915_capture_error_state(struct intel_gt *gt, 2201 intel_engine_mask_t engine_mask, u32 dump_flags) 2202 { 2203 struct i915_gpu_coredump *error; 2204 2205 error = i915_gpu_coredump(gt, engine_mask, dump_flags); 2206 if (IS_ERR(error)) { 2207 cmpxchg(>->i915->gpu_error.first_error, NULL, error); 2208 return; 2209 } 2210 2211 i915_error_state_store(error); 2212 i915_gpu_coredump_put(error); 2213 } 2214 2215 static struct i915_gpu_coredump * 2216 i915_first_error_state(struct drm_i915_private *i915) 2217 { 2218 struct i915_gpu_coredump *error; 2219 2220 spin_lock_irq(&i915->gpu_error.lock); 2221 error = i915->gpu_error.first_error; 2222 if (!IS_ERR_OR_NULL(error)) 2223 i915_gpu_coredump_get(error); 2224 spin_unlock_irq(&i915->gpu_error.lock); 2225 2226 return error; 2227 } 2228 2229 void i915_reset_error_state(struct drm_i915_private *i915) 2230 { 2231 struct i915_gpu_coredump *error; 2232 2233 spin_lock_irq(&i915->gpu_error.lock); 2234 error = i915->gpu_error.first_error; 2235 if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */ 2236 i915->gpu_error.first_error = NULL; 2237 spin_unlock_irq(&i915->gpu_error.lock); 2238 2239 if (!IS_ERR_OR_NULL(error)) 2240 i915_gpu_coredump_put(error); 2241 } 2242 2243 void i915_disable_error_state(struct drm_i915_private *i915, int err) 2244 { 2245 spin_lock_irq(&i915->gpu_error.lock); 2246 if (!i915->gpu_error.first_error) 2247 i915->gpu_error.first_error = ERR_PTR(err); 2248 spin_unlock_irq(&i915->gpu_error.lock); 2249 } 2250 2251 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) 2252 void intel_klog_error_capture(struct intel_gt *gt, 2253 intel_engine_mask_t engine_mask) 2254 { 2255 static int g_count; 2256 struct drm_i915_private *i915 = gt->i915; 2257 struct i915_gpu_coredump *error; 2258 intel_wakeref_t wakeref; 2259 size_t buf_size = PAGE_SIZE * 128; 2260 size_t pos_err; 2261 char *buf, *ptr, *next; 2262 int l_count = g_count++; 2263 int line = 0; 2264 2265 /* Can't allocate memory during a reset */ 2266 if (test_bit(I915_RESET_BACKOFF, >->reset.flags)) { 2267 drm_err(>->i915->drm, "[Capture/%d.%d] Inside GT reset, skipping error capture :(\n", 2268 l_count, line++); 2269 return; 2270 } 2271 2272 error = READ_ONCE(i915->gpu_error.first_error); 2273 if (error) { 2274 drm_err(&i915->drm, "[Capture/%d.%d] Clearing existing error capture first...\n", 2275 l_count, line++); 2276 i915_reset_error_state(i915); 2277 } 2278 2279 with_intel_runtime_pm(&i915->runtime_pm, wakeref) 2280 error = i915_gpu_coredump(gt, engine_mask, CORE_DUMP_FLAG_NONE); 2281 2282 if (IS_ERR(error)) { 2283 drm_err(&i915->drm, "[Capture/%d.%d] Failed to capture error capture: %ld!\n", 2284 l_count, line++, PTR_ERR(error)); 2285 return; 2286 } 2287 2288 buf = kvmalloc(buf_size, GFP_KERNEL); 2289 if (!buf) { 2290 drm_err(&i915->drm, "[Capture/%d.%d] Failed to allocate buffer for error capture!\n", 2291 l_count, line++); 2292 i915_gpu_coredump_put(error); 2293 return; 2294 } 2295 2296 drm_info(&i915->drm, "[Capture/%d.%d] Dumping i915 error capture for %ps...\n", 2297 l_count, line++, __builtin_return_address(0)); 2298 2299 /* Largest string length safe to print via dmesg */ 2300 # define MAX_CHUNK 800 2301 2302 pos_err = 0; 2303 while (1) { 2304 ssize_t got = i915_gpu_coredump_copy_to_buffer(error, buf, pos_err, buf_size - 1); 2305 2306 if (got <= 0) 2307 break; 2308 2309 buf[got] = 0; 2310 pos_err += got; 2311 2312 ptr = buf; 2313 while (got > 0) { 2314 size_t count; 2315 char tag[2]; 2316 2317 next = strnchr(ptr, got, '\n'); 2318 if (next) { 2319 count = next - ptr; 2320 *next = 0; 2321 tag[0] = '>'; 2322 tag[1] = '<'; 2323 } else { 2324 count = got; 2325 tag[0] = '}'; 2326 tag[1] = '{'; 2327 } 2328 2329 if (count > MAX_CHUNK) { 2330 size_t pos; 2331 char *ptr2 = ptr; 2332 2333 for (pos = MAX_CHUNK; pos < count; pos += MAX_CHUNK) { 2334 char chr = ptr[pos]; 2335 2336 ptr[pos] = 0; 2337 drm_info(&i915->drm, "[Capture/%d.%d] }%s{\n", 2338 l_count, line++, ptr2); 2339 ptr[pos] = chr; 2340 ptr2 = ptr + pos; 2341 2342 /* 2343 * If spewing large amounts of data via a serial console, 2344 * this can be a very slow process. So be friendly and try 2345 * not to cause 'softlockup on CPU' problems. 2346 */ 2347 cond_resched(); 2348 } 2349 2350 if (ptr2 < (ptr + count)) 2351 drm_info(&i915->drm, "[Capture/%d.%d] %c%s%c\n", 2352 l_count, line++, tag[0], ptr2, tag[1]); 2353 else if (tag[0] == '>') 2354 drm_info(&i915->drm, "[Capture/%d.%d] ><\n", 2355 l_count, line++); 2356 } else { 2357 drm_info(&i915->drm, "[Capture/%d.%d] %c%s%c\n", 2358 l_count, line++, tag[0], ptr, tag[1]); 2359 } 2360 2361 ptr = next; 2362 got -= count; 2363 if (next) { 2364 ptr++; 2365 got--; 2366 } 2367 2368 /* As above. */ 2369 cond_resched(); 2370 } 2371 2372 if (got) 2373 drm_info(&i915->drm, "[Capture/%d.%d] Got %zd bytes remaining!\n", 2374 l_count, line++, got); 2375 } 2376 2377 kvfree(buf); 2378 2379 drm_info(&i915->drm, "[Capture/%d.%d] Dumped %zd bytes\n", l_count, line++, pos_err); 2380 } 2381 #endif 2382 2383 static ssize_t gpu_state_read(struct file *file, char __user *ubuf, 2384 size_t count, loff_t *pos) 2385 { 2386 struct i915_gpu_coredump *error; 2387 ssize_t ret; 2388 void *buf; 2389 2390 error = file->private_data; 2391 if (!error) 2392 return 0; 2393 2394 /* Bounce buffer required because of kernfs __user API convenience. */ 2395 buf = kmalloc(count, GFP_KERNEL); 2396 if (!buf) 2397 return -ENOMEM; 2398 2399 ret = i915_gpu_coredump_copy_to_buffer(error, buf, *pos, count); 2400 if (ret <= 0) 2401 goto out; 2402 2403 if (!copy_to_user(ubuf, buf, ret)) 2404 *pos += ret; 2405 else 2406 ret = -EFAULT; 2407 2408 out: 2409 kfree(buf); 2410 return ret; 2411 } 2412 2413 static int gpu_state_release(struct inode *inode, struct file *file) 2414 { 2415 i915_gpu_coredump_put(file->private_data); 2416 return 0; 2417 } 2418 2419 static int i915_gpu_info_open(struct inode *inode, struct file *file) 2420 { 2421 struct drm_i915_private *i915 = inode->i_private; 2422 struct i915_gpu_coredump *gpu; 2423 intel_wakeref_t wakeref; 2424 2425 gpu = NULL; 2426 with_intel_runtime_pm(&i915->runtime_pm, wakeref) 2427 gpu = i915_gpu_coredump(to_gt(i915), ALL_ENGINES, CORE_DUMP_FLAG_NONE); 2428 2429 if (IS_ERR(gpu)) 2430 return PTR_ERR(gpu); 2431 2432 file->private_data = gpu; 2433 return 0; 2434 } 2435 2436 static const struct file_operations i915_gpu_info_fops = { 2437 .owner = THIS_MODULE, 2438 .open = i915_gpu_info_open, 2439 .read = gpu_state_read, 2440 .llseek = default_llseek, 2441 .release = gpu_state_release, 2442 }; 2443 2444 static ssize_t 2445 i915_error_state_write(struct file *filp, 2446 const char __user *ubuf, 2447 size_t cnt, 2448 loff_t *ppos) 2449 { 2450 struct i915_gpu_coredump *error = filp->private_data; 2451 2452 if (!error) 2453 return 0; 2454 2455 drm_dbg(&error->i915->drm, "Resetting error state\n"); 2456 i915_reset_error_state(error->i915); 2457 2458 return cnt; 2459 } 2460 2461 static int i915_error_state_open(struct inode *inode, struct file *file) 2462 { 2463 struct i915_gpu_coredump *error; 2464 2465 error = i915_first_error_state(inode->i_private); 2466 if (IS_ERR(error)) 2467 return PTR_ERR(error); 2468 2469 file->private_data = error; 2470 return 0; 2471 } 2472 2473 static const struct file_operations i915_error_state_fops = { 2474 .owner = THIS_MODULE, 2475 .open = i915_error_state_open, 2476 .read = gpu_state_read, 2477 .write = i915_error_state_write, 2478 .llseek = default_llseek, 2479 .release = gpu_state_release, 2480 }; 2481 2482 void i915_gpu_error_debugfs_register(struct drm_i915_private *i915) 2483 { 2484 struct drm_minor *minor = i915->drm.primary; 2485 2486 debugfs_create_file("i915_error_state", 0644, minor->debugfs_root, i915, 2487 &i915_error_state_fops); 2488 debugfs_create_file("i915_gpu_info", 0644, minor->debugfs_root, i915, 2489 &i915_gpu_info_fops); 2490 } 2491 2492 static ssize_t error_state_read(struct file *filp, struct kobject *kobj, 2493 struct bin_attribute *attr, char *buf, 2494 loff_t off, size_t count) 2495 { 2496 2497 struct device *kdev = kobj_to_dev(kobj); 2498 struct drm_i915_private *i915 = kdev_minor_to_i915(kdev); 2499 struct i915_gpu_coredump *gpu; 2500 ssize_t ret = 0; 2501 2502 /* 2503 * FIXME: Concurrent clients triggering resets and reading + clearing 2504 * dumps can cause inconsistent sysfs reads when a user calls in with a 2505 * non-zero offset to complete a prior partial read but the 2506 * gpu_coredump has been cleared or replaced. 2507 */ 2508 2509 gpu = i915_first_error_state(i915); 2510 if (IS_ERR(gpu)) { 2511 ret = PTR_ERR(gpu); 2512 } else if (gpu) { 2513 ret = i915_gpu_coredump_copy_to_buffer(gpu, buf, off, count); 2514 i915_gpu_coredump_put(gpu); 2515 } else { 2516 const char *str = "No error state collected\n"; 2517 size_t len = strlen(str); 2518 2519 if (off < len) { 2520 ret = min_t(size_t, count, len - off); 2521 memcpy(buf, str + off, ret); 2522 } 2523 } 2524 2525 return ret; 2526 } 2527 2528 static ssize_t error_state_write(struct file *file, struct kobject *kobj, 2529 struct bin_attribute *attr, char *buf, 2530 loff_t off, size_t count) 2531 { 2532 struct device *kdev = kobj_to_dev(kobj); 2533 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 2534 2535 drm_dbg(&dev_priv->drm, "Resetting error state\n"); 2536 i915_reset_error_state(dev_priv); 2537 2538 return count; 2539 } 2540 2541 static const struct bin_attribute error_state_attr = { 2542 .attr.name = "error", 2543 .attr.mode = S_IRUSR | S_IWUSR, 2544 .size = 0, 2545 .read = error_state_read, 2546 .write = error_state_write, 2547 }; 2548 2549 void i915_gpu_error_sysfs_setup(struct drm_i915_private *i915) 2550 { 2551 struct device *kdev = i915->drm.primary->kdev; 2552 2553 if (sysfs_create_bin_file(&kdev->kobj, &error_state_attr)) 2554 drm_err(&i915->drm, "error_state sysfs setup failed\n"); 2555 } 2556 2557 void i915_gpu_error_sysfs_teardown(struct drm_i915_private *i915) 2558 { 2559 struct device *kdev = i915->drm.primary->kdev; 2560 2561 sysfs_remove_bin_file(&kdev->kobj, &error_state_attr); 2562 } 2563