1 /* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30 #include <linux/ascii85.h> 31 #include <linux/highmem.h> 32 #include <linux/nmi.h> 33 #include <linux/pagevec.h> 34 #include <linux/scatterlist.h> 35 #include <linux/string_helpers.h> 36 #include <linux/utsname.h> 37 #include <linux/zlib.h> 38 39 #include <drm/drm_cache.h> 40 #include <drm/drm_print.h> 41 42 #include "display/intel_dmc.h" 43 #include "display/intel_overlay.h" 44 45 #include "gem/i915_gem_context.h" 46 #include "gem/i915_gem_lmem.h" 47 #include "gt/intel_engine_regs.h" 48 #include "gt/intel_gt.h" 49 #include "gt/intel_gt_mcr.h" 50 #include "gt/intel_gt_pm.h" 51 #include "gt/intel_gt_regs.h" 52 #include "gt/uc/intel_guc_capture.h" 53 54 #include "i915_driver.h" 55 #include "i915_drv.h" 56 #include "i915_gpu_error.h" 57 #include "i915_memcpy.h" 58 #include "i915_reg.h" 59 #include "i915_scatterlist.h" 60 #include "i915_utils.h" 61 62 #define ALLOW_FAIL (__GFP_KSWAPD_RECLAIM | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) 63 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN) 64 65 static void __sg_set_buf(struct scatterlist *sg, 66 void *addr, unsigned int len, loff_t it) 67 { 68 sg->page_link = (unsigned long)virt_to_page(addr); 69 sg->offset = offset_in_page(addr); 70 sg->length = len; 71 sg->dma_address = it; 72 } 73 74 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len) 75 { 76 if (!len) 77 return false; 78 79 if (e->bytes + len + 1 <= e->size) 80 return true; 81 82 if (e->bytes) { 83 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter); 84 e->iter += e->bytes; 85 e->buf = NULL; 86 e->bytes = 0; 87 } 88 89 if (e->cur == e->end) { 90 struct scatterlist *sgl; 91 92 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL); 93 if (!sgl) { 94 e->err = -ENOMEM; 95 return false; 96 } 97 98 if (e->cur) { 99 e->cur->offset = 0; 100 e->cur->length = 0; 101 e->cur->page_link = 102 (unsigned long)sgl | SG_CHAIN; 103 } else { 104 e->sgl = sgl; 105 } 106 107 e->cur = sgl; 108 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1; 109 } 110 111 e->size = ALIGN(len + 1, SZ_64K); 112 e->buf = kmalloc(e->size, ALLOW_FAIL); 113 if (!e->buf) { 114 e->size = PAGE_ALIGN(len + 1); 115 e->buf = kmalloc(e->size, GFP_KERNEL); 116 } 117 if (!e->buf) { 118 e->err = -ENOMEM; 119 return false; 120 } 121 122 return true; 123 } 124 125 __printf(2, 0) 126 static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 127 const char *fmt, va_list args) 128 { 129 va_list ap; 130 int len; 131 132 if (e->err) 133 return; 134 135 va_copy(ap, args); 136 len = vsnprintf(NULL, 0, fmt, ap); 137 va_end(ap); 138 if (len <= 0) { 139 e->err = len; 140 return; 141 } 142 143 if (!__i915_error_grow(e, len)) 144 return; 145 146 GEM_BUG_ON(e->bytes >= e->size); 147 len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args); 148 if (len < 0) { 149 e->err = len; 150 return; 151 } 152 e->bytes += len; 153 } 154 155 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str) 156 { 157 unsigned len; 158 159 if (e->err || !str) 160 return; 161 162 len = strlen(str); 163 if (!__i915_error_grow(e, len)) 164 return; 165 166 GEM_BUG_ON(e->bytes + len > e->size); 167 memcpy(e->buf + e->bytes, str, len); 168 e->bytes += len; 169 } 170 171 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 172 #define err_puts(e, s) i915_error_puts(e, s) 173 174 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf) 175 { 176 i915_error_vprintf(p->arg, vaf->fmt, *vaf->va); 177 } 178 179 static inline struct drm_printer 180 i915_error_printer(struct drm_i915_error_state_buf *e) 181 { 182 struct drm_printer p = { 183 .printfn = __i915_printfn_error, 184 .arg = e, 185 }; 186 return p; 187 } 188 189 /* single threaded page allocator with a reserved stash for emergencies */ 190 static void pool_fini(struct folio_batch *fbatch) 191 { 192 folio_batch_release(fbatch); 193 } 194 195 static int pool_refill(struct folio_batch *fbatch, gfp_t gfp) 196 { 197 while (folio_batch_space(fbatch)) { 198 struct folio *folio; 199 200 folio = folio_alloc(gfp, 0); 201 if (!folio) 202 return -ENOMEM; 203 204 folio_batch_add(fbatch, folio); 205 } 206 207 return 0; 208 } 209 210 static int pool_init(struct folio_batch *fbatch, gfp_t gfp) 211 { 212 int err; 213 214 folio_batch_init(fbatch); 215 216 err = pool_refill(fbatch, gfp); 217 if (err) 218 pool_fini(fbatch); 219 220 return err; 221 } 222 223 static void *pool_alloc(struct folio_batch *fbatch, gfp_t gfp) 224 { 225 struct folio *folio; 226 227 folio = folio_alloc(gfp, 0); 228 if (!folio && folio_batch_count(fbatch)) 229 folio = fbatch->folios[--fbatch->nr]; 230 231 return folio ? folio_address(folio) : NULL; 232 } 233 234 static void pool_free(struct folio_batch *fbatch, void *addr) 235 { 236 struct folio *folio = virt_to_folio(addr); 237 238 if (folio_batch_space(fbatch)) 239 folio_batch_add(fbatch, folio); 240 else 241 folio_put(folio); 242 } 243 244 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR 245 246 struct i915_vma_compress { 247 struct folio_batch pool; 248 struct z_stream_s zstream; 249 void *tmp; 250 }; 251 252 static bool compress_init(struct i915_vma_compress *c) 253 { 254 struct z_stream_s *zstream = &c->zstream; 255 256 if (pool_init(&c->pool, ALLOW_FAIL)) 257 return false; 258 259 zstream->workspace = 260 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL), 261 ALLOW_FAIL); 262 if (!zstream->workspace) { 263 pool_fini(&c->pool); 264 return false; 265 } 266 267 c->tmp = NULL; 268 if (i915_has_memcpy_from_wc()) 269 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL); 270 271 return true; 272 } 273 274 static bool compress_start(struct i915_vma_compress *c) 275 { 276 struct z_stream_s *zstream = &c->zstream; 277 void *workspace = zstream->workspace; 278 279 memset(zstream, 0, sizeof(*zstream)); 280 zstream->workspace = workspace; 281 282 return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK; 283 } 284 285 static void *compress_next_page(struct i915_vma_compress *c, 286 struct i915_vma_coredump *dst) 287 { 288 void *page_addr; 289 struct page *page; 290 291 page_addr = pool_alloc(&c->pool, ALLOW_FAIL); 292 if (!page_addr) 293 return ERR_PTR(-ENOMEM); 294 295 page = virt_to_page(page_addr); 296 list_add_tail(&page->lru, &dst->page_list); 297 return page_addr; 298 } 299 300 static int compress_page(struct i915_vma_compress *c, 301 void *src, 302 struct i915_vma_coredump *dst, 303 bool wc) 304 { 305 struct z_stream_s *zstream = &c->zstream; 306 307 zstream->next_in = src; 308 if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE)) 309 zstream->next_in = c->tmp; 310 zstream->avail_in = PAGE_SIZE; 311 312 do { 313 if (zstream->avail_out == 0) { 314 zstream->next_out = compress_next_page(c, dst); 315 if (IS_ERR(zstream->next_out)) 316 return PTR_ERR(zstream->next_out); 317 318 zstream->avail_out = PAGE_SIZE; 319 } 320 321 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK) 322 return -EIO; 323 324 cond_resched(); 325 } while (zstream->avail_in); 326 327 /* Fallback to uncompressed if we increase size? */ 328 if (0 && zstream->total_out > zstream->total_in) 329 return -E2BIG; 330 331 return 0; 332 } 333 334 static int compress_flush(struct i915_vma_compress *c, 335 struct i915_vma_coredump *dst) 336 { 337 struct z_stream_s *zstream = &c->zstream; 338 339 do { 340 switch (zlib_deflate(zstream, Z_FINISH)) { 341 case Z_OK: /* more space requested */ 342 zstream->next_out = compress_next_page(c, dst); 343 if (IS_ERR(zstream->next_out)) 344 return PTR_ERR(zstream->next_out); 345 346 zstream->avail_out = PAGE_SIZE; 347 break; 348 349 case Z_STREAM_END: 350 goto end; 351 352 default: /* any error */ 353 return -EIO; 354 } 355 } while (1); 356 357 end: 358 memset(zstream->next_out, 0, zstream->avail_out); 359 dst->unused = zstream->avail_out; 360 return 0; 361 } 362 363 static void compress_finish(struct i915_vma_compress *c) 364 { 365 zlib_deflateEnd(&c->zstream); 366 } 367 368 static void compress_fini(struct i915_vma_compress *c) 369 { 370 kfree(c->zstream.workspace); 371 if (c->tmp) 372 pool_free(&c->pool, c->tmp); 373 pool_fini(&c->pool); 374 } 375 376 static void err_compression_marker(struct drm_i915_error_state_buf *m) 377 { 378 err_puts(m, ":"); 379 } 380 381 #else 382 383 struct i915_vma_compress { 384 struct folio_batch pool; 385 }; 386 387 static bool compress_init(struct i915_vma_compress *c) 388 { 389 return pool_init(&c->pool, ALLOW_FAIL) == 0; 390 } 391 392 static bool compress_start(struct i915_vma_compress *c) 393 { 394 return true; 395 } 396 397 static int compress_page(struct i915_vma_compress *c, 398 void *src, 399 struct i915_vma_coredump *dst, 400 bool wc) 401 { 402 void *ptr; 403 404 ptr = pool_alloc(&c->pool, ALLOW_FAIL); 405 if (!ptr) 406 return -ENOMEM; 407 408 if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE))) 409 memcpy(ptr, src, PAGE_SIZE); 410 list_add_tail(&virt_to_page(ptr)->lru, &dst->page_list); 411 cond_resched(); 412 413 return 0; 414 } 415 416 static int compress_flush(struct i915_vma_compress *c, 417 struct i915_vma_coredump *dst) 418 { 419 return 0; 420 } 421 422 static void compress_finish(struct i915_vma_compress *c) 423 { 424 } 425 426 static void compress_fini(struct i915_vma_compress *c) 427 { 428 pool_fini(&c->pool); 429 } 430 431 static void err_compression_marker(struct drm_i915_error_state_buf *m) 432 { 433 err_puts(m, "~"); 434 } 435 436 #endif 437 438 static void error_print_instdone(struct drm_i915_error_state_buf *m, 439 const struct intel_engine_coredump *ee) 440 { 441 int slice; 442 int subslice; 443 int iter; 444 445 err_printf(m, " INSTDONE: 0x%08x\n", 446 ee->instdone.instdone); 447 448 if (ee->engine->class != RENDER_CLASS || GRAPHICS_VER(m->i915) <= 3) 449 return; 450 451 err_printf(m, " SC_INSTDONE: 0x%08x\n", 452 ee->instdone.slice_common); 453 454 if (GRAPHICS_VER(m->i915) <= 6) 455 return; 456 457 for_each_ss_steering(iter, ee->engine->gt, slice, subslice) 458 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", 459 slice, subslice, 460 ee->instdone.sampler[slice][subslice]); 461 462 for_each_ss_steering(iter, ee->engine->gt, slice, subslice) 463 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", 464 slice, subslice, 465 ee->instdone.row[slice][subslice]); 466 467 if (GRAPHICS_VER(m->i915) < 12) 468 return; 469 470 if (GRAPHICS_VER_FULL(m->i915) >= IP_VER(12, 55)) { 471 for_each_ss_steering(iter, ee->engine->gt, slice, subslice) 472 err_printf(m, " GEOM_SVGUNIT_INSTDONE[%d][%d]: 0x%08x\n", 473 slice, subslice, 474 ee->instdone.geom_svg[slice][subslice]); 475 } 476 477 err_printf(m, " SC_INSTDONE_EXTRA: 0x%08x\n", 478 ee->instdone.slice_common_extra[0]); 479 err_printf(m, " SC_INSTDONE_EXTRA2: 0x%08x\n", 480 ee->instdone.slice_common_extra[1]); 481 } 482 483 static void error_print_request(struct drm_i915_error_state_buf *m, 484 const char *prefix, 485 const struct i915_request_coredump *erq) 486 { 487 if (!erq->seqno) 488 return; 489 490 err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, head %08x, tail %08x\n", 491 prefix, erq->pid, erq->context, erq->seqno, 492 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, 493 &erq->flags) ? "!" : "", 494 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, 495 &erq->flags) ? "+" : "", 496 erq->sched_attr.priority, 497 erq->head, erq->tail); 498 } 499 500 static void error_print_context(struct drm_i915_error_state_buf *m, 501 const char *header, 502 const struct i915_gem_context_coredump *ctx) 503 { 504 err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n", 505 header, ctx->comm, ctx->pid, ctx->sched_attr.priority, 506 ctx->guilty, ctx->active, 507 ctx->total_runtime, ctx->avg_runtime); 508 err_printf(m, " context timeline seqno %u\n", ctx->hwsp_seqno); 509 } 510 511 static struct i915_vma_coredump * 512 __find_vma(struct i915_vma_coredump *vma, const char *name) 513 { 514 while (vma) { 515 if (strcmp(vma->name, name) == 0) 516 return vma; 517 vma = vma->next; 518 } 519 520 return NULL; 521 } 522 523 struct i915_vma_coredump * 524 intel_gpu_error_find_batch(const struct intel_engine_coredump *ee) 525 { 526 return __find_vma(ee->vma, "batch"); 527 } 528 529 static void error_print_engine(struct drm_i915_error_state_buf *m, 530 const struct intel_engine_coredump *ee) 531 { 532 struct i915_vma_coredump *batch; 533 int n; 534 535 err_printf(m, "%s command stream:\n", ee->engine->name); 536 err_printf(m, " CCID: 0x%08x\n", ee->ccid); 537 err_printf(m, " START: 0x%08x\n", ee->start); 538 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head); 539 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n", 540 ee->tail, ee->rq_post, ee->rq_tail); 541 err_printf(m, " CTL: 0x%08x\n", ee->ctl); 542 err_printf(m, " MODE: 0x%08x\n", ee->mode); 543 err_printf(m, " HWS: 0x%08x\n", ee->hws); 544 err_printf(m, " ACTHD: 0x%08x %08x\n", 545 (u32)(ee->acthd>>32), (u32)ee->acthd); 546 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir); 547 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr); 548 err_printf(m, " ESR: 0x%08x\n", ee->esr); 549 550 error_print_instdone(m, ee); 551 552 batch = intel_gpu_error_find_batch(ee); 553 if (batch) { 554 u64 start = batch->gtt_offset; 555 u64 end = start + batch->gtt_size; 556 557 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n", 558 upper_32_bits(start), lower_32_bits(start), 559 upper_32_bits(end), lower_32_bits(end)); 560 } 561 if (GRAPHICS_VER(m->i915) >= 4) { 562 err_printf(m, " BBADDR: 0x%08x_%08x\n", 563 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr); 564 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate); 565 err_printf(m, " INSTPS: 0x%08x\n", ee->instps); 566 } 567 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm); 568 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr), 569 lower_32_bits(ee->faddr)); 570 if (GRAPHICS_VER(m->i915) >= 6) { 571 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi); 572 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg); 573 } 574 if (GRAPHICS_VER(m->i915) >= 11) { 575 err_printf(m, " NOPID: 0x%08x\n", ee->nopid); 576 err_printf(m, " EXCC: 0x%08x\n", ee->excc); 577 err_printf(m, " CMD_CCTL: 0x%08x\n", ee->cmd_cctl); 578 err_printf(m, " CSCMDOP: 0x%08x\n", ee->cscmdop); 579 err_printf(m, " CTX_SR_CTL: 0x%08x\n", ee->ctx_sr_ctl); 580 err_printf(m, " DMA_FADDR_HI: 0x%08x\n", ee->dma_faddr_hi); 581 err_printf(m, " DMA_FADDR_LO: 0x%08x\n", ee->dma_faddr_lo); 582 } 583 if (HAS_PPGTT(m->i915)) { 584 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode); 585 586 if (GRAPHICS_VER(m->i915) >= 8) { 587 int i; 588 for (i = 0; i < 4; i++) 589 err_printf(m, " PDP%d: 0x%016llx\n", 590 i, ee->vm_info.pdp[i]); 591 } else { 592 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 593 ee->vm_info.pp_dir_base); 594 } 595 } 596 597 for (n = 0; n < ee->num_ports; n++) { 598 err_printf(m, " ELSP[%d]:", n); 599 error_print_request(m, " ", &ee->execlist[n]); 600 } 601 } 602 603 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 604 { 605 va_list args; 606 607 va_start(args, f); 608 i915_error_vprintf(e, f, args); 609 va_end(args); 610 } 611 612 void intel_gpu_error_print_vma(struct drm_i915_error_state_buf *m, 613 const struct intel_engine_cs *engine, 614 const struct i915_vma_coredump *vma) 615 { 616 char out[ASCII85_BUFSZ]; 617 struct page *page; 618 619 if (!vma) 620 return; 621 622 err_printf(m, "%s --- %s = 0x%08x %08x\n", 623 engine ? engine->name : "global", vma->name, 624 upper_32_bits(vma->gtt_offset), 625 lower_32_bits(vma->gtt_offset)); 626 627 if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K) 628 err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes); 629 630 err_compression_marker(m); 631 list_for_each_entry(page, &vma->page_list, lru) { 632 int i, len; 633 const u32 *addr = page_address(page); 634 635 len = PAGE_SIZE; 636 if (page == list_last_entry(&vma->page_list, typeof(*page), lru)) 637 len -= vma->unused; 638 len = ascii85_encode_len(len); 639 640 for (i = 0; i < len; i++) 641 err_puts(m, ascii85_encode(addr[i], out)); 642 } 643 err_puts(m, "\n"); 644 } 645 646 static void err_print_capabilities(struct drm_i915_error_state_buf *m, 647 struct i915_gpu_coredump *error) 648 { 649 struct drm_printer p = i915_error_printer(m); 650 651 intel_device_info_print(&error->device_info, &error->runtime_info, &p); 652 intel_display_device_info_print(&error->display_device_info, 653 &error->display_runtime_info, &p); 654 intel_driver_caps_print(&error->driver_caps, &p); 655 } 656 657 static void err_print_params(struct drm_i915_error_state_buf *m, 658 const struct i915_params *params) 659 { 660 struct drm_printer p = i915_error_printer(m); 661 662 i915_params_dump(params, &p); 663 intel_display_params_dump(m->i915, &p); 664 } 665 666 static void err_print_pciid(struct drm_i915_error_state_buf *m, 667 struct drm_i915_private *i915) 668 { 669 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 670 671 err_printf(m, "PCI ID: 0x%04x\n", pdev->device); 672 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision); 673 err_printf(m, "PCI Subsystem: %04x:%04x\n", 674 pdev->subsystem_vendor, 675 pdev->subsystem_device); 676 } 677 678 static void err_print_guc_ctb(struct drm_i915_error_state_buf *m, 679 const char *name, 680 const struct intel_ctb_coredump *ctb) 681 { 682 if (!ctb->size) 683 return; 684 685 err_printf(m, "GuC %s CTB: raw: 0x%08X, 0x%08X/%08X, cached: 0x%08X/%08X, desc = 0x%08X, buf = 0x%08X x 0x%08X\n", 686 name, ctb->raw_status, ctb->raw_head, ctb->raw_tail, 687 ctb->head, ctb->tail, ctb->desc_offset, ctb->cmds_offset, ctb->size); 688 } 689 690 static void err_print_uc(struct drm_i915_error_state_buf *m, 691 const struct intel_uc_coredump *error_uc) 692 { 693 struct drm_printer p = i915_error_printer(m); 694 695 intel_uc_fw_dump(&error_uc->guc_fw, &p); 696 intel_uc_fw_dump(&error_uc->huc_fw, &p); 697 err_printf(m, "GuC timestamp: 0x%08x\n", error_uc->guc.timestamp); 698 intel_gpu_error_print_vma(m, NULL, error_uc->guc.vma_log); 699 err_printf(m, "GuC CTB fence: %d\n", error_uc->guc.last_fence); 700 err_print_guc_ctb(m, "Send", error_uc->guc.ctb + 0); 701 err_print_guc_ctb(m, "Recv", error_uc->guc.ctb + 1); 702 intel_gpu_error_print_vma(m, NULL, error_uc->guc.vma_ctb); 703 } 704 705 static void err_free_sgl(struct scatterlist *sgl) 706 { 707 while (sgl) { 708 struct scatterlist *sg; 709 710 for (sg = sgl; !sg_is_chain(sg); sg++) { 711 kfree(sg_virt(sg)); 712 if (sg_is_last(sg)) 713 break; 714 } 715 716 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg); 717 free_page((unsigned long)sgl); 718 sgl = sg; 719 } 720 } 721 722 static void err_print_gt_info(struct drm_i915_error_state_buf *m, 723 struct intel_gt_coredump *gt) 724 { 725 struct drm_printer p = i915_error_printer(m); 726 727 intel_gt_info_print(>->info, &p); 728 intel_sseu_print_topology(gt->_gt->i915, >->info.sseu, &p); 729 } 730 731 static void err_print_gt_display(struct drm_i915_error_state_buf *m, 732 struct intel_gt_coredump *gt) 733 { 734 err_printf(m, "IER: 0x%08x\n", gt->ier); 735 err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr); 736 } 737 738 static void err_print_gt_global_nonguc(struct drm_i915_error_state_buf *m, 739 struct intel_gt_coredump *gt) 740 { 741 int i; 742 743 err_printf(m, "GT awake: %s\n", str_yes_no(gt->awake)); 744 err_printf(m, "CS timestamp frequency: %u Hz, %d ns\n", 745 gt->clock_frequency, gt->clock_period_ns); 746 err_printf(m, "EIR: 0x%08x\n", gt->eir); 747 err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er); 748 749 for (i = 0; i < gt->ngtier; i++) 750 err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]); 751 } 752 753 static void err_print_gt_global(struct drm_i915_error_state_buf *m, 754 struct intel_gt_coredump *gt) 755 { 756 err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake); 757 758 if (IS_GRAPHICS_VER(m->i915, 6, 11)) { 759 err_printf(m, "ERROR: 0x%08x\n", gt->error); 760 err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg); 761 } 762 763 if (GRAPHICS_VER(m->i915) >= 8) 764 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", 765 gt->fault_data1, gt->fault_data0); 766 767 if (GRAPHICS_VER(m->i915) == 7) 768 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int); 769 770 if (IS_GRAPHICS_VER(m->i915, 8, 11)) 771 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache); 772 773 if (GRAPHICS_VER(m->i915) == 12) 774 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err); 775 776 if (GRAPHICS_VER(m->i915) >= 12) { 777 int i; 778 779 for (i = 0; i < I915_MAX_SFC; i++) { 780 /* 781 * SFC_DONE resides in the VD forcewake domain, so it 782 * only exists if the corresponding VCS engine is 783 * present. 784 */ 785 if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || 786 !HAS_ENGINE(gt->_gt, _VCS(i * 2))) 787 continue; 788 789 err_printf(m, " SFC_DONE[%d]: 0x%08x\n", i, 790 gt->sfc_done[i]); 791 } 792 793 err_printf(m, " GAM_DONE: 0x%08x\n", gt->gam_done); 794 } 795 } 796 797 static void err_print_gt_fences(struct drm_i915_error_state_buf *m, 798 struct intel_gt_coredump *gt) 799 { 800 int i; 801 802 for (i = 0; i < gt->nfence; i++) 803 err_printf(m, " fence[%d] = %08llx\n", i, gt->fence[i]); 804 } 805 806 static void err_print_gt_engines(struct drm_i915_error_state_buf *m, 807 struct intel_gt_coredump *gt) 808 { 809 const struct intel_engine_coredump *ee; 810 811 for (ee = gt->engine; ee; ee = ee->next) { 812 const struct i915_vma_coredump *vma; 813 814 if (gt->uc && gt->uc->guc.is_guc_capture) { 815 if (ee->guc_capture_node) 816 intel_guc_capture_print_engine_node(m, ee); 817 else 818 err_printf(m, " Missing GuC capture node for %s\n", 819 ee->engine->name); 820 } else { 821 error_print_engine(m, ee); 822 } 823 824 err_printf(m, " hung: %u\n", ee->hung); 825 err_printf(m, " engine reset count: %u\n", ee->reset_count); 826 error_print_context(m, " Active context: ", &ee->context); 827 828 for (vma = ee->vma; vma; vma = vma->next) 829 intel_gpu_error_print_vma(m, ee->engine, vma); 830 } 831 832 } 833 834 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, 835 struct i915_gpu_coredump *error) 836 { 837 const struct intel_engine_coredump *ee; 838 struct timespec64 ts; 839 840 if (*error->error_msg) 841 err_printf(m, "%s\n", error->error_msg); 842 err_printf(m, "Kernel: %s %s\n", 843 init_utsname()->release, 844 init_utsname()->machine); 845 err_printf(m, "Driver: %s\n", DRIVER_DATE); 846 ts = ktime_to_timespec64(error->time); 847 err_printf(m, "Time: %lld s %ld us\n", 848 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 849 ts = ktime_to_timespec64(error->boottime); 850 err_printf(m, "Boottime: %lld s %ld us\n", 851 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 852 ts = ktime_to_timespec64(error->uptime); 853 err_printf(m, "Uptime: %lld s %ld us\n", 854 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 855 err_printf(m, "Capture: %lu jiffies; %d ms ago\n", 856 error->capture, jiffies_to_msecs(jiffies - error->capture)); 857 858 for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next) 859 err_printf(m, "Active process (on ring %s): %s [%d]\n", 860 ee->engine->name, 861 ee->context.comm, 862 ee->context.pid); 863 864 err_printf(m, "Reset count: %u\n", error->reset_count); 865 err_printf(m, "Suspend count: %u\n", error->suspend_count); 866 err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform)); 867 err_printf(m, "Subplatform: 0x%x\n", 868 intel_subplatform(&error->runtime_info, 869 error->device_info.platform)); 870 err_print_pciid(m, m->i915); 871 872 err_printf(m, "IOMMU enabled?: %d\n", error->iommu); 873 874 intel_dmc_print_error_state(m, m->i915); 875 876 err_printf(m, "RPM wakelock: %s\n", str_yes_no(error->wakelock)); 877 err_printf(m, "PM suspended: %s\n", str_yes_no(error->suspended)); 878 879 if (error->gt) { 880 bool print_guc_capture = false; 881 882 if (error->gt->uc && error->gt->uc->guc.is_guc_capture) 883 print_guc_capture = true; 884 885 err_print_gt_display(m, error->gt); 886 err_print_gt_global_nonguc(m, error->gt); 887 err_print_gt_fences(m, error->gt); 888 889 /* 890 * GuC dumped global, eng-class and eng-instance registers together 891 * as part of engine state dump so we print in err_print_gt_engines 892 */ 893 if (!print_guc_capture) 894 err_print_gt_global(m, error->gt); 895 896 err_print_gt_engines(m, error->gt); 897 898 if (error->gt->uc) 899 err_print_uc(m, error->gt->uc); 900 901 err_print_gt_info(m, error->gt); 902 } 903 904 if (error->overlay) 905 intel_overlay_print_error_state(m, error->overlay); 906 907 err_print_capabilities(m, error); 908 err_print_params(m, &error->params); 909 } 910 911 static int err_print_to_sgl(struct i915_gpu_coredump *error) 912 { 913 struct drm_i915_error_state_buf m; 914 915 if (IS_ERR(error)) 916 return PTR_ERR(error); 917 918 if (READ_ONCE(error->sgl)) 919 return 0; 920 921 memset(&m, 0, sizeof(m)); 922 m.i915 = error->i915; 923 924 __err_print_to_sgl(&m, error); 925 926 if (m.buf) { 927 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter); 928 m.bytes = 0; 929 m.buf = NULL; 930 } 931 if (m.cur) { 932 GEM_BUG_ON(m.end < m.cur); 933 sg_mark_end(m.cur - 1); 934 } 935 GEM_BUG_ON(m.sgl && !m.cur); 936 937 if (m.err) { 938 err_free_sgl(m.sgl); 939 return m.err; 940 } 941 942 if (cmpxchg(&error->sgl, NULL, m.sgl)) 943 err_free_sgl(m.sgl); 944 945 return 0; 946 } 947 948 ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error, 949 char *buf, loff_t off, size_t rem) 950 { 951 struct scatterlist *sg; 952 size_t count; 953 loff_t pos; 954 int err; 955 956 if (!error || !rem) 957 return 0; 958 959 err = err_print_to_sgl(error); 960 if (err) 961 return err; 962 963 sg = READ_ONCE(error->fit); 964 if (!sg || off < sg->dma_address) 965 sg = error->sgl; 966 if (!sg) 967 return 0; 968 969 pos = sg->dma_address; 970 count = 0; 971 do { 972 size_t len, start; 973 974 if (sg_is_chain(sg)) { 975 sg = sg_chain_ptr(sg); 976 GEM_BUG_ON(sg_is_chain(sg)); 977 } 978 979 len = sg->length; 980 if (pos + len <= off) { 981 pos += len; 982 continue; 983 } 984 985 start = sg->offset; 986 if (pos < off) { 987 GEM_BUG_ON(off - pos > len); 988 len -= off - pos; 989 start += off - pos; 990 pos = off; 991 } 992 993 len = min(len, rem); 994 GEM_BUG_ON(!len || len > sg->length); 995 996 memcpy(buf, page_address(sg_page(sg)) + start, len); 997 998 count += len; 999 pos += len; 1000 1001 buf += len; 1002 rem -= len; 1003 if (!rem) { 1004 WRITE_ONCE(error->fit, sg); 1005 break; 1006 } 1007 } while (!sg_is_last(sg++)); 1008 1009 return count; 1010 } 1011 1012 static void i915_vma_coredump_free(struct i915_vma_coredump *vma) 1013 { 1014 while (vma) { 1015 struct i915_vma_coredump *next = vma->next; 1016 struct page *page, *n; 1017 1018 list_for_each_entry_safe(page, n, &vma->page_list, lru) { 1019 list_del_init(&page->lru); 1020 __free_page(page); 1021 } 1022 1023 kfree(vma); 1024 vma = next; 1025 } 1026 } 1027 1028 static void cleanup_params(struct i915_gpu_coredump *error) 1029 { 1030 i915_params_free(&error->params); 1031 intel_display_params_free(&error->display_params); 1032 } 1033 1034 static void cleanup_uc(struct intel_uc_coredump *uc) 1035 { 1036 kfree(uc->guc_fw.file_selected.path); 1037 kfree(uc->huc_fw.file_selected.path); 1038 kfree(uc->guc_fw.file_wanted.path); 1039 kfree(uc->huc_fw.file_wanted.path); 1040 i915_vma_coredump_free(uc->guc.vma_log); 1041 i915_vma_coredump_free(uc->guc.vma_ctb); 1042 1043 kfree(uc); 1044 } 1045 1046 static void cleanup_gt(struct intel_gt_coredump *gt) 1047 { 1048 while (gt->engine) { 1049 struct intel_engine_coredump *ee = gt->engine; 1050 1051 gt->engine = ee->next; 1052 1053 i915_vma_coredump_free(ee->vma); 1054 intel_guc_capture_free_node(ee); 1055 kfree(ee); 1056 } 1057 1058 if (gt->uc) 1059 cleanup_uc(gt->uc); 1060 1061 kfree(gt); 1062 } 1063 1064 void __i915_gpu_coredump_free(struct kref *error_ref) 1065 { 1066 struct i915_gpu_coredump *error = 1067 container_of(error_ref, typeof(*error), ref); 1068 1069 while (error->gt) { 1070 struct intel_gt_coredump *gt = error->gt; 1071 1072 error->gt = gt->next; 1073 cleanup_gt(gt); 1074 } 1075 1076 kfree(error->overlay); 1077 1078 cleanup_params(error); 1079 1080 err_free_sgl(error->sgl); 1081 kfree(error); 1082 } 1083 1084 static struct i915_vma_coredump * 1085 i915_vma_coredump_create(const struct intel_gt *gt, 1086 const struct i915_vma_resource *vma_res, 1087 struct i915_vma_compress *compress, 1088 const char *name) 1089 1090 { 1091 struct i915_ggtt *ggtt = gt->ggtt; 1092 const u64 slot = ggtt->error_capture.start; 1093 struct i915_vma_coredump *dst; 1094 struct sgt_iter iter; 1095 int ret; 1096 1097 might_sleep(); 1098 1099 if (!vma_res || !vma_res->bi.pages || !compress) 1100 return NULL; 1101 1102 dst = kmalloc(sizeof(*dst), ALLOW_FAIL); 1103 if (!dst) 1104 return NULL; 1105 1106 if (!compress_start(compress)) { 1107 kfree(dst); 1108 return NULL; 1109 } 1110 1111 INIT_LIST_HEAD(&dst->page_list); 1112 strcpy(dst->name, name); 1113 dst->next = NULL; 1114 1115 dst->gtt_offset = vma_res->start; 1116 dst->gtt_size = vma_res->node_size; 1117 dst->gtt_page_sizes = vma_res->page_sizes_gtt; 1118 dst->unused = 0; 1119 1120 ret = -EINVAL; 1121 if (drm_mm_node_allocated(&ggtt->error_capture)) { 1122 void __iomem *s; 1123 dma_addr_t dma; 1124 1125 for_each_sgt_daddr(dma, iter, vma_res->bi.pages) { 1126 mutex_lock(&ggtt->error_mutex); 1127 if (ggtt->vm.raw_insert_page) 1128 ggtt->vm.raw_insert_page(&ggtt->vm, dma, slot, 1129 i915_gem_get_pat_index(gt->i915, 1130 I915_CACHE_NONE), 1131 0); 1132 else 1133 ggtt->vm.insert_page(&ggtt->vm, dma, slot, 1134 i915_gem_get_pat_index(gt->i915, 1135 I915_CACHE_NONE), 1136 0); 1137 mb(); 1138 1139 s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE); 1140 ret = compress_page(compress, 1141 (void __force *)s, dst, 1142 true); 1143 io_mapping_unmap(s); 1144 1145 mb(); 1146 ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE); 1147 mutex_unlock(&ggtt->error_mutex); 1148 if (ret) 1149 break; 1150 } 1151 } else if (vma_res->bi.lmem) { 1152 struct intel_memory_region *mem = vma_res->mr; 1153 dma_addr_t dma; 1154 1155 for_each_sgt_daddr(dma, iter, vma_res->bi.pages) { 1156 dma_addr_t offset = dma - mem->region.start; 1157 void __iomem *s; 1158 1159 if (offset + PAGE_SIZE > mem->io_size) { 1160 ret = -EINVAL; 1161 break; 1162 } 1163 1164 s = io_mapping_map_wc(&mem->iomap, offset, PAGE_SIZE); 1165 ret = compress_page(compress, 1166 (void __force *)s, dst, 1167 true); 1168 io_mapping_unmap(s); 1169 if (ret) 1170 break; 1171 } 1172 } else { 1173 struct page *page; 1174 1175 for_each_sgt_page(page, iter, vma_res->bi.pages) { 1176 void *s; 1177 1178 drm_clflush_pages(&page, 1); 1179 1180 s = kmap_local_page(page); 1181 ret = compress_page(compress, s, dst, false); 1182 kunmap_local(s); 1183 1184 drm_clflush_pages(&page, 1); 1185 1186 if (ret) 1187 break; 1188 } 1189 } 1190 1191 if (ret || compress_flush(compress, dst)) { 1192 struct page *page, *n; 1193 1194 list_for_each_entry_safe_reverse(page, n, &dst->page_list, lru) { 1195 list_del_init(&page->lru); 1196 pool_free(&compress->pool, page_address(page)); 1197 } 1198 1199 kfree(dst); 1200 dst = NULL; 1201 } 1202 compress_finish(compress); 1203 1204 return dst; 1205 } 1206 1207 static void gt_record_fences(struct intel_gt_coredump *gt) 1208 { 1209 struct i915_ggtt *ggtt = gt->_gt->ggtt; 1210 struct intel_uncore *uncore = gt->_gt->uncore; 1211 int i; 1212 1213 if (GRAPHICS_VER(uncore->i915) >= 6) { 1214 for (i = 0; i < ggtt->num_fences; i++) 1215 gt->fence[i] = 1216 intel_uncore_read64(uncore, 1217 FENCE_REG_GEN6_LO(i)); 1218 } else if (GRAPHICS_VER(uncore->i915) >= 4) { 1219 for (i = 0; i < ggtt->num_fences; i++) 1220 gt->fence[i] = 1221 intel_uncore_read64(uncore, 1222 FENCE_REG_965_LO(i)); 1223 } else { 1224 for (i = 0; i < ggtt->num_fences; i++) 1225 gt->fence[i] = 1226 intel_uncore_read(uncore, FENCE_REG(i)); 1227 } 1228 gt->nfence = i; 1229 } 1230 1231 static void engine_record_registers(struct intel_engine_coredump *ee) 1232 { 1233 const struct intel_engine_cs *engine = ee->engine; 1234 struct drm_i915_private *i915 = engine->i915; 1235 1236 if (GRAPHICS_VER(i915) >= 6) { 1237 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL); 1238 1239 /* 1240 * For the media GT, this ring fault register is not replicated, 1241 * so don't do multicast/replicated register read/write 1242 * operation on it. 1243 */ 1244 if (MEDIA_VER(i915) >= 13 && engine->gt->type == GT_MEDIA) 1245 ee->fault_reg = intel_uncore_read(engine->uncore, 1246 XELPMP_RING_FAULT_REG); 1247 1248 else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) 1249 ee->fault_reg = intel_gt_mcr_read_any(engine->gt, 1250 XEHP_RING_FAULT_REG); 1251 else if (GRAPHICS_VER(i915) >= 12) 1252 ee->fault_reg = intel_uncore_read(engine->uncore, 1253 GEN12_RING_FAULT_REG); 1254 else if (GRAPHICS_VER(i915) >= 8) 1255 ee->fault_reg = intel_uncore_read(engine->uncore, 1256 GEN8_RING_FAULT_REG); 1257 else 1258 ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine); 1259 } 1260 1261 if (GRAPHICS_VER(i915) >= 4) { 1262 ee->esr = ENGINE_READ(engine, RING_ESR); 1263 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD); 1264 ee->ipeir = ENGINE_READ(engine, RING_IPEIR); 1265 ee->ipehr = ENGINE_READ(engine, RING_IPEHR); 1266 ee->instps = ENGINE_READ(engine, RING_INSTPS); 1267 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR); 1268 ee->ccid = ENGINE_READ(engine, CCID); 1269 if (GRAPHICS_VER(i915) >= 8) { 1270 ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32; 1271 ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32; 1272 } 1273 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE); 1274 } else { 1275 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX); 1276 ee->ipeir = ENGINE_READ(engine, IPEIR); 1277 ee->ipehr = ENGINE_READ(engine, IPEHR); 1278 } 1279 1280 if (GRAPHICS_VER(i915) >= 11) { 1281 ee->cmd_cctl = ENGINE_READ(engine, RING_CMD_CCTL); 1282 ee->cscmdop = ENGINE_READ(engine, RING_CSCMDOP); 1283 ee->ctx_sr_ctl = ENGINE_READ(engine, RING_CTX_SR_CTL); 1284 ee->dma_faddr_hi = ENGINE_READ(engine, RING_DMA_FADD_UDW); 1285 ee->dma_faddr_lo = ENGINE_READ(engine, RING_DMA_FADD); 1286 ee->nopid = ENGINE_READ(engine, RING_NOPID); 1287 ee->excc = ENGINE_READ(engine, RING_EXCC); 1288 } 1289 1290 intel_engine_get_instdone(engine, &ee->instdone); 1291 1292 ee->instpm = ENGINE_READ(engine, RING_INSTPM); 1293 ee->acthd = intel_engine_get_active_head(engine); 1294 ee->start = ENGINE_READ(engine, RING_START); 1295 ee->head = ENGINE_READ(engine, RING_HEAD); 1296 ee->tail = ENGINE_READ(engine, RING_TAIL); 1297 ee->ctl = ENGINE_READ(engine, RING_CTL); 1298 if (GRAPHICS_VER(i915) > 2) 1299 ee->mode = ENGINE_READ(engine, RING_MI_MODE); 1300 1301 if (!HWS_NEEDS_PHYSICAL(i915)) { 1302 i915_reg_t mmio; 1303 1304 if (GRAPHICS_VER(i915) == 7) { 1305 switch (engine->id) { 1306 default: 1307 MISSING_CASE(engine->id); 1308 fallthrough; 1309 case RCS0: 1310 mmio = RENDER_HWS_PGA_GEN7; 1311 break; 1312 case BCS0: 1313 mmio = BLT_HWS_PGA_GEN7; 1314 break; 1315 case VCS0: 1316 mmio = BSD_HWS_PGA_GEN7; 1317 break; 1318 case VECS0: 1319 mmio = VEBOX_HWS_PGA_GEN7; 1320 break; 1321 } 1322 } else if (GRAPHICS_VER(engine->i915) == 6) { 1323 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); 1324 } else { 1325 /* XXX: gen8 returns to sanity */ 1326 mmio = RING_HWS_PGA(engine->mmio_base); 1327 } 1328 1329 ee->hws = intel_uncore_read(engine->uncore, mmio); 1330 } 1331 1332 ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine); 1333 1334 if (HAS_PPGTT(i915)) { 1335 int i; 1336 1337 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7); 1338 1339 if (GRAPHICS_VER(i915) == 6) { 1340 ee->vm_info.pp_dir_base = 1341 ENGINE_READ(engine, RING_PP_DIR_BASE_READ); 1342 } else if (GRAPHICS_VER(i915) == 7) { 1343 ee->vm_info.pp_dir_base = 1344 ENGINE_READ(engine, RING_PP_DIR_BASE); 1345 } else if (GRAPHICS_VER(i915) >= 8) { 1346 u32 base = engine->mmio_base; 1347 1348 for (i = 0; i < 4; i++) { 1349 ee->vm_info.pdp[i] = 1350 intel_uncore_read(engine->uncore, 1351 GEN8_RING_PDP_UDW(base, i)); 1352 ee->vm_info.pdp[i] <<= 32; 1353 ee->vm_info.pdp[i] |= 1354 intel_uncore_read(engine->uncore, 1355 GEN8_RING_PDP_LDW(base, i)); 1356 } 1357 } 1358 } 1359 } 1360 1361 static void record_request(const struct i915_request *request, 1362 struct i915_request_coredump *erq) 1363 { 1364 erq->flags = request->fence.flags; 1365 erq->context = request->fence.context; 1366 erq->seqno = request->fence.seqno; 1367 erq->sched_attr = request->sched.attr; 1368 erq->head = request->head; 1369 erq->tail = request->tail; 1370 1371 erq->pid = 0; 1372 rcu_read_lock(); 1373 if (!intel_context_is_closed(request->context)) { 1374 const struct i915_gem_context *ctx; 1375 1376 ctx = rcu_dereference(request->context->gem_context); 1377 if (ctx) 1378 erq->pid = pid_nr(ctx->pid); 1379 } 1380 rcu_read_unlock(); 1381 } 1382 1383 static void engine_record_execlists(struct intel_engine_coredump *ee) 1384 { 1385 const struct intel_engine_execlists * const el = &ee->engine->execlists; 1386 struct i915_request * const *port = el->active; 1387 unsigned int n = 0; 1388 1389 while (*port) 1390 record_request(*port++, &ee->execlist[n++]); 1391 1392 ee->num_ports = n; 1393 } 1394 1395 static bool record_context(struct i915_gem_context_coredump *e, 1396 struct intel_context *ce) 1397 { 1398 struct i915_gem_context *ctx; 1399 struct task_struct *task; 1400 bool simulated; 1401 1402 rcu_read_lock(); 1403 ctx = rcu_dereference(ce->gem_context); 1404 if (ctx && !kref_get_unless_zero(&ctx->ref)) 1405 ctx = NULL; 1406 rcu_read_unlock(); 1407 if (!ctx) 1408 return true; 1409 1410 rcu_read_lock(); 1411 task = pid_task(ctx->pid, PIDTYPE_PID); 1412 if (task) { 1413 strcpy(e->comm, task->comm); 1414 e->pid = task->pid; 1415 } 1416 rcu_read_unlock(); 1417 1418 e->sched_attr = ctx->sched; 1419 e->guilty = atomic_read(&ctx->guilty_count); 1420 e->active = atomic_read(&ctx->active_count); 1421 e->hwsp_seqno = (ce->timeline && ce->timeline->hwsp_seqno) ? 1422 *ce->timeline->hwsp_seqno : ~0U; 1423 1424 e->total_runtime = intel_context_get_total_runtime_ns(ce); 1425 e->avg_runtime = intel_context_get_avg_runtime_ns(ce); 1426 1427 simulated = i915_gem_context_no_error_capture(ctx); 1428 1429 i915_gem_context_put(ctx); 1430 return simulated; 1431 } 1432 1433 struct intel_engine_capture_vma { 1434 struct intel_engine_capture_vma *next; 1435 struct i915_vma_resource *vma_res; 1436 char name[16]; 1437 bool lockdep_cookie; 1438 }; 1439 1440 static struct intel_engine_capture_vma * 1441 capture_vma_snapshot(struct intel_engine_capture_vma *next, 1442 struct i915_vma_resource *vma_res, 1443 gfp_t gfp, const char *name) 1444 { 1445 struct intel_engine_capture_vma *c; 1446 1447 if (!vma_res) 1448 return next; 1449 1450 c = kmalloc(sizeof(*c), gfp); 1451 if (!c) 1452 return next; 1453 1454 if (!i915_vma_resource_hold(vma_res, &c->lockdep_cookie)) { 1455 kfree(c); 1456 return next; 1457 } 1458 1459 strcpy(c->name, name); 1460 c->vma_res = i915_vma_resource_get(vma_res); 1461 1462 c->next = next; 1463 return c; 1464 } 1465 1466 static struct intel_engine_capture_vma * 1467 capture_vma(struct intel_engine_capture_vma *next, 1468 struct i915_vma *vma, 1469 const char *name, 1470 gfp_t gfp) 1471 { 1472 if (!vma) 1473 return next; 1474 1475 /* 1476 * If the vma isn't pinned, then the vma should be snapshotted 1477 * to a struct i915_vma_snapshot at command submission time. 1478 * Not here. 1479 */ 1480 if (GEM_WARN_ON(!i915_vma_is_pinned(vma))) 1481 return next; 1482 1483 next = capture_vma_snapshot(next, vma->resource, gfp, name); 1484 1485 return next; 1486 } 1487 1488 static struct intel_engine_capture_vma * 1489 capture_user(struct intel_engine_capture_vma *capture, 1490 const struct i915_request *rq, 1491 gfp_t gfp) 1492 { 1493 struct i915_capture_list *c; 1494 1495 for (c = rq->capture_list; c; c = c->next) 1496 capture = capture_vma_snapshot(capture, c->vma_res, gfp, 1497 "user"); 1498 1499 return capture; 1500 } 1501 1502 static void add_vma(struct intel_engine_coredump *ee, 1503 struct i915_vma_coredump *vma) 1504 { 1505 if (vma) { 1506 vma->next = ee->vma; 1507 ee->vma = vma; 1508 } 1509 } 1510 1511 static struct i915_vma_coredump * 1512 create_vma_coredump(const struct intel_gt *gt, struct i915_vma *vma, 1513 const char *name, struct i915_vma_compress *compress) 1514 { 1515 struct i915_vma_coredump *ret = NULL; 1516 struct i915_vma_resource *vma_res; 1517 bool lockdep_cookie; 1518 1519 if (!vma) 1520 return NULL; 1521 1522 vma_res = vma->resource; 1523 1524 if (i915_vma_resource_hold(vma_res, &lockdep_cookie)) { 1525 ret = i915_vma_coredump_create(gt, vma_res, compress, name); 1526 i915_vma_resource_unhold(vma_res, lockdep_cookie); 1527 } 1528 1529 return ret; 1530 } 1531 1532 static void add_vma_coredump(struct intel_engine_coredump *ee, 1533 const struct intel_gt *gt, 1534 struct i915_vma *vma, 1535 const char *name, 1536 struct i915_vma_compress *compress) 1537 { 1538 add_vma(ee, create_vma_coredump(gt, vma, name, compress)); 1539 } 1540 1541 struct intel_engine_coredump * 1542 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags) 1543 { 1544 struct intel_engine_coredump *ee; 1545 1546 ee = kzalloc(sizeof(*ee), gfp); 1547 if (!ee) 1548 return NULL; 1549 1550 ee->engine = engine; 1551 1552 if (!(dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)) { 1553 engine_record_registers(ee); 1554 engine_record_execlists(ee); 1555 } 1556 1557 return ee; 1558 } 1559 1560 static struct intel_engine_capture_vma * 1561 engine_coredump_add_context(struct intel_engine_coredump *ee, 1562 struct intel_context *ce, 1563 gfp_t gfp) 1564 { 1565 struct intel_engine_capture_vma *vma = NULL; 1566 1567 ee->simulated |= record_context(&ee->context, ce); 1568 if (ee->simulated) 1569 return NULL; 1570 1571 /* 1572 * We need to copy these to an anonymous buffer 1573 * as the simplest method to avoid being overwritten 1574 * by userspace. 1575 */ 1576 vma = capture_vma(vma, ce->ring->vma, "ring", gfp); 1577 vma = capture_vma(vma, ce->state, "HW context", gfp); 1578 1579 return vma; 1580 } 1581 1582 struct intel_engine_capture_vma * 1583 intel_engine_coredump_add_request(struct intel_engine_coredump *ee, 1584 struct i915_request *rq, 1585 gfp_t gfp) 1586 { 1587 struct intel_engine_capture_vma *vma; 1588 1589 vma = engine_coredump_add_context(ee, rq->context, gfp); 1590 if (!vma) 1591 return NULL; 1592 1593 /* 1594 * We need to copy these to an anonymous buffer 1595 * as the simplest method to avoid being overwritten 1596 * by userspace. 1597 */ 1598 vma = capture_vma_snapshot(vma, rq->batch_res, gfp, "batch"); 1599 vma = capture_user(vma, rq, gfp); 1600 1601 ee->rq_head = rq->head; 1602 ee->rq_post = rq->postfix; 1603 ee->rq_tail = rq->tail; 1604 1605 return vma; 1606 } 1607 1608 void 1609 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee, 1610 struct intel_engine_capture_vma *capture, 1611 struct i915_vma_compress *compress) 1612 { 1613 const struct intel_engine_cs *engine = ee->engine; 1614 1615 while (capture) { 1616 struct intel_engine_capture_vma *this = capture; 1617 struct i915_vma_resource *vma_res = this->vma_res; 1618 1619 add_vma(ee, 1620 i915_vma_coredump_create(engine->gt, vma_res, 1621 compress, this->name)); 1622 1623 i915_vma_resource_unhold(vma_res, this->lockdep_cookie); 1624 i915_vma_resource_put(vma_res); 1625 1626 capture = this->next; 1627 kfree(this); 1628 } 1629 1630 add_vma_coredump(ee, engine->gt, engine->status_page.vma, 1631 "HW Status", compress); 1632 1633 add_vma_coredump(ee, engine->gt, engine->wa_ctx.vma, 1634 "WA context", compress); 1635 } 1636 1637 static struct intel_engine_coredump * 1638 capture_engine(struct intel_engine_cs *engine, 1639 struct i915_vma_compress *compress, 1640 u32 dump_flags) 1641 { 1642 struct intel_engine_capture_vma *capture = NULL; 1643 struct intel_engine_coredump *ee; 1644 struct intel_context *ce = NULL; 1645 struct i915_request *rq = NULL; 1646 1647 ee = intel_engine_coredump_alloc(engine, ALLOW_FAIL, dump_flags); 1648 if (!ee) 1649 return NULL; 1650 1651 intel_engine_get_hung_entity(engine, &ce, &rq); 1652 if (rq && !i915_request_started(rq)) 1653 drm_info(&engine->gt->i915->drm, "Got hung context on %s with active request %lld:%lld [0x%04X] not yet started\n", 1654 engine->name, rq->fence.context, rq->fence.seqno, ce->guc_id.id); 1655 1656 if (rq) { 1657 capture = intel_engine_coredump_add_request(ee, rq, ATOMIC_MAYFAIL); 1658 i915_request_put(rq); 1659 } else if (ce) { 1660 capture = engine_coredump_add_context(ee, ce, ATOMIC_MAYFAIL); 1661 } 1662 1663 if (capture) { 1664 intel_engine_coredump_add_vma(ee, capture, compress); 1665 1666 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE) 1667 intel_guc_capture_get_matching_node(engine->gt, ee, ce); 1668 } else { 1669 kfree(ee); 1670 ee = NULL; 1671 } 1672 1673 return ee; 1674 } 1675 1676 static void 1677 gt_record_engines(struct intel_gt_coredump *gt, 1678 intel_engine_mask_t engine_mask, 1679 struct i915_vma_compress *compress, 1680 u32 dump_flags) 1681 { 1682 struct intel_engine_cs *engine; 1683 enum intel_engine_id id; 1684 1685 for_each_engine(engine, gt->_gt, id) { 1686 struct intel_engine_coredump *ee; 1687 1688 /* Refill our page pool before entering atomic section */ 1689 pool_refill(&compress->pool, ALLOW_FAIL); 1690 1691 ee = capture_engine(engine, compress, dump_flags); 1692 if (!ee) 1693 continue; 1694 1695 ee->hung = engine->mask & engine_mask; 1696 1697 gt->simulated |= ee->simulated; 1698 if (ee->simulated) { 1699 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE) 1700 intel_guc_capture_free_node(ee); 1701 kfree(ee); 1702 continue; 1703 } 1704 1705 ee->next = gt->engine; 1706 gt->engine = ee; 1707 } 1708 } 1709 1710 static void gt_record_guc_ctb(struct intel_ctb_coredump *saved, 1711 const struct intel_guc_ct_buffer *ctb, 1712 const void *blob_ptr, struct intel_guc *guc) 1713 { 1714 if (!ctb || !ctb->desc) 1715 return; 1716 1717 saved->raw_status = ctb->desc->status; 1718 saved->raw_head = ctb->desc->head; 1719 saved->raw_tail = ctb->desc->tail; 1720 saved->head = ctb->head; 1721 saved->tail = ctb->tail; 1722 saved->size = ctb->size; 1723 saved->desc_offset = ((void *)ctb->desc) - blob_ptr; 1724 saved->cmds_offset = ((void *)ctb->cmds) - blob_ptr; 1725 } 1726 1727 static struct intel_uc_coredump * 1728 gt_record_uc(struct intel_gt_coredump *gt, 1729 struct i915_vma_compress *compress) 1730 { 1731 const struct intel_uc *uc = >->_gt->uc; 1732 struct intel_uc_coredump *error_uc; 1733 1734 error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL); 1735 if (!error_uc) 1736 return NULL; 1737 1738 memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw)); 1739 memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw)); 1740 1741 error_uc->guc_fw.file_selected.path = kstrdup(uc->guc.fw.file_selected.path, ALLOW_FAIL); 1742 error_uc->huc_fw.file_selected.path = kstrdup(uc->huc.fw.file_selected.path, ALLOW_FAIL); 1743 error_uc->guc_fw.file_wanted.path = kstrdup(uc->guc.fw.file_wanted.path, ALLOW_FAIL); 1744 error_uc->huc_fw.file_wanted.path = kstrdup(uc->huc.fw.file_wanted.path, ALLOW_FAIL); 1745 1746 /* 1747 * Save the GuC log and include a timestamp reference for converting the 1748 * log times to system times (in conjunction with the error->boottime and 1749 * gt->clock_frequency fields saved elsewhere). 1750 */ 1751 error_uc->guc.timestamp = intel_uncore_read(gt->_gt->uncore, GUCPMTIMESTAMP); 1752 error_uc->guc.vma_log = create_vma_coredump(gt->_gt, uc->guc.log.vma, 1753 "GuC log buffer", compress); 1754 error_uc->guc.vma_ctb = create_vma_coredump(gt->_gt, uc->guc.ct.vma, 1755 "GuC CT buffer", compress); 1756 error_uc->guc.last_fence = uc->guc.ct.requests.last_fence; 1757 gt_record_guc_ctb(error_uc->guc.ctb + 0, &uc->guc.ct.ctbs.send, 1758 uc->guc.ct.ctbs.send.desc, (struct intel_guc *)&uc->guc); 1759 gt_record_guc_ctb(error_uc->guc.ctb + 1, &uc->guc.ct.ctbs.recv, 1760 uc->guc.ct.ctbs.send.desc, (struct intel_guc *)&uc->guc); 1761 1762 return error_uc; 1763 } 1764 1765 /* Capture display registers. */ 1766 static void gt_record_display_regs(struct intel_gt_coredump *gt) 1767 { 1768 struct intel_uncore *uncore = gt->_gt->uncore; 1769 struct drm_i915_private *i915 = uncore->i915; 1770 1771 if (DISPLAY_VER(i915) >= 6 && DISPLAY_VER(i915) < 20) 1772 gt->derrmr = intel_uncore_read(uncore, DERRMR); 1773 1774 if (GRAPHICS_VER(i915) >= 8) 1775 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); 1776 else if (IS_VALLEYVIEW(i915)) 1777 gt->ier = intel_uncore_read(uncore, VLV_IER); 1778 else if (HAS_PCH_SPLIT(i915)) 1779 gt->ier = intel_uncore_read(uncore, DEIER); 1780 else if (GRAPHICS_VER(i915) == 2) 1781 gt->ier = intel_uncore_read16(uncore, GEN2_IER); 1782 else 1783 gt->ier = intel_uncore_read(uncore, GEN2_IER); 1784 } 1785 1786 /* Capture all other registers that GuC doesn't capture. */ 1787 static void gt_record_global_nonguc_regs(struct intel_gt_coredump *gt) 1788 { 1789 struct intel_uncore *uncore = gt->_gt->uncore; 1790 struct drm_i915_private *i915 = uncore->i915; 1791 int i; 1792 1793 if (IS_VALLEYVIEW(i915)) { 1794 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1795 gt->ngtier = 1; 1796 } else if (GRAPHICS_VER(i915) >= 11) { 1797 gt->gtier[0] = 1798 intel_uncore_read(uncore, 1799 GEN11_RENDER_COPY_INTR_ENABLE); 1800 gt->gtier[1] = 1801 intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE); 1802 gt->gtier[2] = 1803 intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE); 1804 gt->gtier[3] = 1805 intel_uncore_read(uncore, 1806 GEN11_GPM_WGBOXPERF_INTR_ENABLE); 1807 gt->gtier[4] = 1808 intel_uncore_read(uncore, 1809 GEN11_CRYPTO_RSVD_INTR_ENABLE); 1810 gt->gtier[5] = 1811 intel_uncore_read(uncore, 1812 GEN11_GUNIT_CSME_INTR_ENABLE); 1813 gt->ngtier = 6; 1814 } else if (GRAPHICS_VER(i915) >= 8) { 1815 for (i = 0; i < 4; i++) 1816 gt->gtier[i] = 1817 intel_uncore_read(uncore, GEN8_GT_IER(i)); 1818 gt->ngtier = 4; 1819 } else if (HAS_PCH_SPLIT(i915)) { 1820 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1821 gt->ngtier = 1; 1822 } 1823 1824 gt->eir = intel_uncore_read(uncore, EIR); 1825 gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER); 1826 } 1827 1828 /* 1829 * Capture all registers that relate to workload submission. 1830 * NOTE: In GuC submission, when GuC resets an engine, it can dump these for us 1831 */ 1832 static void gt_record_global_regs(struct intel_gt_coredump *gt) 1833 { 1834 struct intel_uncore *uncore = gt->_gt->uncore; 1835 struct drm_i915_private *i915 = uncore->i915; 1836 int i; 1837 1838 /* 1839 * General organization 1840 * 1. Registers specific to a single generation 1841 * 2. Registers which belong to multiple generations 1842 * 3. Feature specific registers. 1843 * 4. Everything else 1844 * Please try to follow the order. 1845 */ 1846 1847 /* 1: Registers specific to a single generation */ 1848 if (IS_VALLEYVIEW(i915)) 1849 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV); 1850 1851 if (GRAPHICS_VER(i915) == 7) 1852 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT); 1853 1854 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { 1855 gt->fault_data0 = intel_gt_mcr_read_any((struct intel_gt *)gt->_gt, 1856 XEHP_FAULT_TLB_DATA0); 1857 gt->fault_data1 = intel_gt_mcr_read_any((struct intel_gt *)gt->_gt, 1858 XEHP_FAULT_TLB_DATA1); 1859 } else if (GRAPHICS_VER(i915) >= 12) { 1860 gt->fault_data0 = intel_uncore_read(uncore, 1861 GEN12_FAULT_TLB_DATA0); 1862 gt->fault_data1 = intel_uncore_read(uncore, 1863 GEN12_FAULT_TLB_DATA1); 1864 } else if (GRAPHICS_VER(i915) >= 8) { 1865 gt->fault_data0 = intel_uncore_read(uncore, 1866 GEN8_FAULT_TLB_DATA0); 1867 gt->fault_data1 = intel_uncore_read(uncore, 1868 GEN8_FAULT_TLB_DATA1); 1869 } 1870 1871 if (GRAPHICS_VER(i915) == 6) { 1872 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE); 1873 gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL); 1874 gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE); 1875 } 1876 1877 /* 2: Registers which belong to multiple generations */ 1878 if (GRAPHICS_VER(i915) >= 7) 1879 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT); 1880 1881 if (GRAPHICS_VER(i915) >= 6) { 1882 if (GRAPHICS_VER(i915) < 12) { 1883 gt->error = intel_uncore_read(uncore, ERROR_GEN6); 1884 gt->done_reg = intel_uncore_read(uncore, DONE_REG); 1885 } 1886 } 1887 1888 /* 3: Feature specific registers */ 1889 if (IS_GRAPHICS_VER(i915, 6, 7)) { 1890 gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK); 1891 gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS); 1892 } 1893 1894 if (IS_GRAPHICS_VER(i915, 8, 11)) 1895 gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN); 1896 1897 if (GRAPHICS_VER(i915) == 12) 1898 gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG); 1899 1900 if (GRAPHICS_VER(i915) >= 12) { 1901 for (i = 0; i < I915_MAX_SFC; i++) { 1902 /* 1903 * SFC_DONE resides in the VD forcewake domain, so it 1904 * only exists if the corresponding VCS engine is 1905 * present. 1906 */ 1907 if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || 1908 !HAS_ENGINE(gt->_gt, _VCS(i * 2))) 1909 continue; 1910 1911 gt->sfc_done[i] = 1912 intel_uncore_read(uncore, GEN12_SFC_DONE(i)); 1913 } 1914 1915 gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE); 1916 } 1917 } 1918 1919 static void gt_record_info(struct intel_gt_coredump *gt) 1920 { 1921 memcpy(>->info, >->_gt->info, sizeof(struct intel_gt_info)); 1922 gt->clock_frequency = gt->_gt->clock_frequency; 1923 gt->clock_period_ns = gt->_gt->clock_period_ns; 1924 } 1925 1926 /* 1927 * Generate a semi-unique error code. The code is not meant to have meaning, The 1928 * code's only purpose is to try to prevent false duplicated bug reports by 1929 * grossly estimating a GPU error state. 1930 * 1931 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 1932 * the hang if we could strip the GTT offset information from it. 1933 * 1934 * It's only a small step better than a random number in its current form. 1935 */ 1936 static u32 generate_ecode(const struct intel_engine_coredump *ee) 1937 { 1938 /* 1939 * IPEHR would be an ideal way to detect errors, as it's the gross 1940 * measure of "the command that hung." However, has some very common 1941 * synchronization commands which almost always appear in the case 1942 * strictly a client bug. Use instdone to differentiate those some. 1943 */ 1944 return ee ? ee->ipehr ^ ee->instdone.instdone : 0; 1945 } 1946 1947 static const char *error_msg(struct i915_gpu_coredump *error) 1948 { 1949 struct intel_engine_coredump *first = NULL; 1950 unsigned int hung_classes = 0; 1951 struct intel_gt_coredump *gt; 1952 int len; 1953 1954 for (gt = error->gt; gt; gt = gt->next) { 1955 struct intel_engine_coredump *cs; 1956 1957 for (cs = gt->engine; cs; cs = cs->next) { 1958 if (cs->hung) { 1959 hung_classes |= BIT(cs->engine->uabi_class); 1960 if (!first) 1961 first = cs; 1962 } 1963 } 1964 } 1965 1966 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1967 "GPU HANG: ecode %d:%x:%08x", 1968 GRAPHICS_VER(error->i915), hung_classes, 1969 generate_ecode(first)); 1970 if (first && first->context.pid) { 1971 /* Just show the first executing process, more is confusing */ 1972 len += scnprintf(error->error_msg + len, 1973 sizeof(error->error_msg) - len, 1974 ", in %s [%d]", 1975 first->context.comm, first->context.pid); 1976 } 1977 1978 return error->error_msg; 1979 } 1980 1981 static void capture_gen(struct i915_gpu_coredump *error) 1982 { 1983 struct drm_i915_private *i915 = error->i915; 1984 1985 error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count); 1986 error->suspended = pm_runtime_suspended(i915->drm.dev); 1987 1988 error->iommu = i915_vtd_active(i915); 1989 error->reset_count = i915_reset_count(&i915->gpu_error); 1990 error->suspend_count = i915->suspend_count; 1991 1992 i915_params_copy(&error->params, &i915->params); 1993 intel_display_params_copy(&error->display_params); 1994 memcpy(&error->device_info, 1995 INTEL_INFO(i915), 1996 sizeof(error->device_info)); 1997 memcpy(&error->runtime_info, 1998 RUNTIME_INFO(i915), 1999 sizeof(error->runtime_info)); 2000 memcpy(&error->display_device_info, DISPLAY_INFO(i915), 2001 sizeof(error->display_device_info)); 2002 memcpy(&error->display_runtime_info, DISPLAY_RUNTIME_INFO(i915), 2003 sizeof(error->display_runtime_info)); 2004 error->driver_caps = i915->caps; 2005 } 2006 2007 struct i915_gpu_coredump * 2008 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp) 2009 { 2010 struct i915_gpu_coredump *error; 2011 2012 if (!i915->params.error_capture) 2013 return NULL; 2014 2015 error = kzalloc(sizeof(*error), gfp); 2016 if (!error) 2017 return NULL; 2018 2019 kref_init(&error->ref); 2020 error->i915 = i915; 2021 2022 error->time = ktime_get_real(); 2023 error->boottime = ktime_get_boottime(); 2024 error->uptime = ktime_sub(ktime_get(), to_gt(i915)->last_init_time); 2025 error->capture = jiffies; 2026 2027 capture_gen(error); 2028 2029 return error; 2030 } 2031 2032 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x)) 2033 2034 struct intel_gt_coredump * 2035 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags) 2036 { 2037 struct intel_gt_coredump *gc; 2038 2039 gc = kzalloc(sizeof(*gc), gfp); 2040 if (!gc) 2041 return NULL; 2042 2043 gc->_gt = gt; 2044 gc->awake = intel_gt_pm_is_awake(gt); 2045 2046 gt_record_display_regs(gc); 2047 gt_record_global_nonguc_regs(gc); 2048 2049 /* 2050 * GuC dumps global, eng-class and eng-instance registers 2051 * (that can change as part of engine state during execution) 2052 * before an engine is reset due to a hung context. 2053 * GuC captures and reports all three groups of registers 2054 * together as a single set before the engine is reset. 2055 * Thus, if GuC triggered the context reset we retrieve 2056 * the register values as part of gt_record_engines. 2057 */ 2058 if (!(dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)) 2059 gt_record_global_regs(gc); 2060 2061 gt_record_fences(gc); 2062 2063 return gc; 2064 } 2065 2066 struct i915_vma_compress * 2067 i915_vma_capture_prepare(struct intel_gt_coredump *gt) 2068 { 2069 struct i915_vma_compress *compress; 2070 2071 compress = kmalloc(sizeof(*compress), ALLOW_FAIL); 2072 if (!compress) 2073 return NULL; 2074 2075 if (!compress_init(compress)) { 2076 kfree(compress); 2077 return NULL; 2078 } 2079 2080 return compress; 2081 } 2082 2083 void i915_vma_capture_finish(struct intel_gt_coredump *gt, 2084 struct i915_vma_compress *compress) 2085 { 2086 if (!compress) 2087 return; 2088 2089 compress_fini(compress); 2090 kfree(compress); 2091 } 2092 2093 static struct i915_gpu_coredump * 2094 __i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags) 2095 { 2096 struct drm_i915_private *i915 = gt->i915; 2097 struct i915_gpu_coredump *error; 2098 2099 /* Check if GPU capture has been disabled */ 2100 error = READ_ONCE(i915->gpu_error.first_error); 2101 if (IS_ERR(error)) 2102 return error; 2103 2104 error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL); 2105 if (!error) 2106 return ERR_PTR(-ENOMEM); 2107 2108 error->gt = intel_gt_coredump_alloc(gt, ALLOW_FAIL, dump_flags); 2109 if (error->gt) { 2110 struct i915_vma_compress *compress; 2111 2112 compress = i915_vma_capture_prepare(error->gt); 2113 if (!compress) { 2114 kfree(error->gt); 2115 kfree(error); 2116 return ERR_PTR(-ENOMEM); 2117 } 2118 2119 if (INTEL_INFO(i915)->has_gt_uc) { 2120 error->gt->uc = gt_record_uc(error->gt, compress); 2121 if (error->gt->uc) { 2122 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE) 2123 error->gt->uc->guc.is_guc_capture = true; 2124 else 2125 GEM_BUG_ON(error->gt->uc->guc.is_guc_capture); 2126 } 2127 } 2128 2129 gt_record_info(error->gt); 2130 gt_record_engines(error->gt, engine_mask, compress, dump_flags); 2131 2132 2133 i915_vma_capture_finish(error->gt, compress); 2134 2135 error->simulated |= error->gt->simulated; 2136 } 2137 2138 error->overlay = intel_overlay_capture_error_state(i915); 2139 2140 return error; 2141 } 2142 2143 struct i915_gpu_coredump * 2144 i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags) 2145 { 2146 static DEFINE_MUTEX(capture_mutex); 2147 int ret = mutex_lock_interruptible(&capture_mutex); 2148 struct i915_gpu_coredump *dump; 2149 2150 if (ret) 2151 return ERR_PTR(ret); 2152 2153 dump = __i915_gpu_coredump(gt, engine_mask, dump_flags); 2154 mutex_unlock(&capture_mutex); 2155 2156 return dump; 2157 } 2158 2159 void i915_error_state_store(struct i915_gpu_coredump *error) 2160 { 2161 struct drm_i915_private *i915; 2162 static bool warned; 2163 2164 if (IS_ERR_OR_NULL(error)) 2165 return; 2166 2167 i915 = error->i915; 2168 drm_info(&i915->drm, "%s\n", error_msg(error)); 2169 2170 if (error->simulated || 2171 cmpxchg(&i915->gpu_error.first_error, NULL, error)) 2172 return; 2173 2174 i915_gpu_coredump_get(error); 2175 2176 if (!xchg(&warned, true) && 2177 ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) { 2178 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 2179 pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n"); 2180 pr_info("Please see https://drm.pages.freedesktop.org/intel-docs/how-to-file-i915-bugs.html for details.\n"); 2181 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 2182 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n"); 2183 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n", 2184 i915->drm.primary->index); 2185 } 2186 } 2187 2188 /** 2189 * i915_capture_error_state - capture an error record for later analysis 2190 * @gt: intel_gt which originated the hang 2191 * @engine_mask: hung engines 2192 * @dump_flags: dump flags 2193 * 2194 * Should be called when an error is detected (either a hang or an error 2195 * interrupt) to capture error state from the time of the error. Fills 2196 * out a structure which becomes available in debugfs for user level tools 2197 * to pick up. 2198 */ 2199 void i915_capture_error_state(struct intel_gt *gt, 2200 intel_engine_mask_t engine_mask, u32 dump_flags) 2201 { 2202 struct i915_gpu_coredump *error; 2203 2204 error = i915_gpu_coredump(gt, engine_mask, dump_flags); 2205 if (IS_ERR(error)) { 2206 cmpxchg(>->i915->gpu_error.first_error, NULL, error); 2207 return; 2208 } 2209 2210 i915_error_state_store(error); 2211 i915_gpu_coredump_put(error); 2212 } 2213 2214 struct i915_gpu_coredump * 2215 i915_first_error_state(struct drm_i915_private *i915) 2216 { 2217 struct i915_gpu_coredump *error; 2218 2219 spin_lock_irq(&i915->gpu_error.lock); 2220 error = i915->gpu_error.first_error; 2221 if (!IS_ERR_OR_NULL(error)) 2222 i915_gpu_coredump_get(error); 2223 spin_unlock_irq(&i915->gpu_error.lock); 2224 2225 return error; 2226 } 2227 2228 void i915_reset_error_state(struct drm_i915_private *i915) 2229 { 2230 struct i915_gpu_coredump *error; 2231 2232 spin_lock_irq(&i915->gpu_error.lock); 2233 error = i915->gpu_error.first_error; 2234 if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */ 2235 i915->gpu_error.first_error = NULL; 2236 spin_unlock_irq(&i915->gpu_error.lock); 2237 2238 if (!IS_ERR_OR_NULL(error)) 2239 i915_gpu_coredump_put(error); 2240 } 2241 2242 void i915_disable_error_state(struct drm_i915_private *i915, int err) 2243 { 2244 spin_lock_irq(&i915->gpu_error.lock); 2245 if (!i915->gpu_error.first_error) 2246 i915->gpu_error.first_error = ERR_PTR(err); 2247 spin_unlock_irq(&i915->gpu_error.lock); 2248 } 2249 2250 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) 2251 void intel_klog_error_capture(struct intel_gt *gt, 2252 intel_engine_mask_t engine_mask) 2253 { 2254 static int g_count; 2255 struct drm_i915_private *i915 = gt->i915; 2256 struct i915_gpu_coredump *error; 2257 intel_wakeref_t wakeref; 2258 size_t buf_size = PAGE_SIZE * 128; 2259 size_t pos_err; 2260 char *buf, *ptr, *next; 2261 int l_count = g_count++; 2262 int line = 0; 2263 2264 /* Can't allocate memory during a reset */ 2265 if (test_bit(I915_RESET_BACKOFF, >->reset.flags)) { 2266 drm_err(>->i915->drm, "[Capture/%d.%d] Inside GT reset, skipping error capture :(\n", 2267 l_count, line++); 2268 return; 2269 } 2270 2271 error = READ_ONCE(i915->gpu_error.first_error); 2272 if (error) { 2273 drm_err(&i915->drm, "[Capture/%d.%d] Clearing existing error capture first...\n", 2274 l_count, line++); 2275 i915_reset_error_state(i915); 2276 } 2277 2278 with_intel_runtime_pm(&i915->runtime_pm, wakeref) 2279 error = i915_gpu_coredump(gt, engine_mask, CORE_DUMP_FLAG_NONE); 2280 2281 if (IS_ERR(error)) { 2282 drm_err(&i915->drm, "[Capture/%d.%d] Failed to capture error capture: %ld!\n", 2283 l_count, line++, PTR_ERR(error)); 2284 return; 2285 } 2286 2287 buf = kvmalloc(buf_size, GFP_KERNEL); 2288 if (!buf) { 2289 drm_err(&i915->drm, "[Capture/%d.%d] Failed to allocate buffer for error capture!\n", 2290 l_count, line++); 2291 i915_gpu_coredump_put(error); 2292 return; 2293 } 2294 2295 drm_info(&i915->drm, "[Capture/%d.%d] Dumping i915 error capture for %ps...\n", 2296 l_count, line++, __builtin_return_address(0)); 2297 2298 /* Largest string length safe to print via dmesg */ 2299 # define MAX_CHUNK 800 2300 2301 pos_err = 0; 2302 while (1) { 2303 ssize_t got = i915_gpu_coredump_copy_to_buffer(error, buf, pos_err, buf_size - 1); 2304 2305 if (got <= 0) 2306 break; 2307 2308 buf[got] = 0; 2309 pos_err += got; 2310 2311 ptr = buf; 2312 while (got > 0) { 2313 size_t count; 2314 char tag[2]; 2315 2316 next = strnchr(ptr, got, '\n'); 2317 if (next) { 2318 count = next - ptr; 2319 *next = 0; 2320 tag[0] = '>'; 2321 tag[1] = '<'; 2322 } else { 2323 count = got; 2324 tag[0] = '}'; 2325 tag[1] = '{'; 2326 } 2327 2328 if (count > MAX_CHUNK) { 2329 size_t pos; 2330 char *ptr2 = ptr; 2331 2332 for (pos = MAX_CHUNK; pos < count; pos += MAX_CHUNK) { 2333 char chr = ptr[pos]; 2334 2335 ptr[pos] = 0; 2336 drm_info(&i915->drm, "[Capture/%d.%d] }%s{\n", 2337 l_count, line++, ptr2); 2338 ptr[pos] = chr; 2339 ptr2 = ptr + pos; 2340 2341 /* 2342 * If spewing large amounts of data via a serial console, 2343 * this can be a very slow process. So be friendly and try 2344 * not to cause 'softlockup on CPU' problems. 2345 */ 2346 cond_resched(); 2347 } 2348 2349 if (ptr2 < (ptr + count)) 2350 drm_info(&i915->drm, "[Capture/%d.%d] %c%s%c\n", 2351 l_count, line++, tag[0], ptr2, tag[1]); 2352 else if (tag[0] == '>') 2353 drm_info(&i915->drm, "[Capture/%d.%d] ><\n", 2354 l_count, line++); 2355 } else { 2356 drm_info(&i915->drm, "[Capture/%d.%d] %c%s%c\n", 2357 l_count, line++, tag[0], ptr, tag[1]); 2358 } 2359 2360 ptr = next; 2361 got -= count; 2362 if (next) { 2363 ptr++; 2364 got--; 2365 } 2366 2367 /* As above. */ 2368 cond_resched(); 2369 } 2370 2371 if (got) 2372 drm_info(&i915->drm, "[Capture/%d.%d] Got %zd bytes remaining!\n", 2373 l_count, line++, got); 2374 } 2375 2376 kvfree(buf); 2377 2378 drm_info(&i915->drm, "[Capture/%d.%d] Dumped %zd bytes\n", l_count, line++, pos_err); 2379 } 2380 #endif 2381