1 /* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30 #include <linux/ascii85.h> 31 #include <linux/nmi.h> 32 #include <linux/pagevec.h> 33 #include <linux/scatterlist.h> 34 #include <linux/utsname.h> 35 #include <linux/zlib.h> 36 37 #include <drm/drm_print.h> 38 39 #include "display/intel_dmc.h" 40 #include "display/intel_overlay.h" 41 42 #include "gem/i915_gem_context.h" 43 #include "gem/i915_gem_lmem.h" 44 #include "gt/intel_engine_regs.h" 45 #include "gt/intel_gt.h" 46 #include "gt/intel_gt_pm.h" 47 #include "gt/intel_gt_regs.h" 48 49 #include "i915_drv.h" 50 #include "i915_gpu_error.h" 51 #include "i915_memcpy.h" 52 #include "i915_scatterlist.h" 53 #include "i915_vma_snapshot.h" 54 55 #define ALLOW_FAIL (__GFP_KSWAPD_RECLAIM | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) 56 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN) 57 58 static void __sg_set_buf(struct scatterlist *sg, 59 void *addr, unsigned int len, loff_t it) 60 { 61 sg->page_link = (unsigned long)virt_to_page(addr); 62 sg->offset = offset_in_page(addr); 63 sg->length = len; 64 sg->dma_address = it; 65 } 66 67 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len) 68 { 69 if (!len) 70 return false; 71 72 if (e->bytes + len + 1 <= e->size) 73 return true; 74 75 if (e->bytes) { 76 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter); 77 e->iter += e->bytes; 78 e->buf = NULL; 79 e->bytes = 0; 80 } 81 82 if (e->cur == e->end) { 83 struct scatterlist *sgl; 84 85 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL); 86 if (!sgl) { 87 e->err = -ENOMEM; 88 return false; 89 } 90 91 if (e->cur) { 92 e->cur->offset = 0; 93 e->cur->length = 0; 94 e->cur->page_link = 95 (unsigned long)sgl | SG_CHAIN; 96 } else { 97 e->sgl = sgl; 98 } 99 100 e->cur = sgl; 101 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1; 102 } 103 104 e->size = ALIGN(len + 1, SZ_64K); 105 e->buf = kmalloc(e->size, ALLOW_FAIL); 106 if (!e->buf) { 107 e->size = PAGE_ALIGN(len + 1); 108 e->buf = kmalloc(e->size, GFP_KERNEL); 109 } 110 if (!e->buf) { 111 e->err = -ENOMEM; 112 return false; 113 } 114 115 return true; 116 } 117 118 __printf(2, 0) 119 static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 120 const char *fmt, va_list args) 121 { 122 va_list ap; 123 int len; 124 125 if (e->err) 126 return; 127 128 va_copy(ap, args); 129 len = vsnprintf(NULL, 0, fmt, ap); 130 va_end(ap); 131 if (len <= 0) { 132 e->err = len; 133 return; 134 } 135 136 if (!__i915_error_grow(e, len)) 137 return; 138 139 GEM_BUG_ON(e->bytes >= e->size); 140 len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args); 141 if (len < 0) { 142 e->err = len; 143 return; 144 } 145 e->bytes += len; 146 } 147 148 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str) 149 { 150 unsigned len; 151 152 if (e->err || !str) 153 return; 154 155 len = strlen(str); 156 if (!__i915_error_grow(e, len)) 157 return; 158 159 GEM_BUG_ON(e->bytes + len > e->size); 160 memcpy(e->buf + e->bytes, str, len); 161 e->bytes += len; 162 } 163 164 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 165 #define err_puts(e, s) i915_error_puts(e, s) 166 167 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf) 168 { 169 i915_error_vprintf(p->arg, vaf->fmt, *vaf->va); 170 } 171 172 static inline struct drm_printer 173 i915_error_printer(struct drm_i915_error_state_buf *e) 174 { 175 struct drm_printer p = { 176 .printfn = __i915_printfn_error, 177 .arg = e, 178 }; 179 return p; 180 } 181 182 /* single threaded page allocator with a reserved stash for emergencies */ 183 static void pool_fini(struct pagevec *pv) 184 { 185 pagevec_release(pv); 186 } 187 188 static int pool_refill(struct pagevec *pv, gfp_t gfp) 189 { 190 while (pagevec_space(pv)) { 191 struct page *p; 192 193 p = alloc_page(gfp); 194 if (!p) 195 return -ENOMEM; 196 197 pagevec_add(pv, p); 198 } 199 200 return 0; 201 } 202 203 static int pool_init(struct pagevec *pv, gfp_t gfp) 204 { 205 int err; 206 207 pagevec_init(pv); 208 209 err = pool_refill(pv, gfp); 210 if (err) 211 pool_fini(pv); 212 213 return err; 214 } 215 216 static void *pool_alloc(struct pagevec *pv, gfp_t gfp) 217 { 218 struct page *p; 219 220 p = alloc_page(gfp); 221 if (!p && pagevec_count(pv)) 222 p = pv->pages[--pv->nr]; 223 224 return p ? page_address(p) : NULL; 225 } 226 227 static void pool_free(struct pagevec *pv, void *addr) 228 { 229 struct page *p = virt_to_page(addr); 230 231 if (pagevec_space(pv)) 232 pagevec_add(pv, p); 233 else 234 __free_page(p); 235 } 236 237 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR 238 239 struct i915_vma_compress { 240 struct pagevec pool; 241 struct z_stream_s zstream; 242 void *tmp; 243 }; 244 245 static bool compress_init(struct i915_vma_compress *c) 246 { 247 struct z_stream_s *zstream = &c->zstream; 248 249 if (pool_init(&c->pool, ALLOW_FAIL)) 250 return false; 251 252 zstream->workspace = 253 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL), 254 ALLOW_FAIL); 255 if (!zstream->workspace) { 256 pool_fini(&c->pool); 257 return false; 258 } 259 260 c->tmp = NULL; 261 if (i915_has_memcpy_from_wc()) 262 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL); 263 264 return true; 265 } 266 267 static bool compress_start(struct i915_vma_compress *c) 268 { 269 struct z_stream_s *zstream = &c->zstream; 270 void *workspace = zstream->workspace; 271 272 memset(zstream, 0, sizeof(*zstream)); 273 zstream->workspace = workspace; 274 275 return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK; 276 } 277 278 static void *compress_next_page(struct i915_vma_compress *c, 279 struct i915_vma_coredump *dst) 280 { 281 void *page_addr; 282 struct page *page; 283 284 page_addr = pool_alloc(&c->pool, ALLOW_FAIL); 285 if (!page_addr) 286 return ERR_PTR(-ENOMEM); 287 288 page = virt_to_page(page_addr); 289 list_add_tail(&page->lru, &dst->page_list); 290 return page_addr; 291 } 292 293 static int compress_page(struct i915_vma_compress *c, 294 void *src, 295 struct i915_vma_coredump *dst, 296 bool wc) 297 { 298 struct z_stream_s *zstream = &c->zstream; 299 300 zstream->next_in = src; 301 if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE)) 302 zstream->next_in = c->tmp; 303 zstream->avail_in = PAGE_SIZE; 304 305 do { 306 if (zstream->avail_out == 0) { 307 zstream->next_out = compress_next_page(c, dst); 308 if (IS_ERR(zstream->next_out)) 309 return PTR_ERR(zstream->next_out); 310 311 zstream->avail_out = PAGE_SIZE; 312 } 313 314 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK) 315 return -EIO; 316 317 cond_resched(); 318 } while (zstream->avail_in); 319 320 /* Fallback to uncompressed if we increase size? */ 321 if (0 && zstream->total_out > zstream->total_in) 322 return -E2BIG; 323 324 return 0; 325 } 326 327 static int compress_flush(struct i915_vma_compress *c, 328 struct i915_vma_coredump *dst) 329 { 330 struct z_stream_s *zstream = &c->zstream; 331 332 do { 333 switch (zlib_deflate(zstream, Z_FINISH)) { 334 case Z_OK: /* more space requested */ 335 zstream->next_out = compress_next_page(c, dst); 336 if (IS_ERR(zstream->next_out)) 337 return PTR_ERR(zstream->next_out); 338 339 zstream->avail_out = PAGE_SIZE; 340 break; 341 342 case Z_STREAM_END: 343 goto end; 344 345 default: /* any error */ 346 return -EIO; 347 } 348 } while (1); 349 350 end: 351 memset(zstream->next_out, 0, zstream->avail_out); 352 dst->unused = zstream->avail_out; 353 return 0; 354 } 355 356 static void compress_finish(struct i915_vma_compress *c) 357 { 358 zlib_deflateEnd(&c->zstream); 359 } 360 361 static void compress_fini(struct i915_vma_compress *c) 362 { 363 kfree(c->zstream.workspace); 364 if (c->tmp) 365 pool_free(&c->pool, c->tmp); 366 pool_fini(&c->pool); 367 } 368 369 static void err_compression_marker(struct drm_i915_error_state_buf *m) 370 { 371 err_puts(m, ":"); 372 } 373 374 #else 375 376 struct i915_vma_compress { 377 struct pagevec pool; 378 }; 379 380 static bool compress_init(struct i915_vma_compress *c) 381 { 382 return pool_init(&c->pool, ALLOW_FAIL) == 0; 383 } 384 385 static bool compress_start(struct i915_vma_compress *c) 386 { 387 return true; 388 } 389 390 static int compress_page(struct i915_vma_compress *c, 391 void *src, 392 struct i915_vma_coredump *dst, 393 bool wc) 394 { 395 void *ptr; 396 397 ptr = pool_alloc(&c->pool, ALLOW_FAIL); 398 if (!ptr) 399 return -ENOMEM; 400 401 if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE))) 402 memcpy(ptr, src, PAGE_SIZE); 403 list_add_tail(&virt_to_page(ptr)->lru, &dst->page_list); 404 cond_resched(); 405 406 return 0; 407 } 408 409 static int compress_flush(struct i915_vma_compress *c, 410 struct i915_vma_coredump *dst) 411 { 412 return 0; 413 } 414 415 static void compress_finish(struct i915_vma_compress *c) 416 { 417 } 418 419 static void compress_fini(struct i915_vma_compress *c) 420 { 421 pool_fini(&c->pool); 422 } 423 424 static void err_compression_marker(struct drm_i915_error_state_buf *m) 425 { 426 err_puts(m, "~"); 427 } 428 429 #endif 430 431 static void error_print_instdone(struct drm_i915_error_state_buf *m, 432 const struct intel_engine_coredump *ee) 433 { 434 const struct sseu_dev_info *sseu = &ee->engine->gt->info.sseu; 435 int slice; 436 int subslice; 437 int iter; 438 439 err_printf(m, " INSTDONE: 0x%08x\n", 440 ee->instdone.instdone); 441 442 if (ee->engine->class != RENDER_CLASS || GRAPHICS_VER(m->i915) <= 3) 443 return; 444 445 err_printf(m, " SC_INSTDONE: 0x%08x\n", 446 ee->instdone.slice_common); 447 448 if (GRAPHICS_VER(m->i915) <= 6) 449 return; 450 451 if (GRAPHICS_VER_FULL(m->i915) >= IP_VER(12, 50)) { 452 for_each_instdone_gslice_dss_xehp(m->i915, sseu, iter, slice, subslice) 453 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", 454 slice, subslice, 455 ee->instdone.sampler[slice][subslice]); 456 457 for_each_instdone_gslice_dss_xehp(m->i915, sseu, iter, slice, subslice) 458 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", 459 slice, subslice, 460 ee->instdone.row[slice][subslice]); 461 } else { 462 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) 463 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", 464 slice, subslice, 465 ee->instdone.sampler[slice][subslice]); 466 467 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) 468 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", 469 slice, subslice, 470 ee->instdone.row[slice][subslice]); 471 } 472 473 if (GRAPHICS_VER(m->i915) < 12) 474 return; 475 476 if (GRAPHICS_VER_FULL(m->i915) >= IP_VER(12, 55)) { 477 for_each_instdone_gslice_dss_xehp(m->i915, sseu, iter, slice, subslice) 478 err_printf(m, " GEOM_SVGUNIT_INSTDONE[%d][%d]: 0x%08x\n", 479 slice, subslice, 480 ee->instdone.geom_svg[slice][subslice]); 481 } 482 483 err_printf(m, " SC_INSTDONE_EXTRA: 0x%08x\n", 484 ee->instdone.slice_common_extra[0]); 485 err_printf(m, " SC_INSTDONE_EXTRA2: 0x%08x\n", 486 ee->instdone.slice_common_extra[1]); 487 } 488 489 static void error_print_request(struct drm_i915_error_state_buf *m, 490 const char *prefix, 491 const struct i915_request_coredump *erq) 492 { 493 if (!erq->seqno) 494 return; 495 496 err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, head %08x, tail %08x\n", 497 prefix, erq->pid, erq->context, erq->seqno, 498 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, 499 &erq->flags) ? "!" : "", 500 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, 501 &erq->flags) ? "+" : "", 502 erq->sched_attr.priority, 503 erq->head, erq->tail); 504 } 505 506 static void error_print_context(struct drm_i915_error_state_buf *m, 507 const char *header, 508 const struct i915_gem_context_coredump *ctx) 509 { 510 const u32 period = to_gt(m->i915)->clock_period_ns; 511 512 err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n", 513 header, ctx->comm, ctx->pid, ctx->sched_attr.priority, 514 ctx->guilty, ctx->active, 515 ctx->total_runtime * period, 516 mul_u32_u32(ctx->avg_runtime, period)); 517 } 518 519 static struct i915_vma_coredump * 520 __find_vma(struct i915_vma_coredump *vma, const char *name) 521 { 522 while (vma) { 523 if (strcmp(vma->name, name) == 0) 524 return vma; 525 vma = vma->next; 526 } 527 528 return NULL; 529 } 530 531 static struct i915_vma_coredump * 532 find_batch(const struct intel_engine_coredump *ee) 533 { 534 return __find_vma(ee->vma, "batch"); 535 } 536 537 static void error_print_engine(struct drm_i915_error_state_buf *m, 538 const struct intel_engine_coredump *ee) 539 { 540 struct i915_vma_coredump *batch; 541 int n; 542 543 err_printf(m, "%s command stream:\n", ee->engine->name); 544 err_printf(m, " CCID: 0x%08x\n", ee->ccid); 545 err_printf(m, " START: 0x%08x\n", ee->start); 546 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head); 547 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n", 548 ee->tail, ee->rq_post, ee->rq_tail); 549 err_printf(m, " CTL: 0x%08x\n", ee->ctl); 550 err_printf(m, " MODE: 0x%08x\n", ee->mode); 551 err_printf(m, " HWS: 0x%08x\n", ee->hws); 552 err_printf(m, " ACTHD: 0x%08x %08x\n", 553 (u32)(ee->acthd>>32), (u32)ee->acthd); 554 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir); 555 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr); 556 err_printf(m, " ESR: 0x%08x\n", ee->esr); 557 558 error_print_instdone(m, ee); 559 560 batch = find_batch(ee); 561 if (batch) { 562 u64 start = batch->gtt_offset; 563 u64 end = start + batch->gtt_size; 564 565 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n", 566 upper_32_bits(start), lower_32_bits(start), 567 upper_32_bits(end), lower_32_bits(end)); 568 } 569 if (GRAPHICS_VER(m->i915) >= 4) { 570 err_printf(m, " BBADDR: 0x%08x_%08x\n", 571 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr); 572 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate); 573 err_printf(m, " INSTPS: 0x%08x\n", ee->instps); 574 } 575 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm); 576 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr), 577 lower_32_bits(ee->faddr)); 578 if (GRAPHICS_VER(m->i915) >= 6) { 579 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi); 580 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg); 581 } 582 if (HAS_PPGTT(m->i915)) { 583 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode); 584 585 if (GRAPHICS_VER(m->i915) >= 8) { 586 int i; 587 for (i = 0; i < 4; i++) 588 err_printf(m, " PDP%d: 0x%016llx\n", 589 i, ee->vm_info.pdp[i]); 590 } else { 591 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 592 ee->vm_info.pp_dir_base); 593 } 594 } 595 err_printf(m, " hung: %u\n", ee->hung); 596 err_printf(m, " engine reset count: %u\n", ee->reset_count); 597 598 for (n = 0; n < ee->num_ports; n++) { 599 err_printf(m, " ELSP[%d]:", n); 600 error_print_request(m, " ", &ee->execlist[n]); 601 } 602 603 error_print_context(m, " Active context: ", &ee->context); 604 } 605 606 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 607 { 608 va_list args; 609 610 va_start(args, f); 611 i915_error_vprintf(e, f, args); 612 va_end(args); 613 } 614 615 static void print_error_vma(struct drm_i915_error_state_buf *m, 616 const struct intel_engine_cs *engine, 617 const struct i915_vma_coredump *vma) 618 { 619 char out[ASCII85_BUFSZ]; 620 struct page *page; 621 622 if (!vma) 623 return; 624 625 err_printf(m, "%s --- %s = 0x%08x %08x\n", 626 engine ? engine->name : "global", vma->name, 627 upper_32_bits(vma->gtt_offset), 628 lower_32_bits(vma->gtt_offset)); 629 630 if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K) 631 err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes); 632 633 err_compression_marker(m); 634 list_for_each_entry(page, &vma->page_list, lru) { 635 int i, len; 636 const u32 *addr = page_address(page); 637 638 len = PAGE_SIZE; 639 if (page == list_last_entry(&vma->page_list, typeof(*page), lru)) 640 len -= vma->unused; 641 len = ascii85_encode_len(len); 642 643 for (i = 0; i < len; i++) 644 err_puts(m, ascii85_encode(addr[i], out)); 645 } 646 err_puts(m, "\n"); 647 } 648 649 static void err_print_capabilities(struct drm_i915_error_state_buf *m, 650 struct i915_gpu_coredump *error) 651 { 652 struct drm_printer p = i915_error_printer(m); 653 654 intel_device_info_print_static(&error->device_info, &p); 655 intel_device_info_print_runtime(&error->runtime_info, &p); 656 intel_driver_caps_print(&error->driver_caps, &p); 657 } 658 659 static void err_print_params(struct drm_i915_error_state_buf *m, 660 const struct i915_params *params) 661 { 662 struct drm_printer p = i915_error_printer(m); 663 664 i915_params_dump(params, &p); 665 } 666 667 static void err_print_pciid(struct drm_i915_error_state_buf *m, 668 struct drm_i915_private *i915) 669 { 670 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 671 672 err_printf(m, "PCI ID: 0x%04x\n", pdev->device); 673 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision); 674 err_printf(m, "PCI Subsystem: %04x:%04x\n", 675 pdev->subsystem_vendor, 676 pdev->subsystem_device); 677 } 678 679 static void err_print_uc(struct drm_i915_error_state_buf *m, 680 const struct intel_uc_coredump *error_uc) 681 { 682 struct drm_printer p = i915_error_printer(m); 683 684 intel_uc_fw_dump(&error_uc->guc_fw, &p); 685 intel_uc_fw_dump(&error_uc->huc_fw, &p); 686 print_error_vma(m, NULL, error_uc->guc_log); 687 } 688 689 static void err_free_sgl(struct scatterlist *sgl) 690 { 691 while (sgl) { 692 struct scatterlist *sg; 693 694 for (sg = sgl; !sg_is_chain(sg); sg++) { 695 kfree(sg_virt(sg)); 696 if (sg_is_last(sg)) 697 break; 698 } 699 700 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg); 701 free_page((unsigned long)sgl); 702 sgl = sg; 703 } 704 } 705 706 static void err_print_gt_info(struct drm_i915_error_state_buf *m, 707 struct intel_gt_coredump *gt) 708 { 709 struct drm_printer p = i915_error_printer(m); 710 711 intel_gt_info_print(>->info, &p); 712 intel_sseu_print_topology(>->info.sseu, &p); 713 } 714 715 static void err_print_gt(struct drm_i915_error_state_buf *m, 716 struct intel_gt_coredump *gt) 717 { 718 const struct intel_engine_coredump *ee; 719 int i; 720 721 err_printf(m, "GT awake: %s\n", yesno(gt->awake)); 722 err_printf(m, "EIR: 0x%08x\n", gt->eir); 723 err_printf(m, "IER: 0x%08x\n", gt->ier); 724 for (i = 0; i < gt->ngtier; i++) 725 err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]); 726 err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er); 727 err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake); 728 err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr); 729 730 for (i = 0; i < gt->nfence; i++) 731 err_printf(m, " fence[%d] = %08llx\n", i, gt->fence[i]); 732 733 if (IS_GRAPHICS_VER(m->i915, 6, 11)) { 734 err_printf(m, "ERROR: 0x%08x\n", gt->error); 735 err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg); 736 } 737 738 if (GRAPHICS_VER(m->i915) >= 8) 739 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", 740 gt->fault_data1, gt->fault_data0); 741 742 if (GRAPHICS_VER(m->i915) == 7) 743 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int); 744 745 if (IS_GRAPHICS_VER(m->i915, 8, 11)) 746 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache); 747 748 if (GRAPHICS_VER(m->i915) == 12) 749 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err); 750 751 if (GRAPHICS_VER(m->i915) >= 12) { 752 int i; 753 754 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) { 755 /* 756 * SFC_DONE resides in the VD forcewake domain, so it 757 * only exists if the corresponding VCS engine is 758 * present. 759 */ 760 if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || 761 !HAS_ENGINE(gt->_gt, _VCS(i * 2))) 762 continue; 763 764 err_printf(m, " SFC_DONE[%d]: 0x%08x\n", i, 765 gt->sfc_done[i]); 766 } 767 768 err_printf(m, " GAM_DONE: 0x%08x\n", gt->gam_done); 769 } 770 771 for (ee = gt->engine; ee; ee = ee->next) { 772 const struct i915_vma_coredump *vma; 773 774 error_print_engine(m, ee); 775 for (vma = ee->vma; vma; vma = vma->next) 776 print_error_vma(m, ee->engine, vma); 777 } 778 779 if (gt->uc) 780 err_print_uc(m, gt->uc); 781 782 err_print_gt_info(m, gt); 783 } 784 785 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, 786 struct i915_gpu_coredump *error) 787 { 788 const struct intel_engine_coredump *ee; 789 struct timespec64 ts; 790 791 if (*error->error_msg) 792 err_printf(m, "%s\n", error->error_msg); 793 err_printf(m, "Kernel: %s %s\n", 794 init_utsname()->release, 795 init_utsname()->machine); 796 err_printf(m, "Driver: %s\n", DRIVER_DATE); 797 ts = ktime_to_timespec64(error->time); 798 err_printf(m, "Time: %lld s %ld us\n", 799 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 800 ts = ktime_to_timespec64(error->boottime); 801 err_printf(m, "Boottime: %lld s %ld us\n", 802 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 803 ts = ktime_to_timespec64(error->uptime); 804 err_printf(m, "Uptime: %lld s %ld us\n", 805 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 806 err_printf(m, "Capture: %lu jiffies; %d ms ago\n", 807 error->capture, jiffies_to_msecs(jiffies - error->capture)); 808 809 for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next) 810 err_printf(m, "Active process (on ring %s): %s [%d]\n", 811 ee->engine->name, 812 ee->context.comm, 813 ee->context.pid); 814 815 err_printf(m, "Reset count: %u\n", error->reset_count); 816 err_printf(m, "Suspend count: %u\n", error->suspend_count); 817 err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform)); 818 err_printf(m, "Subplatform: 0x%x\n", 819 intel_subplatform(&error->runtime_info, 820 error->device_info.platform)); 821 err_print_pciid(m, m->i915); 822 823 err_printf(m, "IOMMU enabled?: %d\n", error->iommu); 824 825 if (HAS_DMC(m->i915)) { 826 struct intel_dmc *dmc = &m->i915->dmc; 827 828 err_printf(m, "DMC loaded: %s\n", 829 yesno(intel_dmc_has_payload(m->i915) != 0)); 830 err_printf(m, "DMC fw version: %d.%d\n", 831 DMC_VERSION_MAJOR(dmc->version), 832 DMC_VERSION_MINOR(dmc->version)); 833 } 834 835 err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock)); 836 err_printf(m, "PM suspended: %s\n", yesno(error->suspended)); 837 838 if (error->gt) 839 err_print_gt(m, error->gt); 840 841 if (error->overlay) 842 intel_overlay_print_error_state(m, error->overlay); 843 844 err_print_capabilities(m, error); 845 err_print_params(m, &error->params); 846 } 847 848 static int err_print_to_sgl(struct i915_gpu_coredump *error) 849 { 850 struct drm_i915_error_state_buf m; 851 852 if (IS_ERR(error)) 853 return PTR_ERR(error); 854 855 if (READ_ONCE(error->sgl)) 856 return 0; 857 858 memset(&m, 0, sizeof(m)); 859 m.i915 = error->i915; 860 861 __err_print_to_sgl(&m, error); 862 863 if (m.buf) { 864 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter); 865 m.bytes = 0; 866 m.buf = NULL; 867 } 868 if (m.cur) { 869 GEM_BUG_ON(m.end < m.cur); 870 sg_mark_end(m.cur - 1); 871 } 872 GEM_BUG_ON(m.sgl && !m.cur); 873 874 if (m.err) { 875 err_free_sgl(m.sgl); 876 return m.err; 877 } 878 879 if (cmpxchg(&error->sgl, NULL, m.sgl)) 880 err_free_sgl(m.sgl); 881 882 return 0; 883 } 884 885 ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error, 886 char *buf, loff_t off, size_t rem) 887 { 888 struct scatterlist *sg; 889 size_t count; 890 loff_t pos; 891 int err; 892 893 if (!error || !rem) 894 return 0; 895 896 err = err_print_to_sgl(error); 897 if (err) 898 return err; 899 900 sg = READ_ONCE(error->fit); 901 if (!sg || off < sg->dma_address) 902 sg = error->sgl; 903 if (!sg) 904 return 0; 905 906 pos = sg->dma_address; 907 count = 0; 908 do { 909 size_t len, start; 910 911 if (sg_is_chain(sg)) { 912 sg = sg_chain_ptr(sg); 913 GEM_BUG_ON(sg_is_chain(sg)); 914 } 915 916 len = sg->length; 917 if (pos + len <= off) { 918 pos += len; 919 continue; 920 } 921 922 start = sg->offset; 923 if (pos < off) { 924 GEM_BUG_ON(off - pos > len); 925 len -= off - pos; 926 start += off - pos; 927 pos = off; 928 } 929 930 len = min(len, rem); 931 GEM_BUG_ON(!len || len > sg->length); 932 933 memcpy(buf, page_address(sg_page(sg)) + start, len); 934 935 count += len; 936 pos += len; 937 938 buf += len; 939 rem -= len; 940 if (!rem) { 941 WRITE_ONCE(error->fit, sg); 942 break; 943 } 944 } while (!sg_is_last(sg++)); 945 946 return count; 947 } 948 949 static void i915_vma_coredump_free(struct i915_vma_coredump *vma) 950 { 951 while (vma) { 952 struct i915_vma_coredump *next = vma->next; 953 struct page *page, *n; 954 955 list_for_each_entry_safe(page, n, &vma->page_list, lru) { 956 list_del_init(&page->lru); 957 __free_page(page); 958 } 959 960 kfree(vma); 961 vma = next; 962 } 963 } 964 965 static void cleanup_params(struct i915_gpu_coredump *error) 966 { 967 i915_params_free(&error->params); 968 } 969 970 static void cleanup_uc(struct intel_uc_coredump *uc) 971 { 972 kfree(uc->guc_fw.path); 973 kfree(uc->huc_fw.path); 974 i915_vma_coredump_free(uc->guc_log); 975 976 kfree(uc); 977 } 978 979 static void cleanup_gt(struct intel_gt_coredump *gt) 980 { 981 while (gt->engine) { 982 struct intel_engine_coredump *ee = gt->engine; 983 984 gt->engine = ee->next; 985 986 i915_vma_coredump_free(ee->vma); 987 kfree(ee); 988 } 989 990 if (gt->uc) 991 cleanup_uc(gt->uc); 992 993 kfree(gt); 994 } 995 996 void __i915_gpu_coredump_free(struct kref *error_ref) 997 { 998 struct i915_gpu_coredump *error = 999 container_of(error_ref, typeof(*error), ref); 1000 1001 while (error->gt) { 1002 struct intel_gt_coredump *gt = error->gt; 1003 1004 error->gt = gt->next; 1005 cleanup_gt(gt); 1006 } 1007 1008 kfree(error->overlay); 1009 1010 cleanup_params(error); 1011 1012 err_free_sgl(error->sgl); 1013 kfree(error); 1014 } 1015 1016 static struct i915_vma_coredump * 1017 i915_vma_coredump_create(const struct intel_gt *gt, 1018 const struct i915_vma_snapshot *vsnap, 1019 struct i915_vma_compress *compress) 1020 { 1021 struct i915_ggtt *ggtt = gt->ggtt; 1022 const u64 slot = ggtt->error_capture.start; 1023 struct i915_vma_coredump *dst; 1024 struct sgt_iter iter; 1025 int ret; 1026 1027 might_sleep(); 1028 1029 if (!vsnap || !vsnap->pages || !compress) 1030 return NULL; 1031 1032 dst = kmalloc(sizeof(*dst), ALLOW_FAIL); 1033 if (!dst) 1034 return NULL; 1035 1036 if (!compress_start(compress)) { 1037 kfree(dst); 1038 return NULL; 1039 } 1040 1041 INIT_LIST_HEAD(&dst->page_list); 1042 strcpy(dst->name, vsnap->name); 1043 dst->next = NULL; 1044 1045 dst->gtt_offset = vsnap->gtt_offset; 1046 dst->gtt_size = vsnap->gtt_size; 1047 dst->gtt_page_sizes = vsnap->page_sizes; 1048 dst->unused = 0; 1049 1050 ret = -EINVAL; 1051 if (drm_mm_node_allocated(&ggtt->error_capture)) { 1052 void __iomem *s; 1053 dma_addr_t dma; 1054 1055 for_each_sgt_daddr(dma, iter, vsnap->pages) { 1056 mutex_lock(&ggtt->error_mutex); 1057 ggtt->vm.insert_page(&ggtt->vm, dma, slot, 1058 I915_CACHE_NONE, 0); 1059 mb(); 1060 1061 s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE); 1062 ret = compress_page(compress, 1063 (void __force *)s, dst, 1064 true); 1065 io_mapping_unmap(s); 1066 1067 mb(); 1068 ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE); 1069 mutex_unlock(&ggtt->error_mutex); 1070 if (ret) 1071 break; 1072 } 1073 } else if (vsnap->mr && vsnap->mr->type != INTEL_MEMORY_SYSTEM) { 1074 struct intel_memory_region *mem = vsnap->mr; 1075 dma_addr_t dma; 1076 1077 for_each_sgt_daddr(dma, iter, vsnap->pages) { 1078 void __iomem *s; 1079 1080 s = io_mapping_map_wc(&mem->iomap, 1081 dma - mem->region.start, 1082 PAGE_SIZE); 1083 ret = compress_page(compress, 1084 (void __force *)s, dst, 1085 true); 1086 io_mapping_unmap(s); 1087 if (ret) 1088 break; 1089 } 1090 } else { 1091 struct page *page; 1092 1093 for_each_sgt_page(page, iter, vsnap->pages) { 1094 void *s; 1095 1096 drm_clflush_pages(&page, 1); 1097 1098 s = kmap(page); 1099 ret = compress_page(compress, s, dst, false); 1100 kunmap(page); 1101 1102 drm_clflush_pages(&page, 1); 1103 1104 if (ret) 1105 break; 1106 } 1107 } 1108 1109 if (ret || compress_flush(compress, dst)) { 1110 struct page *page, *n; 1111 1112 list_for_each_entry_safe_reverse(page, n, &dst->page_list, lru) { 1113 list_del_init(&page->lru); 1114 pool_free(&compress->pool, page_address(page)); 1115 } 1116 1117 kfree(dst); 1118 dst = NULL; 1119 } 1120 compress_finish(compress); 1121 1122 return dst; 1123 } 1124 1125 static void gt_record_fences(struct intel_gt_coredump *gt) 1126 { 1127 struct i915_ggtt *ggtt = gt->_gt->ggtt; 1128 struct intel_uncore *uncore = gt->_gt->uncore; 1129 int i; 1130 1131 if (GRAPHICS_VER(uncore->i915) >= 6) { 1132 for (i = 0; i < ggtt->num_fences; i++) 1133 gt->fence[i] = 1134 intel_uncore_read64(uncore, 1135 FENCE_REG_GEN6_LO(i)); 1136 } else if (GRAPHICS_VER(uncore->i915) >= 4) { 1137 for (i = 0; i < ggtt->num_fences; i++) 1138 gt->fence[i] = 1139 intel_uncore_read64(uncore, 1140 FENCE_REG_965_LO(i)); 1141 } else { 1142 for (i = 0; i < ggtt->num_fences; i++) 1143 gt->fence[i] = 1144 intel_uncore_read(uncore, FENCE_REG(i)); 1145 } 1146 gt->nfence = i; 1147 } 1148 1149 static void engine_record_registers(struct intel_engine_coredump *ee) 1150 { 1151 const struct intel_engine_cs *engine = ee->engine; 1152 struct drm_i915_private *i915 = engine->i915; 1153 1154 if (GRAPHICS_VER(i915) >= 6) { 1155 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL); 1156 1157 if (GRAPHICS_VER(i915) >= 12) 1158 ee->fault_reg = intel_uncore_read(engine->uncore, 1159 GEN12_RING_FAULT_REG); 1160 else if (GRAPHICS_VER(i915) >= 8) 1161 ee->fault_reg = intel_uncore_read(engine->uncore, 1162 GEN8_RING_FAULT_REG); 1163 else 1164 ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine); 1165 } 1166 1167 if (GRAPHICS_VER(i915) >= 4) { 1168 ee->esr = ENGINE_READ(engine, RING_ESR); 1169 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD); 1170 ee->ipeir = ENGINE_READ(engine, RING_IPEIR); 1171 ee->ipehr = ENGINE_READ(engine, RING_IPEHR); 1172 ee->instps = ENGINE_READ(engine, RING_INSTPS); 1173 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR); 1174 ee->ccid = ENGINE_READ(engine, CCID); 1175 if (GRAPHICS_VER(i915) >= 8) { 1176 ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32; 1177 ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32; 1178 } 1179 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE); 1180 } else { 1181 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX); 1182 ee->ipeir = ENGINE_READ(engine, IPEIR); 1183 ee->ipehr = ENGINE_READ(engine, IPEHR); 1184 } 1185 1186 intel_engine_get_instdone(engine, &ee->instdone); 1187 1188 ee->instpm = ENGINE_READ(engine, RING_INSTPM); 1189 ee->acthd = intel_engine_get_active_head(engine); 1190 ee->start = ENGINE_READ(engine, RING_START); 1191 ee->head = ENGINE_READ(engine, RING_HEAD); 1192 ee->tail = ENGINE_READ(engine, RING_TAIL); 1193 ee->ctl = ENGINE_READ(engine, RING_CTL); 1194 if (GRAPHICS_VER(i915) > 2) 1195 ee->mode = ENGINE_READ(engine, RING_MI_MODE); 1196 1197 if (!HWS_NEEDS_PHYSICAL(i915)) { 1198 i915_reg_t mmio; 1199 1200 if (GRAPHICS_VER(i915) == 7) { 1201 switch (engine->id) { 1202 default: 1203 MISSING_CASE(engine->id); 1204 fallthrough; 1205 case RCS0: 1206 mmio = RENDER_HWS_PGA_GEN7; 1207 break; 1208 case BCS0: 1209 mmio = BLT_HWS_PGA_GEN7; 1210 break; 1211 case VCS0: 1212 mmio = BSD_HWS_PGA_GEN7; 1213 break; 1214 case VECS0: 1215 mmio = VEBOX_HWS_PGA_GEN7; 1216 break; 1217 } 1218 } else if (GRAPHICS_VER(engine->i915) == 6) { 1219 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); 1220 } else { 1221 /* XXX: gen8 returns to sanity */ 1222 mmio = RING_HWS_PGA(engine->mmio_base); 1223 } 1224 1225 ee->hws = intel_uncore_read(engine->uncore, mmio); 1226 } 1227 1228 ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine); 1229 1230 if (HAS_PPGTT(i915)) { 1231 int i; 1232 1233 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7); 1234 1235 if (GRAPHICS_VER(i915) == 6) { 1236 ee->vm_info.pp_dir_base = 1237 ENGINE_READ(engine, RING_PP_DIR_BASE_READ); 1238 } else if (GRAPHICS_VER(i915) == 7) { 1239 ee->vm_info.pp_dir_base = 1240 ENGINE_READ(engine, RING_PP_DIR_BASE); 1241 } else if (GRAPHICS_VER(i915) >= 8) { 1242 u32 base = engine->mmio_base; 1243 1244 for (i = 0; i < 4; i++) { 1245 ee->vm_info.pdp[i] = 1246 intel_uncore_read(engine->uncore, 1247 GEN8_RING_PDP_UDW(base, i)); 1248 ee->vm_info.pdp[i] <<= 32; 1249 ee->vm_info.pdp[i] |= 1250 intel_uncore_read(engine->uncore, 1251 GEN8_RING_PDP_LDW(base, i)); 1252 } 1253 } 1254 } 1255 } 1256 1257 static void record_request(const struct i915_request *request, 1258 struct i915_request_coredump *erq) 1259 { 1260 erq->flags = request->fence.flags; 1261 erq->context = request->fence.context; 1262 erq->seqno = request->fence.seqno; 1263 erq->sched_attr = request->sched.attr; 1264 erq->head = request->head; 1265 erq->tail = request->tail; 1266 1267 erq->pid = 0; 1268 rcu_read_lock(); 1269 if (!intel_context_is_closed(request->context)) { 1270 const struct i915_gem_context *ctx; 1271 1272 ctx = rcu_dereference(request->context->gem_context); 1273 if (ctx) 1274 erq->pid = pid_nr(ctx->pid); 1275 } 1276 rcu_read_unlock(); 1277 } 1278 1279 static void engine_record_execlists(struct intel_engine_coredump *ee) 1280 { 1281 const struct intel_engine_execlists * const el = &ee->engine->execlists; 1282 struct i915_request * const *port = el->active; 1283 unsigned int n = 0; 1284 1285 while (*port) 1286 record_request(*port++, &ee->execlist[n++]); 1287 1288 ee->num_ports = n; 1289 } 1290 1291 static bool record_context(struct i915_gem_context_coredump *e, 1292 const struct i915_request *rq) 1293 { 1294 struct i915_gem_context *ctx; 1295 struct task_struct *task; 1296 bool simulated; 1297 1298 rcu_read_lock(); 1299 ctx = rcu_dereference(rq->context->gem_context); 1300 if (ctx && !kref_get_unless_zero(&ctx->ref)) 1301 ctx = NULL; 1302 rcu_read_unlock(); 1303 if (!ctx) 1304 return true; 1305 1306 rcu_read_lock(); 1307 task = pid_task(ctx->pid, PIDTYPE_PID); 1308 if (task) { 1309 strcpy(e->comm, task->comm); 1310 e->pid = task->pid; 1311 } 1312 rcu_read_unlock(); 1313 1314 e->sched_attr = ctx->sched; 1315 e->guilty = atomic_read(&ctx->guilty_count); 1316 e->active = atomic_read(&ctx->active_count); 1317 1318 e->total_runtime = rq->context->runtime.total; 1319 e->avg_runtime = ewma_runtime_read(&rq->context->runtime.avg); 1320 1321 simulated = i915_gem_context_no_error_capture(ctx); 1322 1323 i915_gem_context_put(ctx); 1324 return simulated; 1325 } 1326 1327 struct intel_engine_capture_vma { 1328 struct intel_engine_capture_vma *next; 1329 struct i915_vma_snapshot *vsnap; 1330 char name[16]; 1331 bool lockdep_cookie; 1332 }; 1333 1334 static struct intel_engine_capture_vma * 1335 capture_vma_snapshot(struct intel_engine_capture_vma *next, 1336 struct i915_vma_snapshot *vsnap, 1337 gfp_t gfp) 1338 { 1339 struct intel_engine_capture_vma *c; 1340 1341 if (!i915_vma_snapshot_present(vsnap)) 1342 return next; 1343 1344 c = kmalloc(sizeof(*c), gfp); 1345 if (!c) 1346 return next; 1347 1348 if (!i915_vma_snapshot_resource_pin(vsnap, &c->lockdep_cookie)) { 1349 kfree(c); 1350 return next; 1351 } 1352 1353 strcpy(c->name, vsnap->name); 1354 c->vsnap = vsnap; 1355 i915_vma_snapshot_get(vsnap); 1356 1357 c->next = next; 1358 return c; 1359 } 1360 1361 static struct intel_engine_capture_vma * 1362 capture_vma(struct intel_engine_capture_vma *next, 1363 struct i915_vma *vma, 1364 const char *name, 1365 gfp_t gfp) 1366 { 1367 struct i915_vma_snapshot *vsnap; 1368 1369 if (!vma) 1370 return next; 1371 1372 /* 1373 * If the vma isn't pinned, then the vma should be snapshotted 1374 * to a struct i915_vma_snapshot at command submission time. 1375 * Not here. 1376 */ 1377 GEM_WARN_ON(!i915_vma_is_pinned(vma)); 1378 if (!i915_vma_is_pinned(vma)) 1379 return next; 1380 1381 vsnap = i915_vma_snapshot_alloc(gfp); 1382 if (!vsnap) 1383 return next; 1384 1385 i915_vma_snapshot_init(vsnap, vma, name); 1386 next = capture_vma_snapshot(next, vsnap, gfp); 1387 1388 /* FIXME: Replace on async unbind. */ 1389 i915_vma_snapshot_put(vsnap); 1390 1391 return next; 1392 } 1393 1394 static struct intel_engine_capture_vma * 1395 capture_user(struct intel_engine_capture_vma *capture, 1396 const struct i915_request *rq, 1397 gfp_t gfp) 1398 { 1399 struct i915_capture_list *c; 1400 1401 for (c = rq->capture_list; c; c = c->next) 1402 capture = capture_vma_snapshot(capture, c->vma_snapshot, gfp); 1403 1404 return capture; 1405 } 1406 1407 static void add_vma(struct intel_engine_coredump *ee, 1408 struct i915_vma_coredump *vma) 1409 { 1410 if (vma) { 1411 vma->next = ee->vma; 1412 ee->vma = vma; 1413 } 1414 } 1415 1416 static struct i915_vma_coredump * 1417 create_vma_coredump(const struct intel_gt *gt, struct i915_vma *vma, 1418 const char *name, struct i915_vma_compress *compress) 1419 { 1420 struct i915_vma_coredump *ret; 1421 struct i915_vma_snapshot tmp; 1422 1423 if (!vma) 1424 return NULL; 1425 1426 GEM_WARN_ON(!i915_vma_is_pinned(vma)); 1427 i915_vma_snapshot_init_onstack(&tmp, vma, name); 1428 ret = i915_vma_coredump_create(gt, &tmp, compress); 1429 i915_vma_snapshot_put_onstack(&tmp); 1430 1431 return ret; 1432 } 1433 1434 static void add_vma_coredump(struct intel_engine_coredump *ee, 1435 const struct intel_gt *gt, 1436 struct i915_vma *vma, 1437 const char *name, 1438 struct i915_vma_compress *compress) 1439 { 1440 add_vma(ee, create_vma_coredump(gt, vma, name, compress)); 1441 } 1442 1443 struct intel_engine_coredump * 1444 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp) 1445 { 1446 struct intel_engine_coredump *ee; 1447 1448 ee = kzalloc(sizeof(*ee), gfp); 1449 if (!ee) 1450 return NULL; 1451 1452 ee->engine = engine; 1453 1454 engine_record_registers(ee); 1455 engine_record_execlists(ee); 1456 1457 return ee; 1458 } 1459 1460 struct intel_engine_capture_vma * 1461 intel_engine_coredump_add_request(struct intel_engine_coredump *ee, 1462 struct i915_request *rq, 1463 gfp_t gfp) 1464 { 1465 struct intel_engine_capture_vma *vma = NULL; 1466 1467 ee->simulated |= record_context(&ee->context, rq); 1468 if (ee->simulated) 1469 return NULL; 1470 1471 /* 1472 * We need to copy these to an anonymous buffer 1473 * as the simplest method to avoid being overwritten 1474 * by userspace. 1475 */ 1476 vma = capture_vma_snapshot(vma, &rq->batch_snapshot, gfp); 1477 vma = capture_user(vma, rq, gfp); 1478 vma = capture_vma(vma, rq->ring->vma, "ring", gfp); 1479 vma = capture_vma(vma, rq->context->state, "HW context", gfp); 1480 1481 ee->rq_head = rq->head; 1482 ee->rq_post = rq->postfix; 1483 ee->rq_tail = rq->tail; 1484 1485 return vma; 1486 } 1487 1488 void 1489 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee, 1490 struct intel_engine_capture_vma *capture, 1491 struct i915_vma_compress *compress) 1492 { 1493 const struct intel_engine_cs *engine = ee->engine; 1494 1495 while (capture) { 1496 struct intel_engine_capture_vma *this = capture; 1497 struct i915_vma_snapshot *vsnap = this->vsnap; 1498 1499 add_vma(ee, 1500 i915_vma_coredump_create(engine->gt, 1501 vsnap, compress)); 1502 1503 i915_vma_snapshot_resource_unpin(vsnap, this->lockdep_cookie); 1504 i915_vma_snapshot_put(vsnap); 1505 1506 capture = this->next; 1507 kfree(this); 1508 } 1509 1510 add_vma_coredump(ee, engine->gt, engine->status_page.vma, 1511 "HW Status", compress); 1512 1513 add_vma_coredump(ee, engine->gt, engine->wa_ctx.vma, 1514 "WA context", compress); 1515 } 1516 1517 static struct intel_engine_coredump * 1518 capture_engine(struct intel_engine_cs *engine, 1519 struct i915_vma_compress *compress) 1520 { 1521 struct intel_engine_capture_vma *capture = NULL; 1522 struct intel_engine_coredump *ee; 1523 struct intel_context *ce; 1524 struct i915_request *rq = NULL; 1525 unsigned long flags; 1526 1527 ee = intel_engine_coredump_alloc(engine, ALLOW_FAIL); 1528 if (!ee) 1529 return NULL; 1530 1531 ce = intel_engine_get_hung_context(engine); 1532 if (ce) { 1533 intel_engine_clear_hung_context(engine); 1534 rq = intel_context_find_active_request(ce); 1535 if (!rq || !i915_request_started(rq)) 1536 goto no_request_capture; 1537 } else { 1538 /* 1539 * Getting here with GuC enabled means it is a forced error capture 1540 * with no actual hang. So, no need to attempt the execlist search. 1541 */ 1542 if (!intel_uc_uses_guc_submission(&engine->gt->uc)) { 1543 spin_lock_irqsave(&engine->sched_engine->lock, flags); 1544 rq = intel_engine_execlist_find_hung_request(engine); 1545 spin_unlock_irqrestore(&engine->sched_engine->lock, 1546 flags); 1547 } 1548 } 1549 if (rq) 1550 rq = i915_request_get_rcu(rq); 1551 1552 if (!rq) 1553 goto no_request_capture; 1554 1555 capture = intel_engine_coredump_add_request(ee, rq, ATOMIC_MAYFAIL); 1556 if (!capture) { 1557 i915_request_put(rq); 1558 goto no_request_capture; 1559 } 1560 1561 intel_engine_coredump_add_vma(ee, capture, compress); 1562 i915_request_put(rq); 1563 1564 return ee; 1565 1566 no_request_capture: 1567 kfree(ee); 1568 return NULL; 1569 } 1570 1571 static void 1572 gt_record_engines(struct intel_gt_coredump *gt, 1573 intel_engine_mask_t engine_mask, 1574 struct i915_vma_compress *compress) 1575 { 1576 struct intel_engine_cs *engine; 1577 enum intel_engine_id id; 1578 1579 for_each_engine(engine, gt->_gt, id) { 1580 struct intel_engine_coredump *ee; 1581 1582 /* Refill our page pool before entering atomic section */ 1583 pool_refill(&compress->pool, ALLOW_FAIL); 1584 1585 ee = capture_engine(engine, compress); 1586 if (!ee) 1587 continue; 1588 1589 ee->hung = engine->mask & engine_mask; 1590 1591 gt->simulated |= ee->simulated; 1592 if (ee->simulated) { 1593 kfree(ee); 1594 continue; 1595 } 1596 1597 ee->next = gt->engine; 1598 gt->engine = ee; 1599 } 1600 } 1601 1602 static struct intel_uc_coredump * 1603 gt_record_uc(struct intel_gt_coredump *gt, 1604 struct i915_vma_compress *compress) 1605 { 1606 const struct intel_uc *uc = >->_gt->uc; 1607 struct intel_uc_coredump *error_uc; 1608 1609 error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL); 1610 if (!error_uc) 1611 return NULL; 1612 1613 memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw)); 1614 memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw)); 1615 1616 /* Non-default firmware paths will be specified by the modparam. 1617 * As modparams are generally accesible from the userspace make 1618 * explicit copies of the firmware paths. 1619 */ 1620 error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, ALLOW_FAIL); 1621 error_uc->huc_fw.path = kstrdup(uc->huc.fw.path, ALLOW_FAIL); 1622 error_uc->guc_log = create_vma_coredump(gt->_gt, uc->guc.log.vma, 1623 "GuC log buffer", compress); 1624 1625 return error_uc; 1626 } 1627 1628 /* Capture all registers which don't fit into another category. */ 1629 static void gt_record_regs(struct intel_gt_coredump *gt) 1630 { 1631 struct intel_uncore *uncore = gt->_gt->uncore; 1632 struct drm_i915_private *i915 = uncore->i915; 1633 int i; 1634 1635 /* 1636 * General organization 1637 * 1. Registers specific to a single generation 1638 * 2. Registers which belong to multiple generations 1639 * 3. Feature specific registers. 1640 * 4. Everything else 1641 * Please try to follow the order. 1642 */ 1643 1644 /* 1: Registers specific to a single generation */ 1645 if (IS_VALLEYVIEW(i915)) { 1646 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1647 gt->ier = intel_uncore_read(uncore, VLV_IER); 1648 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV); 1649 } 1650 1651 if (GRAPHICS_VER(i915) == 7) 1652 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT); 1653 1654 if (GRAPHICS_VER(i915) >= 12) { 1655 gt->fault_data0 = intel_uncore_read(uncore, 1656 GEN12_FAULT_TLB_DATA0); 1657 gt->fault_data1 = intel_uncore_read(uncore, 1658 GEN12_FAULT_TLB_DATA1); 1659 } else if (GRAPHICS_VER(i915) >= 8) { 1660 gt->fault_data0 = intel_uncore_read(uncore, 1661 GEN8_FAULT_TLB_DATA0); 1662 gt->fault_data1 = intel_uncore_read(uncore, 1663 GEN8_FAULT_TLB_DATA1); 1664 } 1665 1666 if (GRAPHICS_VER(i915) == 6) { 1667 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE); 1668 gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL); 1669 gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE); 1670 } 1671 1672 /* 2: Registers which belong to multiple generations */ 1673 if (GRAPHICS_VER(i915) >= 7) 1674 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT); 1675 1676 if (GRAPHICS_VER(i915) >= 6) { 1677 gt->derrmr = intel_uncore_read(uncore, DERRMR); 1678 if (GRAPHICS_VER(i915) < 12) { 1679 gt->error = intel_uncore_read(uncore, ERROR_GEN6); 1680 gt->done_reg = intel_uncore_read(uncore, DONE_REG); 1681 } 1682 } 1683 1684 /* 3: Feature specific registers */ 1685 if (IS_GRAPHICS_VER(i915, 6, 7)) { 1686 gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK); 1687 gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS); 1688 } 1689 1690 if (IS_GRAPHICS_VER(i915, 8, 11)) 1691 gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN); 1692 1693 if (GRAPHICS_VER(i915) == 12) 1694 gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG); 1695 1696 if (GRAPHICS_VER(i915) >= 12) { 1697 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) { 1698 /* 1699 * SFC_DONE resides in the VD forcewake domain, so it 1700 * only exists if the corresponding VCS engine is 1701 * present. 1702 */ 1703 if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || 1704 !HAS_ENGINE(gt->_gt, _VCS(i * 2))) 1705 continue; 1706 1707 gt->sfc_done[i] = 1708 intel_uncore_read(uncore, GEN12_SFC_DONE(i)); 1709 } 1710 1711 gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE); 1712 } 1713 1714 /* 4: Everything else */ 1715 if (GRAPHICS_VER(i915) >= 11) { 1716 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); 1717 gt->gtier[0] = 1718 intel_uncore_read(uncore, 1719 GEN11_RENDER_COPY_INTR_ENABLE); 1720 gt->gtier[1] = 1721 intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE); 1722 gt->gtier[2] = 1723 intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE); 1724 gt->gtier[3] = 1725 intel_uncore_read(uncore, 1726 GEN11_GPM_WGBOXPERF_INTR_ENABLE); 1727 gt->gtier[4] = 1728 intel_uncore_read(uncore, 1729 GEN11_CRYPTO_RSVD_INTR_ENABLE); 1730 gt->gtier[5] = 1731 intel_uncore_read(uncore, 1732 GEN11_GUNIT_CSME_INTR_ENABLE); 1733 gt->ngtier = 6; 1734 } else if (GRAPHICS_VER(i915) >= 8) { 1735 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); 1736 for (i = 0; i < 4; i++) 1737 gt->gtier[i] = 1738 intel_uncore_read(uncore, GEN8_GT_IER(i)); 1739 gt->ngtier = 4; 1740 } else if (HAS_PCH_SPLIT(i915)) { 1741 gt->ier = intel_uncore_read(uncore, DEIER); 1742 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1743 gt->ngtier = 1; 1744 } else if (GRAPHICS_VER(i915) == 2) { 1745 gt->ier = intel_uncore_read16(uncore, GEN2_IER); 1746 } else if (!IS_VALLEYVIEW(i915)) { 1747 gt->ier = intel_uncore_read(uncore, GEN2_IER); 1748 } 1749 gt->eir = intel_uncore_read(uncore, EIR); 1750 gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER); 1751 } 1752 1753 static void gt_record_info(struct intel_gt_coredump *gt) 1754 { 1755 memcpy(>->info, >->_gt->info, sizeof(struct intel_gt_info)); 1756 } 1757 1758 /* 1759 * Generate a semi-unique error code. The code is not meant to have meaning, The 1760 * code's only purpose is to try to prevent false duplicated bug reports by 1761 * grossly estimating a GPU error state. 1762 * 1763 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 1764 * the hang if we could strip the GTT offset information from it. 1765 * 1766 * It's only a small step better than a random number in its current form. 1767 */ 1768 static u32 generate_ecode(const struct intel_engine_coredump *ee) 1769 { 1770 /* 1771 * IPEHR would be an ideal way to detect errors, as it's the gross 1772 * measure of "the command that hung." However, has some very common 1773 * synchronization commands which almost always appear in the case 1774 * strictly a client bug. Use instdone to differentiate those some. 1775 */ 1776 return ee ? ee->ipehr ^ ee->instdone.instdone : 0; 1777 } 1778 1779 static const char *error_msg(struct i915_gpu_coredump *error) 1780 { 1781 struct intel_engine_coredump *first = NULL; 1782 unsigned int hung_classes = 0; 1783 struct intel_gt_coredump *gt; 1784 int len; 1785 1786 for (gt = error->gt; gt; gt = gt->next) { 1787 struct intel_engine_coredump *cs; 1788 1789 for (cs = gt->engine; cs; cs = cs->next) { 1790 if (cs->hung) { 1791 hung_classes |= BIT(cs->engine->uabi_class); 1792 if (!first) 1793 first = cs; 1794 } 1795 } 1796 } 1797 1798 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1799 "GPU HANG: ecode %d:%x:%08x", 1800 GRAPHICS_VER(error->i915), hung_classes, 1801 generate_ecode(first)); 1802 if (first && first->context.pid) { 1803 /* Just show the first executing process, more is confusing */ 1804 len += scnprintf(error->error_msg + len, 1805 sizeof(error->error_msg) - len, 1806 ", in %s [%d]", 1807 first->context.comm, first->context.pid); 1808 } 1809 1810 return error->error_msg; 1811 } 1812 1813 static void capture_gen(struct i915_gpu_coredump *error) 1814 { 1815 struct drm_i915_private *i915 = error->i915; 1816 1817 error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count); 1818 error->suspended = i915->runtime_pm.suspended; 1819 1820 error->iommu = intel_vtd_active(i915); 1821 error->reset_count = i915_reset_count(&i915->gpu_error); 1822 error->suspend_count = i915->suspend_count; 1823 1824 i915_params_copy(&error->params, &i915->params); 1825 memcpy(&error->device_info, 1826 INTEL_INFO(i915), 1827 sizeof(error->device_info)); 1828 memcpy(&error->runtime_info, 1829 RUNTIME_INFO(i915), 1830 sizeof(error->runtime_info)); 1831 error->driver_caps = i915->caps; 1832 } 1833 1834 struct i915_gpu_coredump * 1835 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp) 1836 { 1837 struct i915_gpu_coredump *error; 1838 1839 if (!i915->params.error_capture) 1840 return NULL; 1841 1842 error = kzalloc(sizeof(*error), gfp); 1843 if (!error) 1844 return NULL; 1845 1846 kref_init(&error->ref); 1847 error->i915 = i915; 1848 1849 error->time = ktime_get_real(); 1850 error->boottime = ktime_get_boottime(); 1851 error->uptime = ktime_sub(ktime_get(), to_gt(i915)->last_init_time); 1852 error->capture = jiffies; 1853 1854 capture_gen(error); 1855 1856 return error; 1857 } 1858 1859 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x)) 1860 1861 struct intel_gt_coredump * 1862 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp) 1863 { 1864 struct intel_gt_coredump *gc; 1865 1866 gc = kzalloc(sizeof(*gc), gfp); 1867 if (!gc) 1868 return NULL; 1869 1870 gc->_gt = gt; 1871 gc->awake = intel_gt_pm_is_awake(gt); 1872 1873 gt_record_regs(gc); 1874 gt_record_fences(gc); 1875 1876 return gc; 1877 } 1878 1879 struct i915_vma_compress * 1880 i915_vma_capture_prepare(struct intel_gt_coredump *gt) 1881 { 1882 struct i915_vma_compress *compress; 1883 1884 compress = kmalloc(sizeof(*compress), ALLOW_FAIL); 1885 if (!compress) 1886 return NULL; 1887 1888 if (!compress_init(compress)) { 1889 kfree(compress); 1890 return NULL; 1891 } 1892 1893 return compress; 1894 } 1895 1896 void i915_vma_capture_finish(struct intel_gt_coredump *gt, 1897 struct i915_vma_compress *compress) 1898 { 1899 if (!compress) 1900 return; 1901 1902 compress_fini(compress); 1903 kfree(compress); 1904 } 1905 1906 static struct i915_gpu_coredump * 1907 __i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask) 1908 { 1909 struct drm_i915_private *i915 = gt->i915; 1910 struct i915_gpu_coredump *error; 1911 1912 /* Check if GPU capture has been disabled */ 1913 error = READ_ONCE(i915->gpu_error.first_error); 1914 if (IS_ERR(error)) 1915 return error; 1916 1917 error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL); 1918 if (!error) 1919 return ERR_PTR(-ENOMEM); 1920 1921 error->gt = intel_gt_coredump_alloc(gt, ALLOW_FAIL); 1922 if (error->gt) { 1923 struct i915_vma_compress *compress; 1924 1925 compress = i915_vma_capture_prepare(error->gt); 1926 if (!compress) { 1927 kfree(error->gt); 1928 kfree(error); 1929 return ERR_PTR(-ENOMEM); 1930 } 1931 1932 gt_record_info(error->gt); 1933 gt_record_engines(error->gt, engine_mask, compress); 1934 1935 if (INTEL_INFO(i915)->has_gt_uc) 1936 error->gt->uc = gt_record_uc(error->gt, compress); 1937 1938 i915_vma_capture_finish(error->gt, compress); 1939 1940 error->simulated |= error->gt->simulated; 1941 } 1942 1943 error->overlay = intel_overlay_capture_error_state(i915); 1944 1945 return error; 1946 } 1947 1948 struct i915_gpu_coredump * 1949 i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask) 1950 { 1951 static DEFINE_MUTEX(capture_mutex); 1952 int ret = mutex_lock_interruptible(&capture_mutex); 1953 struct i915_gpu_coredump *dump; 1954 1955 if (ret) 1956 return ERR_PTR(ret); 1957 1958 dump = __i915_gpu_coredump(gt, engine_mask); 1959 mutex_unlock(&capture_mutex); 1960 1961 return dump; 1962 } 1963 1964 void i915_error_state_store(struct i915_gpu_coredump *error) 1965 { 1966 struct drm_i915_private *i915; 1967 static bool warned; 1968 1969 if (IS_ERR_OR_NULL(error)) 1970 return; 1971 1972 i915 = error->i915; 1973 drm_info(&i915->drm, "%s\n", error_msg(error)); 1974 1975 if (error->simulated || 1976 cmpxchg(&i915->gpu_error.first_error, NULL, error)) 1977 return; 1978 1979 i915_gpu_coredump_get(error); 1980 1981 if (!xchg(&warned, true) && 1982 ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) { 1983 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 1984 pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n"); 1985 pr_info("Please see https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs for details.\n"); 1986 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 1987 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n"); 1988 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n", 1989 i915->drm.primary->index); 1990 } 1991 } 1992 1993 /** 1994 * i915_capture_error_state - capture an error record for later analysis 1995 * @gt: intel_gt which originated the hang 1996 * @engine_mask: hung engines 1997 * 1998 * 1999 * Should be called when an error is detected (either a hang or an error 2000 * interrupt) to capture error state from the time of the error. Fills 2001 * out a structure which becomes available in debugfs for user level tools 2002 * to pick up. 2003 */ 2004 void i915_capture_error_state(struct intel_gt *gt, 2005 intel_engine_mask_t engine_mask) 2006 { 2007 struct i915_gpu_coredump *error; 2008 2009 error = i915_gpu_coredump(gt, engine_mask); 2010 if (IS_ERR(error)) { 2011 cmpxchg(>->i915->gpu_error.first_error, NULL, error); 2012 return; 2013 } 2014 2015 i915_error_state_store(error); 2016 i915_gpu_coredump_put(error); 2017 } 2018 2019 struct i915_gpu_coredump * 2020 i915_first_error_state(struct drm_i915_private *i915) 2021 { 2022 struct i915_gpu_coredump *error; 2023 2024 spin_lock_irq(&i915->gpu_error.lock); 2025 error = i915->gpu_error.first_error; 2026 if (!IS_ERR_OR_NULL(error)) 2027 i915_gpu_coredump_get(error); 2028 spin_unlock_irq(&i915->gpu_error.lock); 2029 2030 return error; 2031 } 2032 2033 void i915_reset_error_state(struct drm_i915_private *i915) 2034 { 2035 struct i915_gpu_coredump *error; 2036 2037 spin_lock_irq(&i915->gpu_error.lock); 2038 error = i915->gpu_error.first_error; 2039 if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */ 2040 i915->gpu_error.first_error = NULL; 2041 spin_unlock_irq(&i915->gpu_error.lock); 2042 2043 if (!IS_ERR_OR_NULL(error)) 2044 i915_gpu_coredump_put(error); 2045 } 2046 2047 void i915_disable_error_state(struct drm_i915_private *i915, int err) 2048 { 2049 spin_lock_irq(&i915->gpu_error.lock); 2050 if (!i915->gpu_error.first_error) 2051 i915->gpu_error.first_error = ERR_PTR(err); 2052 spin_unlock_irq(&i915->gpu_error.lock); 2053 } 2054