1 /* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30 #include <linux/ascii85.h> 31 #include <linux/debugfs.h> 32 #include <linux/highmem.h> 33 #include <linux/nmi.h> 34 #include <linux/pagevec.h> 35 #include <linux/scatterlist.h> 36 #include <linux/string_helpers.h> 37 #include <linux/utsname.h> 38 #include <linux/zlib.h> 39 40 #include <drm/drm_cache.h> 41 #include <drm/drm_print.h> 42 43 #include "display/intel_dmc.h" 44 #include "display/intel_overlay.h" 45 46 #include "gem/i915_gem_context.h" 47 #include "gem/i915_gem_lmem.h" 48 #include "gt/intel_engine_regs.h" 49 #include "gt/intel_gt.h" 50 #include "gt/intel_gt_mcr.h" 51 #include "gt/intel_gt_pm.h" 52 #include "gt/intel_gt_regs.h" 53 #include "gt/uc/intel_guc_capture.h" 54 55 #include "i915_driver.h" 56 #include "i915_drv.h" 57 #include "i915_gpu_error.h" 58 #include "i915_memcpy.h" 59 #include "i915_reg.h" 60 #include "i915_scatterlist.h" 61 #include "i915_sysfs.h" 62 #include "i915_utils.h" 63 64 #define ALLOW_FAIL (__GFP_KSWAPD_RECLAIM | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) 65 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN) 66 67 static void __sg_set_buf(struct scatterlist *sg, 68 void *addr, unsigned int len, loff_t it) 69 { 70 sg->page_link = (unsigned long)virt_to_page(addr); 71 sg->offset = offset_in_page(addr); 72 sg->length = len; 73 sg->dma_address = it; 74 } 75 76 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len) 77 { 78 if (!len) 79 return false; 80 81 if (e->bytes + len + 1 <= e->size) 82 return true; 83 84 if (e->bytes) { 85 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter); 86 e->iter += e->bytes; 87 e->buf = NULL; 88 e->bytes = 0; 89 } 90 91 if (e->cur == e->end) { 92 struct scatterlist *sgl; 93 94 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL); 95 if (!sgl) { 96 e->err = -ENOMEM; 97 return false; 98 } 99 100 if (e->cur) { 101 e->cur->offset = 0; 102 e->cur->length = 0; 103 e->cur->page_link = 104 (unsigned long)sgl | SG_CHAIN; 105 } else { 106 e->sgl = sgl; 107 } 108 109 e->cur = sgl; 110 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1; 111 } 112 113 e->size = ALIGN(len + 1, SZ_64K); 114 e->buf = kmalloc(e->size, ALLOW_FAIL); 115 if (!e->buf) { 116 e->size = PAGE_ALIGN(len + 1); 117 e->buf = kmalloc(e->size, GFP_KERNEL); 118 } 119 if (!e->buf) { 120 e->err = -ENOMEM; 121 return false; 122 } 123 124 return true; 125 } 126 127 __printf(2, 0) 128 static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 129 const char *fmt, va_list args) 130 { 131 va_list ap; 132 int len; 133 134 if (e->err) 135 return; 136 137 va_copy(ap, args); 138 len = vsnprintf(NULL, 0, fmt, ap); 139 va_end(ap); 140 if (len <= 0) { 141 e->err = len; 142 return; 143 } 144 145 if (!__i915_error_grow(e, len)) 146 return; 147 148 GEM_BUG_ON(e->bytes >= e->size); 149 len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args); 150 if (len < 0) { 151 e->err = len; 152 return; 153 } 154 e->bytes += len; 155 } 156 157 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str) 158 { 159 unsigned len; 160 161 if (e->err || !str) 162 return; 163 164 len = strlen(str); 165 if (!__i915_error_grow(e, len)) 166 return; 167 168 GEM_BUG_ON(e->bytes + len > e->size); 169 memcpy(e->buf + e->bytes, str, len); 170 e->bytes += len; 171 } 172 173 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 174 #define err_puts(e, s) i915_error_puts(e, s) 175 176 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf) 177 { 178 i915_error_vprintf(p->arg, vaf->fmt, *vaf->va); 179 } 180 181 static inline struct drm_printer 182 i915_error_printer(struct drm_i915_error_state_buf *e) 183 { 184 struct drm_printer p = { 185 .printfn = __i915_printfn_error, 186 .arg = e, 187 }; 188 return p; 189 } 190 191 /* single threaded page allocator with a reserved stash for emergencies */ 192 static void pool_fini(struct folio_batch *fbatch) 193 { 194 folio_batch_release(fbatch); 195 } 196 197 static int pool_refill(struct folio_batch *fbatch, gfp_t gfp) 198 { 199 while (folio_batch_space(fbatch)) { 200 struct folio *folio; 201 202 folio = folio_alloc(gfp, 0); 203 if (!folio) 204 return -ENOMEM; 205 206 folio_batch_add(fbatch, folio); 207 } 208 209 return 0; 210 } 211 212 static int pool_init(struct folio_batch *fbatch, gfp_t gfp) 213 { 214 int err; 215 216 folio_batch_init(fbatch); 217 218 err = pool_refill(fbatch, gfp); 219 if (err) 220 pool_fini(fbatch); 221 222 return err; 223 } 224 225 static void *pool_alloc(struct folio_batch *fbatch, gfp_t gfp) 226 { 227 struct folio *folio; 228 229 folio = folio_alloc(gfp, 0); 230 if (!folio && folio_batch_count(fbatch)) 231 folio = fbatch->folios[--fbatch->nr]; 232 233 return folio ? folio_address(folio) : NULL; 234 } 235 236 static void pool_free(struct folio_batch *fbatch, void *addr) 237 { 238 struct folio *folio = virt_to_folio(addr); 239 240 if (folio_batch_space(fbatch)) 241 folio_batch_add(fbatch, folio); 242 else 243 folio_put(folio); 244 } 245 246 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR 247 248 struct i915_vma_compress { 249 struct folio_batch pool; 250 struct z_stream_s zstream; 251 void *tmp; 252 }; 253 254 static bool compress_init(struct i915_vma_compress *c) 255 { 256 struct z_stream_s *zstream = &c->zstream; 257 258 if (pool_init(&c->pool, ALLOW_FAIL)) 259 return false; 260 261 zstream->workspace = 262 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL), 263 ALLOW_FAIL); 264 if (!zstream->workspace) { 265 pool_fini(&c->pool); 266 return false; 267 } 268 269 c->tmp = NULL; 270 if (i915_has_memcpy_from_wc()) 271 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL); 272 273 return true; 274 } 275 276 static bool compress_start(struct i915_vma_compress *c) 277 { 278 struct z_stream_s *zstream = &c->zstream; 279 void *workspace = zstream->workspace; 280 281 memset(zstream, 0, sizeof(*zstream)); 282 zstream->workspace = workspace; 283 284 return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK; 285 } 286 287 static void *compress_next_page(struct i915_vma_compress *c, 288 struct i915_vma_coredump *dst) 289 { 290 void *page_addr; 291 struct page *page; 292 293 page_addr = pool_alloc(&c->pool, ALLOW_FAIL); 294 if (!page_addr) 295 return ERR_PTR(-ENOMEM); 296 297 page = virt_to_page(page_addr); 298 list_add_tail(&page->lru, &dst->page_list); 299 return page_addr; 300 } 301 302 static int compress_page(struct i915_vma_compress *c, 303 void *src, 304 struct i915_vma_coredump *dst, 305 bool wc) 306 { 307 struct z_stream_s *zstream = &c->zstream; 308 309 zstream->next_in = src; 310 if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE)) 311 zstream->next_in = c->tmp; 312 zstream->avail_in = PAGE_SIZE; 313 314 do { 315 if (zstream->avail_out == 0) { 316 zstream->next_out = compress_next_page(c, dst); 317 if (IS_ERR(zstream->next_out)) 318 return PTR_ERR(zstream->next_out); 319 320 zstream->avail_out = PAGE_SIZE; 321 } 322 323 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK) 324 return -EIO; 325 326 cond_resched(); 327 } while (zstream->avail_in); 328 329 /* Fallback to uncompressed if we increase size? */ 330 if (0 && zstream->total_out > zstream->total_in) 331 return -E2BIG; 332 333 return 0; 334 } 335 336 static int compress_flush(struct i915_vma_compress *c, 337 struct i915_vma_coredump *dst) 338 { 339 struct z_stream_s *zstream = &c->zstream; 340 341 do { 342 switch (zlib_deflate(zstream, Z_FINISH)) { 343 case Z_OK: /* more space requested */ 344 zstream->next_out = compress_next_page(c, dst); 345 if (IS_ERR(zstream->next_out)) 346 return PTR_ERR(zstream->next_out); 347 348 zstream->avail_out = PAGE_SIZE; 349 break; 350 351 case Z_STREAM_END: 352 goto end; 353 354 default: /* any error */ 355 return -EIO; 356 } 357 } while (1); 358 359 end: 360 memset(zstream->next_out, 0, zstream->avail_out); 361 dst->unused = zstream->avail_out; 362 return 0; 363 } 364 365 static void compress_finish(struct i915_vma_compress *c) 366 { 367 zlib_deflateEnd(&c->zstream); 368 } 369 370 static void compress_fini(struct i915_vma_compress *c) 371 { 372 kfree(c->zstream.workspace); 373 if (c->tmp) 374 pool_free(&c->pool, c->tmp); 375 pool_fini(&c->pool); 376 } 377 378 static void err_compression_marker(struct drm_i915_error_state_buf *m) 379 { 380 err_puts(m, ":"); 381 } 382 383 #else 384 385 struct i915_vma_compress { 386 struct folio_batch pool; 387 }; 388 389 static bool compress_init(struct i915_vma_compress *c) 390 { 391 return pool_init(&c->pool, ALLOW_FAIL) == 0; 392 } 393 394 static bool compress_start(struct i915_vma_compress *c) 395 { 396 return true; 397 } 398 399 static int compress_page(struct i915_vma_compress *c, 400 void *src, 401 struct i915_vma_coredump *dst, 402 bool wc) 403 { 404 void *ptr; 405 406 ptr = pool_alloc(&c->pool, ALLOW_FAIL); 407 if (!ptr) 408 return -ENOMEM; 409 410 if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE))) 411 memcpy(ptr, src, PAGE_SIZE); 412 list_add_tail(&virt_to_page(ptr)->lru, &dst->page_list); 413 cond_resched(); 414 415 return 0; 416 } 417 418 static int compress_flush(struct i915_vma_compress *c, 419 struct i915_vma_coredump *dst) 420 { 421 return 0; 422 } 423 424 static void compress_finish(struct i915_vma_compress *c) 425 { 426 } 427 428 static void compress_fini(struct i915_vma_compress *c) 429 { 430 pool_fini(&c->pool); 431 } 432 433 static void err_compression_marker(struct drm_i915_error_state_buf *m) 434 { 435 err_puts(m, "~"); 436 } 437 438 #endif 439 440 static void error_print_instdone(struct drm_i915_error_state_buf *m, 441 const struct intel_engine_coredump *ee) 442 { 443 int slice; 444 int subslice; 445 int iter; 446 447 err_printf(m, " INSTDONE: 0x%08x\n", 448 ee->instdone.instdone); 449 450 if (ee->engine->class != RENDER_CLASS || GRAPHICS_VER(m->i915) <= 3) 451 return; 452 453 err_printf(m, " SC_INSTDONE: 0x%08x\n", 454 ee->instdone.slice_common); 455 456 if (GRAPHICS_VER(m->i915) <= 6) 457 return; 458 459 for_each_ss_steering(iter, ee->engine->gt, slice, subslice) 460 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", 461 slice, subslice, 462 ee->instdone.sampler[slice][subslice]); 463 464 for_each_ss_steering(iter, ee->engine->gt, slice, subslice) 465 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", 466 slice, subslice, 467 ee->instdone.row[slice][subslice]); 468 469 if (GRAPHICS_VER(m->i915) < 12) 470 return; 471 472 if (GRAPHICS_VER_FULL(m->i915) >= IP_VER(12, 55)) { 473 for_each_ss_steering(iter, ee->engine->gt, slice, subslice) 474 err_printf(m, " GEOM_SVGUNIT_INSTDONE[%d][%d]: 0x%08x\n", 475 slice, subslice, 476 ee->instdone.geom_svg[slice][subslice]); 477 } 478 479 err_printf(m, " SC_INSTDONE_EXTRA: 0x%08x\n", 480 ee->instdone.slice_common_extra[0]); 481 err_printf(m, " SC_INSTDONE_EXTRA2: 0x%08x\n", 482 ee->instdone.slice_common_extra[1]); 483 } 484 485 static void error_print_request(struct drm_i915_error_state_buf *m, 486 const char *prefix, 487 const struct i915_request_coredump *erq) 488 { 489 if (!erq->seqno) 490 return; 491 492 err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, head %08x, tail %08x\n", 493 prefix, erq->pid, erq->context, erq->seqno, 494 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, 495 &erq->flags) ? "!" : "", 496 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, 497 &erq->flags) ? "+" : "", 498 erq->sched_attr.priority, 499 erq->head, erq->tail); 500 } 501 502 static void error_print_context(struct drm_i915_error_state_buf *m, 503 const char *header, 504 const struct i915_gem_context_coredump *ctx) 505 { 506 err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n", 507 header, ctx->comm, ctx->pid, ctx->sched_attr.priority, 508 ctx->guilty, ctx->active, 509 ctx->total_runtime, ctx->avg_runtime); 510 err_printf(m, " context timeline seqno %u\n", ctx->hwsp_seqno); 511 } 512 513 static struct i915_vma_coredump * 514 __find_vma(struct i915_vma_coredump *vma, const char *name) 515 { 516 while (vma) { 517 if (strcmp(vma->name, name) == 0) 518 return vma; 519 vma = vma->next; 520 } 521 522 return NULL; 523 } 524 525 static struct i915_vma_coredump * 526 intel_gpu_error_find_batch(const struct intel_engine_coredump *ee) 527 { 528 return __find_vma(ee->vma, "batch"); 529 } 530 531 static void error_print_engine(struct drm_i915_error_state_buf *m, 532 const struct intel_engine_coredump *ee) 533 { 534 struct i915_vma_coredump *batch; 535 int n; 536 537 err_printf(m, "%s command stream:\n", ee->engine->name); 538 err_printf(m, " CCID: 0x%08x\n", ee->ccid); 539 err_printf(m, " START: 0x%08x\n", ee->start); 540 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head); 541 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n", 542 ee->tail, ee->rq_post, ee->rq_tail); 543 err_printf(m, " CTL: 0x%08x\n", ee->ctl); 544 err_printf(m, " MODE: 0x%08x\n", ee->mode); 545 err_printf(m, " HWS: 0x%08x\n", ee->hws); 546 err_printf(m, " ACTHD: 0x%08x %08x\n", 547 (u32)(ee->acthd>>32), (u32)ee->acthd); 548 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir); 549 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr); 550 err_printf(m, " ESR: 0x%08x\n", ee->esr); 551 552 error_print_instdone(m, ee); 553 554 batch = intel_gpu_error_find_batch(ee); 555 if (batch) { 556 u64 start = batch->gtt_offset; 557 u64 end = start + batch->gtt_size; 558 559 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n", 560 upper_32_bits(start), lower_32_bits(start), 561 upper_32_bits(end), lower_32_bits(end)); 562 } 563 if (GRAPHICS_VER(m->i915) >= 4) { 564 err_printf(m, " BBADDR: 0x%08x_%08x\n", 565 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr); 566 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate); 567 err_printf(m, " INSTPS: 0x%08x\n", ee->instps); 568 } 569 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm); 570 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr), 571 lower_32_bits(ee->faddr)); 572 if (GRAPHICS_VER(m->i915) >= 6) { 573 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi); 574 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg); 575 } 576 if (GRAPHICS_VER(m->i915) >= 11) { 577 err_printf(m, " NOPID: 0x%08x\n", ee->nopid); 578 err_printf(m, " EXCC: 0x%08x\n", ee->excc); 579 err_printf(m, " CMD_CCTL: 0x%08x\n", ee->cmd_cctl); 580 err_printf(m, " CSCMDOP: 0x%08x\n", ee->cscmdop); 581 err_printf(m, " CTX_SR_CTL: 0x%08x\n", ee->ctx_sr_ctl); 582 err_printf(m, " DMA_FADDR_HI: 0x%08x\n", ee->dma_faddr_hi); 583 err_printf(m, " DMA_FADDR_LO: 0x%08x\n", ee->dma_faddr_lo); 584 } 585 if (HAS_PPGTT(m->i915)) { 586 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode); 587 588 if (GRAPHICS_VER(m->i915) >= 8) { 589 int i; 590 for (i = 0; i < 4; i++) 591 err_printf(m, " PDP%d: 0x%016llx\n", 592 i, ee->vm_info.pdp[i]); 593 } else { 594 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 595 ee->vm_info.pp_dir_base); 596 } 597 } 598 599 for (n = 0; n < ee->num_ports; n++) { 600 err_printf(m, " ELSP[%d]:", n); 601 error_print_request(m, " ", &ee->execlist[n]); 602 } 603 } 604 605 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 606 { 607 va_list args; 608 609 va_start(args, f); 610 i915_error_vprintf(e, f, args); 611 va_end(args); 612 } 613 614 static void intel_gpu_error_print_vma(struct drm_i915_error_state_buf *m, 615 const struct intel_engine_cs *engine, 616 const struct i915_vma_coredump *vma) 617 { 618 char out[ASCII85_BUFSZ]; 619 struct page *page; 620 621 if (!vma) 622 return; 623 624 err_printf(m, "%s --- %s = 0x%08x %08x\n", 625 engine ? engine->name : "global", vma->name, 626 upper_32_bits(vma->gtt_offset), 627 lower_32_bits(vma->gtt_offset)); 628 629 if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K) 630 err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes); 631 632 err_compression_marker(m); 633 list_for_each_entry(page, &vma->page_list, lru) { 634 int i, len; 635 const u32 *addr = page_address(page); 636 637 len = PAGE_SIZE; 638 if (page == list_last_entry(&vma->page_list, typeof(*page), lru)) 639 len -= vma->unused; 640 len = ascii85_encode_len(len); 641 642 for (i = 0; i < len; i++) 643 err_puts(m, ascii85_encode(addr[i], out)); 644 } 645 err_puts(m, "\n"); 646 } 647 648 static void err_print_capabilities(struct drm_i915_error_state_buf *m, 649 struct i915_gpu_coredump *error) 650 { 651 struct drm_printer p = i915_error_printer(m); 652 653 intel_device_info_print(&error->device_info, &error->runtime_info, &p); 654 intel_display_device_info_print(&error->display_device_info, 655 &error->display_runtime_info, &p); 656 intel_driver_caps_print(&error->driver_caps, &p); 657 } 658 659 static void err_print_params(struct drm_i915_error_state_buf *m, 660 const struct i915_params *params) 661 { 662 struct drm_printer p = i915_error_printer(m); 663 664 i915_params_dump(params, &p); 665 intel_display_params_dump(m->i915, &p); 666 } 667 668 static void err_print_pciid(struct drm_i915_error_state_buf *m, 669 struct drm_i915_private *i915) 670 { 671 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 672 673 err_printf(m, "PCI ID: 0x%04x\n", pdev->device); 674 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision); 675 err_printf(m, "PCI Subsystem: %04x:%04x\n", 676 pdev->subsystem_vendor, 677 pdev->subsystem_device); 678 } 679 680 static void err_print_guc_ctb(struct drm_i915_error_state_buf *m, 681 const char *name, 682 const struct intel_ctb_coredump *ctb) 683 { 684 if (!ctb->size) 685 return; 686 687 err_printf(m, "GuC %s CTB: raw: 0x%08X, 0x%08X/%08X, cached: 0x%08X/%08X, desc = 0x%08X, buf = 0x%08X x 0x%08X\n", 688 name, ctb->raw_status, ctb->raw_head, ctb->raw_tail, 689 ctb->head, ctb->tail, ctb->desc_offset, ctb->cmds_offset, ctb->size); 690 } 691 692 static void err_print_uc(struct drm_i915_error_state_buf *m, 693 const struct intel_uc_coredump *error_uc) 694 { 695 struct drm_printer p = i915_error_printer(m); 696 697 intel_uc_fw_dump(&error_uc->guc_fw, &p); 698 intel_uc_fw_dump(&error_uc->huc_fw, &p); 699 err_printf(m, "GuC timestamp: 0x%08x\n", error_uc->guc.timestamp); 700 intel_gpu_error_print_vma(m, NULL, error_uc->guc.vma_log); 701 err_printf(m, "GuC CTB fence: %d\n", error_uc->guc.last_fence); 702 err_print_guc_ctb(m, "Send", error_uc->guc.ctb + 0); 703 err_print_guc_ctb(m, "Recv", error_uc->guc.ctb + 1); 704 intel_gpu_error_print_vma(m, NULL, error_uc->guc.vma_ctb); 705 } 706 707 static void err_free_sgl(struct scatterlist *sgl) 708 { 709 while (sgl) { 710 struct scatterlist *sg; 711 712 for (sg = sgl; !sg_is_chain(sg); sg++) { 713 kfree(sg_virt(sg)); 714 if (sg_is_last(sg)) 715 break; 716 } 717 718 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg); 719 free_page((unsigned long)sgl); 720 sgl = sg; 721 } 722 } 723 724 static void err_print_gt_info(struct drm_i915_error_state_buf *m, 725 struct intel_gt_coredump *gt) 726 { 727 struct drm_printer p = i915_error_printer(m); 728 729 intel_gt_info_print(>->info, &p); 730 intel_sseu_print_topology(gt->_gt->i915, >->info.sseu, &p); 731 } 732 733 static void err_print_gt_display(struct drm_i915_error_state_buf *m, 734 struct intel_gt_coredump *gt) 735 { 736 err_printf(m, "IER: 0x%08x\n", gt->ier); 737 err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr); 738 } 739 740 static void err_print_gt_global_nonguc(struct drm_i915_error_state_buf *m, 741 struct intel_gt_coredump *gt) 742 { 743 int i; 744 745 err_printf(m, "GT awake: %s\n", str_yes_no(gt->awake)); 746 err_printf(m, "CS timestamp frequency: %u Hz, %d ns\n", 747 gt->clock_frequency, gt->clock_period_ns); 748 err_printf(m, "EIR: 0x%08x\n", gt->eir); 749 err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er); 750 751 for (i = 0; i < gt->ngtier; i++) 752 err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]); 753 } 754 755 static void err_print_gt_global(struct drm_i915_error_state_buf *m, 756 struct intel_gt_coredump *gt) 757 { 758 err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake); 759 760 if (IS_GRAPHICS_VER(m->i915, 6, 11)) { 761 err_printf(m, "ERROR: 0x%08x\n", gt->error); 762 err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg); 763 } 764 765 if (GRAPHICS_VER(m->i915) >= 8) 766 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", 767 gt->fault_data1, gt->fault_data0); 768 769 if (GRAPHICS_VER(m->i915) == 7) 770 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int); 771 772 if (IS_GRAPHICS_VER(m->i915, 8, 11)) 773 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache); 774 775 if (GRAPHICS_VER(m->i915) == 12) 776 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err); 777 778 if (GRAPHICS_VER(m->i915) >= 12) { 779 int i; 780 781 for (i = 0; i < I915_MAX_SFC; i++) { 782 /* 783 * SFC_DONE resides in the VD forcewake domain, so it 784 * only exists if the corresponding VCS engine is 785 * present. 786 */ 787 if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || 788 !HAS_ENGINE(gt->_gt, _VCS(i * 2))) 789 continue; 790 791 err_printf(m, " SFC_DONE[%d]: 0x%08x\n", i, 792 gt->sfc_done[i]); 793 } 794 795 err_printf(m, " GAM_DONE: 0x%08x\n", gt->gam_done); 796 } 797 } 798 799 static void err_print_gt_fences(struct drm_i915_error_state_buf *m, 800 struct intel_gt_coredump *gt) 801 { 802 int i; 803 804 for (i = 0; i < gt->nfence; i++) 805 err_printf(m, " fence[%d] = %08llx\n", i, gt->fence[i]); 806 } 807 808 static void err_print_gt_engines(struct drm_i915_error_state_buf *m, 809 struct intel_gt_coredump *gt) 810 { 811 const struct intel_engine_coredump *ee; 812 813 for (ee = gt->engine; ee; ee = ee->next) { 814 const struct i915_vma_coredump *vma; 815 816 if (gt->uc && gt->uc->guc.is_guc_capture) { 817 if (ee->guc_capture_node) 818 intel_guc_capture_print_engine_node(m, ee); 819 else 820 err_printf(m, " Missing GuC capture node for %s\n", 821 ee->engine->name); 822 } else { 823 error_print_engine(m, ee); 824 } 825 826 err_printf(m, " hung: %u\n", ee->hung); 827 err_printf(m, " engine reset count: %u\n", ee->reset_count); 828 error_print_context(m, " Active context: ", &ee->context); 829 830 for (vma = ee->vma; vma; vma = vma->next) 831 intel_gpu_error_print_vma(m, ee->engine, vma); 832 } 833 834 } 835 836 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, 837 struct i915_gpu_coredump *error) 838 { 839 struct drm_printer p = i915_error_printer(m); 840 const struct intel_engine_coredump *ee; 841 struct timespec64 ts; 842 843 if (*error->error_msg) 844 err_printf(m, "%s\n", error->error_msg); 845 err_printf(m, "Kernel: %s %s\n", 846 init_utsname()->release, 847 init_utsname()->machine); 848 err_printf(m, "Driver: %s\n", DRIVER_DATE); 849 ts = ktime_to_timespec64(error->time); 850 err_printf(m, "Time: %lld s %ld us\n", 851 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 852 ts = ktime_to_timespec64(error->boottime); 853 err_printf(m, "Boottime: %lld s %ld us\n", 854 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 855 ts = ktime_to_timespec64(error->uptime); 856 err_printf(m, "Uptime: %lld s %ld us\n", 857 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 858 err_printf(m, "Capture: %lu jiffies; %d ms ago\n", 859 error->capture, jiffies_to_msecs(jiffies - error->capture)); 860 861 for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next) 862 err_printf(m, "Active process (on ring %s): %s [%d]\n", 863 ee->engine->name, 864 ee->context.comm, 865 ee->context.pid); 866 867 err_printf(m, "Reset count: %u\n", error->reset_count); 868 err_printf(m, "Suspend count: %u\n", error->suspend_count); 869 err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform)); 870 err_printf(m, "Subplatform: 0x%x\n", 871 intel_subplatform(&error->runtime_info, 872 error->device_info.platform)); 873 err_print_pciid(m, m->i915); 874 875 err_printf(m, "IOMMU enabled?: %d\n", error->iommu); 876 877 intel_dmc_print_error_state(&p, m->i915); 878 879 err_printf(m, "RPM wakelock: %s\n", str_yes_no(error->wakelock)); 880 err_printf(m, "PM suspended: %s\n", str_yes_no(error->suspended)); 881 882 if (error->gt) { 883 bool print_guc_capture = false; 884 885 if (error->gt->uc && error->gt->uc->guc.is_guc_capture) 886 print_guc_capture = true; 887 888 err_print_gt_display(m, error->gt); 889 err_print_gt_global_nonguc(m, error->gt); 890 err_print_gt_fences(m, error->gt); 891 892 /* 893 * GuC dumped global, eng-class and eng-instance registers together 894 * as part of engine state dump so we print in err_print_gt_engines 895 */ 896 if (!print_guc_capture) 897 err_print_gt_global(m, error->gt); 898 899 err_print_gt_engines(m, error->gt); 900 901 if (error->gt->uc) 902 err_print_uc(m, error->gt->uc); 903 904 err_print_gt_info(m, error->gt); 905 } 906 907 if (error->overlay) 908 intel_overlay_print_error_state(&p, error->overlay); 909 910 err_print_capabilities(m, error); 911 err_print_params(m, &error->params); 912 } 913 914 static int err_print_to_sgl(struct i915_gpu_coredump *error) 915 { 916 struct drm_i915_error_state_buf m; 917 918 if (IS_ERR(error)) 919 return PTR_ERR(error); 920 921 if (READ_ONCE(error->sgl)) 922 return 0; 923 924 memset(&m, 0, sizeof(m)); 925 m.i915 = error->i915; 926 927 __err_print_to_sgl(&m, error); 928 929 if (m.buf) { 930 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter); 931 m.bytes = 0; 932 m.buf = NULL; 933 } 934 if (m.cur) { 935 GEM_BUG_ON(m.end < m.cur); 936 sg_mark_end(m.cur - 1); 937 } 938 GEM_BUG_ON(m.sgl && !m.cur); 939 940 if (m.err) { 941 err_free_sgl(m.sgl); 942 return m.err; 943 } 944 945 if (cmpxchg(&error->sgl, NULL, m.sgl)) 946 err_free_sgl(m.sgl); 947 948 return 0; 949 } 950 951 ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error, 952 char *buf, loff_t off, size_t rem) 953 { 954 struct scatterlist *sg; 955 size_t count; 956 loff_t pos; 957 int err; 958 959 if (!error || !rem) 960 return 0; 961 962 err = err_print_to_sgl(error); 963 if (err) 964 return err; 965 966 sg = READ_ONCE(error->fit); 967 if (!sg || off < sg->dma_address) 968 sg = error->sgl; 969 if (!sg) 970 return 0; 971 972 pos = sg->dma_address; 973 count = 0; 974 do { 975 size_t len, start; 976 977 if (sg_is_chain(sg)) { 978 sg = sg_chain_ptr(sg); 979 GEM_BUG_ON(sg_is_chain(sg)); 980 } 981 982 len = sg->length; 983 if (pos + len <= off) { 984 pos += len; 985 continue; 986 } 987 988 start = sg->offset; 989 if (pos < off) { 990 GEM_BUG_ON(off - pos > len); 991 len -= off - pos; 992 start += off - pos; 993 pos = off; 994 } 995 996 len = min(len, rem); 997 GEM_BUG_ON(!len || len > sg->length); 998 999 memcpy(buf, page_address(sg_page(sg)) + start, len); 1000 1001 count += len; 1002 pos += len; 1003 1004 buf += len; 1005 rem -= len; 1006 if (!rem) { 1007 WRITE_ONCE(error->fit, sg); 1008 break; 1009 } 1010 } while (!sg_is_last(sg++)); 1011 1012 return count; 1013 } 1014 1015 static void i915_vma_coredump_free(struct i915_vma_coredump *vma) 1016 { 1017 while (vma) { 1018 struct i915_vma_coredump *next = vma->next; 1019 struct page *page, *n; 1020 1021 list_for_each_entry_safe(page, n, &vma->page_list, lru) { 1022 list_del_init(&page->lru); 1023 __free_page(page); 1024 } 1025 1026 kfree(vma); 1027 vma = next; 1028 } 1029 } 1030 1031 static void cleanup_params(struct i915_gpu_coredump *error) 1032 { 1033 i915_params_free(&error->params); 1034 intel_display_params_free(&error->display_params); 1035 } 1036 1037 static void cleanup_uc(struct intel_uc_coredump *uc) 1038 { 1039 kfree(uc->guc_fw.file_selected.path); 1040 kfree(uc->huc_fw.file_selected.path); 1041 kfree(uc->guc_fw.file_wanted.path); 1042 kfree(uc->huc_fw.file_wanted.path); 1043 i915_vma_coredump_free(uc->guc.vma_log); 1044 i915_vma_coredump_free(uc->guc.vma_ctb); 1045 1046 kfree(uc); 1047 } 1048 1049 static void cleanup_gt(struct intel_gt_coredump *gt) 1050 { 1051 while (gt->engine) { 1052 struct intel_engine_coredump *ee = gt->engine; 1053 1054 gt->engine = ee->next; 1055 1056 i915_vma_coredump_free(ee->vma); 1057 intel_guc_capture_free_node(ee); 1058 kfree(ee); 1059 } 1060 1061 if (gt->uc) 1062 cleanup_uc(gt->uc); 1063 1064 kfree(gt); 1065 } 1066 1067 void __i915_gpu_coredump_free(struct kref *error_ref) 1068 { 1069 struct i915_gpu_coredump *error = 1070 container_of(error_ref, typeof(*error), ref); 1071 1072 while (error->gt) { 1073 struct intel_gt_coredump *gt = error->gt; 1074 1075 error->gt = gt->next; 1076 cleanup_gt(gt); 1077 } 1078 1079 kfree(error->overlay); 1080 1081 cleanup_params(error); 1082 1083 err_free_sgl(error->sgl); 1084 kfree(error); 1085 } 1086 1087 static struct i915_vma_coredump * 1088 i915_vma_coredump_create(const struct intel_gt *gt, 1089 const struct i915_vma_resource *vma_res, 1090 struct i915_vma_compress *compress, 1091 const char *name) 1092 1093 { 1094 struct i915_ggtt *ggtt = gt->ggtt; 1095 const u64 slot = ggtt->error_capture.start; 1096 struct i915_vma_coredump *dst; 1097 struct sgt_iter iter; 1098 int ret; 1099 1100 might_sleep(); 1101 1102 if (!vma_res || !vma_res->bi.pages || !compress) 1103 return NULL; 1104 1105 dst = kmalloc(sizeof(*dst), ALLOW_FAIL); 1106 if (!dst) 1107 return NULL; 1108 1109 if (!compress_start(compress)) { 1110 kfree(dst); 1111 return NULL; 1112 } 1113 1114 INIT_LIST_HEAD(&dst->page_list); 1115 strcpy(dst->name, name); 1116 dst->next = NULL; 1117 1118 dst->gtt_offset = vma_res->start; 1119 dst->gtt_size = vma_res->node_size; 1120 dst->gtt_page_sizes = vma_res->page_sizes_gtt; 1121 dst->unused = 0; 1122 1123 ret = -EINVAL; 1124 if (drm_mm_node_allocated(&ggtt->error_capture)) { 1125 void __iomem *s; 1126 dma_addr_t dma; 1127 1128 for_each_sgt_daddr(dma, iter, vma_res->bi.pages) { 1129 mutex_lock(&ggtt->error_mutex); 1130 if (ggtt->vm.raw_insert_page) 1131 ggtt->vm.raw_insert_page(&ggtt->vm, dma, slot, 1132 i915_gem_get_pat_index(gt->i915, 1133 I915_CACHE_NONE), 1134 0); 1135 else 1136 ggtt->vm.insert_page(&ggtt->vm, dma, slot, 1137 i915_gem_get_pat_index(gt->i915, 1138 I915_CACHE_NONE), 1139 0); 1140 mb(); 1141 1142 s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE); 1143 ret = compress_page(compress, 1144 (void __force *)s, dst, 1145 true); 1146 io_mapping_unmap(s); 1147 1148 mb(); 1149 ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE); 1150 mutex_unlock(&ggtt->error_mutex); 1151 if (ret) 1152 break; 1153 } 1154 } else if (vma_res->bi.lmem) { 1155 struct intel_memory_region *mem = vma_res->mr; 1156 dma_addr_t dma; 1157 1158 for_each_sgt_daddr(dma, iter, vma_res->bi.pages) { 1159 dma_addr_t offset = dma - mem->region.start; 1160 void __iomem *s; 1161 1162 if (offset + PAGE_SIZE > resource_size(&mem->io)) { 1163 ret = -EINVAL; 1164 break; 1165 } 1166 1167 s = io_mapping_map_wc(&mem->iomap, offset, PAGE_SIZE); 1168 ret = compress_page(compress, 1169 (void __force *)s, dst, 1170 true); 1171 io_mapping_unmap(s); 1172 if (ret) 1173 break; 1174 } 1175 } else { 1176 struct page *page; 1177 1178 for_each_sgt_page(page, iter, vma_res->bi.pages) { 1179 void *s; 1180 1181 drm_clflush_pages(&page, 1); 1182 1183 s = kmap_local_page(page); 1184 ret = compress_page(compress, s, dst, false); 1185 kunmap_local(s); 1186 1187 drm_clflush_pages(&page, 1); 1188 1189 if (ret) 1190 break; 1191 } 1192 } 1193 1194 if (ret || compress_flush(compress, dst)) { 1195 struct page *page, *n; 1196 1197 list_for_each_entry_safe_reverse(page, n, &dst->page_list, lru) { 1198 list_del_init(&page->lru); 1199 pool_free(&compress->pool, page_address(page)); 1200 } 1201 1202 kfree(dst); 1203 dst = NULL; 1204 } 1205 compress_finish(compress); 1206 1207 return dst; 1208 } 1209 1210 static void gt_record_fences(struct intel_gt_coredump *gt) 1211 { 1212 struct i915_ggtt *ggtt = gt->_gt->ggtt; 1213 struct intel_uncore *uncore = gt->_gt->uncore; 1214 int i; 1215 1216 if (GRAPHICS_VER(uncore->i915) >= 6) { 1217 for (i = 0; i < ggtt->num_fences; i++) 1218 gt->fence[i] = 1219 intel_uncore_read64(uncore, 1220 FENCE_REG_GEN6_LO(i)); 1221 } else if (GRAPHICS_VER(uncore->i915) >= 4) { 1222 for (i = 0; i < ggtt->num_fences; i++) 1223 gt->fence[i] = 1224 intel_uncore_read64(uncore, 1225 FENCE_REG_965_LO(i)); 1226 } else { 1227 for (i = 0; i < ggtt->num_fences; i++) 1228 gt->fence[i] = 1229 intel_uncore_read(uncore, FENCE_REG(i)); 1230 } 1231 gt->nfence = i; 1232 } 1233 1234 static void engine_record_registers(struct intel_engine_coredump *ee) 1235 { 1236 const struct intel_engine_cs *engine = ee->engine; 1237 struct drm_i915_private *i915 = engine->i915; 1238 1239 if (GRAPHICS_VER(i915) >= 6) { 1240 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL); 1241 1242 /* 1243 * For the media GT, this ring fault register is not replicated, 1244 * so don't do multicast/replicated register read/write 1245 * operation on it. 1246 */ 1247 if (MEDIA_VER(i915) >= 13 && engine->gt->type == GT_MEDIA) 1248 ee->fault_reg = intel_uncore_read(engine->uncore, 1249 XELPMP_RING_FAULT_REG); 1250 else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) 1251 ee->fault_reg = intel_gt_mcr_read_any(engine->gt, 1252 XEHP_RING_FAULT_REG); 1253 else if (GRAPHICS_VER(i915) >= 12) 1254 ee->fault_reg = intel_uncore_read(engine->uncore, 1255 GEN12_RING_FAULT_REG); 1256 else if (GRAPHICS_VER(i915) >= 8) 1257 ee->fault_reg = intel_uncore_read(engine->uncore, 1258 GEN8_RING_FAULT_REG); 1259 else 1260 ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine); 1261 } 1262 1263 if (GRAPHICS_VER(i915) >= 4) { 1264 ee->esr = ENGINE_READ(engine, RING_ESR); 1265 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD); 1266 ee->ipeir = ENGINE_READ(engine, RING_IPEIR); 1267 ee->ipehr = ENGINE_READ(engine, RING_IPEHR); 1268 ee->instps = ENGINE_READ(engine, RING_INSTPS); 1269 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR); 1270 ee->ccid = ENGINE_READ(engine, CCID); 1271 if (GRAPHICS_VER(i915) >= 8) { 1272 ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32; 1273 ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32; 1274 } 1275 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE); 1276 } else { 1277 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX); 1278 ee->ipeir = ENGINE_READ(engine, IPEIR); 1279 ee->ipehr = ENGINE_READ(engine, IPEHR); 1280 } 1281 1282 if (GRAPHICS_VER(i915) >= 11) { 1283 ee->cmd_cctl = ENGINE_READ(engine, RING_CMD_CCTL); 1284 ee->cscmdop = ENGINE_READ(engine, RING_CSCMDOP); 1285 ee->ctx_sr_ctl = ENGINE_READ(engine, RING_CTX_SR_CTL); 1286 ee->dma_faddr_hi = ENGINE_READ(engine, RING_DMA_FADD_UDW); 1287 ee->dma_faddr_lo = ENGINE_READ(engine, RING_DMA_FADD); 1288 ee->nopid = ENGINE_READ(engine, RING_NOPID); 1289 ee->excc = ENGINE_READ(engine, RING_EXCC); 1290 } 1291 1292 intel_engine_get_instdone(engine, &ee->instdone); 1293 1294 ee->instpm = ENGINE_READ(engine, RING_INSTPM); 1295 ee->acthd = intel_engine_get_active_head(engine); 1296 ee->start = ENGINE_READ(engine, RING_START); 1297 ee->head = ENGINE_READ(engine, RING_HEAD); 1298 ee->tail = ENGINE_READ(engine, RING_TAIL); 1299 ee->ctl = ENGINE_READ(engine, RING_CTL); 1300 if (GRAPHICS_VER(i915) > 2) 1301 ee->mode = ENGINE_READ(engine, RING_MI_MODE); 1302 1303 if (!HWS_NEEDS_PHYSICAL(i915)) { 1304 i915_reg_t mmio; 1305 1306 if (GRAPHICS_VER(i915) == 7) { 1307 switch (engine->id) { 1308 default: 1309 MISSING_CASE(engine->id); 1310 fallthrough; 1311 case RCS0: 1312 mmio = RENDER_HWS_PGA_GEN7; 1313 break; 1314 case BCS0: 1315 mmio = BLT_HWS_PGA_GEN7; 1316 break; 1317 case VCS0: 1318 mmio = BSD_HWS_PGA_GEN7; 1319 break; 1320 case VECS0: 1321 mmio = VEBOX_HWS_PGA_GEN7; 1322 break; 1323 } 1324 } else if (GRAPHICS_VER(engine->i915) == 6) { 1325 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); 1326 } else { 1327 /* XXX: gen8 returns to sanity */ 1328 mmio = RING_HWS_PGA(engine->mmio_base); 1329 } 1330 1331 ee->hws = intel_uncore_read(engine->uncore, mmio); 1332 } 1333 1334 ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine); 1335 1336 if (HAS_PPGTT(i915)) { 1337 int i; 1338 1339 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7); 1340 1341 if (GRAPHICS_VER(i915) == 6) { 1342 ee->vm_info.pp_dir_base = 1343 ENGINE_READ(engine, RING_PP_DIR_BASE_READ); 1344 } else if (GRAPHICS_VER(i915) == 7) { 1345 ee->vm_info.pp_dir_base = 1346 ENGINE_READ(engine, RING_PP_DIR_BASE); 1347 } else if (GRAPHICS_VER(i915) >= 8) { 1348 u32 base = engine->mmio_base; 1349 1350 for (i = 0; i < 4; i++) { 1351 ee->vm_info.pdp[i] = 1352 intel_uncore_read(engine->uncore, 1353 GEN8_RING_PDP_UDW(base, i)); 1354 ee->vm_info.pdp[i] <<= 32; 1355 ee->vm_info.pdp[i] |= 1356 intel_uncore_read(engine->uncore, 1357 GEN8_RING_PDP_LDW(base, i)); 1358 } 1359 } 1360 } 1361 } 1362 1363 static void record_request(const struct i915_request *request, 1364 struct i915_request_coredump *erq) 1365 { 1366 erq->flags = request->fence.flags; 1367 erq->context = request->fence.context; 1368 erq->seqno = request->fence.seqno; 1369 erq->sched_attr = request->sched.attr; 1370 erq->head = request->head; 1371 erq->tail = request->tail; 1372 1373 erq->pid = 0; 1374 rcu_read_lock(); 1375 if (!intel_context_is_closed(request->context)) { 1376 const struct i915_gem_context *ctx; 1377 1378 ctx = rcu_dereference(request->context->gem_context); 1379 if (ctx) 1380 erq->pid = pid_nr(ctx->pid); 1381 } 1382 rcu_read_unlock(); 1383 } 1384 1385 static void engine_record_execlists(struct intel_engine_coredump *ee) 1386 { 1387 const struct intel_engine_execlists * const el = &ee->engine->execlists; 1388 struct i915_request * const *port = el->active; 1389 unsigned int n = 0; 1390 1391 while (*port) 1392 record_request(*port++, &ee->execlist[n++]); 1393 1394 ee->num_ports = n; 1395 } 1396 1397 static bool record_context(struct i915_gem_context_coredump *e, 1398 struct intel_context *ce) 1399 { 1400 struct i915_gem_context *ctx; 1401 struct task_struct *task; 1402 bool simulated; 1403 1404 rcu_read_lock(); 1405 ctx = rcu_dereference(ce->gem_context); 1406 if (ctx && !kref_get_unless_zero(&ctx->ref)) 1407 ctx = NULL; 1408 rcu_read_unlock(); 1409 if (!ctx) 1410 return true; 1411 1412 rcu_read_lock(); 1413 task = pid_task(ctx->pid, PIDTYPE_PID); 1414 if (task) { 1415 strcpy(e->comm, task->comm); 1416 e->pid = task->pid; 1417 } 1418 rcu_read_unlock(); 1419 1420 e->sched_attr = ctx->sched; 1421 e->guilty = atomic_read(&ctx->guilty_count); 1422 e->active = atomic_read(&ctx->active_count); 1423 e->hwsp_seqno = (ce->timeline && ce->timeline->hwsp_seqno) ? 1424 *ce->timeline->hwsp_seqno : ~0U; 1425 1426 e->total_runtime = intel_context_get_total_runtime_ns(ce); 1427 e->avg_runtime = intel_context_get_avg_runtime_ns(ce); 1428 1429 simulated = i915_gem_context_no_error_capture(ctx); 1430 1431 i915_gem_context_put(ctx); 1432 return simulated; 1433 } 1434 1435 struct intel_engine_capture_vma { 1436 struct intel_engine_capture_vma *next; 1437 struct i915_vma_resource *vma_res; 1438 char name[16]; 1439 bool lockdep_cookie; 1440 }; 1441 1442 static struct intel_engine_capture_vma * 1443 capture_vma_snapshot(struct intel_engine_capture_vma *next, 1444 struct i915_vma_resource *vma_res, 1445 gfp_t gfp, const char *name) 1446 { 1447 struct intel_engine_capture_vma *c; 1448 1449 if (!vma_res) 1450 return next; 1451 1452 c = kmalloc(sizeof(*c), gfp); 1453 if (!c) 1454 return next; 1455 1456 if (!i915_vma_resource_hold(vma_res, &c->lockdep_cookie)) { 1457 kfree(c); 1458 return next; 1459 } 1460 1461 strcpy(c->name, name); 1462 c->vma_res = i915_vma_resource_get(vma_res); 1463 1464 c->next = next; 1465 return c; 1466 } 1467 1468 static struct intel_engine_capture_vma * 1469 capture_vma(struct intel_engine_capture_vma *next, 1470 struct i915_vma *vma, 1471 const char *name, 1472 gfp_t gfp) 1473 { 1474 if (!vma) 1475 return next; 1476 1477 /* 1478 * If the vma isn't pinned, then the vma should be snapshotted 1479 * to a struct i915_vma_snapshot at command submission time. 1480 * Not here. 1481 */ 1482 if (GEM_WARN_ON(!i915_vma_is_pinned(vma))) 1483 return next; 1484 1485 next = capture_vma_snapshot(next, vma->resource, gfp, name); 1486 1487 return next; 1488 } 1489 1490 static struct intel_engine_capture_vma * 1491 capture_user(struct intel_engine_capture_vma *capture, 1492 const struct i915_request *rq, 1493 gfp_t gfp) 1494 { 1495 struct i915_capture_list *c; 1496 1497 for (c = rq->capture_list; c; c = c->next) 1498 capture = capture_vma_snapshot(capture, c->vma_res, gfp, 1499 "user"); 1500 1501 return capture; 1502 } 1503 1504 static void add_vma(struct intel_engine_coredump *ee, 1505 struct i915_vma_coredump *vma) 1506 { 1507 if (vma) { 1508 vma->next = ee->vma; 1509 ee->vma = vma; 1510 } 1511 } 1512 1513 static struct i915_vma_coredump * 1514 create_vma_coredump(const struct intel_gt *gt, struct i915_vma *vma, 1515 const char *name, struct i915_vma_compress *compress) 1516 { 1517 struct i915_vma_coredump *ret = NULL; 1518 struct i915_vma_resource *vma_res; 1519 bool lockdep_cookie; 1520 1521 if (!vma) 1522 return NULL; 1523 1524 vma_res = vma->resource; 1525 1526 if (i915_vma_resource_hold(vma_res, &lockdep_cookie)) { 1527 ret = i915_vma_coredump_create(gt, vma_res, compress, name); 1528 i915_vma_resource_unhold(vma_res, lockdep_cookie); 1529 } 1530 1531 return ret; 1532 } 1533 1534 static void add_vma_coredump(struct intel_engine_coredump *ee, 1535 const struct intel_gt *gt, 1536 struct i915_vma *vma, 1537 const char *name, 1538 struct i915_vma_compress *compress) 1539 { 1540 add_vma(ee, create_vma_coredump(gt, vma, name, compress)); 1541 } 1542 1543 struct intel_engine_coredump * 1544 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags) 1545 { 1546 struct intel_engine_coredump *ee; 1547 1548 ee = kzalloc(sizeof(*ee), gfp); 1549 if (!ee) 1550 return NULL; 1551 1552 ee->engine = engine; 1553 1554 if (!(dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)) { 1555 engine_record_registers(ee); 1556 engine_record_execlists(ee); 1557 } 1558 1559 return ee; 1560 } 1561 1562 static struct intel_engine_capture_vma * 1563 engine_coredump_add_context(struct intel_engine_coredump *ee, 1564 struct intel_context *ce, 1565 gfp_t gfp) 1566 { 1567 struct intel_engine_capture_vma *vma = NULL; 1568 1569 ee->simulated |= record_context(&ee->context, ce); 1570 if (ee->simulated) 1571 return NULL; 1572 1573 /* 1574 * We need to copy these to an anonymous buffer 1575 * as the simplest method to avoid being overwritten 1576 * by userspace. 1577 */ 1578 vma = capture_vma(vma, ce->ring->vma, "ring", gfp); 1579 vma = capture_vma(vma, ce->state, "HW context", gfp); 1580 1581 return vma; 1582 } 1583 1584 struct intel_engine_capture_vma * 1585 intel_engine_coredump_add_request(struct intel_engine_coredump *ee, 1586 struct i915_request *rq, 1587 gfp_t gfp) 1588 { 1589 struct intel_engine_capture_vma *vma; 1590 1591 vma = engine_coredump_add_context(ee, rq->context, gfp); 1592 if (!vma) 1593 return NULL; 1594 1595 /* 1596 * We need to copy these to an anonymous buffer 1597 * as the simplest method to avoid being overwritten 1598 * by userspace. 1599 */ 1600 vma = capture_vma_snapshot(vma, rq->batch_res, gfp, "batch"); 1601 vma = capture_user(vma, rq, gfp); 1602 1603 ee->rq_head = rq->head; 1604 ee->rq_post = rq->postfix; 1605 ee->rq_tail = rq->tail; 1606 1607 return vma; 1608 } 1609 1610 void 1611 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee, 1612 struct intel_engine_capture_vma *capture, 1613 struct i915_vma_compress *compress) 1614 { 1615 const struct intel_engine_cs *engine = ee->engine; 1616 1617 while (capture) { 1618 struct intel_engine_capture_vma *this = capture; 1619 struct i915_vma_resource *vma_res = this->vma_res; 1620 1621 add_vma(ee, 1622 i915_vma_coredump_create(engine->gt, vma_res, 1623 compress, this->name)); 1624 1625 i915_vma_resource_unhold(vma_res, this->lockdep_cookie); 1626 i915_vma_resource_put(vma_res); 1627 1628 capture = this->next; 1629 kfree(this); 1630 } 1631 1632 add_vma_coredump(ee, engine->gt, engine->status_page.vma, 1633 "HW Status", compress); 1634 1635 add_vma_coredump(ee, engine->gt, engine->wa_ctx.vma, 1636 "WA context", compress); 1637 } 1638 1639 static struct intel_engine_coredump * 1640 capture_engine(struct intel_engine_cs *engine, 1641 struct i915_vma_compress *compress, 1642 u32 dump_flags) 1643 { 1644 struct intel_engine_capture_vma *capture = NULL; 1645 struct intel_engine_coredump *ee; 1646 struct intel_context *ce = NULL; 1647 struct i915_request *rq = NULL; 1648 1649 ee = intel_engine_coredump_alloc(engine, ALLOW_FAIL, dump_flags); 1650 if (!ee) 1651 return NULL; 1652 1653 intel_engine_get_hung_entity(engine, &ce, &rq); 1654 if (rq && !i915_request_started(rq)) 1655 drm_info(&engine->gt->i915->drm, "Got hung context on %s with active request %lld:%lld [0x%04X] not yet started\n", 1656 engine->name, rq->fence.context, rq->fence.seqno, ce->guc_id.id); 1657 1658 if (rq) { 1659 capture = intel_engine_coredump_add_request(ee, rq, ATOMIC_MAYFAIL); 1660 i915_request_put(rq); 1661 } else if (ce) { 1662 capture = engine_coredump_add_context(ee, ce, ATOMIC_MAYFAIL); 1663 } 1664 1665 if (capture) { 1666 intel_engine_coredump_add_vma(ee, capture, compress); 1667 1668 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE) 1669 intel_guc_capture_get_matching_node(engine->gt, ee, ce); 1670 } else { 1671 kfree(ee); 1672 ee = NULL; 1673 } 1674 1675 return ee; 1676 } 1677 1678 static void 1679 gt_record_engines(struct intel_gt_coredump *gt, 1680 intel_engine_mask_t engine_mask, 1681 struct i915_vma_compress *compress, 1682 u32 dump_flags) 1683 { 1684 struct intel_engine_cs *engine; 1685 enum intel_engine_id id; 1686 1687 for_each_engine(engine, gt->_gt, id) { 1688 struct intel_engine_coredump *ee; 1689 1690 /* Refill our page pool before entering atomic section */ 1691 pool_refill(&compress->pool, ALLOW_FAIL); 1692 1693 ee = capture_engine(engine, compress, dump_flags); 1694 if (!ee) 1695 continue; 1696 1697 ee->hung = engine->mask & engine_mask; 1698 1699 gt->simulated |= ee->simulated; 1700 if (ee->simulated) { 1701 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE) 1702 intel_guc_capture_free_node(ee); 1703 kfree(ee); 1704 continue; 1705 } 1706 1707 ee->next = gt->engine; 1708 gt->engine = ee; 1709 } 1710 } 1711 1712 static void gt_record_guc_ctb(struct intel_ctb_coredump *saved, 1713 const struct intel_guc_ct_buffer *ctb, 1714 const void *blob_ptr, struct intel_guc *guc) 1715 { 1716 if (!ctb || !ctb->desc) 1717 return; 1718 1719 saved->raw_status = ctb->desc->status; 1720 saved->raw_head = ctb->desc->head; 1721 saved->raw_tail = ctb->desc->tail; 1722 saved->head = ctb->head; 1723 saved->tail = ctb->tail; 1724 saved->size = ctb->size; 1725 saved->desc_offset = ((void *)ctb->desc) - blob_ptr; 1726 saved->cmds_offset = ((void *)ctb->cmds) - blob_ptr; 1727 } 1728 1729 static struct intel_uc_coredump * 1730 gt_record_uc(struct intel_gt_coredump *gt, 1731 struct i915_vma_compress *compress) 1732 { 1733 const struct intel_uc *uc = >->_gt->uc; 1734 struct intel_uc_coredump *error_uc; 1735 1736 error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL); 1737 if (!error_uc) 1738 return NULL; 1739 1740 memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw)); 1741 memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw)); 1742 1743 error_uc->guc_fw.file_selected.path = kstrdup(uc->guc.fw.file_selected.path, ALLOW_FAIL); 1744 error_uc->huc_fw.file_selected.path = kstrdup(uc->huc.fw.file_selected.path, ALLOW_FAIL); 1745 error_uc->guc_fw.file_wanted.path = kstrdup(uc->guc.fw.file_wanted.path, ALLOW_FAIL); 1746 error_uc->huc_fw.file_wanted.path = kstrdup(uc->huc.fw.file_wanted.path, ALLOW_FAIL); 1747 1748 /* 1749 * Save the GuC log and include a timestamp reference for converting the 1750 * log times to system times (in conjunction with the error->boottime and 1751 * gt->clock_frequency fields saved elsewhere). 1752 */ 1753 error_uc->guc.timestamp = intel_uncore_read(gt->_gt->uncore, GUCPMTIMESTAMP); 1754 error_uc->guc.vma_log = create_vma_coredump(gt->_gt, uc->guc.log.vma, 1755 "GuC log buffer", compress); 1756 error_uc->guc.vma_ctb = create_vma_coredump(gt->_gt, uc->guc.ct.vma, 1757 "GuC CT buffer", compress); 1758 error_uc->guc.last_fence = uc->guc.ct.requests.last_fence; 1759 gt_record_guc_ctb(error_uc->guc.ctb + 0, &uc->guc.ct.ctbs.send, 1760 uc->guc.ct.ctbs.send.desc, (struct intel_guc *)&uc->guc); 1761 gt_record_guc_ctb(error_uc->guc.ctb + 1, &uc->guc.ct.ctbs.recv, 1762 uc->guc.ct.ctbs.send.desc, (struct intel_guc *)&uc->guc); 1763 1764 return error_uc; 1765 } 1766 1767 /* Capture display registers. */ 1768 static void gt_record_display_regs(struct intel_gt_coredump *gt) 1769 { 1770 struct intel_uncore *uncore = gt->_gt->uncore; 1771 struct drm_i915_private *i915 = uncore->i915; 1772 1773 if (DISPLAY_VER(i915) >= 6 && DISPLAY_VER(i915) < 20) 1774 gt->derrmr = intel_uncore_read(uncore, DERRMR); 1775 1776 if (GRAPHICS_VER(i915) >= 8) 1777 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); 1778 else if (IS_VALLEYVIEW(i915)) 1779 gt->ier = intel_uncore_read(uncore, VLV_IER); 1780 else if (HAS_PCH_SPLIT(i915)) 1781 gt->ier = intel_uncore_read(uncore, DEIER); 1782 else if (GRAPHICS_VER(i915) == 2) 1783 gt->ier = intel_uncore_read16(uncore, GEN2_IER); 1784 else 1785 gt->ier = intel_uncore_read(uncore, GEN2_IER); 1786 } 1787 1788 /* Capture all other registers that GuC doesn't capture. */ 1789 static void gt_record_global_nonguc_regs(struct intel_gt_coredump *gt) 1790 { 1791 struct intel_uncore *uncore = gt->_gt->uncore; 1792 struct drm_i915_private *i915 = uncore->i915; 1793 int i; 1794 1795 if (IS_VALLEYVIEW(i915)) { 1796 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1797 gt->ngtier = 1; 1798 } else if (GRAPHICS_VER(i915) >= 11) { 1799 gt->gtier[0] = 1800 intel_uncore_read(uncore, 1801 GEN11_RENDER_COPY_INTR_ENABLE); 1802 gt->gtier[1] = 1803 intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE); 1804 gt->gtier[2] = 1805 intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE); 1806 gt->gtier[3] = 1807 intel_uncore_read(uncore, 1808 GEN11_GPM_WGBOXPERF_INTR_ENABLE); 1809 gt->gtier[4] = 1810 intel_uncore_read(uncore, 1811 GEN11_CRYPTO_RSVD_INTR_ENABLE); 1812 gt->gtier[5] = 1813 intel_uncore_read(uncore, 1814 GEN11_GUNIT_CSME_INTR_ENABLE); 1815 gt->ngtier = 6; 1816 } else if (GRAPHICS_VER(i915) >= 8) { 1817 for (i = 0; i < 4; i++) 1818 gt->gtier[i] = 1819 intel_uncore_read(uncore, GEN8_GT_IER(i)); 1820 gt->ngtier = 4; 1821 } else if (HAS_PCH_SPLIT(i915)) { 1822 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1823 gt->ngtier = 1; 1824 } 1825 1826 gt->eir = intel_uncore_read(uncore, EIR); 1827 gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER); 1828 } 1829 1830 /* 1831 * Capture all registers that relate to workload submission. 1832 * NOTE: In GuC submission, when GuC resets an engine, it can dump these for us 1833 */ 1834 static void gt_record_global_regs(struct intel_gt_coredump *gt) 1835 { 1836 struct intel_uncore *uncore = gt->_gt->uncore; 1837 struct drm_i915_private *i915 = uncore->i915; 1838 int i; 1839 1840 /* 1841 * General organization 1842 * 1. Registers specific to a single generation 1843 * 2. Registers which belong to multiple generations 1844 * 3. Feature specific registers. 1845 * 4. Everything else 1846 * Please try to follow the order. 1847 */ 1848 1849 /* 1: Registers specific to a single generation */ 1850 if (IS_VALLEYVIEW(i915)) 1851 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV); 1852 1853 if (GRAPHICS_VER(i915) == 7) 1854 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT); 1855 1856 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) { 1857 gt->fault_data0 = intel_gt_mcr_read_any((struct intel_gt *)gt->_gt, 1858 XEHP_FAULT_TLB_DATA0); 1859 gt->fault_data1 = intel_gt_mcr_read_any((struct intel_gt *)gt->_gt, 1860 XEHP_FAULT_TLB_DATA1); 1861 } else if (GRAPHICS_VER(i915) >= 12) { 1862 gt->fault_data0 = intel_uncore_read(uncore, 1863 GEN12_FAULT_TLB_DATA0); 1864 gt->fault_data1 = intel_uncore_read(uncore, 1865 GEN12_FAULT_TLB_DATA1); 1866 } else if (GRAPHICS_VER(i915) >= 8) { 1867 gt->fault_data0 = intel_uncore_read(uncore, 1868 GEN8_FAULT_TLB_DATA0); 1869 gt->fault_data1 = intel_uncore_read(uncore, 1870 GEN8_FAULT_TLB_DATA1); 1871 } 1872 1873 if (GRAPHICS_VER(i915) == 6) { 1874 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE); 1875 gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL); 1876 gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE); 1877 } 1878 1879 /* 2: Registers which belong to multiple generations */ 1880 if (GRAPHICS_VER(i915) >= 7) 1881 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT); 1882 1883 if (GRAPHICS_VER(i915) >= 6) { 1884 if (GRAPHICS_VER(i915) < 12) { 1885 gt->error = intel_uncore_read(uncore, ERROR_GEN6); 1886 gt->done_reg = intel_uncore_read(uncore, DONE_REG); 1887 } 1888 } 1889 1890 /* 3: Feature specific registers */ 1891 if (IS_GRAPHICS_VER(i915, 6, 7)) { 1892 gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK); 1893 gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS); 1894 } 1895 1896 if (IS_GRAPHICS_VER(i915, 8, 11)) 1897 gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN); 1898 1899 if (GRAPHICS_VER(i915) == 12) 1900 gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG); 1901 1902 if (GRAPHICS_VER(i915) >= 12) { 1903 for (i = 0; i < I915_MAX_SFC; i++) { 1904 /* 1905 * SFC_DONE resides in the VD forcewake domain, so it 1906 * only exists if the corresponding VCS engine is 1907 * present. 1908 */ 1909 if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || 1910 !HAS_ENGINE(gt->_gt, _VCS(i * 2))) 1911 continue; 1912 1913 gt->sfc_done[i] = 1914 intel_uncore_read(uncore, GEN12_SFC_DONE(i)); 1915 } 1916 1917 gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE); 1918 } 1919 } 1920 1921 static void gt_record_info(struct intel_gt_coredump *gt) 1922 { 1923 memcpy(>->info, >->_gt->info, sizeof(struct intel_gt_info)); 1924 gt->clock_frequency = gt->_gt->clock_frequency; 1925 gt->clock_period_ns = gt->_gt->clock_period_ns; 1926 } 1927 1928 /* 1929 * Generate a semi-unique error code. The code is not meant to have meaning, The 1930 * code's only purpose is to try to prevent false duplicated bug reports by 1931 * grossly estimating a GPU error state. 1932 * 1933 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 1934 * the hang if we could strip the GTT offset information from it. 1935 * 1936 * It's only a small step better than a random number in its current form. 1937 */ 1938 static u32 generate_ecode(const struct intel_engine_coredump *ee) 1939 { 1940 /* 1941 * IPEHR would be an ideal way to detect errors, as it's the gross 1942 * measure of "the command that hung." However, has some very common 1943 * synchronization commands which almost always appear in the case 1944 * strictly a client bug. Use instdone to differentiate those some. 1945 */ 1946 return ee ? ee->ipehr ^ ee->instdone.instdone : 0; 1947 } 1948 1949 static const char *error_msg(struct i915_gpu_coredump *error) 1950 { 1951 struct intel_engine_coredump *first = NULL; 1952 unsigned int hung_classes = 0; 1953 struct intel_gt_coredump *gt; 1954 int len; 1955 1956 for (gt = error->gt; gt; gt = gt->next) { 1957 struct intel_engine_coredump *cs; 1958 1959 for (cs = gt->engine; cs; cs = cs->next) { 1960 if (cs->hung) { 1961 hung_classes |= BIT(cs->engine->uabi_class); 1962 if (!first) 1963 first = cs; 1964 } 1965 } 1966 } 1967 1968 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1969 "GPU HANG: ecode %d:%x:%08x", 1970 GRAPHICS_VER(error->i915), hung_classes, 1971 generate_ecode(first)); 1972 if (first && first->context.pid) { 1973 /* Just show the first executing process, more is confusing */ 1974 len += scnprintf(error->error_msg + len, 1975 sizeof(error->error_msg) - len, 1976 ", in %s [%d]", 1977 first->context.comm, first->context.pid); 1978 } 1979 1980 return error->error_msg; 1981 } 1982 1983 static void capture_gen(struct i915_gpu_coredump *error) 1984 { 1985 struct drm_i915_private *i915 = error->i915; 1986 1987 error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count); 1988 error->suspended = pm_runtime_suspended(i915->drm.dev); 1989 1990 error->iommu = i915_vtd_active(i915); 1991 error->reset_count = i915_reset_count(&i915->gpu_error); 1992 error->suspend_count = i915->suspend_count; 1993 1994 i915_params_copy(&error->params, &i915->params); 1995 intel_display_params_copy(&error->display_params); 1996 memcpy(&error->device_info, 1997 INTEL_INFO(i915), 1998 sizeof(error->device_info)); 1999 memcpy(&error->runtime_info, 2000 RUNTIME_INFO(i915), 2001 sizeof(error->runtime_info)); 2002 memcpy(&error->display_device_info, DISPLAY_INFO(i915), 2003 sizeof(error->display_device_info)); 2004 memcpy(&error->display_runtime_info, DISPLAY_RUNTIME_INFO(i915), 2005 sizeof(error->display_runtime_info)); 2006 error->driver_caps = i915->caps; 2007 } 2008 2009 struct i915_gpu_coredump * 2010 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp) 2011 { 2012 struct i915_gpu_coredump *error; 2013 2014 if (!i915->params.error_capture) 2015 return NULL; 2016 2017 error = kzalloc(sizeof(*error), gfp); 2018 if (!error) 2019 return NULL; 2020 2021 kref_init(&error->ref); 2022 error->i915 = i915; 2023 2024 error->time = ktime_get_real(); 2025 error->boottime = ktime_get_boottime(); 2026 error->uptime = ktime_sub(ktime_get(), to_gt(i915)->last_init_time); 2027 error->capture = jiffies; 2028 2029 capture_gen(error); 2030 2031 return error; 2032 } 2033 2034 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x)) 2035 2036 struct intel_gt_coredump * 2037 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags) 2038 { 2039 struct intel_gt_coredump *gc; 2040 2041 gc = kzalloc(sizeof(*gc), gfp); 2042 if (!gc) 2043 return NULL; 2044 2045 gc->_gt = gt; 2046 gc->awake = intel_gt_pm_is_awake(gt); 2047 2048 gt_record_display_regs(gc); 2049 gt_record_global_nonguc_regs(gc); 2050 2051 /* 2052 * GuC dumps global, eng-class and eng-instance registers 2053 * (that can change as part of engine state during execution) 2054 * before an engine is reset due to a hung context. 2055 * GuC captures and reports all three groups of registers 2056 * together as a single set before the engine is reset. 2057 * Thus, if GuC triggered the context reset we retrieve 2058 * the register values as part of gt_record_engines. 2059 */ 2060 if (!(dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)) 2061 gt_record_global_regs(gc); 2062 2063 gt_record_fences(gc); 2064 2065 return gc; 2066 } 2067 2068 struct i915_vma_compress * 2069 i915_vma_capture_prepare(struct intel_gt_coredump *gt) 2070 { 2071 struct i915_vma_compress *compress; 2072 2073 compress = kmalloc(sizeof(*compress), ALLOW_FAIL); 2074 if (!compress) 2075 return NULL; 2076 2077 if (!compress_init(compress)) { 2078 kfree(compress); 2079 return NULL; 2080 } 2081 2082 return compress; 2083 } 2084 2085 void i915_vma_capture_finish(struct intel_gt_coredump *gt, 2086 struct i915_vma_compress *compress) 2087 { 2088 if (!compress) 2089 return; 2090 2091 compress_fini(compress); 2092 kfree(compress); 2093 } 2094 2095 static struct i915_gpu_coredump * 2096 __i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags) 2097 { 2098 struct drm_i915_private *i915 = gt->i915; 2099 struct i915_gpu_coredump *error; 2100 2101 /* Check if GPU capture has been disabled */ 2102 error = READ_ONCE(i915->gpu_error.first_error); 2103 if (IS_ERR(error)) 2104 return error; 2105 2106 error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL); 2107 if (!error) 2108 return ERR_PTR(-ENOMEM); 2109 2110 error->gt = intel_gt_coredump_alloc(gt, ALLOW_FAIL, dump_flags); 2111 if (error->gt) { 2112 struct i915_vma_compress *compress; 2113 2114 compress = i915_vma_capture_prepare(error->gt); 2115 if (!compress) { 2116 kfree(error->gt); 2117 kfree(error); 2118 return ERR_PTR(-ENOMEM); 2119 } 2120 2121 if (INTEL_INFO(i915)->has_gt_uc) { 2122 error->gt->uc = gt_record_uc(error->gt, compress); 2123 if (error->gt->uc) { 2124 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE) 2125 error->gt->uc->guc.is_guc_capture = true; 2126 else 2127 GEM_BUG_ON(error->gt->uc->guc.is_guc_capture); 2128 } 2129 } 2130 2131 gt_record_info(error->gt); 2132 gt_record_engines(error->gt, engine_mask, compress, dump_flags); 2133 2134 2135 i915_vma_capture_finish(error->gt, compress); 2136 2137 error->simulated |= error->gt->simulated; 2138 } 2139 2140 error->overlay = intel_overlay_capture_error_state(i915); 2141 2142 return error; 2143 } 2144 2145 static struct i915_gpu_coredump * 2146 i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags) 2147 { 2148 static DEFINE_MUTEX(capture_mutex); 2149 int ret = mutex_lock_interruptible(&capture_mutex); 2150 struct i915_gpu_coredump *dump; 2151 2152 if (ret) 2153 return ERR_PTR(ret); 2154 2155 dump = __i915_gpu_coredump(gt, engine_mask, dump_flags); 2156 mutex_unlock(&capture_mutex); 2157 2158 return dump; 2159 } 2160 2161 void i915_error_state_store(struct i915_gpu_coredump *error) 2162 { 2163 struct drm_i915_private *i915; 2164 static bool warned; 2165 2166 if (IS_ERR_OR_NULL(error)) 2167 return; 2168 2169 i915 = error->i915; 2170 drm_info(&i915->drm, "%s\n", error_msg(error)); 2171 2172 if (error->simulated || 2173 cmpxchg(&i915->gpu_error.first_error, NULL, error)) 2174 return; 2175 2176 i915_gpu_coredump_get(error); 2177 2178 if (!xchg(&warned, true) && 2179 ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) { 2180 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 2181 pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n"); 2182 pr_info("Please see https://drm.pages.freedesktop.org/intel-docs/how-to-file-i915-bugs.html for details.\n"); 2183 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 2184 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n"); 2185 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n", 2186 i915->drm.primary->index); 2187 } 2188 } 2189 2190 /** 2191 * i915_capture_error_state - capture an error record for later analysis 2192 * @gt: intel_gt which originated the hang 2193 * @engine_mask: hung engines 2194 * @dump_flags: dump flags 2195 * 2196 * Should be called when an error is detected (either a hang or an error 2197 * interrupt) to capture error state from the time of the error. Fills 2198 * out a structure which becomes available in debugfs for user level tools 2199 * to pick up. 2200 */ 2201 void i915_capture_error_state(struct intel_gt *gt, 2202 intel_engine_mask_t engine_mask, u32 dump_flags) 2203 { 2204 struct i915_gpu_coredump *error; 2205 2206 error = i915_gpu_coredump(gt, engine_mask, dump_flags); 2207 if (IS_ERR(error)) { 2208 cmpxchg(>->i915->gpu_error.first_error, NULL, error); 2209 return; 2210 } 2211 2212 i915_error_state_store(error); 2213 i915_gpu_coredump_put(error); 2214 } 2215 2216 static struct i915_gpu_coredump * 2217 i915_first_error_state(struct drm_i915_private *i915) 2218 { 2219 struct i915_gpu_coredump *error; 2220 2221 spin_lock_irq(&i915->gpu_error.lock); 2222 error = i915->gpu_error.first_error; 2223 if (!IS_ERR_OR_NULL(error)) 2224 i915_gpu_coredump_get(error); 2225 spin_unlock_irq(&i915->gpu_error.lock); 2226 2227 return error; 2228 } 2229 2230 void i915_reset_error_state(struct drm_i915_private *i915) 2231 { 2232 struct i915_gpu_coredump *error; 2233 2234 spin_lock_irq(&i915->gpu_error.lock); 2235 error = i915->gpu_error.first_error; 2236 if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */ 2237 i915->gpu_error.first_error = NULL; 2238 spin_unlock_irq(&i915->gpu_error.lock); 2239 2240 if (!IS_ERR_OR_NULL(error)) 2241 i915_gpu_coredump_put(error); 2242 } 2243 2244 void i915_disable_error_state(struct drm_i915_private *i915, int err) 2245 { 2246 spin_lock_irq(&i915->gpu_error.lock); 2247 if (!i915->gpu_error.first_error) 2248 i915->gpu_error.first_error = ERR_PTR(err); 2249 spin_unlock_irq(&i915->gpu_error.lock); 2250 } 2251 2252 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) 2253 void intel_klog_error_capture(struct intel_gt *gt, 2254 intel_engine_mask_t engine_mask) 2255 { 2256 static int g_count; 2257 struct drm_i915_private *i915 = gt->i915; 2258 struct i915_gpu_coredump *error; 2259 intel_wakeref_t wakeref; 2260 size_t buf_size = PAGE_SIZE * 128; 2261 size_t pos_err; 2262 char *buf, *ptr, *next; 2263 int l_count = g_count++; 2264 int line = 0; 2265 2266 /* Can't allocate memory during a reset */ 2267 if (test_bit(I915_RESET_BACKOFF, >->reset.flags)) { 2268 drm_err(>->i915->drm, "[Capture/%d.%d] Inside GT reset, skipping error capture :(\n", 2269 l_count, line++); 2270 return; 2271 } 2272 2273 error = READ_ONCE(i915->gpu_error.first_error); 2274 if (error) { 2275 drm_err(&i915->drm, "[Capture/%d.%d] Clearing existing error capture first...\n", 2276 l_count, line++); 2277 i915_reset_error_state(i915); 2278 } 2279 2280 with_intel_runtime_pm(&i915->runtime_pm, wakeref) 2281 error = i915_gpu_coredump(gt, engine_mask, CORE_DUMP_FLAG_NONE); 2282 2283 if (IS_ERR(error)) { 2284 drm_err(&i915->drm, "[Capture/%d.%d] Failed to capture error capture: %ld!\n", 2285 l_count, line++, PTR_ERR(error)); 2286 return; 2287 } 2288 2289 buf = kvmalloc(buf_size, GFP_KERNEL); 2290 if (!buf) { 2291 drm_err(&i915->drm, "[Capture/%d.%d] Failed to allocate buffer for error capture!\n", 2292 l_count, line++); 2293 i915_gpu_coredump_put(error); 2294 return; 2295 } 2296 2297 drm_info(&i915->drm, "[Capture/%d.%d] Dumping i915 error capture for %ps...\n", 2298 l_count, line++, __builtin_return_address(0)); 2299 2300 /* Largest string length safe to print via dmesg */ 2301 # define MAX_CHUNK 800 2302 2303 pos_err = 0; 2304 while (1) { 2305 ssize_t got = i915_gpu_coredump_copy_to_buffer(error, buf, pos_err, buf_size - 1); 2306 2307 if (got <= 0) 2308 break; 2309 2310 buf[got] = 0; 2311 pos_err += got; 2312 2313 ptr = buf; 2314 while (got > 0) { 2315 size_t count; 2316 char tag[2]; 2317 2318 next = strnchr(ptr, got, '\n'); 2319 if (next) { 2320 count = next - ptr; 2321 *next = 0; 2322 tag[0] = '>'; 2323 tag[1] = '<'; 2324 } else { 2325 count = got; 2326 tag[0] = '}'; 2327 tag[1] = '{'; 2328 } 2329 2330 if (count > MAX_CHUNK) { 2331 size_t pos; 2332 char *ptr2 = ptr; 2333 2334 for (pos = MAX_CHUNK; pos < count; pos += MAX_CHUNK) { 2335 char chr = ptr[pos]; 2336 2337 ptr[pos] = 0; 2338 drm_info(&i915->drm, "[Capture/%d.%d] }%s{\n", 2339 l_count, line++, ptr2); 2340 ptr[pos] = chr; 2341 ptr2 = ptr + pos; 2342 2343 /* 2344 * If spewing large amounts of data via a serial console, 2345 * this can be a very slow process. So be friendly and try 2346 * not to cause 'softlockup on CPU' problems. 2347 */ 2348 cond_resched(); 2349 } 2350 2351 if (ptr2 < (ptr + count)) 2352 drm_info(&i915->drm, "[Capture/%d.%d] %c%s%c\n", 2353 l_count, line++, tag[0], ptr2, tag[1]); 2354 else if (tag[0] == '>') 2355 drm_info(&i915->drm, "[Capture/%d.%d] ><\n", 2356 l_count, line++); 2357 } else { 2358 drm_info(&i915->drm, "[Capture/%d.%d] %c%s%c\n", 2359 l_count, line++, tag[0], ptr, tag[1]); 2360 } 2361 2362 ptr = next; 2363 got -= count; 2364 if (next) { 2365 ptr++; 2366 got--; 2367 } 2368 2369 /* As above. */ 2370 cond_resched(); 2371 } 2372 2373 if (got) 2374 drm_info(&i915->drm, "[Capture/%d.%d] Got %zd bytes remaining!\n", 2375 l_count, line++, got); 2376 } 2377 2378 kvfree(buf); 2379 2380 drm_info(&i915->drm, "[Capture/%d.%d] Dumped %zd bytes\n", l_count, line++, pos_err); 2381 } 2382 #endif 2383 2384 static ssize_t gpu_state_read(struct file *file, char __user *ubuf, 2385 size_t count, loff_t *pos) 2386 { 2387 struct i915_gpu_coredump *error; 2388 ssize_t ret; 2389 void *buf; 2390 2391 error = file->private_data; 2392 if (!error) 2393 return 0; 2394 2395 /* Bounce buffer required because of kernfs __user API convenience. */ 2396 buf = kmalloc(count, GFP_KERNEL); 2397 if (!buf) 2398 return -ENOMEM; 2399 2400 ret = i915_gpu_coredump_copy_to_buffer(error, buf, *pos, count); 2401 if (ret <= 0) 2402 goto out; 2403 2404 if (!copy_to_user(ubuf, buf, ret)) 2405 *pos += ret; 2406 else 2407 ret = -EFAULT; 2408 2409 out: 2410 kfree(buf); 2411 return ret; 2412 } 2413 2414 static int gpu_state_release(struct inode *inode, struct file *file) 2415 { 2416 i915_gpu_coredump_put(file->private_data); 2417 return 0; 2418 } 2419 2420 static int i915_gpu_info_open(struct inode *inode, struct file *file) 2421 { 2422 struct drm_i915_private *i915 = inode->i_private; 2423 struct i915_gpu_coredump *gpu; 2424 intel_wakeref_t wakeref; 2425 2426 gpu = NULL; 2427 with_intel_runtime_pm(&i915->runtime_pm, wakeref) 2428 gpu = i915_gpu_coredump(to_gt(i915), ALL_ENGINES, CORE_DUMP_FLAG_NONE); 2429 2430 if (IS_ERR(gpu)) 2431 return PTR_ERR(gpu); 2432 2433 file->private_data = gpu; 2434 return 0; 2435 } 2436 2437 static const struct file_operations i915_gpu_info_fops = { 2438 .owner = THIS_MODULE, 2439 .open = i915_gpu_info_open, 2440 .read = gpu_state_read, 2441 .llseek = default_llseek, 2442 .release = gpu_state_release, 2443 }; 2444 2445 static ssize_t 2446 i915_error_state_write(struct file *filp, 2447 const char __user *ubuf, 2448 size_t cnt, 2449 loff_t *ppos) 2450 { 2451 struct i915_gpu_coredump *error = filp->private_data; 2452 2453 if (!error) 2454 return 0; 2455 2456 drm_dbg(&error->i915->drm, "Resetting error state\n"); 2457 i915_reset_error_state(error->i915); 2458 2459 return cnt; 2460 } 2461 2462 static int i915_error_state_open(struct inode *inode, struct file *file) 2463 { 2464 struct i915_gpu_coredump *error; 2465 2466 error = i915_first_error_state(inode->i_private); 2467 if (IS_ERR(error)) 2468 return PTR_ERR(error); 2469 2470 file->private_data = error; 2471 return 0; 2472 } 2473 2474 static const struct file_operations i915_error_state_fops = { 2475 .owner = THIS_MODULE, 2476 .open = i915_error_state_open, 2477 .read = gpu_state_read, 2478 .write = i915_error_state_write, 2479 .llseek = default_llseek, 2480 .release = gpu_state_release, 2481 }; 2482 2483 void i915_gpu_error_debugfs_register(struct drm_i915_private *i915) 2484 { 2485 struct drm_minor *minor = i915->drm.primary; 2486 2487 debugfs_create_file("i915_error_state", 0644, minor->debugfs_root, i915, 2488 &i915_error_state_fops); 2489 debugfs_create_file("i915_gpu_info", 0644, minor->debugfs_root, i915, 2490 &i915_gpu_info_fops); 2491 } 2492 2493 static ssize_t error_state_read(struct file *filp, struct kobject *kobj, 2494 struct bin_attribute *attr, char *buf, 2495 loff_t off, size_t count) 2496 { 2497 2498 struct device *kdev = kobj_to_dev(kobj); 2499 struct drm_i915_private *i915 = kdev_minor_to_i915(kdev); 2500 struct i915_gpu_coredump *gpu; 2501 ssize_t ret = 0; 2502 2503 /* 2504 * FIXME: Concurrent clients triggering resets and reading + clearing 2505 * dumps can cause inconsistent sysfs reads when a user calls in with a 2506 * non-zero offset to complete a prior partial read but the 2507 * gpu_coredump has been cleared or replaced. 2508 */ 2509 2510 gpu = i915_first_error_state(i915); 2511 if (IS_ERR(gpu)) { 2512 ret = PTR_ERR(gpu); 2513 } else if (gpu) { 2514 ret = i915_gpu_coredump_copy_to_buffer(gpu, buf, off, count); 2515 i915_gpu_coredump_put(gpu); 2516 } else { 2517 const char *str = "No error state collected\n"; 2518 size_t len = strlen(str); 2519 2520 if (off < len) { 2521 ret = min_t(size_t, count, len - off); 2522 memcpy(buf, str + off, ret); 2523 } 2524 } 2525 2526 return ret; 2527 } 2528 2529 static ssize_t error_state_write(struct file *file, struct kobject *kobj, 2530 struct bin_attribute *attr, char *buf, 2531 loff_t off, size_t count) 2532 { 2533 struct device *kdev = kobj_to_dev(kobj); 2534 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 2535 2536 drm_dbg(&dev_priv->drm, "Resetting error state\n"); 2537 i915_reset_error_state(dev_priv); 2538 2539 return count; 2540 } 2541 2542 static const struct bin_attribute error_state_attr = { 2543 .attr.name = "error", 2544 .attr.mode = S_IRUSR | S_IWUSR, 2545 .size = 0, 2546 .read = error_state_read, 2547 .write = error_state_write, 2548 }; 2549 2550 void i915_gpu_error_sysfs_setup(struct drm_i915_private *i915) 2551 { 2552 struct device *kdev = i915->drm.primary->kdev; 2553 2554 if (sysfs_create_bin_file(&kdev->kobj, &error_state_attr)) 2555 drm_err(&i915->drm, "error_state sysfs setup failed\n"); 2556 } 2557 2558 void i915_gpu_error_sysfs_teardown(struct drm_i915_private *i915) 2559 { 2560 struct device *kdev = i915->drm.primary->kdev; 2561 2562 sysfs_remove_bin_file(&kdev->kobj, &error_state_attr); 2563 } 2564