1 /* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30 #include <linux/ascii85.h> 31 #include <linux/debugfs.h> 32 #include <linux/highmem.h> 33 #include <linux/nmi.h> 34 #include <linux/pagevec.h> 35 #include <linux/scatterlist.h> 36 #include <linux/string_helpers.h> 37 #include <linux/utsname.h> 38 #include <linux/zlib.h> 39 40 #include <drm/drm_cache.h> 41 #include <drm/drm_print.h> 42 43 #include "display/intel_display_snapshot.h" 44 45 #include "gem/i915_gem_context.h" 46 #include "gem/i915_gem_lmem.h" 47 #include "gt/intel_engine_regs.h" 48 #include "gt/intel_gt.h" 49 #include "gt/intel_gt_mcr.h" 50 #include "gt/intel_gt_pm.h" 51 #include "gt/intel_gt_regs.h" 52 #include "gt/uc/intel_guc_capture.h" 53 54 #include "i915_driver.h" 55 #include "i915_drv.h" 56 #include "i915_gpu_error.h" 57 #include "i915_memcpy.h" 58 #include "i915_reg.h" 59 #include "i915_scatterlist.h" 60 #include "i915_sysfs.h" 61 #include "i915_utils.h" 62 63 #define ALLOW_FAIL (__GFP_KSWAPD_RECLAIM | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) 64 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN) 65 66 static void __sg_set_buf(struct scatterlist *sg, 67 void *addr, unsigned int len, loff_t it) 68 { 69 sg->page_link = (unsigned long)virt_to_page(addr); 70 sg->offset = offset_in_page(addr); 71 sg->length = len; 72 sg->dma_address = it; 73 } 74 75 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len) 76 { 77 if (!len) 78 return false; 79 80 if (e->bytes + len + 1 <= e->size) 81 return true; 82 83 if (e->bytes) { 84 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter); 85 e->iter += e->bytes; 86 e->buf = NULL; 87 e->bytes = 0; 88 } 89 90 if (e->cur == e->end) { 91 struct scatterlist *sgl; 92 93 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL); 94 if (!sgl) { 95 e->err = -ENOMEM; 96 return false; 97 } 98 99 if (e->cur) { 100 e->cur->offset = 0; 101 e->cur->length = 0; 102 e->cur->page_link = 103 (unsigned long)sgl | SG_CHAIN; 104 } else { 105 e->sgl = sgl; 106 } 107 108 e->cur = sgl; 109 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1; 110 } 111 112 e->size = ALIGN(len + 1, SZ_64K); 113 e->buf = kmalloc(e->size, ALLOW_FAIL); 114 if (!e->buf) { 115 e->size = PAGE_ALIGN(len + 1); 116 e->buf = kmalloc(e->size, GFP_KERNEL); 117 } 118 if (!e->buf) { 119 e->err = -ENOMEM; 120 return false; 121 } 122 123 return true; 124 } 125 126 __printf(2, 0) 127 static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 128 const char *fmt, va_list args) 129 { 130 va_list ap; 131 int len; 132 133 if (e->err) 134 return; 135 136 va_copy(ap, args); 137 len = vsnprintf(NULL, 0, fmt, ap); 138 va_end(ap); 139 if (len <= 0) { 140 e->err = len; 141 return; 142 } 143 144 if (!__i915_error_grow(e, len)) 145 return; 146 147 GEM_BUG_ON(e->bytes >= e->size); 148 len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args); 149 if (len < 0) { 150 e->err = len; 151 return; 152 } 153 e->bytes += len; 154 } 155 156 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str) 157 { 158 unsigned len; 159 160 if (e->err || !str) 161 return; 162 163 len = strlen(str); 164 if (!__i915_error_grow(e, len)) 165 return; 166 167 GEM_BUG_ON(e->bytes + len > e->size); 168 memcpy(e->buf + e->bytes, str, len); 169 e->bytes += len; 170 } 171 172 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 173 #define err_puts(e, s) i915_error_puts(e, s) 174 175 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf) 176 { 177 i915_error_vprintf(p->arg, vaf->fmt, *vaf->va); 178 } 179 180 static inline struct drm_printer 181 i915_error_printer(struct drm_i915_error_state_buf *e) 182 { 183 struct drm_printer p = { 184 .printfn = __i915_printfn_error, 185 .arg = e, 186 }; 187 return p; 188 } 189 190 /* single threaded page allocator with a reserved stash for emergencies */ 191 static void pool_fini(struct folio_batch *fbatch) 192 { 193 folio_batch_release(fbatch); 194 } 195 196 static int pool_refill(struct folio_batch *fbatch, gfp_t gfp) 197 { 198 while (folio_batch_space(fbatch)) { 199 struct folio *folio; 200 201 folio = folio_alloc(gfp, 0); 202 if (!folio) 203 return -ENOMEM; 204 205 folio_batch_add(fbatch, folio); 206 } 207 208 return 0; 209 } 210 211 static int pool_init(struct folio_batch *fbatch, gfp_t gfp) 212 { 213 int err; 214 215 folio_batch_init(fbatch); 216 217 err = pool_refill(fbatch, gfp); 218 if (err) 219 pool_fini(fbatch); 220 221 return err; 222 } 223 224 static void *pool_alloc(struct folio_batch *fbatch, gfp_t gfp) 225 { 226 struct folio *folio; 227 228 folio = folio_alloc(gfp, 0); 229 if (!folio && folio_batch_count(fbatch)) 230 folio = fbatch->folios[--fbatch->nr]; 231 232 return folio ? folio_address(folio) : NULL; 233 } 234 235 static void pool_free(struct folio_batch *fbatch, void *addr) 236 { 237 struct folio *folio = virt_to_folio(addr); 238 239 if (folio_batch_space(fbatch)) 240 folio_batch_add(fbatch, folio); 241 else 242 folio_put(folio); 243 } 244 245 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR 246 247 struct i915_vma_compress { 248 struct folio_batch pool; 249 struct z_stream_s zstream; 250 void *tmp; 251 }; 252 253 static bool compress_init(struct i915_vma_compress *c) 254 { 255 struct z_stream_s *zstream = &c->zstream; 256 257 if (pool_init(&c->pool, ALLOW_FAIL)) 258 return false; 259 260 zstream->workspace = 261 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL), 262 ALLOW_FAIL); 263 if (!zstream->workspace) { 264 pool_fini(&c->pool); 265 return false; 266 } 267 268 c->tmp = NULL; 269 if (i915_has_memcpy_from_wc()) 270 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL); 271 272 return true; 273 } 274 275 static bool compress_start(struct i915_vma_compress *c) 276 { 277 struct z_stream_s *zstream = &c->zstream; 278 void *workspace = zstream->workspace; 279 280 memset(zstream, 0, sizeof(*zstream)); 281 zstream->workspace = workspace; 282 283 return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK; 284 } 285 286 static void *compress_next_page(struct i915_vma_compress *c, 287 struct i915_vma_coredump *dst) 288 { 289 void *page_addr; 290 struct page *page; 291 292 page_addr = pool_alloc(&c->pool, ALLOW_FAIL); 293 if (!page_addr) 294 return ERR_PTR(-ENOMEM); 295 296 page = virt_to_page(page_addr); 297 list_add_tail(&page->lru, &dst->page_list); 298 return page_addr; 299 } 300 301 static int compress_page(struct i915_vma_compress *c, 302 void *src, 303 struct i915_vma_coredump *dst, 304 bool wc) 305 { 306 struct z_stream_s *zstream = &c->zstream; 307 308 zstream->next_in = src; 309 if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE)) 310 zstream->next_in = c->tmp; 311 zstream->avail_in = PAGE_SIZE; 312 313 do { 314 if (zstream->avail_out == 0) { 315 zstream->next_out = compress_next_page(c, dst); 316 if (IS_ERR(zstream->next_out)) 317 return PTR_ERR(zstream->next_out); 318 319 zstream->avail_out = PAGE_SIZE; 320 } 321 322 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK) 323 return -EIO; 324 325 cond_resched(); 326 } while (zstream->avail_in); 327 328 /* Fallback to uncompressed if we increase size? */ 329 if (0 && zstream->total_out > zstream->total_in) 330 return -E2BIG; 331 332 return 0; 333 } 334 335 static int compress_flush(struct i915_vma_compress *c, 336 struct i915_vma_coredump *dst) 337 { 338 struct z_stream_s *zstream = &c->zstream; 339 340 do { 341 switch (zlib_deflate(zstream, Z_FINISH)) { 342 case Z_OK: /* more space requested */ 343 zstream->next_out = compress_next_page(c, dst); 344 if (IS_ERR(zstream->next_out)) 345 return PTR_ERR(zstream->next_out); 346 347 zstream->avail_out = PAGE_SIZE; 348 break; 349 350 case Z_STREAM_END: 351 goto end; 352 353 default: /* any error */ 354 return -EIO; 355 } 356 } while (1); 357 358 end: 359 memset(zstream->next_out, 0, zstream->avail_out); 360 dst->unused = zstream->avail_out; 361 return 0; 362 } 363 364 static void compress_finish(struct i915_vma_compress *c) 365 { 366 zlib_deflateEnd(&c->zstream); 367 } 368 369 static void compress_fini(struct i915_vma_compress *c) 370 { 371 kfree(c->zstream.workspace); 372 if (c->tmp) 373 pool_free(&c->pool, c->tmp); 374 pool_fini(&c->pool); 375 } 376 377 static void err_compression_marker(struct drm_i915_error_state_buf *m) 378 { 379 err_puts(m, ":"); 380 } 381 382 #else 383 384 struct i915_vma_compress { 385 struct folio_batch pool; 386 }; 387 388 static bool compress_init(struct i915_vma_compress *c) 389 { 390 return pool_init(&c->pool, ALLOW_FAIL) == 0; 391 } 392 393 static bool compress_start(struct i915_vma_compress *c) 394 { 395 return true; 396 } 397 398 static int compress_page(struct i915_vma_compress *c, 399 void *src, 400 struct i915_vma_coredump *dst, 401 bool wc) 402 { 403 void *ptr; 404 405 ptr = pool_alloc(&c->pool, ALLOW_FAIL); 406 if (!ptr) 407 return -ENOMEM; 408 409 if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE))) 410 memcpy(ptr, src, PAGE_SIZE); 411 list_add_tail(&virt_to_page(ptr)->lru, &dst->page_list); 412 cond_resched(); 413 414 return 0; 415 } 416 417 static int compress_flush(struct i915_vma_compress *c, 418 struct i915_vma_coredump *dst) 419 { 420 return 0; 421 } 422 423 static void compress_finish(struct i915_vma_compress *c) 424 { 425 } 426 427 static void compress_fini(struct i915_vma_compress *c) 428 { 429 pool_fini(&c->pool); 430 } 431 432 static void err_compression_marker(struct drm_i915_error_state_buf *m) 433 { 434 err_puts(m, "~"); 435 } 436 437 #endif 438 439 static void error_print_instdone(struct drm_i915_error_state_buf *m, 440 const struct intel_engine_coredump *ee) 441 { 442 int slice; 443 int subslice; 444 int iter; 445 446 err_printf(m, " INSTDONE: 0x%08x\n", 447 ee->instdone.instdone); 448 449 if (ee->engine->class != RENDER_CLASS || GRAPHICS_VER(m->i915) <= 3) 450 return; 451 452 err_printf(m, " SC_INSTDONE: 0x%08x\n", 453 ee->instdone.slice_common); 454 455 if (GRAPHICS_VER(m->i915) <= 6) 456 return; 457 458 for_each_ss_steering(iter, ee->engine->gt, slice, subslice) 459 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", 460 slice, subslice, 461 ee->instdone.sampler[slice][subslice]); 462 463 for_each_ss_steering(iter, ee->engine->gt, slice, subslice) 464 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", 465 slice, subslice, 466 ee->instdone.row[slice][subslice]); 467 468 if (GRAPHICS_VER(m->i915) < 12) 469 return; 470 471 if (GRAPHICS_VER_FULL(m->i915) >= IP_VER(12, 55)) { 472 for_each_ss_steering(iter, ee->engine->gt, slice, subslice) 473 err_printf(m, " GEOM_SVGUNIT_INSTDONE[%d][%d]: 0x%08x\n", 474 slice, subslice, 475 ee->instdone.geom_svg[slice][subslice]); 476 } 477 478 err_printf(m, " SC_INSTDONE_EXTRA: 0x%08x\n", 479 ee->instdone.slice_common_extra[0]); 480 err_printf(m, " SC_INSTDONE_EXTRA2: 0x%08x\n", 481 ee->instdone.slice_common_extra[1]); 482 } 483 484 static void error_print_request(struct drm_i915_error_state_buf *m, 485 const char *prefix, 486 const struct i915_request_coredump *erq) 487 { 488 if (!erq->seqno) 489 return; 490 491 err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, head %08x, tail %08x\n", 492 prefix, erq->pid, erq->context, erq->seqno, 493 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, 494 &erq->flags) ? "!" : "", 495 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, 496 &erq->flags) ? "+" : "", 497 erq->sched_attr.priority, 498 erq->head, erq->tail); 499 } 500 501 static void error_print_context(struct drm_i915_error_state_buf *m, 502 const char *header, 503 const struct i915_gem_context_coredump *ctx) 504 { 505 err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n", 506 header, ctx->comm, ctx->pid, ctx->sched_attr.priority, 507 ctx->guilty, ctx->active, 508 ctx->total_runtime, ctx->avg_runtime); 509 err_printf(m, " context timeline seqno %u\n", ctx->hwsp_seqno); 510 } 511 512 static struct i915_vma_coredump * 513 __find_vma(struct i915_vma_coredump *vma, const char *name) 514 { 515 while (vma) { 516 if (strcmp(vma->name, name) == 0) 517 return vma; 518 vma = vma->next; 519 } 520 521 return NULL; 522 } 523 524 static struct i915_vma_coredump * 525 intel_gpu_error_find_batch(const struct intel_engine_coredump *ee) 526 { 527 return __find_vma(ee->vma, "batch"); 528 } 529 530 static void error_print_engine(struct drm_i915_error_state_buf *m, 531 const struct intel_engine_coredump *ee) 532 { 533 struct i915_vma_coredump *batch; 534 int n; 535 536 err_printf(m, "%s command stream:\n", ee->engine->name); 537 err_printf(m, " CCID: 0x%08x\n", ee->ccid); 538 err_printf(m, " START: 0x%08x\n", ee->start); 539 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head); 540 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n", 541 ee->tail, ee->rq_post, ee->rq_tail); 542 err_printf(m, " CTL: 0x%08x\n", ee->ctl); 543 err_printf(m, " MODE: 0x%08x\n", ee->mode); 544 err_printf(m, " HWS: 0x%08x\n", ee->hws); 545 err_printf(m, " ACTHD: 0x%08x %08x\n", 546 (u32)(ee->acthd>>32), (u32)ee->acthd); 547 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir); 548 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr); 549 err_printf(m, " ESR: 0x%08x\n", ee->esr); 550 551 error_print_instdone(m, ee); 552 553 batch = intel_gpu_error_find_batch(ee); 554 if (batch) { 555 u64 start = batch->gtt_offset; 556 u64 end = start + batch->gtt_size; 557 558 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n", 559 upper_32_bits(start), lower_32_bits(start), 560 upper_32_bits(end), lower_32_bits(end)); 561 } 562 if (GRAPHICS_VER(m->i915) >= 4) { 563 err_printf(m, " BBADDR: 0x%08x_%08x\n", 564 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr); 565 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate); 566 err_printf(m, " INSTPS: 0x%08x\n", ee->instps); 567 } 568 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm); 569 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr), 570 lower_32_bits(ee->faddr)); 571 if (GRAPHICS_VER(m->i915) >= 6) { 572 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi); 573 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg); 574 } 575 if (GRAPHICS_VER(m->i915) >= 11) { 576 err_printf(m, " NOPID: 0x%08x\n", ee->nopid); 577 err_printf(m, " EXCC: 0x%08x\n", ee->excc); 578 err_printf(m, " CMD_CCTL: 0x%08x\n", ee->cmd_cctl); 579 err_printf(m, " CSCMDOP: 0x%08x\n", ee->cscmdop); 580 err_printf(m, " CTX_SR_CTL: 0x%08x\n", ee->ctx_sr_ctl); 581 err_printf(m, " DMA_FADDR_HI: 0x%08x\n", ee->dma_faddr_hi); 582 err_printf(m, " DMA_FADDR_LO: 0x%08x\n", ee->dma_faddr_lo); 583 } 584 if (HAS_PPGTT(m->i915)) { 585 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode); 586 587 if (GRAPHICS_VER(m->i915) >= 8) { 588 int i; 589 for (i = 0; i < 4; i++) 590 err_printf(m, " PDP%d: 0x%016llx\n", 591 i, ee->vm_info.pdp[i]); 592 } else { 593 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 594 ee->vm_info.pp_dir_base); 595 } 596 } 597 598 for (n = 0; n < ee->num_ports; n++) { 599 err_printf(m, " ELSP[%d]:", n); 600 error_print_request(m, " ", &ee->execlist[n]); 601 } 602 } 603 604 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 605 { 606 va_list args; 607 608 va_start(args, f); 609 i915_error_vprintf(e, f, args); 610 va_end(args); 611 } 612 613 static void intel_gpu_error_print_vma(struct drm_i915_error_state_buf *m, 614 const struct intel_engine_cs *engine, 615 const struct i915_vma_coredump *vma) 616 { 617 char out[ASCII85_BUFSZ]; 618 struct page *page; 619 620 if (!vma) 621 return; 622 623 err_printf(m, "%s --- %s = 0x%08x %08x\n", 624 engine ? engine->name : "global", vma->name, 625 upper_32_bits(vma->gtt_offset), 626 lower_32_bits(vma->gtt_offset)); 627 628 if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K) 629 err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes); 630 631 err_compression_marker(m); 632 list_for_each_entry(page, &vma->page_list, lru) { 633 int i, len; 634 const u32 *addr = page_address(page); 635 636 len = PAGE_SIZE; 637 if (page == list_last_entry(&vma->page_list, typeof(*page), lru)) 638 len -= vma->unused; 639 len = ascii85_encode_len(len); 640 641 for (i = 0; i < len; i++) 642 err_puts(m, ascii85_encode(addr[i], out)); 643 } 644 err_puts(m, "\n"); 645 } 646 647 static void err_print_capabilities(struct drm_i915_error_state_buf *m, 648 struct i915_gpu_coredump *error) 649 { 650 struct drm_printer p = i915_error_printer(m); 651 652 intel_device_info_print(&error->device_info, &error->runtime_info, &p); 653 intel_driver_caps_print(&error->driver_caps, &p); 654 } 655 656 static void err_print_params(struct drm_i915_error_state_buf *m, 657 const struct i915_params *params) 658 { 659 struct drm_printer p = i915_error_printer(m); 660 661 i915_params_dump(params, &p); 662 } 663 664 static void err_print_pciid(struct drm_i915_error_state_buf *m, 665 struct drm_i915_private *i915) 666 { 667 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 668 669 err_printf(m, "PCI ID: 0x%04x\n", pdev->device); 670 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision); 671 err_printf(m, "PCI Subsystem: %04x:%04x\n", 672 pdev->subsystem_vendor, 673 pdev->subsystem_device); 674 } 675 676 static void err_print_guc_ctb(struct drm_i915_error_state_buf *m, 677 const char *name, 678 const struct intel_ctb_coredump *ctb) 679 { 680 if (!ctb->size) 681 return; 682 683 err_printf(m, "GuC %s CTB: raw: 0x%08X, 0x%08X/%08X, cached: 0x%08X/%08X, desc = 0x%08X, buf = 0x%08X x 0x%08X\n", 684 name, ctb->raw_status, ctb->raw_head, ctb->raw_tail, 685 ctb->head, ctb->tail, ctb->desc_offset, ctb->cmds_offset, ctb->size); 686 } 687 688 static void err_print_uc(struct drm_i915_error_state_buf *m, 689 const struct intel_uc_coredump *error_uc) 690 { 691 struct drm_printer p = i915_error_printer(m); 692 693 intel_uc_fw_dump(&error_uc->guc_fw, &p); 694 intel_uc_fw_dump(&error_uc->huc_fw, &p); 695 err_printf(m, "GuC timestamp: 0x%08x\n", error_uc->guc.timestamp); 696 intel_gpu_error_print_vma(m, NULL, error_uc->guc.vma_log); 697 err_printf(m, "GuC CTB fence: %d\n", error_uc->guc.last_fence); 698 err_print_guc_ctb(m, "Send", error_uc->guc.ctb + 0); 699 err_print_guc_ctb(m, "Recv", error_uc->guc.ctb + 1); 700 intel_gpu_error_print_vma(m, NULL, error_uc->guc.vma_ctb); 701 } 702 703 static void err_free_sgl(struct scatterlist *sgl) 704 { 705 while (sgl) { 706 struct scatterlist *sg; 707 708 for (sg = sgl; !sg_is_chain(sg); sg++) { 709 kfree(sg_virt(sg)); 710 if (sg_is_last(sg)) 711 break; 712 } 713 714 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg); 715 free_page((unsigned long)sgl); 716 sgl = sg; 717 } 718 } 719 720 static void err_print_gt_info(struct drm_i915_error_state_buf *m, 721 struct intel_gt_coredump *gt) 722 { 723 struct drm_printer p = i915_error_printer(m); 724 725 intel_gt_info_print(>->info, &p); 726 intel_sseu_print_topology(gt->_gt->i915, >->info.sseu, &p); 727 } 728 729 static void err_print_gt_global_nonguc(struct drm_i915_error_state_buf *m, 730 struct intel_gt_coredump *gt) 731 { 732 int i; 733 734 err_printf(m, "GT awake: %s\n", str_yes_no(gt->awake)); 735 err_printf(m, "CS timestamp frequency: %u Hz, %d ns\n", 736 gt->clock_frequency, gt->clock_period_ns); 737 err_printf(m, "EIR: 0x%08x\n", gt->eir); 738 err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er); 739 740 for (i = 0; i < gt->ngtier; i++) 741 err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]); 742 } 743 744 static void err_print_gt_global(struct drm_i915_error_state_buf *m, 745 struct intel_gt_coredump *gt) 746 { 747 err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake); 748 749 if (IS_GRAPHICS_VER(m->i915, 6, 11)) { 750 err_printf(m, "ERROR: 0x%08x\n", gt->error); 751 err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg); 752 } 753 754 if (GRAPHICS_VER(m->i915) >= 8) 755 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", 756 gt->fault_data1, gt->fault_data0); 757 758 if (GRAPHICS_VER(m->i915) == 7) 759 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int); 760 761 if (IS_GRAPHICS_VER(m->i915, 8, 11)) 762 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache); 763 764 if (GRAPHICS_VER(m->i915) == 12) 765 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err); 766 767 if (GRAPHICS_VER(m->i915) >= 12) { 768 int i; 769 770 for (i = 0; i < I915_MAX_SFC; i++) { 771 /* 772 * SFC_DONE resides in the VD forcewake domain, so it 773 * only exists if the corresponding VCS engine is 774 * present. 775 */ 776 if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || 777 !HAS_ENGINE(gt->_gt, _VCS(i * 2))) 778 continue; 779 780 err_printf(m, " SFC_DONE[%d]: 0x%08x\n", i, 781 gt->sfc_done[i]); 782 } 783 784 err_printf(m, " GAM_DONE: 0x%08x\n", gt->gam_done); 785 } 786 } 787 788 static void err_print_gt_fences(struct drm_i915_error_state_buf *m, 789 struct intel_gt_coredump *gt) 790 { 791 int i; 792 793 for (i = 0; i < gt->nfence; i++) 794 err_printf(m, " fence[%d] = %08llx\n", i, gt->fence[i]); 795 } 796 797 static void err_print_gt_engines(struct drm_i915_error_state_buf *m, 798 struct intel_gt_coredump *gt) 799 { 800 const struct intel_engine_coredump *ee; 801 802 for (ee = gt->engine; ee; ee = ee->next) { 803 const struct i915_vma_coredump *vma; 804 805 if (gt->uc && gt->uc->guc.is_guc_capture) { 806 if (ee->guc_capture_node) 807 intel_guc_capture_print_engine_node(m, ee); 808 else 809 err_printf(m, " Missing GuC capture node for %s\n", 810 ee->engine->name); 811 } else { 812 error_print_engine(m, ee); 813 } 814 815 err_printf(m, " hung: %u\n", ee->hung); 816 err_printf(m, " engine reset count: %u\n", ee->reset_count); 817 error_print_context(m, " Active context: ", &ee->context); 818 819 for (vma = ee->vma; vma; vma = vma->next) 820 intel_gpu_error_print_vma(m, ee->engine, vma); 821 } 822 823 } 824 825 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, 826 struct i915_gpu_coredump *error) 827 { 828 struct drm_printer p = i915_error_printer(m); 829 const struct intel_engine_coredump *ee; 830 struct timespec64 ts; 831 832 if (*error->error_msg) 833 err_printf(m, "%s\n", error->error_msg); 834 err_printf(m, "Kernel: %s %s\n", 835 init_utsname()->release, 836 init_utsname()->machine); 837 ts = ktime_to_timespec64(error->time); 838 err_printf(m, "Time: %lld s %ld us\n", 839 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 840 ts = ktime_to_timespec64(error->boottime); 841 err_printf(m, "Boottime: %lld s %ld us\n", 842 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 843 ts = ktime_to_timespec64(error->uptime); 844 err_printf(m, "Uptime: %lld s %ld us\n", 845 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 846 err_printf(m, "Capture: %lu jiffies; %d ms ago\n", 847 error->capture, jiffies_to_msecs(jiffies - error->capture)); 848 849 for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next) 850 err_printf(m, "Active process (on ring %s): %s [%d]\n", 851 ee->engine->name, 852 ee->context.comm, 853 ee->context.pid); 854 855 err_printf(m, "Reset count: %u\n", error->reset_count); 856 err_printf(m, "Suspend count: %u\n", error->suspend_count); 857 err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform)); 858 err_printf(m, "Subplatform: 0x%x\n", 859 intel_subplatform(&error->runtime_info, 860 error->device_info.platform)); 861 err_print_pciid(m, m->i915); 862 863 err_printf(m, "IOMMU enabled?: %d\n", error->iommu); 864 865 err_printf(m, "RPM wakelock: %s\n", str_yes_no(error->wakelock)); 866 err_printf(m, "PM suspended: %s\n", str_yes_no(error->suspended)); 867 868 if (error->gt) { 869 bool print_guc_capture = false; 870 871 if (error->gt->uc && error->gt->uc->guc.is_guc_capture) 872 print_guc_capture = true; 873 874 err_print_gt_global_nonguc(m, error->gt); 875 err_print_gt_fences(m, error->gt); 876 877 /* 878 * GuC dumped global, eng-class and eng-instance registers together 879 * as part of engine state dump so we print in err_print_gt_engines 880 */ 881 if (!print_guc_capture) 882 err_print_gt_global(m, error->gt); 883 884 err_print_gt_engines(m, error->gt); 885 886 if (error->gt->uc) 887 err_print_uc(m, error->gt->uc); 888 889 err_print_gt_info(m, error->gt); 890 } 891 892 err_print_capabilities(m, error); 893 err_print_params(m, &error->params); 894 895 intel_display_snapshot_print(error->display_snapshot, &p); 896 } 897 898 static int err_print_to_sgl(struct i915_gpu_coredump *error) 899 { 900 struct drm_i915_error_state_buf m; 901 902 if (IS_ERR(error)) 903 return PTR_ERR(error); 904 905 if (READ_ONCE(error->sgl)) 906 return 0; 907 908 memset(&m, 0, sizeof(m)); 909 m.i915 = error->i915; 910 911 __err_print_to_sgl(&m, error); 912 913 if (m.buf) { 914 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter); 915 m.bytes = 0; 916 m.buf = NULL; 917 } 918 if (m.cur) { 919 GEM_BUG_ON(m.end < m.cur); 920 sg_mark_end(m.cur - 1); 921 } 922 GEM_BUG_ON(m.sgl && !m.cur); 923 924 if (m.err) { 925 err_free_sgl(m.sgl); 926 return m.err; 927 } 928 929 if (cmpxchg(&error->sgl, NULL, m.sgl)) 930 err_free_sgl(m.sgl); 931 932 return 0; 933 } 934 935 ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error, 936 char *buf, loff_t off, size_t rem) 937 { 938 struct scatterlist *sg; 939 size_t count; 940 loff_t pos; 941 int err; 942 943 if (!error || !rem) 944 return 0; 945 946 err = err_print_to_sgl(error); 947 if (err) 948 return err; 949 950 sg = READ_ONCE(error->fit); 951 if (!sg || off < sg->dma_address) 952 sg = error->sgl; 953 if (!sg) 954 return 0; 955 956 pos = sg->dma_address; 957 count = 0; 958 do { 959 size_t len, start; 960 961 if (sg_is_chain(sg)) { 962 sg = sg_chain_ptr(sg); 963 GEM_BUG_ON(sg_is_chain(sg)); 964 } 965 966 len = sg->length; 967 if (pos + len <= off) { 968 pos += len; 969 continue; 970 } 971 972 start = sg->offset; 973 if (pos < off) { 974 GEM_BUG_ON(off - pos > len); 975 len -= off - pos; 976 start += off - pos; 977 pos = off; 978 } 979 980 len = min(len, rem); 981 GEM_BUG_ON(!len || len > sg->length); 982 983 memcpy(buf, page_address(sg_page(sg)) + start, len); 984 985 count += len; 986 pos += len; 987 988 buf += len; 989 rem -= len; 990 if (!rem) { 991 WRITE_ONCE(error->fit, sg); 992 break; 993 } 994 } while (!sg_is_last(sg++)); 995 996 return count; 997 } 998 999 static void i915_vma_coredump_free(struct i915_vma_coredump *vma) 1000 { 1001 while (vma) { 1002 struct i915_vma_coredump *next = vma->next; 1003 struct page *page, *n; 1004 1005 list_for_each_entry_safe(page, n, &vma->page_list, lru) { 1006 list_del_init(&page->lru); 1007 __free_page(page); 1008 } 1009 1010 kfree(vma); 1011 vma = next; 1012 } 1013 } 1014 1015 static void cleanup_params(struct i915_gpu_coredump *error) 1016 { 1017 i915_params_free(&error->params); 1018 } 1019 1020 static void cleanup_uc(struct intel_uc_coredump *uc) 1021 { 1022 kfree(uc->guc_fw.file_selected.path); 1023 kfree(uc->huc_fw.file_selected.path); 1024 kfree(uc->guc_fw.file_wanted.path); 1025 kfree(uc->huc_fw.file_wanted.path); 1026 i915_vma_coredump_free(uc->guc.vma_log); 1027 i915_vma_coredump_free(uc->guc.vma_ctb); 1028 1029 kfree(uc); 1030 } 1031 1032 static void cleanup_gt(struct intel_gt_coredump *gt) 1033 { 1034 while (gt->engine) { 1035 struct intel_engine_coredump *ee = gt->engine; 1036 1037 gt->engine = ee->next; 1038 1039 i915_vma_coredump_free(ee->vma); 1040 intel_guc_capture_free_node(ee); 1041 kfree(ee); 1042 } 1043 1044 if (gt->uc) 1045 cleanup_uc(gt->uc); 1046 1047 kfree(gt); 1048 } 1049 1050 void __i915_gpu_coredump_free(struct kref *error_ref) 1051 { 1052 struct i915_gpu_coredump *error = 1053 container_of(error_ref, typeof(*error), ref); 1054 1055 while (error->gt) { 1056 struct intel_gt_coredump *gt = error->gt; 1057 1058 error->gt = gt->next; 1059 cleanup_gt(gt); 1060 } 1061 1062 intel_display_snapshot_free(error->display_snapshot); 1063 1064 cleanup_params(error); 1065 1066 err_free_sgl(error->sgl); 1067 kfree(error); 1068 } 1069 1070 static struct i915_vma_coredump * 1071 i915_vma_coredump_create(const struct intel_gt *gt, 1072 const struct i915_vma_resource *vma_res, 1073 struct i915_vma_compress *compress, 1074 const char *name) 1075 1076 { 1077 struct i915_ggtt *ggtt = gt->ggtt; 1078 const u64 slot = ggtt->error_capture.start; 1079 struct i915_vma_coredump *dst; 1080 struct sgt_iter iter; 1081 int ret; 1082 1083 might_sleep(); 1084 1085 if (!vma_res || !vma_res->bi.pages || !compress) 1086 return NULL; 1087 1088 dst = kmalloc(sizeof(*dst), ALLOW_FAIL); 1089 if (!dst) 1090 return NULL; 1091 1092 if (!compress_start(compress)) { 1093 kfree(dst); 1094 return NULL; 1095 } 1096 1097 INIT_LIST_HEAD(&dst->page_list); 1098 strscpy(dst->name, name); 1099 dst->next = NULL; 1100 1101 dst->gtt_offset = vma_res->start; 1102 dst->gtt_size = vma_res->node_size; 1103 dst->gtt_page_sizes = vma_res->page_sizes_gtt; 1104 dst->unused = 0; 1105 1106 ret = -EINVAL; 1107 if (drm_mm_node_allocated(&ggtt->error_capture)) { 1108 void __iomem *s; 1109 dma_addr_t dma; 1110 1111 for_each_sgt_daddr(dma, iter, vma_res->bi.pages) { 1112 mutex_lock(&ggtt->error_mutex); 1113 if (ggtt->vm.raw_insert_page) 1114 ggtt->vm.raw_insert_page(&ggtt->vm, dma, slot, 1115 i915_gem_get_pat_index(gt->i915, 1116 I915_CACHE_NONE), 1117 0); 1118 else 1119 ggtt->vm.insert_page(&ggtt->vm, dma, slot, 1120 i915_gem_get_pat_index(gt->i915, 1121 I915_CACHE_NONE), 1122 0); 1123 mb(); 1124 1125 s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE); 1126 ret = compress_page(compress, 1127 (void __force *)s, dst, 1128 true); 1129 io_mapping_unmap(s); 1130 1131 mb(); 1132 ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE); 1133 mutex_unlock(&ggtt->error_mutex); 1134 if (ret) 1135 break; 1136 } 1137 } else if (vma_res->bi.lmem) { 1138 struct intel_memory_region *mem = vma_res->mr; 1139 dma_addr_t dma; 1140 1141 for_each_sgt_daddr(dma, iter, vma_res->bi.pages) { 1142 dma_addr_t offset = dma - mem->region.start; 1143 void __iomem *s; 1144 1145 if (offset + PAGE_SIZE > resource_size(&mem->io)) { 1146 ret = -EINVAL; 1147 break; 1148 } 1149 1150 s = io_mapping_map_wc(&mem->iomap, offset, PAGE_SIZE); 1151 ret = compress_page(compress, 1152 (void __force *)s, dst, 1153 true); 1154 io_mapping_unmap(s); 1155 if (ret) 1156 break; 1157 } 1158 } else { 1159 struct page *page; 1160 1161 for_each_sgt_page(page, iter, vma_res->bi.pages) { 1162 void *s; 1163 1164 drm_clflush_pages(&page, 1); 1165 1166 s = kmap_local_page(page); 1167 ret = compress_page(compress, s, dst, false); 1168 kunmap_local(s); 1169 1170 drm_clflush_pages(&page, 1); 1171 1172 if (ret) 1173 break; 1174 } 1175 } 1176 1177 if (ret || compress_flush(compress, dst)) { 1178 struct page *page, *n; 1179 1180 list_for_each_entry_safe_reverse(page, n, &dst->page_list, lru) { 1181 list_del_init(&page->lru); 1182 pool_free(&compress->pool, page_address(page)); 1183 } 1184 1185 kfree(dst); 1186 dst = NULL; 1187 } 1188 compress_finish(compress); 1189 1190 return dst; 1191 } 1192 1193 static void gt_record_fences(struct intel_gt_coredump *gt) 1194 { 1195 struct i915_ggtt *ggtt = gt->_gt->ggtt; 1196 struct intel_uncore *uncore = gt->_gt->uncore; 1197 int i; 1198 1199 if (GRAPHICS_VER(uncore->i915) >= 6) { 1200 for (i = 0; i < ggtt->num_fences; i++) 1201 gt->fence[i] = 1202 intel_uncore_read64(uncore, 1203 FENCE_REG_GEN6_LO(i)); 1204 } else if (GRAPHICS_VER(uncore->i915) >= 4) { 1205 for (i = 0; i < ggtt->num_fences; i++) 1206 gt->fence[i] = 1207 intel_uncore_read64(uncore, 1208 FENCE_REG_965_LO(i)); 1209 } else { 1210 for (i = 0; i < ggtt->num_fences; i++) 1211 gt->fence[i] = 1212 intel_uncore_read(uncore, FENCE_REG(i)); 1213 } 1214 gt->nfence = i; 1215 } 1216 1217 static void engine_record_registers(struct intel_engine_coredump *ee) 1218 { 1219 const struct intel_engine_cs *engine = ee->engine; 1220 struct drm_i915_private *i915 = engine->i915; 1221 1222 if (GRAPHICS_VER(i915) >= 6) { 1223 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL); 1224 1225 /* 1226 * For the media GT, this ring fault register is not replicated, 1227 * so don't do multicast/replicated register read/write 1228 * operation on it. 1229 */ 1230 if (MEDIA_VER(i915) >= 13 && engine->gt->type == GT_MEDIA) 1231 ee->fault_reg = intel_uncore_read(engine->uncore, 1232 XELPMP_RING_FAULT_REG); 1233 else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) 1234 ee->fault_reg = intel_gt_mcr_read_any(engine->gt, 1235 XEHP_RING_FAULT_REG); 1236 else if (GRAPHICS_VER(i915) >= 12) 1237 ee->fault_reg = intel_uncore_read(engine->uncore, 1238 GEN12_RING_FAULT_REG); 1239 else if (GRAPHICS_VER(i915) >= 8) 1240 ee->fault_reg = intel_uncore_read(engine->uncore, 1241 GEN8_RING_FAULT_REG); 1242 else 1243 ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine); 1244 } 1245 1246 if (GRAPHICS_VER(i915) >= 4) { 1247 ee->esr = ENGINE_READ(engine, RING_ESR); 1248 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD); 1249 ee->ipeir = ENGINE_READ(engine, RING_IPEIR); 1250 ee->ipehr = ENGINE_READ(engine, RING_IPEHR); 1251 ee->instps = ENGINE_READ(engine, RING_INSTPS); 1252 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR); 1253 ee->ccid = ENGINE_READ(engine, CCID); 1254 if (GRAPHICS_VER(i915) >= 8) { 1255 ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32; 1256 ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32; 1257 } 1258 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE); 1259 } else { 1260 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX); 1261 ee->ipeir = ENGINE_READ(engine, IPEIR); 1262 ee->ipehr = ENGINE_READ(engine, IPEHR); 1263 } 1264 1265 if (GRAPHICS_VER(i915) >= 11) { 1266 ee->cmd_cctl = ENGINE_READ(engine, RING_CMD_CCTL); 1267 ee->cscmdop = ENGINE_READ(engine, RING_CSCMDOP); 1268 ee->ctx_sr_ctl = ENGINE_READ(engine, RING_CTX_SR_CTL); 1269 ee->dma_faddr_hi = ENGINE_READ(engine, RING_DMA_FADD_UDW); 1270 ee->dma_faddr_lo = ENGINE_READ(engine, RING_DMA_FADD); 1271 ee->nopid = ENGINE_READ(engine, RING_NOPID); 1272 ee->excc = ENGINE_READ(engine, RING_EXCC); 1273 } 1274 1275 intel_engine_get_instdone(engine, &ee->instdone); 1276 1277 ee->instpm = ENGINE_READ(engine, RING_INSTPM); 1278 ee->acthd = intel_engine_get_active_head(engine); 1279 ee->start = ENGINE_READ(engine, RING_START); 1280 ee->head = ENGINE_READ(engine, RING_HEAD); 1281 ee->tail = ENGINE_READ(engine, RING_TAIL); 1282 ee->ctl = ENGINE_READ(engine, RING_CTL); 1283 if (GRAPHICS_VER(i915) > 2) 1284 ee->mode = ENGINE_READ(engine, RING_MI_MODE); 1285 1286 if (!HWS_NEEDS_PHYSICAL(i915)) { 1287 i915_reg_t mmio; 1288 1289 if (GRAPHICS_VER(i915) == 7) { 1290 switch (engine->id) { 1291 default: 1292 MISSING_CASE(engine->id); 1293 fallthrough; 1294 case RCS0: 1295 mmio = RENDER_HWS_PGA_GEN7; 1296 break; 1297 case BCS0: 1298 mmio = BLT_HWS_PGA_GEN7; 1299 break; 1300 case VCS0: 1301 mmio = BSD_HWS_PGA_GEN7; 1302 break; 1303 case VECS0: 1304 mmio = VEBOX_HWS_PGA_GEN7; 1305 break; 1306 } 1307 } else if (GRAPHICS_VER(engine->i915) == 6) { 1308 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); 1309 } else { 1310 /* XXX: gen8 returns to sanity */ 1311 mmio = RING_HWS_PGA(engine->mmio_base); 1312 } 1313 1314 ee->hws = intel_uncore_read(engine->uncore, mmio); 1315 } 1316 1317 ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine); 1318 1319 if (HAS_PPGTT(i915)) { 1320 int i; 1321 1322 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7); 1323 1324 if (GRAPHICS_VER(i915) == 6) { 1325 ee->vm_info.pp_dir_base = 1326 ENGINE_READ(engine, RING_PP_DIR_BASE_READ); 1327 } else if (GRAPHICS_VER(i915) == 7) { 1328 ee->vm_info.pp_dir_base = 1329 ENGINE_READ(engine, RING_PP_DIR_BASE); 1330 } else if (GRAPHICS_VER(i915) >= 8) { 1331 u32 base = engine->mmio_base; 1332 1333 for (i = 0; i < 4; i++) { 1334 ee->vm_info.pdp[i] = 1335 intel_uncore_read(engine->uncore, 1336 GEN8_RING_PDP_UDW(base, i)); 1337 ee->vm_info.pdp[i] <<= 32; 1338 ee->vm_info.pdp[i] |= 1339 intel_uncore_read(engine->uncore, 1340 GEN8_RING_PDP_LDW(base, i)); 1341 } 1342 } 1343 } 1344 } 1345 1346 static void record_request(const struct i915_request *request, 1347 struct i915_request_coredump *erq) 1348 { 1349 erq->flags = request->fence.flags; 1350 erq->context = request->fence.context; 1351 erq->seqno = request->fence.seqno; 1352 erq->sched_attr = request->sched.attr; 1353 erq->head = request->head; 1354 erq->tail = request->tail; 1355 1356 erq->pid = 0; 1357 rcu_read_lock(); 1358 if (!intel_context_is_closed(request->context)) { 1359 const struct i915_gem_context *ctx; 1360 1361 ctx = rcu_dereference(request->context->gem_context); 1362 if (ctx) 1363 erq->pid = pid_nr(ctx->pid); 1364 } 1365 rcu_read_unlock(); 1366 } 1367 1368 static void engine_record_execlists(struct intel_engine_coredump *ee) 1369 { 1370 const struct intel_engine_execlists * const el = &ee->engine->execlists; 1371 struct i915_request * const *port = el->active; 1372 unsigned int n = 0; 1373 1374 while (*port) 1375 record_request(*port++, &ee->execlist[n++]); 1376 1377 ee->num_ports = n; 1378 } 1379 1380 static bool record_context(struct i915_gem_context_coredump *e, 1381 struct intel_context *ce) 1382 { 1383 struct i915_gem_context *ctx; 1384 struct task_struct *task; 1385 bool simulated; 1386 1387 rcu_read_lock(); 1388 ctx = rcu_dereference(ce->gem_context); 1389 if (ctx && !kref_get_unless_zero(&ctx->ref)) 1390 ctx = NULL; 1391 rcu_read_unlock(); 1392 if (!ctx) 1393 return true; 1394 1395 rcu_read_lock(); 1396 task = pid_task(ctx->pid, PIDTYPE_PID); 1397 if (task) { 1398 strscpy(e->comm, task->comm); 1399 e->pid = task->pid; 1400 } 1401 rcu_read_unlock(); 1402 1403 e->sched_attr = ctx->sched; 1404 e->guilty = atomic_read(&ctx->guilty_count); 1405 e->active = atomic_read(&ctx->active_count); 1406 e->hwsp_seqno = (ce->timeline && ce->timeline->hwsp_seqno) ? 1407 *ce->timeline->hwsp_seqno : ~0U; 1408 1409 e->total_runtime = intel_context_get_total_runtime_ns(ce); 1410 e->avg_runtime = intel_context_get_avg_runtime_ns(ce); 1411 1412 simulated = i915_gem_context_no_error_capture(ctx); 1413 1414 i915_gem_context_put(ctx); 1415 return simulated; 1416 } 1417 1418 struct intel_engine_capture_vma { 1419 struct intel_engine_capture_vma *next; 1420 struct i915_vma_resource *vma_res; 1421 char name[16]; 1422 bool lockdep_cookie; 1423 }; 1424 1425 static struct intel_engine_capture_vma * 1426 capture_vma_snapshot(struct intel_engine_capture_vma *next, 1427 struct i915_vma_resource *vma_res, 1428 gfp_t gfp, const char *name) 1429 { 1430 struct intel_engine_capture_vma *c; 1431 1432 if (!vma_res) 1433 return next; 1434 1435 c = kmalloc(sizeof(*c), gfp); 1436 if (!c) 1437 return next; 1438 1439 if (!i915_vma_resource_hold(vma_res, &c->lockdep_cookie)) { 1440 kfree(c); 1441 return next; 1442 } 1443 1444 strscpy(c->name, name); 1445 c->vma_res = i915_vma_resource_get(vma_res); 1446 1447 c->next = next; 1448 return c; 1449 } 1450 1451 static struct intel_engine_capture_vma * 1452 capture_vma(struct intel_engine_capture_vma *next, 1453 struct i915_vma *vma, 1454 const char *name, 1455 gfp_t gfp) 1456 { 1457 if (!vma) 1458 return next; 1459 1460 /* 1461 * If the vma isn't pinned, then the vma should be snapshotted 1462 * to a struct i915_vma_snapshot at command submission time. 1463 * Not here. 1464 */ 1465 if (GEM_WARN_ON(!i915_vma_is_pinned(vma))) 1466 return next; 1467 1468 next = capture_vma_snapshot(next, vma->resource, gfp, name); 1469 1470 return next; 1471 } 1472 1473 static struct intel_engine_capture_vma * 1474 capture_user(struct intel_engine_capture_vma *capture, 1475 const struct i915_request *rq, 1476 gfp_t gfp) 1477 { 1478 struct i915_capture_list *c; 1479 1480 for (c = rq->capture_list; c; c = c->next) 1481 capture = capture_vma_snapshot(capture, c->vma_res, gfp, 1482 "user"); 1483 1484 return capture; 1485 } 1486 1487 static void add_vma(struct intel_engine_coredump *ee, 1488 struct i915_vma_coredump *vma) 1489 { 1490 if (vma) { 1491 vma->next = ee->vma; 1492 ee->vma = vma; 1493 } 1494 } 1495 1496 static struct i915_vma_coredump * 1497 create_vma_coredump(const struct intel_gt *gt, struct i915_vma *vma, 1498 const char *name, struct i915_vma_compress *compress) 1499 { 1500 struct i915_vma_coredump *ret = NULL; 1501 struct i915_vma_resource *vma_res; 1502 bool lockdep_cookie; 1503 1504 if (!vma) 1505 return NULL; 1506 1507 vma_res = vma->resource; 1508 1509 if (i915_vma_resource_hold(vma_res, &lockdep_cookie)) { 1510 ret = i915_vma_coredump_create(gt, vma_res, compress, name); 1511 i915_vma_resource_unhold(vma_res, lockdep_cookie); 1512 } 1513 1514 return ret; 1515 } 1516 1517 static void add_vma_coredump(struct intel_engine_coredump *ee, 1518 const struct intel_gt *gt, 1519 struct i915_vma *vma, 1520 const char *name, 1521 struct i915_vma_compress *compress) 1522 { 1523 add_vma(ee, create_vma_coredump(gt, vma, name, compress)); 1524 } 1525 1526 struct intel_engine_coredump * 1527 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags) 1528 { 1529 struct intel_engine_coredump *ee; 1530 1531 ee = kzalloc(sizeof(*ee), gfp); 1532 if (!ee) 1533 return NULL; 1534 1535 ee->engine = engine; 1536 1537 if (!(dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)) { 1538 engine_record_registers(ee); 1539 engine_record_execlists(ee); 1540 } 1541 1542 return ee; 1543 } 1544 1545 static struct intel_engine_capture_vma * 1546 engine_coredump_add_context(struct intel_engine_coredump *ee, 1547 struct intel_context *ce, 1548 gfp_t gfp) 1549 { 1550 struct intel_engine_capture_vma *vma = NULL; 1551 1552 ee->simulated |= record_context(&ee->context, ce); 1553 if (ee->simulated) 1554 return NULL; 1555 1556 /* 1557 * We need to copy these to an anonymous buffer 1558 * as the simplest method to avoid being overwritten 1559 * by userspace. 1560 */ 1561 vma = capture_vma(vma, ce->ring->vma, "ring", gfp); 1562 vma = capture_vma(vma, ce->state, "HW context", gfp); 1563 1564 return vma; 1565 } 1566 1567 struct intel_engine_capture_vma * 1568 intel_engine_coredump_add_request(struct intel_engine_coredump *ee, 1569 struct i915_request *rq, 1570 gfp_t gfp) 1571 { 1572 struct intel_engine_capture_vma *vma; 1573 1574 vma = engine_coredump_add_context(ee, rq->context, gfp); 1575 if (!vma) 1576 return NULL; 1577 1578 /* 1579 * We need to copy these to an anonymous buffer 1580 * as the simplest method to avoid being overwritten 1581 * by userspace. 1582 */ 1583 vma = capture_vma_snapshot(vma, rq->batch_res, gfp, "batch"); 1584 vma = capture_user(vma, rq, gfp); 1585 1586 ee->rq_head = rq->head; 1587 ee->rq_post = rq->postfix; 1588 ee->rq_tail = rq->tail; 1589 1590 return vma; 1591 } 1592 1593 void 1594 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee, 1595 struct intel_engine_capture_vma *capture, 1596 struct i915_vma_compress *compress) 1597 { 1598 const struct intel_engine_cs *engine = ee->engine; 1599 1600 while (capture) { 1601 struct intel_engine_capture_vma *this = capture; 1602 struct i915_vma_resource *vma_res = this->vma_res; 1603 1604 add_vma(ee, 1605 i915_vma_coredump_create(engine->gt, vma_res, 1606 compress, this->name)); 1607 1608 i915_vma_resource_unhold(vma_res, this->lockdep_cookie); 1609 i915_vma_resource_put(vma_res); 1610 1611 capture = this->next; 1612 kfree(this); 1613 } 1614 1615 add_vma_coredump(ee, engine->gt, engine->status_page.vma, 1616 "HW Status", compress); 1617 1618 add_vma_coredump(ee, engine->gt, engine->wa_ctx.vma, 1619 "WA context", compress); 1620 } 1621 1622 static struct intel_engine_coredump * 1623 capture_engine(struct intel_engine_cs *engine, 1624 struct i915_vma_compress *compress, 1625 u32 dump_flags) 1626 { 1627 struct intel_engine_capture_vma *capture = NULL; 1628 struct intel_engine_coredump *ee; 1629 struct intel_context *ce = NULL; 1630 struct i915_request *rq = NULL; 1631 1632 ee = intel_engine_coredump_alloc(engine, ALLOW_FAIL, dump_flags); 1633 if (!ee) 1634 return NULL; 1635 1636 intel_engine_get_hung_entity(engine, &ce, &rq); 1637 if (rq && !i915_request_started(rq)) { 1638 /* 1639 * We want to know also what is the guc_id of the context, 1640 * but if we don't have the context reference, then skip 1641 * printing it. 1642 */ 1643 if (ce) 1644 drm_info(&engine->gt->i915->drm, 1645 "Got hung context on %s with active request %lld:%lld [0x%04X] not yet started\n", 1646 engine->name, rq->fence.context, rq->fence.seqno, ce->guc_id.id); 1647 else 1648 drm_info(&engine->gt->i915->drm, 1649 "Got hung context on %s with active request %lld:%lld not yet started\n", 1650 engine->name, rq->fence.context, rq->fence.seqno); 1651 } 1652 1653 if (rq) { 1654 capture = intel_engine_coredump_add_request(ee, rq, ATOMIC_MAYFAIL); 1655 i915_request_put(rq); 1656 } else if (ce) { 1657 capture = engine_coredump_add_context(ee, ce, ATOMIC_MAYFAIL); 1658 } 1659 1660 if (capture) { 1661 intel_engine_coredump_add_vma(ee, capture, compress); 1662 1663 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE) 1664 intel_guc_capture_get_matching_node(engine->gt, ee, ce); 1665 } else { 1666 kfree(ee); 1667 ee = NULL; 1668 } 1669 1670 return ee; 1671 } 1672 1673 static void 1674 gt_record_engines(struct intel_gt_coredump *gt, 1675 intel_engine_mask_t engine_mask, 1676 struct i915_vma_compress *compress, 1677 u32 dump_flags) 1678 { 1679 struct intel_engine_cs *engine; 1680 enum intel_engine_id id; 1681 1682 for_each_engine(engine, gt->_gt, id) { 1683 struct intel_engine_coredump *ee; 1684 1685 /* Refill our page pool before entering atomic section */ 1686 pool_refill(&compress->pool, ALLOW_FAIL); 1687 1688 ee = capture_engine(engine, compress, dump_flags); 1689 if (!ee) 1690 continue; 1691 1692 ee->hung = engine->mask & engine_mask; 1693 1694 gt->simulated |= ee->simulated; 1695 if (ee->simulated) { 1696 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE) 1697 intel_guc_capture_free_node(ee); 1698 kfree(ee); 1699 continue; 1700 } 1701 1702 ee->next = gt->engine; 1703 gt->engine = ee; 1704 } 1705 } 1706 1707 static void gt_record_guc_ctb(struct intel_ctb_coredump *saved, 1708 const struct intel_guc_ct_buffer *ctb, 1709 const void *blob_ptr, struct intel_guc *guc) 1710 { 1711 if (!ctb || !ctb->desc) 1712 return; 1713 1714 saved->raw_status = ctb->desc->status; 1715 saved->raw_head = ctb->desc->head; 1716 saved->raw_tail = ctb->desc->tail; 1717 saved->head = ctb->head; 1718 saved->tail = ctb->tail; 1719 saved->size = ctb->size; 1720 saved->desc_offset = ((void *)ctb->desc) - blob_ptr; 1721 saved->cmds_offset = ((void *)ctb->cmds) - blob_ptr; 1722 } 1723 1724 static struct intel_uc_coredump * 1725 gt_record_uc(struct intel_gt_coredump *gt, 1726 struct i915_vma_compress *compress) 1727 { 1728 const struct intel_uc *uc = >->_gt->uc; 1729 struct intel_uc_coredump *error_uc; 1730 1731 error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL); 1732 if (!error_uc) 1733 return NULL; 1734 1735 memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw)); 1736 memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw)); 1737 1738 error_uc->guc_fw.file_selected.path = kstrdup(uc->guc.fw.file_selected.path, ALLOW_FAIL); 1739 error_uc->huc_fw.file_selected.path = kstrdup(uc->huc.fw.file_selected.path, ALLOW_FAIL); 1740 error_uc->guc_fw.file_wanted.path = kstrdup(uc->guc.fw.file_wanted.path, ALLOW_FAIL); 1741 error_uc->huc_fw.file_wanted.path = kstrdup(uc->huc.fw.file_wanted.path, ALLOW_FAIL); 1742 1743 /* 1744 * Save the GuC log and include a timestamp reference for converting the 1745 * log times to system times (in conjunction with the error->boottime and 1746 * gt->clock_frequency fields saved elsewhere). 1747 */ 1748 error_uc->guc.timestamp = intel_uncore_read(gt->_gt->uncore, GUCPMTIMESTAMP); 1749 error_uc->guc.vma_log = create_vma_coredump(gt->_gt, uc->guc.log.vma, 1750 "GuC log buffer", compress); 1751 error_uc->guc.vma_ctb = create_vma_coredump(gt->_gt, uc->guc.ct.vma, 1752 "GuC CT buffer", compress); 1753 error_uc->guc.last_fence = uc->guc.ct.requests.last_fence; 1754 gt_record_guc_ctb(error_uc->guc.ctb + 0, &uc->guc.ct.ctbs.send, 1755 uc->guc.ct.ctbs.send.desc, (struct intel_guc *)&uc->guc); 1756 gt_record_guc_ctb(error_uc->guc.ctb + 1, &uc->guc.ct.ctbs.recv, 1757 uc->guc.ct.ctbs.send.desc, (struct intel_guc *)&uc->guc); 1758 1759 return error_uc; 1760 } 1761 1762 /* Capture all other registers that GuC doesn't capture. */ 1763 static void gt_record_global_nonguc_regs(struct intel_gt_coredump *gt) 1764 { 1765 struct intel_uncore *uncore = gt->_gt->uncore; 1766 struct drm_i915_private *i915 = uncore->i915; 1767 int i; 1768 1769 if (IS_VALLEYVIEW(i915)) { 1770 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1771 gt->ngtier = 1; 1772 } else if (GRAPHICS_VER(i915) >= 11) { 1773 gt->gtier[0] = 1774 intel_uncore_read(uncore, 1775 GEN11_RENDER_COPY_INTR_ENABLE); 1776 gt->gtier[1] = 1777 intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE); 1778 gt->gtier[2] = 1779 intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE); 1780 gt->gtier[3] = 1781 intel_uncore_read(uncore, 1782 GEN11_GPM_WGBOXPERF_INTR_ENABLE); 1783 gt->gtier[4] = 1784 intel_uncore_read(uncore, 1785 GEN11_CRYPTO_RSVD_INTR_ENABLE); 1786 gt->gtier[5] = 1787 intel_uncore_read(uncore, 1788 GEN11_GUNIT_CSME_INTR_ENABLE); 1789 gt->ngtier = 6; 1790 } else if (GRAPHICS_VER(i915) >= 8) { 1791 for (i = 0; i < 4; i++) 1792 gt->gtier[i] = 1793 intel_uncore_read(uncore, GEN8_GT_IER(i)); 1794 gt->ngtier = 4; 1795 } else if (GRAPHICS_VER(i915) >= 5) { 1796 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1797 gt->ngtier = 1; 1798 } else { 1799 gt->gtier[0] = intel_uncore_read(uncore, GEN2_IER); 1800 gt->ngtier = 1; 1801 } 1802 1803 gt->eir = intel_uncore_read(uncore, EIR); 1804 gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER); 1805 } 1806 1807 /* 1808 * Capture all registers that relate to workload submission. 1809 * NOTE: In GuC submission, when GuC resets an engine, it can dump these for us 1810 */ 1811 static void gt_record_global_regs(struct intel_gt_coredump *gt) 1812 { 1813 struct intel_uncore *uncore = gt->_gt->uncore; 1814 struct drm_i915_private *i915 = uncore->i915; 1815 int i; 1816 1817 /* 1818 * General organization 1819 * 1. Registers specific to a single generation 1820 * 2. Registers which belong to multiple generations 1821 * 3. Feature specific registers. 1822 * 4. Everything else 1823 * Please try to follow the order. 1824 */ 1825 1826 /* 1: Registers specific to a single generation */ 1827 if (IS_VALLEYVIEW(i915)) 1828 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV); 1829 1830 if (GRAPHICS_VER(i915) == 7) 1831 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT); 1832 1833 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) { 1834 gt->fault_data0 = intel_gt_mcr_read_any((struct intel_gt *)gt->_gt, 1835 XEHP_FAULT_TLB_DATA0); 1836 gt->fault_data1 = intel_gt_mcr_read_any((struct intel_gt *)gt->_gt, 1837 XEHP_FAULT_TLB_DATA1); 1838 } else if (GRAPHICS_VER(i915) >= 12) { 1839 gt->fault_data0 = intel_uncore_read(uncore, 1840 GEN12_FAULT_TLB_DATA0); 1841 gt->fault_data1 = intel_uncore_read(uncore, 1842 GEN12_FAULT_TLB_DATA1); 1843 } else if (GRAPHICS_VER(i915) >= 8) { 1844 gt->fault_data0 = intel_uncore_read(uncore, 1845 GEN8_FAULT_TLB_DATA0); 1846 gt->fault_data1 = intel_uncore_read(uncore, 1847 GEN8_FAULT_TLB_DATA1); 1848 } 1849 1850 if (GRAPHICS_VER(i915) == 6) { 1851 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE); 1852 gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL); 1853 gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE); 1854 } 1855 1856 /* 2: Registers which belong to multiple generations */ 1857 if (GRAPHICS_VER(i915) >= 7) 1858 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT); 1859 1860 if (GRAPHICS_VER(i915) >= 6) { 1861 if (GRAPHICS_VER(i915) < 12) { 1862 gt->error = intel_uncore_read(uncore, ERROR_GEN6); 1863 gt->done_reg = intel_uncore_read(uncore, DONE_REG); 1864 } 1865 } 1866 1867 /* 3: Feature specific registers */ 1868 if (IS_GRAPHICS_VER(i915, 6, 7)) { 1869 gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK); 1870 gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS); 1871 } 1872 1873 if (IS_GRAPHICS_VER(i915, 8, 11)) 1874 gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN); 1875 1876 if (GRAPHICS_VER(i915) == 12) 1877 gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG); 1878 1879 if (GRAPHICS_VER(i915) >= 12) { 1880 for (i = 0; i < I915_MAX_SFC; i++) { 1881 /* 1882 * SFC_DONE resides in the VD forcewake domain, so it 1883 * only exists if the corresponding VCS engine is 1884 * present. 1885 */ 1886 if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || 1887 !HAS_ENGINE(gt->_gt, _VCS(i * 2))) 1888 continue; 1889 1890 gt->sfc_done[i] = 1891 intel_uncore_read(uncore, GEN12_SFC_DONE(i)); 1892 } 1893 1894 gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE); 1895 } 1896 } 1897 1898 static void gt_record_info(struct intel_gt_coredump *gt) 1899 { 1900 memcpy(>->info, >->_gt->info, sizeof(struct intel_gt_info)); 1901 gt->clock_frequency = gt->_gt->clock_frequency; 1902 gt->clock_period_ns = gt->_gt->clock_period_ns; 1903 } 1904 1905 /* 1906 * Generate a semi-unique error code. The code is not meant to have meaning, The 1907 * code's only purpose is to try to prevent false duplicated bug reports by 1908 * grossly estimating a GPU error state. 1909 * 1910 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 1911 * the hang if we could strip the GTT offset information from it. 1912 * 1913 * It's only a small step better than a random number in its current form. 1914 */ 1915 static u32 generate_ecode(const struct intel_engine_coredump *ee) 1916 { 1917 /* 1918 * IPEHR would be an ideal way to detect errors, as it's the gross 1919 * measure of "the command that hung." However, has some very common 1920 * synchronization commands which almost always appear in the case 1921 * strictly a client bug. Use instdone to differentiate those some. 1922 */ 1923 return ee ? ee->ipehr ^ ee->instdone.instdone : 0; 1924 } 1925 1926 static const char *error_msg(struct i915_gpu_coredump *error) 1927 { 1928 struct intel_engine_coredump *first = NULL; 1929 unsigned int hung_classes = 0; 1930 struct intel_gt_coredump *gt; 1931 int len; 1932 1933 for (gt = error->gt; gt; gt = gt->next) { 1934 struct intel_engine_coredump *cs; 1935 1936 for (cs = gt->engine; cs; cs = cs->next) { 1937 if (cs->hung) { 1938 hung_classes |= BIT(cs->engine->uabi_class); 1939 if (!first) 1940 first = cs; 1941 } 1942 } 1943 } 1944 1945 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1946 "GPU HANG: ecode %d:%x:%08x", 1947 GRAPHICS_VER(error->i915), hung_classes, 1948 generate_ecode(first)); 1949 if (first && first->context.pid) { 1950 /* Just show the first executing process, more is confusing */ 1951 len += scnprintf(error->error_msg + len, 1952 sizeof(error->error_msg) - len, 1953 ", in %s [%d]", 1954 first->context.comm, first->context.pid); 1955 } 1956 1957 return error->error_msg; 1958 } 1959 1960 static void capture_gen(struct i915_gpu_coredump *error) 1961 { 1962 struct drm_i915_private *i915 = error->i915; 1963 1964 error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count); 1965 error->suspended = pm_runtime_suspended(i915->drm.dev); 1966 1967 error->iommu = i915_vtd_active(i915); 1968 error->reset_count = i915_reset_count(&i915->gpu_error); 1969 error->suspend_count = i915->suspend_count; 1970 1971 i915_params_copy(&error->params, &i915->params); 1972 memcpy(&error->device_info, 1973 INTEL_INFO(i915), 1974 sizeof(error->device_info)); 1975 memcpy(&error->runtime_info, 1976 RUNTIME_INFO(i915), 1977 sizeof(error->runtime_info)); 1978 error->driver_caps = i915->caps; 1979 } 1980 1981 struct i915_gpu_coredump * 1982 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp) 1983 { 1984 struct i915_gpu_coredump *error; 1985 1986 if (!i915->params.error_capture) 1987 return NULL; 1988 1989 error = kzalloc(sizeof(*error), gfp); 1990 if (!error) 1991 return NULL; 1992 1993 kref_init(&error->ref); 1994 error->i915 = i915; 1995 1996 error->time = ktime_get_real(); 1997 error->boottime = ktime_get_boottime(); 1998 error->uptime = ktime_sub(ktime_get(), to_gt(i915)->last_init_time); 1999 error->capture = jiffies; 2000 2001 capture_gen(error); 2002 2003 return error; 2004 } 2005 2006 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x)) 2007 2008 struct intel_gt_coredump * 2009 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags) 2010 { 2011 struct intel_gt_coredump *gc; 2012 2013 gc = kzalloc(sizeof(*gc), gfp); 2014 if (!gc) 2015 return NULL; 2016 2017 gc->_gt = gt; 2018 gc->awake = intel_gt_pm_is_awake(gt); 2019 2020 gt_record_global_nonguc_regs(gc); 2021 2022 /* 2023 * GuC dumps global, eng-class and eng-instance registers 2024 * (that can change as part of engine state during execution) 2025 * before an engine is reset due to a hung context. 2026 * GuC captures and reports all three groups of registers 2027 * together as a single set before the engine is reset. 2028 * Thus, if GuC triggered the context reset we retrieve 2029 * the register values as part of gt_record_engines. 2030 */ 2031 if (!(dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)) 2032 gt_record_global_regs(gc); 2033 2034 gt_record_fences(gc); 2035 2036 return gc; 2037 } 2038 2039 struct i915_vma_compress * 2040 i915_vma_capture_prepare(struct intel_gt_coredump *gt) 2041 { 2042 struct i915_vma_compress *compress; 2043 2044 compress = kmalloc(sizeof(*compress), ALLOW_FAIL); 2045 if (!compress) 2046 return NULL; 2047 2048 if (!compress_init(compress)) { 2049 kfree(compress); 2050 return NULL; 2051 } 2052 2053 return compress; 2054 } 2055 2056 void i915_vma_capture_finish(struct intel_gt_coredump *gt, 2057 struct i915_vma_compress *compress) 2058 { 2059 if (!compress) 2060 return; 2061 2062 compress_fini(compress); 2063 kfree(compress); 2064 } 2065 2066 static struct i915_gpu_coredump * 2067 __i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags) 2068 { 2069 struct drm_i915_private *i915 = gt->i915; 2070 struct intel_display *display = i915->display; 2071 struct i915_gpu_coredump *error; 2072 2073 /* Check if GPU capture has been disabled */ 2074 error = READ_ONCE(i915->gpu_error.first_error); 2075 if (IS_ERR(error)) 2076 return error; 2077 2078 error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL); 2079 if (!error) 2080 return ERR_PTR(-ENOMEM); 2081 2082 error->gt = intel_gt_coredump_alloc(gt, ALLOW_FAIL, dump_flags); 2083 if (error->gt) { 2084 struct i915_vma_compress *compress; 2085 2086 compress = i915_vma_capture_prepare(error->gt); 2087 if (!compress) { 2088 kfree(error->gt); 2089 kfree(error); 2090 return ERR_PTR(-ENOMEM); 2091 } 2092 2093 if (INTEL_INFO(i915)->has_gt_uc) { 2094 error->gt->uc = gt_record_uc(error->gt, compress); 2095 if (error->gt->uc) { 2096 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE) 2097 error->gt->uc->guc.is_guc_capture = true; 2098 else 2099 GEM_BUG_ON(error->gt->uc->guc.is_guc_capture); 2100 } 2101 } 2102 2103 gt_record_info(error->gt); 2104 gt_record_engines(error->gt, engine_mask, compress, dump_flags); 2105 2106 2107 i915_vma_capture_finish(error->gt, compress); 2108 2109 error->simulated |= error->gt->simulated; 2110 } 2111 2112 error->display_snapshot = intel_display_snapshot_capture(display); 2113 2114 return error; 2115 } 2116 2117 static struct i915_gpu_coredump * 2118 i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags) 2119 { 2120 static DEFINE_MUTEX(capture_mutex); 2121 int ret = mutex_lock_interruptible(&capture_mutex); 2122 struct i915_gpu_coredump *dump; 2123 2124 if (ret) 2125 return ERR_PTR(ret); 2126 2127 dump = __i915_gpu_coredump(gt, engine_mask, dump_flags); 2128 mutex_unlock(&capture_mutex); 2129 2130 return dump; 2131 } 2132 2133 void i915_error_state_store(struct i915_gpu_coredump *error) 2134 { 2135 struct drm_i915_private *i915; 2136 2137 if (IS_ERR_OR_NULL(error)) 2138 return; 2139 2140 i915 = error->i915; 2141 drm_info(&i915->drm, "%s\n", error_msg(error)); 2142 2143 if (error->simulated || 2144 cmpxchg(&i915->gpu_error.first_error, NULL, error)) 2145 return; 2146 2147 i915_gpu_coredump_get(error); 2148 2149 drm_info(&i915->drm, "GPU error state saved to /sys/class/drm/card%d/error\n", 2150 i915->drm.primary->index); 2151 } 2152 2153 /** 2154 * i915_capture_error_state - capture an error record for later analysis 2155 * @gt: intel_gt which originated the hang 2156 * @engine_mask: hung engines 2157 * @dump_flags: dump flags 2158 * 2159 * Should be called when an error is detected (either a hang or an error 2160 * interrupt) to capture error state from the time of the error. Fills 2161 * out a structure which becomes available in debugfs for user level tools 2162 * to pick up. 2163 */ 2164 void i915_capture_error_state(struct intel_gt *gt, 2165 intel_engine_mask_t engine_mask, u32 dump_flags) 2166 { 2167 struct i915_gpu_coredump *error; 2168 2169 error = i915_gpu_coredump(gt, engine_mask, dump_flags); 2170 if (IS_ERR(error)) { 2171 cmpxchg(>->i915->gpu_error.first_error, NULL, error); 2172 return; 2173 } 2174 2175 i915_error_state_store(error); 2176 i915_gpu_coredump_put(error); 2177 } 2178 2179 static struct i915_gpu_coredump * 2180 i915_first_error_state(struct drm_i915_private *i915) 2181 { 2182 struct i915_gpu_coredump *error; 2183 2184 spin_lock_irq(&i915->gpu_error.lock); 2185 error = i915->gpu_error.first_error; 2186 if (!IS_ERR_OR_NULL(error)) 2187 i915_gpu_coredump_get(error); 2188 spin_unlock_irq(&i915->gpu_error.lock); 2189 2190 return error; 2191 } 2192 2193 void i915_reset_error_state(struct drm_i915_private *i915) 2194 { 2195 struct i915_gpu_coredump *error; 2196 2197 spin_lock_irq(&i915->gpu_error.lock); 2198 error = i915->gpu_error.first_error; 2199 if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */ 2200 i915->gpu_error.first_error = NULL; 2201 spin_unlock_irq(&i915->gpu_error.lock); 2202 2203 if (!IS_ERR_OR_NULL(error)) 2204 i915_gpu_coredump_put(error); 2205 } 2206 2207 void i915_disable_error_state(struct drm_i915_private *i915, int err) 2208 { 2209 spin_lock_irq(&i915->gpu_error.lock); 2210 if (!i915->gpu_error.first_error) 2211 i915->gpu_error.first_error = ERR_PTR(err); 2212 spin_unlock_irq(&i915->gpu_error.lock); 2213 } 2214 2215 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) 2216 void intel_klog_error_capture(struct intel_gt *gt, 2217 intel_engine_mask_t engine_mask) 2218 { 2219 static int g_count; 2220 struct drm_i915_private *i915 = gt->i915; 2221 struct i915_gpu_coredump *error; 2222 intel_wakeref_t wakeref; 2223 size_t buf_size = PAGE_SIZE * 128; 2224 size_t pos_err; 2225 char *buf, *ptr, *next; 2226 int l_count = g_count++; 2227 int line = 0; 2228 2229 /* Can't allocate memory during a reset */ 2230 if (test_bit(I915_RESET_BACKOFF, >->reset.flags)) { 2231 drm_err(>->i915->drm, "[Capture/%d.%d] Inside GT reset, skipping error capture :(\n", 2232 l_count, line++); 2233 return; 2234 } 2235 2236 error = READ_ONCE(i915->gpu_error.first_error); 2237 if (error) { 2238 drm_err(&i915->drm, "[Capture/%d.%d] Clearing existing error capture first...\n", 2239 l_count, line++); 2240 i915_reset_error_state(i915); 2241 } 2242 2243 with_intel_runtime_pm(&i915->runtime_pm, wakeref) 2244 error = i915_gpu_coredump(gt, engine_mask, CORE_DUMP_FLAG_NONE); 2245 2246 if (IS_ERR(error)) { 2247 drm_err(&i915->drm, "[Capture/%d.%d] Failed to capture error capture: %ld!\n", 2248 l_count, line++, PTR_ERR(error)); 2249 return; 2250 } 2251 2252 buf = kvmalloc(buf_size, GFP_KERNEL); 2253 if (!buf) { 2254 drm_err(&i915->drm, "[Capture/%d.%d] Failed to allocate buffer for error capture!\n", 2255 l_count, line++); 2256 i915_gpu_coredump_put(error); 2257 return; 2258 } 2259 2260 drm_info(&i915->drm, "[Capture/%d.%d] Dumping i915 error capture for %ps...\n", 2261 l_count, line++, __builtin_return_address(0)); 2262 2263 /* Largest string length safe to print via dmesg */ 2264 # define MAX_CHUNK 800 2265 2266 pos_err = 0; 2267 while (1) { 2268 ssize_t got = i915_gpu_coredump_copy_to_buffer(error, buf, pos_err, buf_size - 1); 2269 2270 if (got <= 0) 2271 break; 2272 2273 buf[got] = 0; 2274 pos_err += got; 2275 2276 ptr = buf; 2277 while (got > 0) { 2278 size_t count; 2279 char tag[2]; 2280 2281 next = strnchr(ptr, got, '\n'); 2282 if (next) { 2283 count = next - ptr; 2284 *next = 0; 2285 tag[0] = '>'; 2286 tag[1] = '<'; 2287 } else { 2288 count = got; 2289 tag[0] = '}'; 2290 tag[1] = '{'; 2291 } 2292 2293 if (count > MAX_CHUNK) { 2294 size_t pos; 2295 char *ptr2 = ptr; 2296 2297 for (pos = MAX_CHUNK; pos < count; pos += MAX_CHUNK) { 2298 char chr = ptr[pos]; 2299 2300 ptr[pos] = 0; 2301 drm_info(&i915->drm, "[Capture/%d.%d] }%s{\n", 2302 l_count, line++, ptr2); 2303 ptr[pos] = chr; 2304 ptr2 = ptr + pos; 2305 2306 /* 2307 * If spewing large amounts of data via a serial console, 2308 * this can be a very slow process. So be friendly and try 2309 * not to cause 'softlockup on CPU' problems. 2310 */ 2311 cond_resched(); 2312 } 2313 2314 if (ptr2 < (ptr + count)) 2315 drm_info(&i915->drm, "[Capture/%d.%d] %c%s%c\n", 2316 l_count, line++, tag[0], ptr2, tag[1]); 2317 else if (tag[0] == '>') 2318 drm_info(&i915->drm, "[Capture/%d.%d] ><\n", 2319 l_count, line++); 2320 } else { 2321 drm_info(&i915->drm, "[Capture/%d.%d] %c%s%c\n", 2322 l_count, line++, tag[0], ptr, tag[1]); 2323 } 2324 2325 ptr = next; 2326 got -= count; 2327 if (next) { 2328 ptr++; 2329 got--; 2330 } 2331 2332 /* As above. */ 2333 cond_resched(); 2334 } 2335 2336 if (got) 2337 drm_info(&i915->drm, "[Capture/%d.%d] Got %zd bytes remaining!\n", 2338 l_count, line++, got); 2339 } 2340 2341 kvfree(buf); 2342 2343 drm_info(&i915->drm, "[Capture/%d.%d] Dumped %zd bytes\n", l_count, line++, pos_err); 2344 } 2345 #endif 2346 2347 static ssize_t gpu_state_read(struct file *file, char __user *ubuf, 2348 size_t count, loff_t *pos) 2349 { 2350 struct i915_gpu_coredump *error; 2351 ssize_t ret; 2352 void *buf; 2353 2354 error = file->private_data; 2355 if (!error) 2356 return 0; 2357 2358 /* Bounce buffer required because of kernfs __user API convenience. */ 2359 buf = kmalloc(count, GFP_KERNEL); 2360 if (!buf) 2361 return -ENOMEM; 2362 2363 ret = i915_gpu_coredump_copy_to_buffer(error, buf, *pos, count); 2364 if (ret <= 0) 2365 goto out; 2366 2367 if (!copy_to_user(ubuf, buf, ret)) 2368 *pos += ret; 2369 else 2370 ret = -EFAULT; 2371 2372 out: 2373 kfree(buf); 2374 return ret; 2375 } 2376 2377 static int gpu_state_release(struct inode *inode, struct file *file) 2378 { 2379 i915_gpu_coredump_put(file->private_data); 2380 return 0; 2381 } 2382 2383 static int i915_gpu_info_open(struct inode *inode, struct file *file) 2384 { 2385 struct drm_i915_private *i915 = inode->i_private; 2386 struct i915_gpu_coredump *gpu; 2387 intel_wakeref_t wakeref; 2388 2389 gpu = NULL; 2390 with_intel_runtime_pm(&i915->runtime_pm, wakeref) 2391 gpu = i915_gpu_coredump(to_gt(i915), ALL_ENGINES, CORE_DUMP_FLAG_NONE); 2392 2393 if (IS_ERR(gpu)) 2394 return PTR_ERR(gpu); 2395 2396 file->private_data = gpu; 2397 return 0; 2398 } 2399 2400 static const struct file_operations i915_gpu_info_fops = { 2401 .owner = THIS_MODULE, 2402 .open = i915_gpu_info_open, 2403 .read = gpu_state_read, 2404 .llseek = default_llseek, 2405 .release = gpu_state_release, 2406 }; 2407 2408 static ssize_t 2409 i915_error_state_write(struct file *filp, 2410 const char __user *ubuf, 2411 size_t cnt, 2412 loff_t *ppos) 2413 { 2414 struct i915_gpu_coredump *error = filp->private_data; 2415 2416 if (!error) 2417 return 0; 2418 2419 drm_dbg(&error->i915->drm, "Resetting error state\n"); 2420 i915_reset_error_state(error->i915); 2421 2422 return cnt; 2423 } 2424 2425 static int i915_error_state_open(struct inode *inode, struct file *file) 2426 { 2427 struct i915_gpu_coredump *error; 2428 2429 error = i915_first_error_state(inode->i_private); 2430 if (IS_ERR(error)) 2431 return PTR_ERR(error); 2432 2433 file->private_data = error; 2434 return 0; 2435 } 2436 2437 static const struct file_operations i915_error_state_fops = { 2438 .owner = THIS_MODULE, 2439 .open = i915_error_state_open, 2440 .read = gpu_state_read, 2441 .write = i915_error_state_write, 2442 .llseek = default_llseek, 2443 .release = gpu_state_release, 2444 }; 2445 2446 void i915_gpu_error_debugfs_register(struct drm_i915_private *i915) 2447 { 2448 struct drm_minor *minor = i915->drm.primary; 2449 2450 debugfs_create_file("i915_error_state", 0644, minor->debugfs_root, i915, 2451 &i915_error_state_fops); 2452 debugfs_create_file("i915_gpu_info", 0644, minor->debugfs_root, i915, 2453 &i915_gpu_info_fops); 2454 } 2455 2456 static ssize_t error_state_read(struct file *filp, struct kobject *kobj, 2457 const struct bin_attribute *attr, char *buf, 2458 loff_t off, size_t count) 2459 { 2460 2461 struct device *kdev = kobj_to_dev(kobj); 2462 struct drm_i915_private *i915 = kdev_minor_to_i915(kdev); 2463 struct i915_gpu_coredump *gpu; 2464 ssize_t ret = 0; 2465 2466 /* 2467 * FIXME: Concurrent clients triggering resets and reading + clearing 2468 * dumps can cause inconsistent sysfs reads when a user calls in with a 2469 * non-zero offset to complete a prior partial read but the 2470 * gpu_coredump has been cleared or replaced. 2471 */ 2472 2473 gpu = i915_first_error_state(i915); 2474 if (IS_ERR(gpu)) { 2475 ret = PTR_ERR(gpu); 2476 } else if (gpu) { 2477 ret = i915_gpu_coredump_copy_to_buffer(gpu, buf, off, count); 2478 i915_gpu_coredump_put(gpu); 2479 } else { 2480 const char *str = "No error state collected\n"; 2481 size_t len = strlen(str); 2482 2483 if (off < len) { 2484 ret = min_t(size_t, count, len - off); 2485 memcpy(buf, str + off, ret); 2486 } 2487 } 2488 2489 return ret; 2490 } 2491 2492 static ssize_t error_state_write(struct file *file, struct kobject *kobj, 2493 const struct bin_attribute *attr, char *buf, 2494 loff_t off, size_t count) 2495 { 2496 struct device *kdev = kobj_to_dev(kobj); 2497 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 2498 2499 drm_dbg(&dev_priv->drm, "Resetting error state\n"); 2500 i915_reset_error_state(dev_priv); 2501 2502 return count; 2503 } 2504 2505 static const struct bin_attribute error_state_attr = { 2506 .attr.name = "error", 2507 .attr.mode = S_IRUSR | S_IWUSR, 2508 .size = 0, 2509 .read = error_state_read, 2510 .write = error_state_write, 2511 }; 2512 2513 void i915_gpu_error_sysfs_setup(struct drm_i915_private *i915) 2514 { 2515 struct device *kdev = i915->drm.primary->kdev; 2516 2517 if (sysfs_create_bin_file(&kdev->kobj, &error_state_attr)) 2518 drm_err(&i915->drm, "error_state sysfs setup failed\n"); 2519 } 2520 2521 void i915_gpu_error_sysfs_teardown(struct drm_i915_private *i915) 2522 { 2523 struct device *kdev = i915->drm.primary->kdev; 2524 2525 sysfs_remove_bin_file(&kdev->kobj, &error_state_attr); 2526 } 2527