1 /* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30 #include <generated/utsrelease.h> 31 #include "i915_drv.h" 32 33 static const char *ring_str(int ring) 34 { 35 switch (ring) { 36 case RCS: return "render"; 37 case VCS: return "bsd"; 38 case BCS: return "blt"; 39 case VECS: return "vebox"; 40 case VCS2: return "bsd2"; 41 default: return ""; 42 } 43 } 44 45 static const char *pin_flag(int pinned) 46 { 47 if (pinned > 0) 48 return " P"; 49 else if (pinned < 0) 50 return " p"; 51 else 52 return ""; 53 } 54 55 static const char *tiling_flag(int tiling) 56 { 57 switch (tiling) { 58 default: 59 case I915_TILING_NONE: return ""; 60 case I915_TILING_X: return " X"; 61 case I915_TILING_Y: return " Y"; 62 } 63 } 64 65 static const char *dirty_flag(int dirty) 66 { 67 return dirty ? " dirty" : ""; 68 } 69 70 static const char *purgeable_flag(int purgeable) 71 { 72 return purgeable ? " purgeable" : ""; 73 } 74 75 static bool __i915_error_ok(struct drm_i915_error_state_buf *e) 76 { 77 78 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) { 79 e->err = -ENOSPC; 80 return false; 81 } 82 83 if (e->bytes == e->size - 1 || e->err) 84 return false; 85 86 return true; 87 } 88 89 static bool __i915_error_seek(struct drm_i915_error_state_buf *e, 90 unsigned len) 91 { 92 if (e->pos + len <= e->start) { 93 e->pos += len; 94 return false; 95 } 96 97 /* First vsnprintf needs to fit in its entirety for memmove */ 98 if (len >= e->size) { 99 e->err = -EIO; 100 return false; 101 } 102 103 return true; 104 } 105 106 static void __i915_error_advance(struct drm_i915_error_state_buf *e, 107 unsigned len) 108 { 109 /* If this is first printf in this window, adjust it so that 110 * start position matches start of the buffer 111 */ 112 113 if (e->pos < e->start) { 114 const size_t off = e->start - e->pos; 115 116 /* Should not happen but be paranoid */ 117 if (off > len || e->bytes) { 118 e->err = -EIO; 119 return; 120 } 121 122 memmove(e->buf, e->buf + off, len - off); 123 e->bytes = len - off; 124 e->pos = e->start; 125 return; 126 } 127 128 e->bytes += len; 129 e->pos += len; 130 } 131 132 static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 133 const char *f, va_list args) 134 { 135 unsigned len; 136 137 if (!__i915_error_ok(e)) 138 return; 139 140 /* Seek the first printf which is hits start position */ 141 if (e->pos < e->start) { 142 va_list tmp; 143 144 va_copy(tmp, args); 145 len = vsnprintf(NULL, 0, f, tmp); 146 va_end(tmp); 147 148 if (!__i915_error_seek(e, len)) 149 return; 150 } 151 152 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args); 153 if (len >= e->size - e->bytes) 154 len = e->size - e->bytes - 1; 155 156 __i915_error_advance(e, len); 157 } 158 159 static void i915_error_puts(struct drm_i915_error_state_buf *e, 160 const char *str) 161 { 162 unsigned len; 163 164 if (!__i915_error_ok(e)) 165 return; 166 167 len = strlen(str); 168 169 /* Seek the first printf which is hits start position */ 170 if (e->pos < e->start) { 171 if (!__i915_error_seek(e, len)) 172 return; 173 } 174 175 if (len >= e->size - e->bytes) 176 len = e->size - e->bytes - 1; 177 memcpy(e->buf + e->bytes, str, len); 178 179 __i915_error_advance(e, len); 180 } 181 182 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 183 #define err_puts(e, s) i915_error_puts(e, s) 184 185 static void print_error_buffers(struct drm_i915_error_state_buf *m, 186 const char *name, 187 struct drm_i915_error_buffer *err, 188 int count) 189 { 190 int i; 191 192 err_printf(m, " %s [%d]:\n", name, count); 193 194 while (count--) { 195 err_printf(m, " %08x_%08x %8u %02x %02x [ ", 196 upper_32_bits(err->gtt_offset), 197 lower_32_bits(err->gtt_offset), 198 err->size, 199 err->read_domains, 200 err->write_domain); 201 for (i = 0; i < I915_NUM_ENGINES; i++) 202 err_printf(m, "%02x ", err->rseqno[i]); 203 204 err_printf(m, "] %02x", err->wseqno); 205 err_puts(m, pin_flag(err->pinned)); 206 err_puts(m, tiling_flag(err->tiling)); 207 err_puts(m, dirty_flag(err->dirty)); 208 err_puts(m, purgeable_flag(err->purgeable)); 209 err_puts(m, err->userptr ? " userptr" : ""); 210 err_puts(m, err->ring != -1 ? " " : ""); 211 err_puts(m, ring_str(err->ring)); 212 err_puts(m, i915_cache_level_str(m->i915, err->cache_level)); 213 214 if (err->name) 215 err_printf(m, " (name: %d)", err->name); 216 if (err->fence_reg != I915_FENCE_REG_NONE) 217 err_printf(m, " (fence: %d)", err->fence_reg); 218 219 err_puts(m, "\n"); 220 err++; 221 } 222 } 223 224 static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a) 225 { 226 switch (a) { 227 case HANGCHECK_IDLE: 228 return "idle"; 229 case HANGCHECK_WAIT: 230 return "wait"; 231 case HANGCHECK_ACTIVE: 232 return "active"; 233 case HANGCHECK_KICK: 234 return "kick"; 235 case HANGCHECK_HUNG: 236 return "hung"; 237 } 238 239 return "unknown"; 240 } 241 242 static void i915_ring_error_state(struct drm_i915_error_state_buf *m, 243 struct drm_device *dev, 244 struct drm_i915_error_state *error, 245 int ring_idx) 246 { 247 struct drm_i915_error_ring *ring = &error->ring[ring_idx]; 248 249 if (!ring->valid) 250 return; 251 252 err_printf(m, "%s command stream:\n", ring_str(ring_idx)); 253 err_printf(m, " START: 0x%08x\n", ring->start); 254 err_printf(m, " HEAD: 0x%08x\n", ring->head); 255 err_printf(m, " TAIL: 0x%08x\n", ring->tail); 256 err_printf(m, " CTL: 0x%08x\n", ring->ctl); 257 err_printf(m, " HWS: 0x%08x\n", ring->hws); 258 err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd); 259 err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir); 260 err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr); 261 err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone); 262 if (INTEL_INFO(dev)->gen >= 4) { 263 err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr); 264 err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate); 265 err_printf(m, " INSTPS: 0x%08x\n", ring->instps); 266 } 267 err_printf(m, " INSTPM: 0x%08x\n", ring->instpm); 268 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr), 269 lower_32_bits(ring->faddr)); 270 if (INTEL_INFO(dev)->gen >= 6) { 271 err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi); 272 err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg); 273 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n", 274 ring->semaphore_mboxes[0], 275 ring->semaphore_seqno[0]); 276 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n", 277 ring->semaphore_mboxes[1], 278 ring->semaphore_seqno[1]); 279 if (HAS_VEBOX(dev)) { 280 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n", 281 ring->semaphore_mboxes[2], 282 ring->semaphore_seqno[2]); 283 } 284 } 285 if (USES_PPGTT(dev)) { 286 err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode); 287 288 if (INTEL_INFO(dev)->gen >= 8) { 289 int i; 290 for (i = 0; i < 4; i++) 291 err_printf(m, " PDP%d: 0x%016llx\n", 292 i, ring->vm_info.pdp[i]); 293 } else { 294 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 295 ring->vm_info.pp_dir_base); 296 } 297 } 298 err_printf(m, " seqno: 0x%08x\n", ring->seqno); 299 err_printf(m, " last_seqno: 0x%08x\n", ring->last_seqno); 300 err_printf(m, " waiting: %s\n", yesno(ring->waiting)); 301 err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head); 302 err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail); 303 err_printf(m, " hangcheck: %s [%d]\n", 304 hangcheck_action_to_str(ring->hangcheck_action), 305 ring->hangcheck_score); 306 } 307 308 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 309 { 310 va_list args; 311 312 va_start(args, f); 313 i915_error_vprintf(e, f, args); 314 va_end(args); 315 } 316 317 static void print_error_obj(struct drm_i915_error_state_buf *m, 318 struct drm_i915_error_object *obj) 319 { 320 int page, offset, elt; 321 322 for (page = offset = 0; page < obj->page_count; page++) { 323 for (elt = 0; elt < PAGE_SIZE/4; elt++) { 324 err_printf(m, "%08x : %08x\n", offset, 325 obj->pages[page][elt]); 326 offset += 4; 327 } 328 } 329 } 330 331 int i915_error_state_to_str(struct drm_i915_error_state_buf *m, 332 const struct i915_error_state_file_priv *error_priv) 333 { 334 struct drm_device *dev = error_priv->dev; 335 struct drm_i915_private *dev_priv = to_i915(dev); 336 struct drm_i915_error_state *error = error_priv->error; 337 struct drm_i915_error_object *obj; 338 int i, j, offset, elt; 339 int max_hangcheck_score; 340 341 if (!error) { 342 err_printf(m, "no error state collected\n"); 343 goto out; 344 } 345 346 err_printf(m, "%s\n", error->error_msg); 347 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, 348 error->time.tv_usec); 349 err_printf(m, "Kernel: " UTS_RELEASE "\n"); 350 max_hangcheck_score = 0; 351 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 352 if (error->ring[i].hangcheck_score > max_hangcheck_score) 353 max_hangcheck_score = error->ring[i].hangcheck_score; 354 } 355 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 356 if (error->ring[i].hangcheck_score == max_hangcheck_score && 357 error->ring[i].pid != -1) { 358 err_printf(m, "Active process (on ring %s): %s [%d]\n", 359 ring_str(i), 360 error->ring[i].comm, 361 error->ring[i].pid); 362 } 363 } 364 err_printf(m, "Reset count: %u\n", error->reset_count); 365 err_printf(m, "Suspend count: %u\n", error->suspend_count); 366 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device); 367 err_printf(m, "PCI Revision: 0x%02x\n", dev->pdev->revision); 368 err_printf(m, "PCI Subsystem: %04x:%04x\n", 369 dev->pdev->subsystem_vendor, 370 dev->pdev->subsystem_device); 371 err_printf(m, "IOMMU enabled?: %d\n", error->iommu); 372 373 if (HAS_CSR(dev)) { 374 struct intel_csr *csr = &dev_priv->csr; 375 376 err_printf(m, "DMC loaded: %s\n", 377 yesno(csr->dmc_payload != NULL)); 378 err_printf(m, "DMC fw version: %d.%d\n", 379 CSR_VERSION_MAJOR(csr->version), 380 CSR_VERSION_MINOR(csr->version)); 381 } 382 383 err_printf(m, "EIR: 0x%08x\n", error->eir); 384 err_printf(m, "IER: 0x%08x\n", error->ier); 385 if (INTEL_INFO(dev)->gen >= 8) { 386 for (i = 0; i < 4; i++) 387 err_printf(m, "GTIER gt %d: 0x%08x\n", i, 388 error->gtier[i]); 389 } else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev)) 390 err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]); 391 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); 392 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); 393 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); 394 err_printf(m, "CCID: 0x%08x\n", error->ccid); 395 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings); 396 397 for (i = 0; i < dev_priv->num_fence_regs; i++) 398 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); 399 400 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++) 401 err_printf(m, " INSTDONE_%d: 0x%08x\n", i, 402 error->extra_instdone[i]); 403 404 if (INTEL_INFO(dev)->gen >= 6) { 405 err_printf(m, "ERROR: 0x%08x\n", error->error); 406 407 if (INTEL_INFO(dev)->gen >= 8) 408 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", 409 error->fault_data1, error->fault_data0); 410 411 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); 412 } 413 414 if (IS_GEN7(dev)) 415 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); 416 417 for (i = 0; i < ARRAY_SIZE(error->ring); i++) 418 i915_ring_error_state(m, dev, error, i); 419 420 for (i = 0; i < error->vm_count; i++) { 421 err_printf(m, "vm[%d]\n", i); 422 423 print_error_buffers(m, "Active", 424 error->active_bo[i], 425 error->active_bo_count[i]); 426 427 print_error_buffers(m, "Pinned", 428 error->pinned_bo[i], 429 error->pinned_bo_count[i]); 430 } 431 432 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 433 obj = error->ring[i].batchbuffer; 434 if (obj) { 435 err_puts(m, dev_priv->engine[i].name); 436 if (error->ring[i].pid != -1) 437 err_printf(m, " (submitted by %s [%d])", 438 error->ring[i].comm, 439 error->ring[i].pid); 440 err_printf(m, " --- gtt_offset = 0x%08x %08x\n", 441 upper_32_bits(obj->gtt_offset), 442 lower_32_bits(obj->gtt_offset)); 443 print_error_obj(m, obj); 444 } 445 446 obj = error->ring[i].wa_batchbuffer; 447 if (obj) { 448 err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n", 449 dev_priv->engine[i].name, 450 lower_32_bits(obj->gtt_offset)); 451 print_error_obj(m, obj); 452 } 453 454 if (error->ring[i].num_requests) { 455 err_printf(m, "%s --- %d requests\n", 456 dev_priv->engine[i].name, 457 error->ring[i].num_requests); 458 for (j = 0; j < error->ring[i].num_requests; j++) { 459 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n", 460 error->ring[i].requests[j].seqno, 461 error->ring[i].requests[j].jiffies, 462 error->ring[i].requests[j].tail); 463 } 464 } 465 466 if (error->ring[i].num_waiters) { 467 err_printf(m, "%s --- %d waiters\n", 468 dev_priv->engine[i].name, 469 error->ring[i].num_waiters); 470 for (j = 0; j < error->ring[i].num_waiters; j++) { 471 err_printf(m, " seqno 0x%08x for %s [%d]\n", 472 error->ring[i].waiters[j].seqno, 473 error->ring[i].waiters[j].comm, 474 error->ring[i].waiters[j].pid); 475 } 476 } 477 478 if ((obj = error->ring[i].ringbuffer)) { 479 err_printf(m, "%s --- ringbuffer = 0x%08x\n", 480 dev_priv->engine[i].name, 481 lower_32_bits(obj->gtt_offset)); 482 print_error_obj(m, obj); 483 } 484 485 if ((obj = error->ring[i].hws_page)) { 486 u64 hws_offset = obj->gtt_offset; 487 u32 *hws_page = &obj->pages[0][0]; 488 489 if (i915.enable_execlists) { 490 hws_offset += LRC_PPHWSP_PN * PAGE_SIZE; 491 hws_page = &obj->pages[LRC_PPHWSP_PN][0]; 492 } 493 err_printf(m, "%s --- HW Status = 0x%08llx\n", 494 dev_priv->engine[i].name, hws_offset); 495 offset = 0; 496 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { 497 err_printf(m, "[%04x] %08x %08x %08x %08x\n", 498 offset, 499 hws_page[elt], 500 hws_page[elt+1], 501 hws_page[elt+2], 502 hws_page[elt+3]); 503 offset += 16; 504 } 505 } 506 507 obj = error->ring[i].wa_ctx; 508 if (obj) { 509 u64 wa_ctx_offset = obj->gtt_offset; 510 u32 *wa_ctx_page = &obj->pages[0][0]; 511 struct intel_engine_cs *engine = &dev_priv->engine[RCS]; 512 u32 wa_ctx_size = (engine->wa_ctx.indirect_ctx.size + 513 engine->wa_ctx.per_ctx.size); 514 515 err_printf(m, "%s --- WA ctx batch buffer = 0x%08llx\n", 516 dev_priv->engine[i].name, wa_ctx_offset); 517 offset = 0; 518 for (elt = 0; elt < wa_ctx_size; elt += 4) { 519 err_printf(m, "[%04x] %08x %08x %08x %08x\n", 520 offset, 521 wa_ctx_page[elt + 0], 522 wa_ctx_page[elt + 1], 523 wa_ctx_page[elt + 2], 524 wa_ctx_page[elt + 3]); 525 offset += 16; 526 } 527 } 528 529 if ((obj = error->ring[i].ctx)) { 530 err_printf(m, "%s --- HW Context = 0x%08x\n", 531 dev_priv->engine[i].name, 532 lower_32_bits(obj->gtt_offset)); 533 print_error_obj(m, obj); 534 } 535 } 536 537 if ((obj = error->semaphore_obj)) { 538 err_printf(m, "Semaphore page = 0x%08x\n", 539 lower_32_bits(obj->gtt_offset)); 540 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { 541 err_printf(m, "[%04x] %08x %08x %08x %08x\n", 542 elt * 4, 543 obj->pages[0][elt], 544 obj->pages[0][elt+1], 545 obj->pages[0][elt+2], 546 obj->pages[0][elt+3]); 547 } 548 } 549 550 if (error->overlay) 551 intel_overlay_print_error_state(m, error->overlay); 552 553 if (error->display) 554 intel_display_print_error_state(m, dev, error->display); 555 556 out: 557 if (m->bytes == 0 && m->err) 558 return m->err; 559 560 return 0; 561 } 562 563 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf, 564 struct drm_i915_private *i915, 565 size_t count, loff_t pos) 566 { 567 memset(ebuf, 0, sizeof(*ebuf)); 568 ebuf->i915 = i915; 569 570 /* We need to have enough room to store any i915_error_state printf 571 * so that we can move it to start position. 572 */ 573 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE; 574 ebuf->buf = kmalloc(ebuf->size, 575 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN); 576 577 if (ebuf->buf == NULL) { 578 ebuf->size = PAGE_SIZE; 579 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 580 } 581 582 if (ebuf->buf == NULL) { 583 ebuf->size = 128; 584 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 585 } 586 587 if (ebuf->buf == NULL) 588 return -ENOMEM; 589 590 ebuf->start = pos; 591 592 return 0; 593 } 594 595 static void i915_error_object_free(struct drm_i915_error_object *obj) 596 { 597 int page; 598 599 if (obj == NULL) 600 return; 601 602 for (page = 0; page < obj->page_count; page++) 603 kfree(obj->pages[page]); 604 605 kfree(obj); 606 } 607 608 static void i915_error_state_free(struct kref *error_ref) 609 { 610 struct drm_i915_error_state *error = container_of(error_ref, 611 typeof(*error), ref); 612 int i; 613 614 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 615 i915_error_object_free(error->ring[i].batchbuffer); 616 i915_error_object_free(error->ring[i].wa_batchbuffer); 617 i915_error_object_free(error->ring[i].ringbuffer); 618 i915_error_object_free(error->ring[i].hws_page); 619 i915_error_object_free(error->ring[i].ctx); 620 i915_error_object_free(error->ring[i].wa_ctx); 621 kfree(error->ring[i].requests); 622 kfree(error->ring[i].waiters); 623 } 624 625 i915_error_object_free(error->semaphore_obj); 626 627 for (i = 0; i < error->vm_count; i++) 628 kfree(error->active_bo[i]); 629 630 kfree(error->active_bo); 631 kfree(error->active_bo_count); 632 kfree(error->pinned_bo); 633 kfree(error->pinned_bo_count); 634 kfree(error->overlay); 635 kfree(error->display); 636 kfree(error); 637 } 638 639 static struct drm_i915_error_object * 640 i915_error_object_create(struct drm_i915_private *dev_priv, 641 struct drm_i915_gem_object *src, 642 struct i915_address_space *vm) 643 { 644 struct i915_ggtt *ggtt = &dev_priv->ggtt; 645 struct drm_i915_error_object *dst; 646 struct i915_vma *vma = NULL; 647 int num_pages; 648 bool use_ggtt; 649 int i = 0; 650 u64 reloc_offset; 651 652 if (src == NULL || src->pages == NULL) 653 return NULL; 654 655 num_pages = src->base.size >> PAGE_SHIFT; 656 657 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC); 658 if (dst == NULL) 659 return NULL; 660 661 if (i915_gem_obj_bound(src, vm)) 662 dst->gtt_offset = i915_gem_obj_offset(src, vm); 663 else 664 dst->gtt_offset = -1; 665 666 reloc_offset = dst->gtt_offset; 667 if (i915_is_ggtt(vm)) 668 vma = i915_gem_obj_to_ggtt(src); 669 use_ggtt = (src->cache_level == I915_CACHE_NONE && 670 vma && (vma->bound & GLOBAL_BIND) && 671 reloc_offset + num_pages * PAGE_SIZE <= ggtt->mappable_end); 672 673 /* Cannot access stolen address directly, try to use the aperture */ 674 if (src->stolen) { 675 use_ggtt = true; 676 677 if (!(vma && vma->bound & GLOBAL_BIND)) 678 goto unwind; 679 680 reloc_offset = i915_gem_obj_ggtt_offset(src); 681 if (reloc_offset + num_pages * PAGE_SIZE > ggtt->mappable_end) 682 goto unwind; 683 } 684 685 /* Cannot access snooped pages through the aperture */ 686 if (use_ggtt && src->cache_level != I915_CACHE_NONE && 687 !HAS_LLC(dev_priv)) 688 goto unwind; 689 690 dst->page_count = num_pages; 691 while (num_pages--) { 692 unsigned long flags; 693 void *d; 694 695 d = kmalloc(PAGE_SIZE, GFP_ATOMIC); 696 if (d == NULL) 697 goto unwind; 698 699 local_irq_save(flags); 700 if (use_ggtt) { 701 void __iomem *s; 702 703 /* Simply ignore tiling or any overlapping fence. 704 * It's part of the error state, and this hopefully 705 * captures what the GPU read. 706 */ 707 708 s = io_mapping_map_atomic_wc(ggtt->mappable, 709 reloc_offset); 710 memcpy_fromio(d, s, PAGE_SIZE); 711 io_mapping_unmap_atomic(s); 712 } else { 713 struct page *page; 714 void *s; 715 716 page = i915_gem_object_get_page(src, i); 717 718 drm_clflush_pages(&page, 1); 719 720 s = kmap_atomic(page); 721 memcpy(d, s, PAGE_SIZE); 722 kunmap_atomic(s); 723 724 drm_clflush_pages(&page, 1); 725 } 726 local_irq_restore(flags); 727 728 dst->pages[i++] = d; 729 reloc_offset += PAGE_SIZE; 730 } 731 732 return dst; 733 734 unwind: 735 while (i--) 736 kfree(dst->pages[i]); 737 kfree(dst); 738 return NULL; 739 } 740 #define i915_error_ggtt_object_create(dev_priv, src) \ 741 i915_error_object_create((dev_priv), (src), &(dev_priv)->ggtt.base) 742 743 static void capture_bo(struct drm_i915_error_buffer *err, 744 struct i915_vma *vma) 745 { 746 struct drm_i915_gem_object *obj = vma->obj; 747 int i; 748 749 err->size = obj->base.size; 750 err->name = obj->base.name; 751 for (i = 0; i < I915_NUM_ENGINES; i++) 752 err->rseqno[i] = i915_gem_request_get_seqno(obj->last_read_req[i]); 753 err->wseqno = i915_gem_request_get_seqno(obj->last_write_req); 754 err->gtt_offset = vma->node.start; 755 err->read_domains = obj->base.read_domains; 756 err->write_domain = obj->base.write_domain; 757 err->fence_reg = obj->fence_reg; 758 err->pinned = 0; 759 if (i915_gem_obj_is_pinned(obj)) 760 err->pinned = 1; 761 err->tiling = obj->tiling_mode; 762 err->dirty = obj->dirty; 763 err->purgeable = obj->madv != I915_MADV_WILLNEED; 764 err->userptr = obj->userptr.mm != NULL; 765 err->ring = obj->last_write_req ? 766 i915_gem_request_get_engine(obj->last_write_req)->id : -1; 767 err->cache_level = obj->cache_level; 768 } 769 770 static u32 capture_active_bo(struct drm_i915_error_buffer *err, 771 int count, struct list_head *head) 772 { 773 struct i915_vma *vma; 774 int i = 0; 775 776 list_for_each_entry(vma, head, vm_link) { 777 capture_bo(err++, vma); 778 if (++i == count) 779 break; 780 } 781 782 return i; 783 } 784 785 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err, 786 int count, struct list_head *head, 787 struct i915_address_space *vm) 788 { 789 struct drm_i915_gem_object *obj; 790 struct drm_i915_error_buffer * const first = err; 791 struct drm_i915_error_buffer * const last = err + count; 792 793 list_for_each_entry(obj, head, global_list) { 794 struct i915_vma *vma; 795 796 if (err == last) 797 break; 798 799 list_for_each_entry(vma, &obj->vma_list, obj_link) 800 if (vma->vm == vm && vma->pin_count > 0) 801 capture_bo(err++, vma); 802 } 803 804 return err - first; 805 } 806 807 /* Generate a semi-unique error code. The code is not meant to have meaning, The 808 * code's only purpose is to try to prevent false duplicated bug reports by 809 * grossly estimating a GPU error state. 810 * 811 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 812 * the hang if we could strip the GTT offset information from it. 813 * 814 * It's only a small step better than a random number in its current form. 815 */ 816 static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv, 817 struct drm_i915_error_state *error, 818 int *ring_id) 819 { 820 uint32_t error_code = 0; 821 int i; 822 823 /* IPEHR would be an ideal way to detect errors, as it's the gross 824 * measure of "the command that hung." However, has some very common 825 * synchronization commands which almost always appear in the case 826 * strictly a client bug. Use instdone to differentiate those some. 827 */ 828 for (i = 0; i < I915_NUM_ENGINES; i++) { 829 if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) { 830 if (ring_id) 831 *ring_id = i; 832 833 return error->ring[i].ipehr ^ error->ring[i].instdone; 834 } 835 } 836 837 return error_code; 838 } 839 840 static void i915_gem_record_fences(struct drm_i915_private *dev_priv, 841 struct drm_i915_error_state *error) 842 { 843 int i; 844 845 if (IS_GEN3(dev_priv) || IS_GEN2(dev_priv)) { 846 for (i = 0; i < dev_priv->num_fence_regs; i++) 847 error->fence[i] = I915_READ(FENCE_REG(i)); 848 } else if (IS_GEN5(dev_priv) || IS_GEN4(dev_priv)) { 849 for (i = 0; i < dev_priv->num_fence_regs; i++) 850 error->fence[i] = I915_READ64(FENCE_REG_965_LO(i)); 851 } else if (INTEL_GEN(dev_priv) >= 6) { 852 for (i = 0; i < dev_priv->num_fence_regs; i++) 853 error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i)); 854 } 855 } 856 857 858 static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv, 859 struct drm_i915_error_state *error, 860 struct intel_engine_cs *engine, 861 struct drm_i915_error_ring *ering) 862 { 863 struct intel_engine_cs *to; 864 enum intel_engine_id id; 865 866 if (!i915_semaphore_is_enabled(dev_priv)) 867 return; 868 869 if (!error->semaphore_obj) 870 error->semaphore_obj = 871 i915_error_ggtt_object_create(dev_priv, 872 dev_priv->semaphore_obj); 873 874 for_each_engine_id(to, dev_priv, id) { 875 int idx; 876 u16 signal_offset; 877 u32 *tmp; 878 879 if (engine == to) 880 continue; 881 882 signal_offset = (GEN8_SIGNAL_OFFSET(engine, id) & (PAGE_SIZE - 1)) 883 / 4; 884 tmp = error->semaphore_obj->pages[0]; 885 idx = intel_ring_sync_index(engine, to); 886 887 ering->semaphore_mboxes[idx] = tmp[signal_offset]; 888 ering->semaphore_seqno[idx] = engine->semaphore.sync_seqno[idx]; 889 } 890 } 891 892 static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv, 893 struct intel_engine_cs *engine, 894 struct drm_i915_error_ring *ering) 895 { 896 ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base)); 897 ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base)); 898 ering->semaphore_seqno[0] = engine->semaphore.sync_seqno[0]; 899 ering->semaphore_seqno[1] = engine->semaphore.sync_seqno[1]; 900 901 if (HAS_VEBOX(dev_priv)) { 902 ering->semaphore_mboxes[2] = 903 I915_READ(RING_SYNC_2(engine->mmio_base)); 904 ering->semaphore_seqno[2] = engine->semaphore.sync_seqno[2]; 905 } 906 } 907 908 static void engine_record_waiters(struct intel_engine_cs *engine, 909 struct drm_i915_error_ring *ering) 910 { 911 struct intel_breadcrumbs *b = &engine->breadcrumbs; 912 struct drm_i915_error_waiter *waiter; 913 struct rb_node *rb; 914 int count; 915 916 ering->num_waiters = 0; 917 ering->waiters = NULL; 918 919 spin_lock(&b->lock); 920 count = 0; 921 for (rb = rb_first(&b->waiters); rb != NULL; rb = rb_next(rb)) 922 count++; 923 spin_unlock(&b->lock); 924 925 waiter = NULL; 926 if (count) 927 waiter = kmalloc_array(count, 928 sizeof(struct drm_i915_error_waiter), 929 GFP_ATOMIC); 930 if (!waiter) 931 return; 932 933 ering->waiters = waiter; 934 935 spin_lock(&b->lock); 936 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { 937 struct intel_wait *w = container_of(rb, typeof(*w), node); 938 939 strcpy(waiter->comm, w->tsk->comm); 940 waiter->pid = w->tsk->pid; 941 waiter->seqno = w->seqno; 942 waiter++; 943 944 if (++ering->num_waiters == count) 945 break; 946 } 947 spin_unlock(&b->lock); 948 } 949 950 static void i915_record_ring_state(struct drm_i915_private *dev_priv, 951 struct drm_i915_error_state *error, 952 struct intel_engine_cs *engine, 953 struct drm_i915_error_ring *ering) 954 { 955 if (INTEL_GEN(dev_priv) >= 6) { 956 ering->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base)); 957 ering->fault_reg = I915_READ(RING_FAULT_REG(engine)); 958 if (INTEL_GEN(dev_priv) >= 8) 959 gen8_record_semaphore_state(dev_priv, error, engine, 960 ering); 961 else 962 gen6_record_semaphore_state(dev_priv, engine, ering); 963 } 964 965 if (INTEL_GEN(dev_priv) >= 4) { 966 ering->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base)); 967 ering->ipeir = I915_READ(RING_IPEIR(engine->mmio_base)); 968 ering->ipehr = I915_READ(RING_IPEHR(engine->mmio_base)); 969 ering->instdone = I915_READ(RING_INSTDONE(engine->mmio_base)); 970 ering->instps = I915_READ(RING_INSTPS(engine->mmio_base)); 971 ering->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base)); 972 if (INTEL_GEN(dev_priv) >= 8) { 973 ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32; 974 ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32; 975 } 976 ering->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base)); 977 } else { 978 ering->faddr = I915_READ(DMA_FADD_I8XX); 979 ering->ipeir = I915_READ(IPEIR); 980 ering->ipehr = I915_READ(IPEHR); 981 ering->instdone = I915_READ(GEN2_INSTDONE); 982 } 983 984 ering->waiting = intel_engine_has_waiter(engine); 985 ering->instpm = I915_READ(RING_INSTPM(engine->mmio_base)); 986 ering->acthd = intel_ring_get_active_head(engine); 987 ering->seqno = intel_engine_get_seqno(engine); 988 ering->last_seqno = engine->last_submitted_seqno; 989 ering->start = I915_READ_START(engine); 990 ering->head = I915_READ_HEAD(engine); 991 ering->tail = I915_READ_TAIL(engine); 992 ering->ctl = I915_READ_CTL(engine); 993 994 if (I915_NEED_GFX_HWS(dev_priv)) { 995 i915_reg_t mmio; 996 997 if (IS_GEN7(dev_priv)) { 998 switch (engine->id) { 999 default: 1000 case RCS: 1001 mmio = RENDER_HWS_PGA_GEN7; 1002 break; 1003 case BCS: 1004 mmio = BLT_HWS_PGA_GEN7; 1005 break; 1006 case VCS: 1007 mmio = BSD_HWS_PGA_GEN7; 1008 break; 1009 case VECS: 1010 mmio = VEBOX_HWS_PGA_GEN7; 1011 break; 1012 } 1013 } else if (IS_GEN6(engine->i915)) { 1014 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); 1015 } else { 1016 /* XXX: gen8 returns to sanity */ 1017 mmio = RING_HWS_PGA(engine->mmio_base); 1018 } 1019 1020 ering->hws = I915_READ(mmio); 1021 } 1022 1023 ering->hangcheck_score = engine->hangcheck.score; 1024 ering->hangcheck_action = engine->hangcheck.action; 1025 1026 if (USES_PPGTT(dev_priv)) { 1027 int i; 1028 1029 ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine)); 1030 1031 if (IS_GEN6(dev_priv)) 1032 ering->vm_info.pp_dir_base = 1033 I915_READ(RING_PP_DIR_BASE_READ(engine)); 1034 else if (IS_GEN7(dev_priv)) 1035 ering->vm_info.pp_dir_base = 1036 I915_READ(RING_PP_DIR_BASE(engine)); 1037 else if (INTEL_GEN(dev_priv) >= 8) 1038 for (i = 0; i < 4; i++) { 1039 ering->vm_info.pdp[i] = 1040 I915_READ(GEN8_RING_PDP_UDW(engine, i)); 1041 ering->vm_info.pdp[i] <<= 32; 1042 ering->vm_info.pdp[i] |= 1043 I915_READ(GEN8_RING_PDP_LDW(engine, i)); 1044 } 1045 } 1046 } 1047 1048 1049 static void i915_gem_record_active_context(struct intel_engine_cs *engine, 1050 struct drm_i915_error_state *error, 1051 struct drm_i915_error_ring *ering) 1052 { 1053 struct drm_i915_private *dev_priv = engine->i915; 1054 struct drm_i915_gem_object *obj; 1055 1056 /* Currently render ring is the only HW context user */ 1057 if (engine->id != RCS || !error->ccid) 1058 return; 1059 1060 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 1061 if (!i915_gem_obj_ggtt_bound(obj)) 1062 continue; 1063 1064 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) { 1065 ering->ctx = i915_error_ggtt_object_create(dev_priv, obj); 1066 break; 1067 } 1068 } 1069 } 1070 1071 static void i915_gem_record_rings(struct drm_i915_private *dev_priv, 1072 struct drm_i915_error_state *error) 1073 { 1074 struct i915_ggtt *ggtt = &dev_priv->ggtt; 1075 struct drm_i915_gem_request *request; 1076 int i, count; 1077 1078 for (i = 0; i < I915_NUM_ENGINES; i++) { 1079 struct intel_engine_cs *engine = &dev_priv->engine[i]; 1080 1081 error->ring[i].pid = -1; 1082 1083 if (!intel_engine_initialized(engine)) 1084 continue; 1085 1086 error->ring[i].valid = true; 1087 1088 i915_record_ring_state(dev_priv, error, engine, &error->ring[i]); 1089 engine_record_waiters(engine, &error->ring[i]); 1090 1091 request = i915_gem_find_active_request(engine); 1092 if (request) { 1093 struct i915_address_space *vm; 1094 struct intel_ringbuffer *rb; 1095 1096 vm = request->ctx->ppgtt ? 1097 &request->ctx->ppgtt->base : &ggtt->base; 1098 1099 /* We need to copy these to an anonymous buffer 1100 * as the simplest method to avoid being overwritten 1101 * by userspace. 1102 */ 1103 error->ring[i].batchbuffer = 1104 i915_error_object_create(dev_priv, 1105 request->batch_obj, 1106 vm); 1107 1108 if (HAS_BROKEN_CS_TLB(dev_priv)) 1109 error->ring[i].wa_batchbuffer = 1110 i915_error_ggtt_object_create(dev_priv, 1111 engine->scratch.obj); 1112 1113 if (request->pid) { 1114 struct task_struct *task; 1115 1116 rcu_read_lock(); 1117 task = pid_task(request->pid, PIDTYPE_PID); 1118 if (task) { 1119 strcpy(error->ring[i].comm, task->comm); 1120 error->ring[i].pid = task->pid; 1121 } 1122 rcu_read_unlock(); 1123 } 1124 1125 error->simulated |= 1126 request->ctx->flags & CONTEXT_NO_ERROR_CAPTURE; 1127 1128 rb = request->ringbuf; 1129 error->ring[i].cpu_ring_head = rb->head; 1130 error->ring[i].cpu_ring_tail = rb->tail; 1131 error->ring[i].ringbuffer = 1132 i915_error_ggtt_object_create(dev_priv, 1133 rb->obj); 1134 } 1135 1136 error->ring[i].hws_page = 1137 i915_error_ggtt_object_create(dev_priv, 1138 engine->status_page.obj); 1139 1140 if (engine->wa_ctx.obj) { 1141 error->ring[i].wa_ctx = 1142 i915_error_ggtt_object_create(dev_priv, 1143 engine->wa_ctx.obj); 1144 } 1145 1146 i915_gem_record_active_context(engine, error, &error->ring[i]); 1147 1148 count = 0; 1149 list_for_each_entry(request, &engine->request_list, list) 1150 count++; 1151 1152 error->ring[i].num_requests = count; 1153 error->ring[i].requests = 1154 kcalloc(count, sizeof(*error->ring[i].requests), 1155 GFP_ATOMIC); 1156 if (error->ring[i].requests == NULL) { 1157 error->ring[i].num_requests = 0; 1158 continue; 1159 } 1160 1161 count = 0; 1162 list_for_each_entry(request, &engine->request_list, list) { 1163 struct drm_i915_error_request *erq; 1164 1165 if (count >= error->ring[i].num_requests) { 1166 /* 1167 * If the ring request list was changed in 1168 * between the point where the error request 1169 * list was created and dimensioned and this 1170 * point then just exit early to avoid crashes. 1171 * 1172 * We don't need to communicate that the 1173 * request list changed state during error 1174 * state capture and that the error state is 1175 * slightly incorrect as a consequence since we 1176 * are typically only interested in the request 1177 * list state at the point of error state 1178 * capture, not in any changes happening during 1179 * the capture. 1180 */ 1181 break; 1182 } 1183 1184 erq = &error->ring[i].requests[count++]; 1185 erq->seqno = request->seqno; 1186 erq->jiffies = request->emitted_jiffies; 1187 erq->tail = request->postfix; 1188 } 1189 } 1190 } 1191 1192 /* FIXME: Since pin count/bound list is global, we duplicate what we capture per 1193 * VM. 1194 */ 1195 static void i915_gem_capture_vm(struct drm_i915_private *dev_priv, 1196 struct drm_i915_error_state *error, 1197 struct i915_address_space *vm, 1198 const int ndx) 1199 { 1200 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL; 1201 struct drm_i915_gem_object *obj; 1202 struct i915_vma *vma; 1203 int i; 1204 1205 i = 0; 1206 list_for_each_entry(vma, &vm->active_list, vm_link) 1207 i++; 1208 error->active_bo_count[ndx] = i; 1209 1210 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 1211 list_for_each_entry(vma, &obj->vma_list, obj_link) 1212 if (vma->vm == vm && vma->pin_count > 0) 1213 i++; 1214 } 1215 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx]; 1216 1217 if (i) { 1218 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC); 1219 if (active_bo) 1220 pinned_bo = active_bo + error->active_bo_count[ndx]; 1221 } 1222 1223 if (active_bo) 1224 error->active_bo_count[ndx] = 1225 capture_active_bo(active_bo, 1226 error->active_bo_count[ndx], 1227 &vm->active_list); 1228 1229 if (pinned_bo) 1230 error->pinned_bo_count[ndx] = 1231 capture_pinned_bo(pinned_bo, 1232 error->pinned_bo_count[ndx], 1233 &dev_priv->mm.bound_list, vm); 1234 error->active_bo[ndx] = active_bo; 1235 error->pinned_bo[ndx] = pinned_bo; 1236 } 1237 1238 static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv, 1239 struct drm_i915_error_state *error) 1240 { 1241 struct i915_address_space *vm; 1242 int cnt = 0, i = 0; 1243 1244 list_for_each_entry(vm, &dev_priv->vm_list, global_link) 1245 cnt++; 1246 1247 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC); 1248 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC); 1249 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count), 1250 GFP_ATOMIC); 1251 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count), 1252 GFP_ATOMIC); 1253 1254 if (error->active_bo == NULL || 1255 error->pinned_bo == NULL || 1256 error->active_bo_count == NULL || 1257 error->pinned_bo_count == NULL) { 1258 kfree(error->active_bo); 1259 kfree(error->active_bo_count); 1260 kfree(error->pinned_bo); 1261 kfree(error->pinned_bo_count); 1262 1263 error->active_bo = NULL; 1264 error->active_bo_count = NULL; 1265 error->pinned_bo = NULL; 1266 error->pinned_bo_count = NULL; 1267 } else { 1268 list_for_each_entry(vm, &dev_priv->vm_list, global_link) 1269 i915_gem_capture_vm(dev_priv, error, vm, i++); 1270 1271 error->vm_count = cnt; 1272 } 1273 } 1274 1275 /* Capture all registers which don't fit into another category. */ 1276 static void i915_capture_reg_state(struct drm_i915_private *dev_priv, 1277 struct drm_i915_error_state *error) 1278 { 1279 struct drm_device *dev = &dev_priv->drm; 1280 int i; 1281 1282 /* General organization 1283 * 1. Registers specific to a single generation 1284 * 2. Registers which belong to multiple generations 1285 * 3. Feature specific registers. 1286 * 4. Everything else 1287 * Please try to follow the order. 1288 */ 1289 1290 /* 1: Registers specific to a single generation */ 1291 if (IS_VALLEYVIEW(dev)) { 1292 error->gtier[0] = I915_READ(GTIER); 1293 error->ier = I915_READ(VLV_IER); 1294 error->forcewake = I915_READ_FW(FORCEWAKE_VLV); 1295 } 1296 1297 if (IS_GEN7(dev)) 1298 error->err_int = I915_READ(GEN7_ERR_INT); 1299 1300 if (INTEL_INFO(dev)->gen >= 8) { 1301 error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0); 1302 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1); 1303 } 1304 1305 if (IS_GEN6(dev)) { 1306 error->forcewake = I915_READ_FW(FORCEWAKE); 1307 error->gab_ctl = I915_READ(GAB_CTL); 1308 error->gfx_mode = I915_READ(GFX_MODE); 1309 } 1310 1311 /* 2: Registers which belong to multiple generations */ 1312 if (INTEL_INFO(dev)->gen >= 7) 1313 error->forcewake = I915_READ_FW(FORCEWAKE_MT); 1314 1315 if (INTEL_INFO(dev)->gen >= 6) { 1316 error->derrmr = I915_READ(DERRMR); 1317 error->error = I915_READ(ERROR_GEN6); 1318 error->done_reg = I915_READ(DONE_REG); 1319 } 1320 1321 /* 3: Feature specific registers */ 1322 if (IS_GEN6(dev) || IS_GEN7(dev)) { 1323 error->gam_ecochk = I915_READ(GAM_ECOCHK); 1324 error->gac_eco = I915_READ(GAC_ECO_BITS); 1325 } 1326 1327 /* 4: Everything else */ 1328 if (HAS_HW_CONTEXTS(dev)) 1329 error->ccid = I915_READ(CCID); 1330 1331 if (INTEL_INFO(dev)->gen >= 8) { 1332 error->ier = I915_READ(GEN8_DE_MISC_IER); 1333 for (i = 0; i < 4; i++) 1334 error->gtier[i] = I915_READ(GEN8_GT_IER(i)); 1335 } else if (HAS_PCH_SPLIT(dev)) { 1336 error->ier = I915_READ(DEIER); 1337 error->gtier[0] = I915_READ(GTIER); 1338 } else if (IS_GEN2(dev)) { 1339 error->ier = I915_READ16(IER); 1340 } else if (!IS_VALLEYVIEW(dev)) { 1341 error->ier = I915_READ(IER); 1342 } 1343 error->eir = I915_READ(EIR); 1344 error->pgtbl_er = I915_READ(PGTBL_ER); 1345 1346 i915_get_extra_instdone(dev_priv, error->extra_instdone); 1347 } 1348 1349 static void i915_error_capture_msg(struct drm_i915_private *dev_priv, 1350 struct drm_i915_error_state *error, 1351 u32 engine_mask, 1352 const char *error_msg) 1353 { 1354 u32 ecode; 1355 int ring_id = -1, len; 1356 1357 ecode = i915_error_generate_code(dev_priv, error, &ring_id); 1358 1359 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1360 "GPU HANG: ecode %d:%d:0x%08x", 1361 INTEL_GEN(dev_priv), ring_id, ecode); 1362 1363 if (ring_id != -1 && error->ring[ring_id].pid != -1) 1364 len += scnprintf(error->error_msg + len, 1365 sizeof(error->error_msg) - len, 1366 ", in %s [%d]", 1367 error->ring[ring_id].comm, 1368 error->ring[ring_id].pid); 1369 1370 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len, 1371 ", reason: %s, action: %s", 1372 error_msg, 1373 engine_mask ? "reset" : "continue"); 1374 } 1375 1376 static void i915_capture_gen_state(struct drm_i915_private *dev_priv, 1377 struct drm_i915_error_state *error) 1378 { 1379 error->iommu = -1; 1380 #ifdef CONFIG_INTEL_IOMMU 1381 error->iommu = intel_iommu_gfx_mapped; 1382 #endif 1383 error->reset_count = i915_reset_count(&dev_priv->gpu_error); 1384 error->suspend_count = dev_priv->suspend_count; 1385 } 1386 1387 /** 1388 * i915_capture_error_state - capture an error record for later analysis 1389 * @dev: drm device 1390 * 1391 * Should be called when an error is detected (either a hang or an error 1392 * interrupt) to capture error state from the time of the error. Fills 1393 * out a structure which becomes available in debugfs for user level tools 1394 * to pick up. 1395 */ 1396 void i915_capture_error_state(struct drm_i915_private *dev_priv, 1397 u32 engine_mask, 1398 const char *error_msg) 1399 { 1400 static bool warned; 1401 struct drm_i915_error_state *error; 1402 unsigned long flags; 1403 1404 if (READ_ONCE(dev_priv->gpu_error.first_error)) 1405 return; 1406 1407 /* Account for pipe specific data like PIPE*STAT */ 1408 error = kzalloc(sizeof(*error), GFP_ATOMIC); 1409 if (!error) { 1410 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); 1411 return; 1412 } 1413 1414 kref_init(&error->ref); 1415 1416 i915_capture_gen_state(dev_priv, error); 1417 i915_capture_reg_state(dev_priv, error); 1418 i915_gem_capture_buffers(dev_priv, error); 1419 i915_gem_record_fences(dev_priv, error); 1420 i915_gem_record_rings(dev_priv, error); 1421 1422 do_gettimeofday(&error->time); 1423 1424 error->overlay = intel_overlay_capture_error_state(dev_priv); 1425 error->display = intel_display_capture_error_state(dev_priv); 1426 1427 i915_error_capture_msg(dev_priv, error, engine_mask, error_msg); 1428 DRM_INFO("%s\n", error->error_msg); 1429 1430 if (!error->simulated) { 1431 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 1432 if (!dev_priv->gpu_error.first_error) { 1433 dev_priv->gpu_error.first_error = error; 1434 error = NULL; 1435 } 1436 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 1437 } 1438 1439 if (error) { 1440 i915_error_state_free(&error->ref); 1441 return; 1442 } 1443 1444 if (!warned) { 1445 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 1446 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n"); 1447 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 1448 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n"); 1449 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", 1450 dev_priv->drm.primary->index); 1451 warned = true; 1452 } 1453 } 1454 1455 void i915_error_state_get(struct drm_device *dev, 1456 struct i915_error_state_file_priv *error_priv) 1457 { 1458 struct drm_i915_private *dev_priv = to_i915(dev); 1459 1460 spin_lock_irq(&dev_priv->gpu_error.lock); 1461 error_priv->error = dev_priv->gpu_error.first_error; 1462 if (error_priv->error) 1463 kref_get(&error_priv->error->ref); 1464 spin_unlock_irq(&dev_priv->gpu_error.lock); 1465 1466 } 1467 1468 void i915_error_state_put(struct i915_error_state_file_priv *error_priv) 1469 { 1470 if (error_priv->error) 1471 kref_put(&error_priv->error->ref, i915_error_state_free); 1472 } 1473 1474 void i915_destroy_error_state(struct drm_device *dev) 1475 { 1476 struct drm_i915_private *dev_priv = to_i915(dev); 1477 struct drm_i915_error_state *error; 1478 1479 spin_lock_irq(&dev_priv->gpu_error.lock); 1480 error = dev_priv->gpu_error.first_error; 1481 dev_priv->gpu_error.first_error = NULL; 1482 spin_unlock_irq(&dev_priv->gpu_error.lock); 1483 1484 if (error) 1485 kref_put(&error->ref, i915_error_state_free); 1486 } 1487 1488 const char *i915_cache_level_str(struct drm_i915_private *i915, int type) 1489 { 1490 switch (type) { 1491 case I915_CACHE_NONE: return " uncached"; 1492 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped"; 1493 case I915_CACHE_L3_LLC: return " L3+LLC"; 1494 case I915_CACHE_WT: return " WT"; 1495 default: return ""; 1496 } 1497 } 1498 1499 /* NB: please notice the memset */ 1500 void i915_get_extra_instdone(struct drm_i915_private *dev_priv, 1501 uint32_t *instdone) 1502 { 1503 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG); 1504 1505 if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv)) 1506 instdone[0] = I915_READ(GEN2_INSTDONE); 1507 else if (IS_GEN4(dev_priv) || IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) { 1508 instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE)); 1509 instdone[1] = I915_READ(GEN4_INSTDONE1); 1510 } else if (INTEL_GEN(dev_priv) >= 7) { 1511 instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE)); 1512 instdone[1] = I915_READ(GEN7_SC_INSTDONE); 1513 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE); 1514 instdone[3] = I915_READ(GEN7_ROW_INSTDONE); 1515 } 1516 } 1517