1 /* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30 #include <generated/utsrelease.h> 31 #include "i915_drv.h" 32 33 static const char *yesno(int v) 34 { 35 return v ? "yes" : "no"; 36 } 37 38 static const char *ring_str(int ring) 39 { 40 switch (ring) { 41 case RCS: return "render"; 42 case VCS: return "bsd"; 43 case BCS: return "blt"; 44 case VECS: return "vebox"; 45 case VCS2: return "bsd2"; 46 default: return ""; 47 } 48 } 49 50 static const char *pin_flag(int pinned) 51 { 52 if (pinned > 0) 53 return " P"; 54 else if (pinned < 0) 55 return " p"; 56 else 57 return ""; 58 } 59 60 static const char *tiling_flag(int tiling) 61 { 62 switch (tiling) { 63 default: 64 case I915_TILING_NONE: return ""; 65 case I915_TILING_X: return " X"; 66 case I915_TILING_Y: return " Y"; 67 } 68 } 69 70 static const char *dirty_flag(int dirty) 71 { 72 return dirty ? " dirty" : ""; 73 } 74 75 static const char *purgeable_flag(int purgeable) 76 { 77 return purgeable ? " purgeable" : ""; 78 } 79 80 static bool __i915_error_ok(struct drm_i915_error_state_buf *e) 81 { 82 83 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) { 84 e->err = -ENOSPC; 85 return false; 86 } 87 88 if (e->bytes == e->size - 1 || e->err) 89 return false; 90 91 return true; 92 } 93 94 static bool __i915_error_seek(struct drm_i915_error_state_buf *e, 95 unsigned len) 96 { 97 if (e->pos + len <= e->start) { 98 e->pos += len; 99 return false; 100 } 101 102 /* First vsnprintf needs to fit in its entirety for memmove */ 103 if (len >= e->size) { 104 e->err = -EIO; 105 return false; 106 } 107 108 return true; 109 } 110 111 static void __i915_error_advance(struct drm_i915_error_state_buf *e, 112 unsigned len) 113 { 114 /* If this is first printf in this window, adjust it so that 115 * start position matches start of the buffer 116 */ 117 118 if (e->pos < e->start) { 119 const size_t off = e->start - e->pos; 120 121 /* Should not happen but be paranoid */ 122 if (off > len || e->bytes) { 123 e->err = -EIO; 124 return; 125 } 126 127 memmove(e->buf, e->buf + off, len - off); 128 e->bytes = len - off; 129 e->pos = e->start; 130 return; 131 } 132 133 e->bytes += len; 134 e->pos += len; 135 } 136 137 static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 138 const char *f, va_list args) 139 { 140 unsigned len; 141 142 if (!__i915_error_ok(e)) 143 return; 144 145 /* Seek the first printf which is hits start position */ 146 if (e->pos < e->start) { 147 va_list tmp; 148 149 va_copy(tmp, args); 150 len = vsnprintf(NULL, 0, f, tmp); 151 va_end(tmp); 152 153 if (!__i915_error_seek(e, len)) 154 return; 155 } 156 157 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args); 158 if (len >= e->size - e->bytes) 159 len = e->size - e->bytes - 1; 160 161 __i915_error_advance(e, len); 162 } 163 164 static void i915_error_puts(struct drm_i915_error_state_buf *e, 165 const char *str) 166 { 167 unsigned len; 168 169 if (!__i915_error_ok(e)) 170 return; 171 172 len = strlen(str); 173 174 /* Seek the first printf which is hits start position */ 175 if (e->pos < e->start) { 176 if (!__i915_error_seek(e, len)) 177 return; 178 } 179 180 if (len >= e->size - e->bytes) 181 len = e->size - e->bytes - 1; 182 memcpy(e->buf + e->bytes, str, len); 183 184 __i915_error_advance(e, len); 185 } 186 187 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 188 #define err_puts(e, s) i915_error_puts(e, s) 189 190 static void print_error_buffers(struct drm_i915_error_state_buf *m, 191 const char *name, 192 struct drm_i915_error_buffer *err, 193 int count) 194 { 195 int i; 196 197 err_printf(m, " %s [%d]:\n", name, count); 198 199 while (count--) { 200 err_printf(m, " %08x %8u %02x %02x [ ", 201 err->gtt_offset, 202 err->size, 203 err->read_domains, 204 err->write_domain); 205 for (i = 0; i < I915_NUM_RINGS; i++) 206 err_printf(m, "%02x ", err->rseqno[i]); 207 208 err_printf(m, "] %02x", err->wseqno); 209 err_puts(m, pin_flag(err->pinned)); 210 err_puts(m, tiling_flag(err->tiling)); 211 err_puts(m, dirty_flag(err->dirty)); 212 err_puts(m, purgeable_flag(err->purgeable)); 213 err_puts(m, err->userptr ? " userptr" : ""); 214 err_puts(m, err->ring != -1 ? " " : ""); 215 err_puts(m, ring_str(err->ring)); 216 err_puts(m, i915_cache_level_str(m->i915, err->cache_level)); 217 218 if (err->name) 219 err_printf(m, " (name: %d)", err->name); 220 if (err->fence_reg != I915_FENCE_REG_NONE) 221 err_printf(m, " (fence: %d)", err->fence_reg); 222 223 err_puts(m, "\n"); 224 err++; 225 } 226 } 227 228 static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a) 229 { 230 switch (a) { 231 case HANGCHECK_IDLE: 232 return "idle"; 233 case HANGCHECK_WAIT: 234 return "wait"; 235 case HANGCHECK_ACTIVE: 236 return "active"; 237 case HANGCHECK_ACTIVE_LOOP: 238 return "active (loop)"; 239 case HANGCHECK_KICK: 240 return "kick"; 241 case HANGCHECK_HUNG: 242 return "hung"; 243 } 244 245 return "unknown"; 246 } 247 248 static void i915_ring_error_state(struct drm_i915_error_state_buf *m, 249 struct drm_device *dev, 250 struct drm_i915_error_state *error, 251 int ring_idx) 252 { 253 struct drm_i915_error_ring *ring = &error->ring[ring_idx]; 254 255 if (!ring->valid) 256 return; 257 258 err_printf(m, "%s command stream:\n", ring_str(ring_idx)); 259 err_printf(m, " START: 0x%08x\n", ring->start); 260 err_printf(m, " HEAD: 0x%08x\n", ring->head); 261 err_printf(m, " TAIL: 0x%08x\n", ring->tail); 262 err_printf(m, " CTL: 0x%08x\n", ring->ctl); 263 err_printf(m, " HWS: 0x%08x\n", ring->hws); 264 err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd); 265 err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir); 266 err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr); 267 err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone); 268 if (INTEL_INFO(dev)->gen >= 4) { 269 err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr); 270 err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate); 271 err_printf(m, " INSTPS: 0x%08x\n", ring->instps); 272 } 273 err_printf(m, " INSTPM: 0x%08x\n", ring->instpm); 274 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr), 275 lower_32_bits(ring->faddr)); 276 if (INTEL_INFO(dev)->gen >= 6) { 277 err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi); 278 err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg); 279 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n", 280 ring->semaphore_mboxes[0], 281 ring->semaphore_seqno[0]); 282 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n", 283 ring->semaphore_mboxes[1], 284 ring->semaphore_seqno[1]); 285 if (HAS_VEBOX(dev)) { 286 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n", 287 ring->semaphore_mboxes[2], 288 ring->semaphore_seqno[2]); 289 } 290 } 291 if (USES_PPGTT(dev)) { 292 err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode); 293 294 if (INTEL_INFO(dev)->gen >= 8) { 295 int i; 296 for (i = 0; i < 4; i++) 297 err_printf(m, " PDP%d: 0x%016llx\n", 298 i, ring->vm_info.pdp[i]); 299 } else { 300 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 301 ring->vm_info.pp_dir_base); 302 } 303 } 304 err_printf(m, " seqno: 0x%08x\n", ring->seqno); 305 err_printf(m, " waiting: %s\n", yesno(ring->waiting)); 306 err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head); 307 err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail); 308 err_printf(m, " hangcheck: %s [%d]\n", 309 hangcheck_action_to_str(ring->hangcheck_action), 310 ring->hangcheck_score); 311 } 312 313 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 314 { 315 va_list args; 316 317 va_start(args, f); 318 i915_error_vprintf(e, f, args); 319 va_end(args); 320 } 321 322 static void print_error_obj(struct drm_i915_error_state_buf *m, 323 struct drm_i915_error_object *obj) 324 { 325 int page, offset, elt; 326 327 for (page = offset = 0; page < obj->page_count; page++) { 328 for (elt = 0; elt < PAGE_SIZE/4; elt++) { 329 err_printf(m, "%08x : %08x\n", offset, 330 obj->pages[page][elt]); 331 offset += 4; 332 } 333 } 334 } 335 336 int i915_error_state_to_str(struct drm_i915_error_state_buf *m, 337 const struct i915_error_state_file_priv *error_priv) 338 { 339 struct drm_device *dev = error_priv->dev; 340 struct drm_i915_private *dev_priv = dev->dev_private; 341 struct drm_i915_error_state *error = error_priv->error; 342 struct drm_i915_error_object *obj; 343 int i, j, offset, elt; 344 int max_hangcheck_score; 345 346 if (!error) { 347 err_printf(m, "no error state collected\n"); 348 goto out; 349 } 350 351 err_printf(m, "%s\n", error->error_msg); 352 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, 353 error->time.tv_usec); 354 err_printf(m, "Kernel: " UTS_RELEASE "\n"); 355 max_hangcheck_score = 0; 356 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 357 if (error->ring[i].hangcheck_score > max_hangcheck_score) 358 max_hangcheck_score = error->ring[i].hangcheck_score; 359 } 360 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 361 if (error->ring[i].hangcheck_score == max_hangcheck_score && 362 error->ring[i].pid != -1) { 363 err_printf(m, "Active process (on ring %s): %s [%d]\n", 364 ring_str(i), 365 error->ring[i].comm, 366 error->ring[i].pid); 367 } 368 } 369 err_printf(m, "Reset count: %u\n", error->reset_count); 370 err_printf(m, "Suspend count: %u\n", error->suspend_count); 371 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device); 372 err_printf(m, "EIR: 0x%08x\n", error->eir); 373 err_printf(m, "IER: 0x%08x\n", error->ier); 374 if (INTEL_INFO(dev)->gen >= 8) { 375 for (i = 0; i < 4; i++) 376 err_printf(m, "GTIER gt %d: 0x%08x\n", i, 377 error->gtier[i]); 378 } else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev)) 379 err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]); 380 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); 381 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); 382 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); 383 err_printf(m, "CCID: 0x%08x\n", error->ccid); 384 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings); 385 386 for (i = 0; i < dev_priv->num_fence_regs; i++) 387 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); 388 389 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++) 390 err_printf(m, " INSTDONE_%d: 0x%08x\n", i, 391 error->extra_instdone[i]); 392 393 if (INTEL_INFO(dev)->gen >= 6) { 394 err_printf(m, "ERROR: 0x%08x\n", error->error); 395 396 if (INTEL_INFO(dev)->gen >= 8) 397 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", 398 error->fault_data1, error->fault_data0); 399 400 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); 401 } 402 403 if (INTEL_INFO(dev)->gen == 7) 404 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); 405 406 for (i = 0; i < ARRAY_SIZE(error->ring); i++) 407 i915_ring_error_state(m, dev, error, i); 408 409 for (i = 0; i < error->vm_count; i++) { 410 err_printf(m, "vm[%d]\n", i); 411 412 print_error_buffers(m, "Active", 413 error->active_bo[i], 414 error->active_bo_count[i]); 415 416 print_error_buffers(m, "Pinned", 417 error->pinned_bo[i], 418 error->pinned_bo_count[i]); 419 } 420 421 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 422 obj = error->ring[i].batchbuffer; 423 if (obj) { 424 err_puts(m, dev_priv->ring[i].name); 425 if (error->ring[i].pid != -1) 426 err_printf(m, " (submitted by %s [%d])", 427 error->ring[i].comm, 428 error->ring[i].pid); 429 err_printf(m, " --- gtt_offset = 0x%08x\n", 430 obj->gtt_offset); 431 print_error_obj(m, obj); 432 } 433 434 obj = error->ring[i].wa_batchbuffer; 435 if (obj) { 436 err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n", 437 dev_priv->ring[i].name, obj->gtt_offset); 438 print_error_obj(m, obj); 439 } 440 441 if (error->ring[i].num_requests) { 442 err_printf(m, "%s --- %d requests\n", 443 dev_priv->ring[i].name, 444 error->ring[i].num_requests); 445 for (j = 0; j < error->ring[i].num_requests; j++) { 446 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n", 447 error->ring[i].requests[j].seqno, 448 error->ring[i].requests[j].jiffies, 449 error->ring[i].requests[j].tail); 450 } 451 } 452 453 if ((obj = error->ring[i].ringbuffer)) { 454 err_printf(m, "%s --- ringbuffer = 0x%08x\n", 455 dev_priv->ring[i].name, 456 obj->gtt_offset); 457 print_error_obj(m, obj); 458 } 459 460 if ((obj = error->ring[i].hws_page)) { 461 err_printf(m, "%s --- HW Status = 0x%08x\n", 462 dev_priv->ring[i].name, 463 obj->gtt_offset); 464 offset = 0; 465 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { 466 err_printf(m, "[%04x] %08x %08x %08x %08x\n", 467 offset, 468 obj->pages[0][elt], 469 obj->pages[0][elt+1], 470 obj->pages[0][elt+2], 471 obj->pages[0][elt+3]); 472 offset += 16; 473 } 474 } 475 476 if ((obj = error->ring[i].ctx)) { 477 err_printf(m, "%s --- HW Context = 0x%08x\n", 478 dev_priv->ring[i].name, 479 obj->gtt_offset); 480 print_error_obj(m, obj); 481 } 482 } 483 484 if ((obj = error->semaphore_obj)) { 485 err_printf(m, "Semaphore page = 0x%08x\n", obj->gtt_offset); 486 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { 487 err_printf(m, "[%04x] %08x %08x %08x %08x\n", 488 elt * 4, 489 obj->pages[0][elt], 490 obj->pages[0][elt+1], 491 obj->pages[0][elt+2], 492 obj->pages[0][elt+3]); 493 } 494 } 495 496 if (error->overlay) 497 intel_overlay_print_error_state(m, error->overlay); 498 499 if (error->display) 500 intel_display_print_error_state(m, dev, error->display); 501 502 out: 503 if (m->bytes == 0 && m->err) 504 return m->err; 505 506 return 0; 507 } 508 509 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf, 510 struct drm_i915_private *i915, 511 size_t count, loff_t pos) 512 { 513 memset(ebuf, 0, sizeof(*ebuf)); 514 ebuf->i915 = i915; 515 516 /* We need to have enough room to store any i915_error_state printf 517 * so that we can move it to start position. 518 */ 519 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE; 520 ebuf->buf = kmalloc(ebuf->size, 521 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN); 522 523 if (ebuf->buf == NULL) { 524 ebuf->size = PAGE_SIZE; 525 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 526 } 527 528 if (ebuf->buf == NULL) { 529 ebuf->size = 128; 530 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 531 } 532 533 if (ebuf->buf == NULL) 534 return -ENOMEM; 535 536 ebuf->start = pos; 537 538 return 0; 539 } 540 541 static void i915_error_object_free(struct drm_i915_error_object *obj) 542 { 543 int page; 544 545 if (obj == NULL) 546 return; 547 548 for (page = 0; page < obj->page_count; page++) 549 kfree(obj->pages[page]); 550 551 kfree(obj); 552 } 553 554 static void i915_error_state_free(struct kref *error_ref) 555 { 556 struct drm_i915_error_state *error = container_of(error_ref, 557 typeof(*error), ref); 558 int i; 559 560 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 561 i915_error_object_free(error->ring[i].batchbuffer); 562 i915_error_object_free(error->ring[i].wa_batchbuffer); 563 i915_error_object_free(error->ring[i].ringbuffer); 564 i915_error_object_free(error->ring[i].hws_page); 565 i915_error_object_free(error->ring[i].ctx); 566 kfree(error->ring[i].requests); 567 } 568 569 i915_error_object_free(error->semaphore_obj); 570 571 for (i = 0; i < error->vm_count; i++) 572 kfree(error->active_bo[i]); 573 574 kfree(error->active_bo); 575 kfree(error->active_bo_count); 576 kfree(error->pinned_bo); 577 kfree(error->pinned_bo_count); 578 kfree(error->overlay); 579 kfree(error->display); 580 kfree(error); 581 } 582 583 static struct drm_i915_error_object * 584 i915_error_object_create(struct drm_i915_private *dev_priv, 585 struct drm_i915_gem_object *src, 586 struct i915_address_space *vm) 587 { 588 struct drm_i915_error_object *dst; 589 struct i915_vma *vma = NULL; 590 int num_pages; 591 bool use_ggtt; 592 int i = 0; 593 u32 reloc_offset; 594 595 if (src == NULL || src->pages == NULL) 596 return NULL; 597 598 num_pages = src->base.size >> PAGE_SHIFT; 599 600 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC); 601 if (dst == NULL) 602 return NULL; 603 604 if (i915_gem_obj_bound(src, vm)) 605 dst->gtt_offset = i915_gem_obj_offset(src, vm); 606 else 607 dst->gtt_offset = -1; 608 609 reloc_offset = dst->gtt_offset; 610 if (i915_is_ggtt(vm)) 611 vma = i915_gem_obj_to_ggtt(src); 612 use_ggtt = (src->cache_level == I915_CACHE_NONE && 613 vma && (vma->bound & GLOBAL_BIND) && 614 reloc_offset + num_pages * PAGE_SIZE <= dev_priv->gtt.mappable_end); 615 616 /* Cannot access stolen address directly, try to use the aperture */ 617 if (src->stolen) { 618 use_ggtt = true; 619 620 if (!(vma && vma->bound & GLOBAL_BIND)) 621 goto unwind; 622 623 reloc_offset = i915_gem_obj_ggtt_offset(src); 624 if (reloc_offset + num_pages * PAGE_SIZE > dev_priv->gtt.mappable_end) 625 goto unwind; 626 } 627 628 /* Cannot access snooped pages through the aperture */ 629 if (use_ggtt && src->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv->dev)) 630 goto unwind; 631 632 dst->page_count = num_pages; 633 while (num_pages--) { 634 unsigned long flags; 635 void *d; 636 637 d = kmalloc(PAGE_SIZE, GFP_ATOMIC); 638 if (d == NULL) 639 goto unwind; 640 641 local_irq_save(flags); 642 if (use_ggtt) { 643 void __iomem *s; 644 645 /* Simply ignore tiling or any overlapping fence. 646 * It's part of the error state, and this hopefully 647 * captures what the GPU read. 648 */ 649 650 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, 651 reloc_offset); 652 memcpy_fromio(d, s, PAGE_SIZE); 653 io_mapping_unmap_atomic(s); 654 } else { 655 struct page *page; 656 void *s; 657 658 page = i915_gem_object_get_page(src, i); 659 660 drm_clflush_pages(&page, 1); 661 662 s = kmap_atomic(page); 663 memcpy(d, s, PAGE_SIZE); 664 kunmap_atomic(s); 665 666 drm_clflush_pages(&page, 1); 667 } 668 local_irq_restore(flags); 669 670 dst->pages[i++] = d; 671 reloc_offset += PAGE_SIZE; 672 } 673 674 return dst; 675 676 unwind: 677 while (i--) 678 kfree(dst->pages[i]); 679 kfree(dst); 680 return NULL; 681 } 682 #define i915_error_ggtt_object_create(dev_priv, src) \ 683 i915_error_object_create((dev_priv), (src), &(dev_priv)->gtt.base) 684 685 static void capture_bo(struct drm_i915_error_buffer *err, 686 struct i915_vma *vma) 687 { 688 struct drm_i915_gem_object *obj = vma->obj; 689 int i; 690 691 err->size = obj->base.size; 692 err->name = obj->base.name; 693 for (i = 0; i < I915_NUM_RINGS; i++) 694 err->rseqno[i] = i915_gem_request_get_seqno(obj->last_read_req[i]); 695 err->wseqno = i915_gem_request_get_seqno(obj->last_write_req); 696 err->gtt_offset = vma->node.start; 697 err->read_domains = obj->base.read_domains; 698 err->write_domain = obj->base.write_domain; 699 err->fence_reg = obj->fence_reg; 700 err->pinned = 0; 701 if (i915_gem_obj_is_pinned(obj)) 702 err->pinned = 1; 703 err->tiling = obj->tiling_mode; 704 err->dirty = obj->dirty; 705 err->purgeable = obj->madv != I915_MADV_WILLNEED; 706 err->userptr = obj->userptr.mm != NULL; 707 err->ring = obj->last_write_req ? 708 i915_gem_request_get_ring(obj->last_write_req)->id : -1; 709 err->cache_level = obj->cache_level; 710 } 711 712 static u32 capture_active_bo(struct drm_i915_error_buffer *err, 713 int count, struct list_head *head) 714 { 715 struct i915_vma *vma; 716 int i = 0; 717 718 list_for_each_entry(vma, head, mm_list) { 719 capture_bo(err++, vma); 720 if (++i == count) 721 break; 722 } 723 724 return i; 725 } 726 727 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err, 728 int count, struct list_head *head, 729 struct i915_address_space *vm) 730 { 731 struct drm_i915_gem_object *obj; 732 struct drm_i915_error_buffer * const first = err; 733 struct drm_i915_error_buffer * const last = err + count; 734 735 list_for_each_entry(obj, head, global_list) { 736 struct i915_vma *vma; 737 738 if (err == last) 739 break; 740 741 list_for_each_entry(vma, &obj->vma_list, vma_link) 742 if (vma->vm == vm && vma->pin_count > 0) 743 capture_bo(err++, vma); 744 } 745 746 return err - first; 747 } 748 749 /* Generate a semi-unique error code. The code is not meant to have meaning, The 750 * code's only purpose is to try to prevent false duplicated bug reports by 751 * grossly estimating a GPU error state. 752 * 753 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 754 * the hang if we could strip the GTT offset information from it. 755 * 756 * It's only a small step better than a random number in its current form. 757 */ 758 static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv, 759 struct drm_i915_error_state *error, 760 int *ring_id) 761 { 762 uint32_t error_code = 0; 763 int i; 764 765 /* IPEHR would be an ideal way to detect errors, as it's the gross 766 * measure of "the command that hung." However, has some very common 767 * synchronization commands which almost always appear in the case 768 * strictly a client bug. Use instdone to differentiate those some. 769 */ 770 for (i = 0; i < I915_NUM_RINGS; i++) { 771 if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) { 772 if (ring_id) 773 *ring_id = i; 774 775 return error->ring[i].ipehr ^ error->ring[i].instdone; 776 } 777 } 778 779 return error_code; 780 } 781 782 static void i915_gem_record_fences(struct drm_device *dev, 783 struct drm_i915_error_state *error) 784 { 785 struct drm_i915_private *dev_priv = dev->dev_private; 786 int i; 787 788 if (IS_GEN3(dev) || IS_GEN2(dev)) { 789 for (i = 0; i < 8; i++) 790 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); 791 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 792 for (i = 0; i < 8; i++) 793 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + 794 (i * 4)); 795 } else if (IS_GEN5(dev) || IS_GEN4(dev)) 796 for (i = 0; i < 16; i++) 797 error->fence[i] = I915_READ64(FENCE_REG_965_0 + 798 (i * 8)); 799 else if (INTEL_INFO(dev)->gen >= 6) 800 for (i = 0; i < dev_priv->num_fence_regs; i++) 801 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + 802 (i * 8)); 803 } 804 805 806 static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv, 807 struct drm_i915_error_state *error, 808 struct intel_engine_cs *ring, 809 struct drm_i915_error_ring *ering) 810 { 811 struct intel_engine_cs *to; 812 int i; 813 814 if (!i915_semaphore_is_enabled(dev_priv->dev)) 815 return; 816 817 if (!error->semaphore_obj) 818 error->semaphore_obj = 819 i915_error_ggtt_object_create(dev_priv, 820 dev_priv->semaphore_obj); 821 822 for_each_ring(to, dev_priv, i) { 823 int idx; 824 u16 signal_offset; 825 u32 *tmp; 826 827 if (ring == to) 828 continue; 829 830 signal_offset = (GEN8_SIGNAL_OFFSET(ring, i) & (PAGE_SIZE - 1)) 831 / 4; 832 tmp = error->semaphore_obj->pages[0]; 833 idx = intel_ring_sync_index(ring, to); 834 835 ering->semaphore_mboxes[idx] = tmp[signal_offset]; 836 ering->semaphore_seqno[idx] = ring->semaphore.sync_seqno[idx]; 837 } 838 } 839 840 static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv, 841 struct intel_engine_cs *ring, 842 struct drm_i915_error_ring *ering) 843 { 844 ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(ring->mmio_base)); 845 ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(ring->mmio_base)); 846 ering->semaphore_seqno[0] = ring->semaphore.sync_seqno[0]; 847 ering->semaphore_seqno[1] = ring->semaphore.sync_seqno[1]; 848 849 if (HAS_VEBOX(dev_priv->dev)) { 850 ering->semaphore_mboxes[2] = 851 I915_READ(RING_SYNC_2(ring->mmio_base)); 852 ering->semaphore_seqno[2] = ring->semaphore.sync_seqno[2]; 853 } 854 } 855 856 static void i915_record_ring_state(struct drm_device *dev, 857 struct drm_i915_error_state *error, 858 struct intel_engine_cs *ring, 859 struct drm_i915_error_ring *ering) 860 { 861 struct drm_i915_private *dev_priv = dev->dev_private; 862 863 if (INTEL_INFO(dev)->gen >= 6) { 864 ering->rc_psmi = I915_READ(ring->mmio_base + 0x50); 865 ering->fault_reg = I915_READ(RING_FAULT_REG(ring)); 866 if (INTEL_INFO(dev)->gen >= 8) 867 gen8_record_semaphore_state(dev_priv, error, ring, ering); 868 else 869 gen6_record_semaphore_state(dev_priv, ring, ering); 870 } 871 872 if (INTEL_INFO(dev)->gen >= 4) { 873 ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base)); 874 ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base)); 875 ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); 876 ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base)); 877 ering->instps = I915_READ(RING_INSTPS(ring->mmio_base)); 878 ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base)); 879 if (INTEL_INFO(dev)->gen >= 8) { 880 ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(ring->mmio_base)) << 32; 881 ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32; 882 } 883 ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base)); 884 } else { 885 ering->faddr = I915_READ(DMA_FADD_I8XX); 886 ering->ipeir = I915_READ(IPEIR); 887 ering->ipehr = I915_READ(IPEHR); 888 ering->instdone = I915_READ(INSTDONE); 889 } 890 891 ering->waiting = waitqueue_active(&ring->irq_queue); 892 ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base)); 893 ering->seqno = ring->get_seqno(ring, false); 894 ering->acthd = intel_ring_get_active_head(ring); 895 ering->start = I915_READ_START(ring); 896 ering->head = I915_READ_HEAD(ring); 897 ering->tail = I915_READ_TAIL(ring); 898 ering->ctl = I915_READ_CTL(ring); 899 900 if (I915_NEED_GFX_HWS(dev)) { 901 int mmio; 902 903 if (IS_GEN7(dev)) { 904 switch (ring->id) { 905 default: 906 case RCS: 907 mmio = RENDER_HWS_PGA_GEN7; 908 break; 909 case BCS: 910 mmio = BLT_HWS_PGA_GEN7; 911 break; 912 case VCS: 913 mmio = BSD_HWS_PGA_GEN7; 914 break; 915 case VECS: 916 mmio = VEBOX_HWS_PGA_GEN7; 917 break; 918 } 919 } else if (IS_GEN6(ring->dev)) { 920 mmio = RING_HWS_PGA_GEN6(ring->mmio_base); 921 } else { 922 /* XXX: gen8 returns to sanity */ 923 mmio = RING_HWS_PGA(ring->mmio_base); 924 } 925 926 ering->hws = I915_READ(mmio); 927 } 928 929 ering->hangcheck_score = ring->hangcheck.score; 930 ering->hangcheck_action = ring->hangcheck.action; 931 932 if (USES_PPGTT(dev)) { 933 int i; 934 935 ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring)); 936 937 if (IS_GEN6(dev)) 938 ering->vm_info.pp_dir_base = 939 I915_READ(RING_PP_DIR_BASE_READ(ring)); 940 else if (IS_GEN7(dev)) 941 ering->vm_info.pp_dir_base = 942 I915_READ(RING_PP_DIR_BASE(ring)); 943 else if (INTEL_INFO(dev)->gen >= 8) 944 for (i = 0; i < 4; i++) { 945 ering->vm_info.pdp[i] = 946 I915_READ(GEN8_RING_PDP_UDW(ring, i)); 947 ering->vm_info.pdp[i] <<= 32; 948 ering->vm_info.pdp[i] |= 949 I915_READ(GEN8_RING_PDP_LDW(ring, i)); 950 } 951 } 952 } 953 954 955 static void i915_gem_record_active_context(struct intel_engine_cs *ring, 956 struct drm_i915_error_state *error, 957 struct drm_i915_error_ring *ering) 958 { 959 struct drm_i915_private *dev_priv = ring->dev->dev_private; 960 struct drm_i915_gem_object *obj; 961 962 /* Currently render ring is the only HW context user */ 963 if (ring->id != RCS || !error->ccid) 964 return; 965 966 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 967 if (!i915_gem_obj_ggtt_bound(obj)) 968 continue; 969 970 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) { 971 ering->ctx = i915_error_ggtt_object_create(dev_priv, obj); 972 break; 973 } 974 } 975 } 976 977 static void i915_gem_record_rings(struct drm_device *dev, 978 struct drm_i915_error_state *error) 979 { 980 struct drm_i915_private *dev_priv = dev->dev_private; 981 struct drm_i915_gem_request *request; 982 int i, count; 983 984 for (i = 0; i < I915_NUM_RINGS; i++) { 985 struct intel_engine_cs *ring = &dev_priv->ring[i]; 986 struct intel_ringbuffer *rbuf; 987 988 error->ring[i].pid = -1; 989 990 if (ring->dev == NULL) 991 continue; 992 993 error->ring[i].valid = true; 994 995 i915_record_ring_state(dev, error, ring, &error->ring[i]); 996 997 request = i915_gem_find_active_request(ring); 998 if (request) { 999 struct i915_address_space *vm; 1000 1001 vm = request->ctx && request->ctx->ppgtt ? 1002 &request->ctx->ppgtt->base : 1003 &dev_priv->gtt.base; 1004 1005 /* We need to copy these to an anonymous buffer 1006 * as the simplest method to avoid being overwritten 1007 * by userspace. 1008 */ 1009 error->ring[i].batchbuffer = 1010 i915_error_object_create(dev_priv, 1011 request->batch_obj, 1012 vm); 1013 1014 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) 1015 error->ring[i].wa_batchbuffer = 1016 i915_error_ggtt_object_create(dev_priv, 1017 ring->scratch.obj); 1018 1019 if (request->pid) { 1020 struct task_struct *task; 1021 1022 rcu_read_lock(); 1023 task = pid_task(request->pid, PIDTYPE_PID); 1024 if (task) { 1025 strcpy(error->ring[i].comm, task->comm); 1026 error->ring[i].pid = task->pid; 1027 } 1028 rcu_read_unlock(); 1029 } 1030 } 1031 1032 if (i915.enable_execlists) { 1033 /* TODO: This is only a small fix to keep basic error 1034 * capture working, but we need to add more information 1035 * for it to be useful (e.g. dump the context being 1036 * executed). 1037 */ 1038 if (request) 1039 rbuf = request->ctx->engine[ring->id].ringbuf; 1040 else 1041 rbuf = ring->default_context->engine[ring->id].ringbuf; 1042 } else 1043 rbuf = ring->buffer; 1044 1045 error->ring[i].cpu_ring_head = rbuf->head; 1046 error->ring[i].cpu_ring_tail = rbuf->tail; 1047 1048 error->ring[i].ringbuffer = 1049 i915_error_ggtt_object_create(dev_priv, rbuf->obj); 1050 1051 error->ring[i].hws_page = 1052 i915_error_ggtt_object_create(dev_priv, ring->status_page.obj); 1053 1054 i915_gem_record_active_context(ring, error, &error->ring[i]); 1055 1056 count = 0; 1057 list_for_each_entry(request, &ring->request_list, list) 1058 count++; 1059 1060 error->ring[i].num_requests = count; 1061 error->ring[i].requests = 1062 kcalloc(count, sizeof(*error->ring[i].requests), 1063 GFP_ATOMIC); 1064 if (error->ring[i].requests == NULL) { 1065 error->ring[i].num_requests = 0; 1066 continue; 1067 } 1068 1069 count = 0; 1070 list_for_each_entry(request, &ring->request_list, list) { 1071 struct drm_i915_error_request *erq; 1072 1073 erq = &error->ring[i].requests[count++]; 1074 erq->seqno = request->seqno; 1075 erq->jiffies = request->emitted_jiffies; 1076 erq->tail = request->postfix; 1077 } 1078 } 1079 } 1080 1081 /* FIXME: Since pin count/bound list is global, we duplicate what we capture per 1082 * VM. 1083 */ 1084 static void i915_gem_capture_vm(struct drm_i915_private *dev_priv, 1085 struct drm_i915_error_state *error, 1086 struct i915_address_space *vm, 1087 const int ndx) 1088 { 1089 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL; 1090 struct drm_i915_gem_object *obj; 1091 struct i915_vma *vma; 1092 int i; 1093 1094 i = 0; 1095 list_for_each_entry(vma, &vm->active_list, mm_list) 1096 i++; 1097 error->active_bo_count[ndx] = i; 1098 1099 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 1100 list_for_each_entry(vma, &obj->vma_list, vma_link) 1101 if (vma->vm == vm && vma->pin_count > 0) 1102 i++; 1103 } 1104 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx]; 1105 1106 if (i) { 1107 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC); 1108 if (active_bo) 1109 pinned_bo = active_bo + error->active_bo_count[ndx]; 1110 } 1111 1112 if (active_bo) 1113 error->active_bo_count[ndx] = 1114 capture_active_bo(active_bo, 1115 error->active_bo_count[ndx], 1116 &vm->active_list); 1117 1118 if (pinned_bo) 1119 error->pinned_bo_count[ndx] = 1120 capture_pinned_bo(pinned_bo, 1121 error->pinned_bo_count[ndx], 1122 &dev_priv->mm.bound_list, vm); 1123 error->active_bo[ndx] = active_bo; 1124 error->pinned_bo[ndx] = pinned_bo; 1125 } 1126 1127 static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv, 1128 struct drm_i915_error_state *error) 1129 { 1130 struct i915_address_space *vm; 1131 int cnt = 0, i = 0; 1132 1133 list_for_each_entry(vm, &dev_priv->vm_list, global_link) 1134 cnt++; 1135 1136 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC); 1137 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC); 1138 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count), 1139 GFP_ATOMIC); 1140 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count), 1141 GFP_ATOMIC); 1142 1143 if (error->active_bo == NULL || 1144 error->pinned_bo == NULL || 1145 error->active_bo_count == NULL || 1146 error->pinned_bo_count == NULL) { 1147 kfree(error->active_bo); 1148 kfree(error->active_bo_count); 1149 kfree(error->pinned_bo); 1150 kfree(error->pinned_bo_count); 1151 1152 error->active_bo = NULL; 1153 error->active_bo_count = NULL; 1154 error->pinned_bo = NULL; 1155 error->pinned_bo_count = NULL; 1156 } else { 1157 list_for_each_entry(vm, &dev_priv->vm_list, global_link) 1158 i915_gem_capture_vm(dev_priv, error, vm, i++); 1159 1160 error->vm_count = cnt; 1161 } 1162 } 1163 1164 /* Capture all registers which don't fit into another category. */ 1165 static void i915_capture_reg_state(struct drm_i915_private *dev_priv, 1166 struct drm_i915_error_state *error) 1167 { 1168 struct drm_device *dev = dev_priv->dev; 1169 int i; 1170 1171 /* General organization 1172 * 1. Registers specific to a single generation 1173 * 2. Registers which belong to multiple generations 1174 * 3. Feature specific registers. 1175 * 4. Everything else 1176 * Please try to follow the order. 1177 */ 1178 1179 /* 1: Registers specific to a single generation */ 1180 if (IS_VALLEYVIEW(dev)) { 1181 error->gtier[0] = I915_READ(GTIER); 1182 error->ier = I915_READ(VLV_IER); 1183 error->forcewake = I915_READ(FORCEWAKE_VLV); 1184 } 1185 1186 if (IS_GEN7(dev)) 1187 error->err_int = I915_READ(GEN7_ERR_INT); 1188 1189 if (INTEL_INFO(dev)->gen >= 8) { 1190 error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0); 1191 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1); 1192 } 1193 1194 if (IS_GEN6(dev)) { 1195 error->forcewake = I915_READ(FORCEWAKE); 1196 error->gab_ctl = I915_READ(GAB_CTL); 1197 error->gfx_mode = I915_READ(GFX_MODE); 1198 } 1199 1200 /* 2: Registers which belong to multiple generations */ 1201 if (INTEL_INFO(dev)->gen >= 7) 1202 error->forcewake = I915_READ(FORCEWAKE_MT); 1203 1204 if (INTEL_INFO(dev)->gen >= 6) { 1205 error->derrmr = I915_READ(DERRMR); 1206 error->error = I915_READ(ERROR_GEN6); 1207 error->done_reg = I915_READ(DONE_REG); 1208 } 1209 1210 /* 3: Feature specific registers */ 1211 if (IS_GEN6(dev) || IS_GEN7(dev)) { 1212 error->gam_ecochk = I915_READ(GAM_ECOCHK); 1213 error->gac_eco = I915_READ(GAC_ECO_BITS); 1214 } 1215 1216 /* 4: Everything else */ 1217 if (HAS_HW_CONTEXTS(dev)) 1218 error->ccid = I915_READ(CCID); 1219 1220 if (INTEL_INFO(dev)->gen >= 8) { 1221 error->ier = I915_READ(GEN8_DE_MISC_IER); 1222 for (i = 0; i < 4; i++) 1223 error->gtier[i] = I915_READ(GEN8_GT_IER(i)); 1224 } else if (HAS_PCH_SPLIT(dev)) { 1225 error->ier = I915_READ(DEIER); 1226 error->gtier[0] = I915_READ(GTIER); 1227 } else if (IS_GEN2(dev)) { 1228 error->ier = I915_READ16(IER); 1229 } else if (!IS_VALLEYVIEW(dev)) { 1230 error->ier = I915_READ(IER); 1231 } 1232 error->eir = I915_READ(EIR); 1233 error->pgtbl_er = I915_READ(PGTBL_ER); 1234 1235 i915_get_extra_instdone(dev, error->extra_instdone); 1236 } 1237 1238 static void i915_error_capture_msg(struct drm_device *dev, 1239 struct drm_i915_error_state *error, 1240 bool wedged, 1241 const char *error_msg) 1242 { 1243 struct drm_i915_private *dev_priv = dev->dev_private; 1244 u32 ecode; 1245 int ring_id = -1, len; 1246 1247 ecode = i915_error_generate_code(dev_priv, error, &ring_id); 1248 1249 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1250 "GPU HANG: ecode %d:%d:0x%08x", 1251 INTEL_INFO(dev)->gen, ring_id, ecode); 1252 1253 if (ring_id != -1 && error->ring[ring_id].pid != -1) 1254 len += scnprintf(error->error_msg + len, 1255 sizeof(error->error_msg) - len, 1256 ", in %s [%d]", 1257 error->ring[ring_id].comm, 1258 error->ring[ring_id].pid); 1259 1260 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len, 1261 ", reason: %s, action: %s", 1262 error_msg, 1263 wedged ? "reset" : "continue"); 1264 } 1265 1266 static void i915_capture_gen_state(struct drm_i915_private *dev_priv, 1267 struct drm_i915_error_state *error) 1268 { 1269 error->reset_count = i915_reset_count(&dev_priv->gpu_error); 1270 error->suspend_count = dev_priv->suspend_count; 1271 } 1272 1273 /** 1274 * i915_capture_error_state - capture an error record for later analysis 1275 * @dev: drm device 1276 * 1277 * Should be called when an error is detected (either a hang or an error 1278 * interrupt) to capture error state from the time of the error. Fills 1279 * out a structure which becomes available in debugfs for user level tools 1280 * to pick up. 1281 */ 1282 void i915_capture_error_state(struct drm_device *dev, bool wedged, 1283 const char *error_msg) 1284 { 1285 static bool warned; 1286 struct drm_i915_private *dev_priv = dev->dev_private; 1287 struct drm_i915_error_state *error; 1288 unsigned long flags; 1289 1290 /* Account for pipe specific data like PIPE*STAT */ 1291 error = kzalloc(sizeof(*error), GFP_ATOMIC); 1292 if (!error) { 1293 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); 1294 return; 1295 } 1296 1297 kref_init(&error->ref); 1298 1299 i915_capture_gen_state(dev_priv, error); 1300 i915_capture_reg_state(dev_priv, error); 1301 i915_gem_capture_buffers(dev_priv, error); 1302 i915_gem_record_fences(dev, error); 1303 i915_gem_record_rings(dev, error); 1304 1305 do_gettimeofday(&error->time); 1306 1307 error->overlay = intel_overlay_capture_error_state(dev); 1308 error->display = intel_display_capture_error_state(dev); 1309 1310 i915_error_capture_msg(dev, error, wedged, error_msg); 1311 DRM_INFO("%s\n", error->error_msg); 1312 1313 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 1314 if (dev_priv->gpu_error.first_error == NULL) { 1315 dev_priv->gpu_error.first_error = error; 1316 error = NULL; 1317 } 1318 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 1319 1320 if (error) { 1321 i915_error_state_free(&error->ref); 1322 return; 1323 } 1324 1325 if (!warned) { 1326 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 1327 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n"); 1328 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 1329 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n"); 1330 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index); 1331 warned = true; 1332 } 1333 } 1334 1335 void i915_error_state_get(struct drm_device *dev, 1336 struct i915_error_state_file_priv *error_priv) 1337 { 1338 struct drm_i915_private *dev_priv = dev->dev_private; 1339 1340 spin_lock_irq(&dev_priv->gpu_error.lock); 1341 error_priv->error = dev_priv->gpu_error.first_error; 1342 if (error_priv->error) 1343 kref_get(&error_priv->error->ref); 1344 spin_unlock_irq(&dev_priv->gpu_error.lock); 1345 1346 } 1347 1348 void i915_error_state_put(struct i915_error_state_file_priv *error_priv) 1349 { 1350 if (error_priv->error) 1351 kref_put(&error_priv->error->ref, i915_error_state_free); 1352 } 1353 1354 void i915_destroy_error_state(struct drm_device *dev) 1355 { 1356 struct drm_i915_private *dev_priv = dev->dev_private; 1357 struct drm_i915_error_state *error; 1358 1359 spin_lock_irq(&dev_priv->gpu_error.lock); 1360 error = dev_priv->gpu_error.first_error; 1361 dev_priv->gpu_error.first_error = NULL; 1362 spin_unlock_irq(&dev_priv->gpu_error.lock); 1363 1364 if (error) 1365 kref_put(&error->ref, i915_error_state_free); 1366 } 1367 1368 const char *i915_cache_level_str(struct drm_i915_private *i915, int type) 1369 { 1370 switch (type) { 1371 case I915_CACHE_NONE: return " uncached"; 1372 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped"; 1373 case I915_CACHE_L3_LLC: return " L3+LLC"; 1374 case I915_CACHE_WT: return " WT"; 1375 default: return ""; 1376 } 1377 } 1378 1379 /* NB: please notice the memset */ 1380 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone) 1381 { 1382 struct drm_i915_private *dev_priv = dev->dev_private; 1383 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG); 1384 1385 if (IS_GEN2(dev) || IS_GEN3(dev)) 1386 instdone[0] = I915_READ(INSTDONE); 1387 else if (IS_GEN4(dev) || IS_GEN5(dev) || IS_GEN6(dev)) { 1388 instdone[0] = I915_READ(INSTDONE_I965); 1389 instdone[1] = I915_READ(INSTDONE1); 1390 } else if (INTEL_INFO(dev)->gen >= 7) { 1391 instdone[0] = I915_READ(GEN7_INSTDONE_1); 1392 instdone[1] = I915_READ(GEN7_SC_INSTDONE); 1393 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE); 1394 instdone[3] = I915_READ(GEN7_ROW_INSTDONE); 1395 } 1396 } 1397