1 // SPDX-License-Identifier: MIT 2 /* Copyright © 2025 Intel Corporation */ 3 4 #include <linux/pnp.h> 5 6 #include <drm/drm_managed.h> 7 #include <drm/drm_print.h> 8 9 #include "i915_drv.h" 10 #include "i915_gmch.h" 11 #include "intel_pci_config.h" 12 13 static void i915_gmch_bridge_release(struct drm_device *dev, void *bridge) 14 { 15 pci_dev_put(bridge); 16 } 17 18 int i915_gmch_bridge_setup(struct drm_i915_private *i915) 19 { 20 int domain = pci_domain_nr(to_pci_dev(i915->drm.dev)->bus); 21 22 i915->gmch.pdev = pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0)); 23 if (!i915->gmch.pdev) { 24 drm_err(&i915->drm, "bridge device not found\n"); 25 return -EIO; 26 } 27 28 return drmm_add_action_or_reset(&i915->drm, i915_gmch_bridge_release, 29 i915->gmch.pdev); 30 } 31 32 static int mchbar_reg(struct drm_i915_private *i915) 33 { 34 return GRAPHICS_VER(i915) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 35 } 36 37 /* Allocate space for the MCH regs if needed, return nonzero on error */ 38 static int 39 intel_alloc_mchbar_resource(struct drm_i915_private *i915) 40 { 41 u32 temp_lo, temp_hi = 0; 42 u64 mchbar_addr; 43 int ret; 44 45 if (GRAPHICS_VER(i915) >= 4) 46 pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915) + 4, &temp_hi); 47 pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp_lo); 48 mchbar_addr = ((u64)temp_hi << 32) | temp_lo; 49 50 /* If ACPI doesn't have it, assume we need to allocate it ourselves */ 51 if (IS_ENABLED(CONFIG_PNP) && mchbar_addr && 52 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) 53 return 0; 54 55 /* Get some space for it */ 56 i915->gmch.mch_res.name = "i915 MCHBAR"; 57 i915->gmch.mch_res.flags = IORESOURCE_MEM; 58 ret = pci_bus_alloc_resource(i915->gmch.pdev->bus, 59 &i915->gmch.mch_res, 60 MCHBAR_SIZE, MCHBAR_SIZE, 61 PCIBIOS_MIN_MEM, 62 0, pcibios_align_resource, 63 i915->gmch.pdev); 64 if (ret) { 65 drm_dbg(&i915->drm, "failed bus alloc: %d\n", ret); 66 i915->gmch.mch_res.start = 0; 67 return ret; 68 } 69 70 if (GRAPHICS_VER(i915) >= 4) 71 pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915) + 4, 72 upper_32_bits(i915->gmch.mch_res.start)); 73 74 pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915), 75 lower_32_bits(i915->gmch.mch_res.start)); 76 return 0; 77 } 78 79 /* Setup MCHBAR if possible, return true if we should disable it again */ 80 void i915_gmch_bar_setup(struct drm_i915_private *i915) 81 { 82 u32 temp; 83 bool enabled; 84 85 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 86 return; 87 88 i915->gmch.mchbar_need_disable = false; 89 90 if (IS_I915G(i915) || IS_I915GM(i915)) { 91 pci_read_config_dword(i915->gmch.pdev, DEVEN, &temp); 92 enabled = !!(temp & DEVEN_MCHBAR_EN); 93 } else { 94 pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp); 95 enabled = temp & 1; 96 } 97 98 /* If it's already enabled, don't have to do anything */ 99 if (enabled) 100 return; 101 102 if (intel_alloc_mchbar_resource(i915)) 103 return; 104 105 i915->gmch.mchbar_need_disable = true; 106 107 /* Space is allocated or reserved, so enable it. */ 108 if (IS_I915G(i915) || IS_I915GM(i915)) { 109 pci_write_config_dword(i915->gmch.pdev, DEVEN, 110 temp | DEVEN_MCHBAR_EN); 111 } else { 112 pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp); 113 pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915), temp | 1); 114 } 115 } 116 117 void i915_gmch_bar_teardown(struct drm_i915_private *i915) 118 { 119 if (i915->gmch.mchbar_need_disable) { 120 if (IS_I915G(i915) || IS_I915GM(i915)) { 121 u32 deven_val; 122 123 pci_read_config_dword(i915->gmch.pdev, DEVEN, 124 &deven_val); 125 deven_val &= ~DEVEN_MCHBAR_EN; 126 pci_write_config_dword(i915->gmch.pdev, DEVEN, 127 deven_val); 128 } else { 129 u32 mchbar_val; 130 131 pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), 132 &mchbar_val); 133 mchbar_val &= ~1; 134 pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915), 135 mchbar_val); 136 } 137 } 138 139 if (i915->gmch.mch_res.start) 140 release_resource(&i915->gmch.mch_res); 141 } 142