1 /* 2 * SPDX-License-Identifier: MIT 3 */ 4 5 #include "display/intel_overlay.h" 6 #include "gem/i915_gem_mman.h" 7 #include "gt/intel_engine_user.h" 8 #include "pxp/intel_pxp.h" 9 10 #include "i915_cmd_parser.h" 11 #include "i915_drv.h" 12 #include "i915_getparam.h" 13 #include "i915_perf.h" 14 15 int i915_getparam_ioctl(struct drm_device *dev, void *data, 16 struct drm_file *file_priv) 17 { 18 struct drm_i915_private *i915 = to_i915(dev); 19 struct intel_display *display = &i915->display; 20 struct pci_dev *pdev = to_pci_dev(dev->dev); 21 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu; 22 drm_i915_getparam_t *param = data; 23 int value = 0; 24 25 switch (param->param) { 26 case I915_PARAM_IRQ_ACTIVE: 27 case I915_PARAM_ALLOW_BATCHBUFFER: 28 case I915_PARAM_LAST_DISPATCH: 29 case I915_PARAM_HAS_EXEC_CONSTANTS: 30 /* Reject all old ums/dri params. */ 31 return -ENODEV; 32 case I915_PARAM_CHIPSET_ID: 33 value = pdev->device; 34 break; 35 case I915_PARAM_REVISION: 36 value = pdev->revision; 37 break; 38 case I915_PARAM_NUM_FENCES_AVAIL: 39 value = to_gt(i915)->ggtt->num_fences; 40 break; 41 case I915_PARAM_HAS_OVERLAY: 42 value = intel_overlay_available(display); 43 break; 44 case I915_PARAM_HAS_BSD: 45 value = !!intel_engine_lookup_user(i915, 46 I915_ENGINE_CLASS_VIDEO, 0); 47 break; 48 case I915_PARAM_HAS_BLT: 49 value = !!intel_engine_lookup_user(i915, 50 I915_ENGINE_CLASS_COPY, 0); 51 break; 52 case I915_PARAM_HAS_VEBOX: 53 value = !!intel_engine_lookup_user(i915, 54 I915_ENGINE_CLASS_VIDEO_ENHANCE, 0); 55 break; 56 case I915_PARAM_HAS_BSD2: 57 value = !!intel_engine_lookup_user(i915, 58 I915_ENGINE_CLASS_VIDEO, 1); 59 break; 60 case I915_PARAM_HAS_LLC: 61 value = HAS_LLC(i915); 62 break; 63 case I915_PARAM_HAS_WT: 64 value = HAS_WT(i915); 65 break; 66 case I915_PARAM_HAS_ALIASING_PPGTT: 67 value = INTEL_PPGTT(i915); 68 break; 69 case I915_PARAM_HAS_SEMAPHORES: 70 value = !!(i915->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES); 71 break; 72 case I915_PARAM_HAS_SECURE_BATCHES: 73 value = HAS_SECURE_BATCHES(i915) && capable(CAP_SYS_ADMIN); 74 break; 75 case I915_PARAM_CMD_PARSER_VERSION: 76 value = i915_cmd_parser_get_version(i915); 77 break; 78 case I915_PARAM_SUBSLICE_TOTAL: 79 value = intel_sseu_subslice_total(sseu); 80 if (!value) 81 return -ENODEV; 82 break; 83 case I915_PARAM_EU_TOTAL: 84 value = sseu->eu_total; 85 if (!value) 86 return -ENODEV; 87 break; 88 case I915_PARAM_HAS_GPU_RESET: 89 value = i915->params.enable_hangcheck && 90 intel_has_gpu_reset(to_gt(i915)); 91 if (value && intel_has_reset_engine(to_gt(i915))) 92 value = 2; 93 break; 94 case I915_PARAM_HAS_RESOURCE_STREAMER: 95 value = 0; 96 break; 97 case I915_PARAM_HAS_POOLED_EU: 98 value = HAS_POOLED_EU(i915); 99 break; 100 case I915_PARAM_MIN_EU_IN_POOL: 101 value = sseu->min_eu_in_pool; 102 break; 103 case I915_PARAM_HUC_STATUS: 104 /* On platform with a media GT, the HuC is on that GT */ 105 if (i915->media_gt) 106 value = intel_huc_check_status(&i915->media_gt->uc.huc); 107 else 108 value = intel_huc_check_status(&to_gt(i915)->uc.huc); 109 if (value < 0) 110 return value; 111 break; 112 case I915_PARAM_PXP_STATUS: 113 value = intel_pxp_get_readiness_status(i915->pxp, 0); 114 if (value < 0) 115 return value; 116 break; 117 case I915_PARAM_MMAP_GTT_VERSION: 118 /* Though we've started our numbering from 1, and so class all 119 * earlier versions as 0, in effect their value is undefined as 120 * the ioctl will report EINVAL for the unknown param! 121 */ 122 value = i915_gem_mmap_gtt_version(); 123 break; 124 case I915_PARAM_HAS_SCHEDULER: 125 value = i915->caps.scheduler; 126 break; 127 128 case I915_PARAM_MMAP_VERSION: 129 /* Remember to bump this if the version changes! */ 130 case I915_PARAM_HAS_GEM: 131 case I915_PARAM_HAS_PAGEFLIPPING: 132 case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */ 133 case I915_PARAM_HAS_RELAXED_FENCING: 134 case I915_PARAM_HAS_COHERENT_RINGS: 135 case I915_PARAM_HAS_RELAXED_DELTA: 136 case I915_PARAM_HAS_GEN7_SOL_RESET: 137 case I915_PARAM_HAS_WAIT_TIMEOUT: 138 case I915_PARAM_HAS_PRIME_VMAP_FLUSH: 139 case I915_PARAM_HAS_PINNED_BATCHES: 140 case I915_PARAM_HAS_EXEC_NO_RELOC: 141 case I915_PARAM_HAS_EXEC_HANDLE_LUT: 142 case I915_PARAM_HAS_COHERENT_PHYS_GTT: 143 case I915_PARAM_HAS_EXEC_SOFTPIN: 144 case I915_PARAM_HAS_EXEC_ASYNC: 145 case I915_PARAM_HAS_EXEC_FENCE: 146 case I915_PARAM_HAS_EXEC_CAPTURE: 147 case I915_PARAM_HAS_EXEC_BATCH_FIRST: 148 case I915_PARAM_HAS_EXEC_FENCE_ARRAY: 149 case I915_PARAM_HAS_EXEC_SUBMIT_FENCE: 150 case I915_PARAM_HAS_EXEC_TIMELINE_FENCES: 151 case I915_PARAM_HAS_USERPTR_PROBE: 152 /* For the time being all of these are always true; 153 * if some supported hardware does not have one of these 154 * features this value needs to be provided from 155 * INTEL_INFO(), a feature macro, or similar. 156 */ 157 value = 1; 158 break; 159 case I915_PARAM_HAS_CONTEXT_FREQ_HINT: 160 if (intel_uc_uses_guc_submission(&to_gt(i915)->uc)) 161 value = 1; 162 else 163 value = -EINVAL; 164 break; 165 case I915_PARAM_HAS_CONTEXT_ISOLATION: 166 value = intel_engines_has_context_isolation(i915); 167 break; 168 case I915_PARAM_SLICE_MASK: 169 /* Not supported from Xe_HP onward; use topology queries */ 170 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) 171 return -EINVAL; 172 173 value = sseu->slice_mask; 174 if (!value) 175 return -ENODEV; 176 break; 177 case I915_PARAM_SUBSLICE_MASK: 178 /* Not supported from Xe_HP onward; use topology queries */ 179 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) 180 return -EINVAL; 181 182 /* Only copy bits from the first slice */ 183 value = intel_sseu_get_hsw_subslices(sseu, 0); 184 if (!value) 185 return -ENODEV; 186 break; 187 case I915_PARAM_CS_TIMESTAMP_FREQUENCY: 188 value = to_gt(i915)->clock_frequency; 189 break; 190 case I915_PARAM_MMAP_GTT_COHERENT: 191 value = INTEL_INFO(i915)->has_coherent_ggtt; 192 break; 193 case I915_PARAM_PERF_REVISION: 194 value = i915_perf_ioctl_version(i915); 195 break; 196 case I915_PARAM_OA_TIMESTAMP_FREQUENCY: 197 value = i915_perf_oa_timestamp_frequency(i915); 198 break; 199 default: 200 drm_dbg(&i915->drm, "Unknown parameter %d\n", param->param); 201 return -EINVAL; 202 } 203 204 if (put_user(value, param->value)) 205 return -EFAULT; 206 207 return 0; 208 } 209