1 /* 2 * SPDX-License-Identifier: MIT 3 */ 4 5 #include "gt/intel_engine_user.h" 6 7 #include "i915_drv.h" 8 #include "i915_perf.h" 9 10 int i915_getparam_ioctl(struct drm_device *dev, void *data, 11 struct drm_file *file_priv) 12 { 13 struct drm_i915_private *i915 = to_i915(dev); 14 const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; 15 drm_i915_getparam_t *param = data; 16 int value; 17 18 switch (param->param) { 19 case I915_PARAM_IRQ_ACTIVE: 20 case I915_PARAM_ALLOW_BATCHBUFFER: 21 case I915_PARAM_LAST_DISPATCH: 22 case I915_PARAM_HAS_EXEC_CONSTANTS: 23 /* Reject all old ums/dri params. */ 24 return -ENODEV; 25 case I915_PARAM_CHIPSET_ID: 26 value = i915->drm.pdev->device; 27 break; 28 case I915_PARAM_REVISION: 29 value = i915->drm.pdev->revision; 30 break; 31 case I915_PARAM_NUM_FENCES_AVAIL: 32 value = i915->ggtt.num_fences; 33 break; 34 case I915_PARAM_HAS_OVERLAY: 35 value = !!i915->overlay; 36 break; 37 case I915_PARAM_HAS_BSD: 38 value = !!intel_engine_lookup_user(i915, 39 I915_ENGINE_CLASS_VIDEO, 0); 40 break; 41 case I915_PARAM_HAS_BLT: 42 value = !!intel_engine_lookup_user(i915, 43 I915_ENGINE_CLASS_COPY, 0); 44 break; 45 case I915_PARAM_HAS_VEBOX: 46 value = !!intel_engine_lookup_user(i915, 47 I915_ENGINE_CLASS_VIDEO_ENHANCE, 0); 48 break; 49 case I915_PARAM_HAS_BSD2: 50 value = !!intel_engine_lookup_user(i915, 51 I915_ENGINE_CLASS_VIDEO, 1); 52 break; 53 case I915_PARAM_HAS_LLC: 54 value = HAS_LLC(i915); 55 break; 56 case I915_PARAM_HAS_WT: 57 value = HAS_WT(i915); 58 break; 59 case I915_PARAM_HAS_ALIASING_PPGTT: 60 value = INTEL_PPGTT(i915); 61 break; 62 case I915_PARAM_HAS_SEMAPHORES: 63 value = !!(i915->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES); 64 break; 65 case I915_PARAM_HAS_SECURE_BATCHES: 66 value = HAS_SECURE_BATCHES(i915) && capable(CAP_SYS_ADMIN); 67 break; 68 case I915_PARAM_CMD_PARSER_VERSION: 69 value = i915_cmd_parser_get_version(i915); 70 break; 71 case I915_PARAM_SUBSLICE_TOTAL: 72 value = intel_sseu_subslice_total(sseu); 73 if (!value) 74 return -ENODEV; 75 break; 76 case I915_PARAM_EU_TOTAL: 77 value = sseu->eu_total; 78 if (!value) 79 return -ENODEV; 80 break; 81 case I915_PARAM_HAS_GPU_RESET: 82 value = i915_modparams.enable_hangcheck && 83 intel_has_gpu_reset(&i915->gt); 84 if (value && intel_has_reset_engine(&i915->gt)) 85 value = 2; 86 break; 87 case I915_PARAM_HAS_RESOURCE_STREAMER: 88 value = 0; 89 break; 90 case I915_PARAM_HAS_POOLED_EU: 91 value = HAS_POOLED_EU(i915); 92 break; 93 case I915_PARAM_MIN_EU_IN_POOL: 94 value = sseu->min_eu_in_pool; 95 break; 96 case I915_PARAM_HUC_STATUS: 97 value = intel_huc_check_status(&i915->gt.uc.huc); 98 if (value < 0) 99 return value; 100 break; 101 case I915_PARAM_MMAP_GTT_VERSION: 102 /* Though we've started our numbering from 1, and so class all 103 * earlier versions as 0, in effect their value is undefined as 104 * the ioctl will report EINVAL for the unknown param! 105 */ 106 value = i915_gem_mmap_gtt_version(); 107 break; 108 case I915_PARAM_HAS_SCHEDULER: 109 value = i915->caps.scheduler; 110 break; 111 112 case I915_PARAM_MMAP_VERSION: 113 /* Remember to bump this if the version changes! */ 114 case I915_PARAM_HAS_GEM: 115 case I915_PARAM_HAS_PAGEFLIPPING: 116 case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */ 117 case I915_PARAM_HAS_RELAXED_FENCING: 118 case I915_PARAM_HAS_COHERENT_RINGS: 119 case I915_PARAM_HAS_RELAXED_DELTA: 120 case I915_PARAM_HAS_GEN7_SOL_RESET: 121 case I915_PARAM_HAS_WAIT_TIMEOUT: 122 case I915_PARAM_HAS_PRIME_VMAP_FLUSH: 123 case I915_PARAM_HAS_PINNED_BATCHES: 124 case I915_PARAM_HAS_EXEC_NO_RELOC: 125 case I915_PARAM_HAS_EXEC_HANDLE_LUT: 126 case I915_PARAM_HAS_COHERENT_PHYS_GTT: 127 case I915_PARAM_HAS_EXEC_SOFTPIN: 128 case I915_PARAM_HAS_EXEC_ASYNC: 129 case I915_PARAM_HAS_EXEC_FENCE: 130 case I915_PARAM_HAS_EXEC_CAPTURE: 131 case I915_PARAM_HAS_EXEC_BATCH_FIRST: 132 case I915_PARAM_HAS_EXEC_FENCE_ARRAY: 133 case I915_PARAM_HAS_EXEC_SUBMIT_FENCE: 134 /* For the time being all of these are always true; 135 * if some supported hardware does not have one of these 136 * features this value needs to be provided from 137 * INTEL_INFO(), a feature macro, or similar. 138 */ 139 value = 1; 140 break; 141 case I915_PARAM_HAS_CONTEXT_ISOLATION: 142 value = intel_engines_has_context_isolation(i915); 143 break; 144 case I915_PARAM_SLICE_MASK: 145 value = sseu->slice_mask; 146 if (!value) 147 return -ENODEV; 148 break; 149 case I915_PARAM_SUBSLICE_MASK: 150 value = sseu->subslice_mask[0]; 151 if (!value) 152 return -ENODEV; 153 break; 154 case I915_PARAM_CS_TIMESTAMP_FREQUENCY: 155 value = 1000 * RUNTIME_INFO(i915)->cs_timestamp_frequency_khz; 156 break; 157 case I915_PARAM_MMAP_GTT_COHERENT: 158 value = INTEL_INFO(i915)->has_coherent_ggtt; 159 break; 160 case I915_PARAM_PERF_REVISION: 161 value = i915_perf_ioctl_version(); 162 break; 163 default: 164 DRM_DEBUG("Unknown parameter %d\n", param->param); 165 return -EINVAL; 166 } 167 168 if (put_user(value, param->value)) 169 return -EFAULT; 170 171 return 0; 172 } 173