xref: /linux/drivers/gpu/drm/i915/i915_gem_gtt.h (revision a4eb44a6435d6d8f9e642407a4a06f65eb90ca04)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2020 Intel Corporation
4  */
5 
6 #ifndef __I915_GEM_GTT_H__
7 #define __I915_GEM_GTT_H__
8 
9 #include <linux/io-mapping.h>
10 #include <linux/types.h>
11 
12 #include <drm/drm_mm.h>
13 
14 #include "gt/intel_gtt.h"
15 #include "i915_scatterlist.h"
16 
17 struct drm_i915_gem_object;
18 struct i915_address_space;
19 
20 int __must_check i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj,
21 					    struct sg_table *pages);
22 void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj,
23 			       struct sg_table *pages);
24 
25 int i915_gem_gtt_reserve(struct i915_address_space *vm,
26 			 struct drm_mm_node *node,
27 			 u64 size, u64 offset, unsigned long color,
28 			 unsigned int flags);
29 
30 int i915_gem_gtt_insert(struct i915_address_space *vm,
31 			struct drm_mm_node *node,
32 			u64 size, u64 alignment, unsigned long color,
33 			u64 start, u64 end, unsigned int flags);
34 
35 /* Flags used by pin/bind&friends. */
36 #define PIN_NOEVICT		BIT_ULL(0)
37 #define PIN_NOSEARCH		BIT_ULL(1)
38 #define PIN_NONBLOCK		BIT_ULL(2)
39 #define PIN_MAPPABLE		BIT_ULL(3)
40 #define PIN_ZONE_4G		BIT_ULL(4)
41 #define PIN_HIGH		BIT_ULL(5)
42 #define PIN_OFFSET_BIAS		BIT_ULL(6)
43 #define PIN_OFFSET_FIXED	BIT_ULL(7)
44 
45 #define PIN_GLOBAL		BIT_ULL(10) /* I915_VMA_GLOBAL_BIND */
46 #define PIN_USER		BIT_ULL(11) /* I915_VMA_LOCAL_BIND */
47 
48 #define PIN_OFFSET_MASK		I915_GTT_PAGE_MASK
49 
50 #endif
51