1 // SPDX-License-Identifier: MIT 2 /* Copyright © 2025 Intel Corporation */ 3 4 #include <drm/drm_print.h> 5 6 #include "i915_drv.h" 7 #include "i915_freq.h" 8 #include "intel_mchbar_regs.h" 9 10 unsigned int i9xx_fsb_freq(struct drm_i915_private *i915) 11 { 12 u32 fsb; 13 14 /* 15 * Note that this only reads the state of the FSB 16 * straps, not the actual FSB frequency. Some BIOSen 17 * let you configure each independently. Ideally we'd 18 * read out the actual FSB frequency but sadly we 19 * don't know which registers have that information, 20 * and all the relevant docs have gone to bit heaven :( 21 */ 22 fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK; 23 24 if (IS_PINEVIEW(i915) || IS_MOBILE(i915)) { 25 switch (fsb) { 26 case CLKCFG_FSB_400: 27 return 400000; 28 case CLKCFG_FSB_533: 29 return 533333; 30 case CLKCFG_FSB_667: 31 return 666667; 32 case CLKCFG_FSB_800: 33 return 800000; 34 case CLKCFG_FSB_1067: 35 return 1066667; 36 case CLKCFG_FSB_1333: 37 return 1333333; 38 default: 39 MISSING_CASE(fsb); 40 return 1333333; 41 } 42 } else { 43 switch (fsb) { 44 case CLKCFG_FSB_400_ALT: 45 return 400000; 46 case CLKCFG_FSB_533: 47 return 533333; 48 case CLKCFG_FSB_667: 49 return 666667; 50 case CLKCFG_FSB_800: 51 return 800000; 52 case CLKCFG_FSB_1067_ALT: 53 return 1066667; 54 case CLKCFG_FSB_1333_ALT: 55 return 1333333; 56 case CLKCFG_FSB_1600_ALT: 57 return 1600000; 58 default: 59 MISSING_CASE(fsb); 60 return 1333333; 61 } 62 } 63 } 64 65 unsigned int ilk_fsb_freq(struct drm_i915_private *i915) 66 { 67 u16 fsb; 68 69 fsb = intel_uncore_read16(&i915->uncore, CSIPLL0) & 0x3ff; 70 71 switch (fsb) { 72 case 0x00c: 73 return 3200000; 74 case 0x00e: 75 return 3733333; 76 case 0x010: 77 return 4266667; 78 case 0x012: 79 return 4800000; 80 case 0x014: 81 return 5333333; 82 case 0x016: 83 return 5866667; 84 case 0x018: 85 return 6400000; 86 default: 87 drm_dbg(&i915->drm, "unknown fsb frequency 0x%04x\n", fsb); 88 return 0; 89 } 90 } 91 92 unsigned int ilk_mem_freq(struct drm_i915_private *i915) 93 { 94 u16 ddrpll; 95 96 ddrpll = intel_uncore_read16(&i915->uncore, DDRMPLL1); 97 switch (ddrpll & 0xff) { 98 case 0xc: 99 return 800000; 100 case 0x10: 101 return 1066667; 102 case 0x14: 103 return 1333333; 104 case 0x18: 105 return 1600000; 106 default: 107 drm_dbg(&i915->drm, "unknown memory frequency 0x%02x\n", 108 ddrpll & 0xff); 109 return 0; 110 } 111 } 112