1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 35 #include <linux/pci.h> 36 #include <linux/pm_qos.h> 37 38 #include <drm/ttm/ttm_device.h> 39 40 #include "gem/i915_gem_context_types.h" 41 #include "gem/i915_gem_shrinker.h" 42 #include "gem/i915_gem_stolen.h" 43 44 #include "gt/intel_engine.h" 45 #include "gt/intel_gt_types.h" 46 #include "gt/intel_region_lmem.h" 47 #include "gt/intel_workarounds.h" 48 #include "gt/uc/intel_uc.h" 49 50 #include "i915_drm_client.h" 51 #include "i915_gem.h" 52 #include "i915_gpu_error.h" 53 #include "i915_params.h" 54 #include "i915_perf_types.h" 55 #include "i915_scheduler.h" 56 #include "i915_utils.h" 57 #include "intel_device_info.h" 58 #include "intel_memory_region.h" 59 #include "intel_runtime_pm.h" 60 #include "intel_step.h" 61 #include "intel_uncore.h" 62 63 struct drm_i915_clock_gating_funcs; 64 struct i915_overlay; 65 struct intel_display; 66 struct intel_pxp; 67 struct vlv_s0ix_state; 68 69 /* Data Stolen Memory (DSM) aka "i915 stolen memory" */ 70 struct i915_dsm { 71 /* 72 * The start and end of DSM which we can optionally use to create GEM 73 * objects backed by stolen memory. 74 * 75 * Note that usable_size tells us exactly how much of this we are 76 * actually allowed to use, given that some portion of it is in fact 77 * reserved for use by hardware functions. 78 */ 79 struct resource stolen; 80 81 /* 82 * Reserved portion of DSM. 83 */ 84 struct resource reserved; 85 86 /* 87 * Total size minus reserved ranges. 88 * 89 * DSM is segmented in hardware with different portions offlimits to 90 * certain functions. 91 * 92 * The drm_mm is initialised to the total accessible range, as found 93 * from the PCI config. On Broadwell+, this is further restricted to 94 * avoid the first page! The upper end of DSM is reserved for hardware 95 * functions and similarly removed from the accessible range. 96 */ 97 resource_size_t usable_size; 98 }; 99 100 #define MAX_L3_SLICES 2 101 struct intel_l3_parity { 102 u32 *remap_info[MAX_L3_SLICES]; 103 struct work_struct error_work; 104 int which_slice; 105 }; 106 107 struct i915_gem_mm { 108 /* 109 * Shortcut for the stolen region. This points to either 110 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or 111 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't 112 * support stolen. 113 */ 114 struct intel_memory_region *stolen_region; 115 /** Memory allocator for GTT stolen memory */ 116 struct drm_mm stolen; 117 /** Protects the usage of the GTT stolen memory allocator */ 118 struct mutex stolen_lock; 119 120 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ 121 spinlock_t obj_lock; 122 123 /** 124 * List of objects which are purgeable. 125 */ 126 struct list_head purge_list; 127 128 /** 129 * List of objects which have allocated pages and are shrinkable. 130 */ 131 struct list_head shrink_list; 132 133 /** 134 * List of objects which are pending destruction. 135 */ 136 struct llist_head free_list; 137 struct work_struct free_work; 138 /** 139 * Count of objects pending destructions. Used to skip needlessly 140 * waiting on an RCU barrier if no objects are waiting to be freed. 141 */ 142 atomic_t free_count; 143 144 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN]; 145 146 struct notifier_block oom_notifier; 147 struct notifier_block vmap_notifier; 148 struct shrinker *shrinker; 149 150 /* shrinker accounting, also useful for userland debugging */ 151 u64 shrink_memory; 152 u32 shrink_count; 153 }; 154 155 struct i915_virtual_gpu { 156 struct mutex lock; /* serialises sending of g2v_notify command pkts */ 157 bool active; 158 u32 caps; 159 u32 *initial_mmio; 160 u8 *initial_cfg_space; 161 struct list_head entry; 162 }; 163 164 struct i915_selftest_stash { 165 atomic_t counter; 166 struct ida mock_region_instances; 167 }; 168 169 struct drm_i915_private { 170 struct drm_device drm; 171 172 /* display device data, must be placed after drm device member */ 173 struct intel_display *display; 174 175 /* FIXME: Device release actions should all be moved to drmm_ */ 176 bool do_release; 177 178 /* i915 device parameters */ 179 struct i915_params params; 180 181 const struct intel_device_info *__info; /* Use INTEL_INFO() to access. */ 182 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ 183 struct intel_driver_caps caps; 184 185 struct i915_dsm dsm; 186 187 struct intel_uncore uncore; 188 struct intel_uncore_mmio_debug mmio_debug; 189 190 struct i915_virtual_gpu vgpu; 191 192 struct intel_gvt *gvt; 193 194 struct { 195 struct pci_dev *pdev; 196 struct resource mch_res; 197 bool mchbar_need_disable; 198 } gmch; 199 200 /* 201 * Chaining user engines happens in multiple stages, starting with a 202 * simple lock-less linked list created by intel_engine_add_user(), 203 * which later gets sorted and converted to an intermediate regular 204 * list, just to be converted once again to its final rb tree structure 205 * in intel_engines_driver_register(). 206 * 207 * Make sure to use the right iterator helper, depending on if the code 208 * in question runs before or after intel_engines_driver_register() -- 209 * for_each_uabi_engine() can only be used afterwards! 210 */ 211 union { 212 struct llist_head uabi_engines_llist; 213 struct list_head uabi_engines_list; 214 struct rb_root uabi_engines; 215 }; 216 unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1]; 217 218 bool irqs_enabled; 219 220 /* LPT/WPT IOSF sideband protection */ 221 struct mutex sbi_lock; 222 223 /* VLV/CHV IOSF sideband */ 224 struct { 225 struct mutex lock; /* protect sideband access */ 226 unsigned long locked_unit_mask; 227 struct pm_qos_request qos; 228 } vlv_iosf_sb; 229 230 /* Sideband mailbox protection */ 231 struct mutex sb_lock; 232 233 /* Cached value of gen 2-4 IMR to avoid reads in updating the bitfield */ 234 u32 gen2_imr_mask; 235 236 bool preserve_bios_swizzle; 237 238 /** 239 * wq - Driver workqueue for GEM. 240 * 241 * NOTE: Work items scheduled here are not allowed to grab any modeset 242 * locks, for otherwise the flushing done in the pageflip code will 243 * result in deadlocks. 244 */ 245 struct workqueue_struct *wq; 246 247 /** 248 * unordered_wq - internal workqueue for unordered work 249 * 250 * This workqueue should be used for all unordered work 251 * scheduling within i915, which used to be scheduled on the 252 * system_percpu_wq before moving to a driver instance due 253 * deprecation of flush_scheduled_work(). 254 */ 255 struct workqueue_struct *unordered_wq; 256 257 /* pm private clock gating functions */ 258 const struct drm_i915_clock_gating_funcs *clock_gating_funcs; 259 260 unsigned long gem_quirks; 261 262 struct i915_gem_mm mm; 263 264 struct intel_l3_parity l3_parity; 265 266 /* 267 * edram size in MB. 268 * Cannot be determined by PCIID. You must always read a register. 269 */ 270 u32 edram_size_mb; 271 272 struct i915_gpu_error gpu_error; 273 274 u32 suspend_count; 275 struct vlv_s0ix_state *vlv_s0ix_state; 276 277 struct intel_runtime_pm runtime_pm; 278 279 struct i915_perf perf; 280 281 struct i915_hwmon *hwmon; 282 283 struct intel_gt *gt[I915_MAX_GT]; 284 285 struct kobject *sysfs_gt; 286 287 /* Quick lookup of media GT (current platforms only have one) */ 288 struct intel_gt *media_gt; 289 290 struct { 291 struct i915_gem_contexts { 292 spinlock_t lock; /* locks list */ 293 struct list_head list; 294 } contexts; 295 296 /* 297 * We replace the local file with a global mappings as the 298 * backing storage for the mmap is on the device and not 299 * on the struct file, and we do not want to prolong the 300 * lifetime of the local fd. To minimise the number of 301 * anonymous inodes we create, we use a global singleton to 302 * share the global mapping. 303 */ 304 struct file *mmap_singleton; 305 } gem; 306 307 spinlock_t frontbuffer_lock; /* protects obj->frontbuffer (write-side) */ 308 309 struct intel_pxp *pxp; 310 311 struct i915_overlay *overlay; 312 313 struct i915_pmu pmu; 314 315 /* The TTM device structure. */ 316 struct ttm_device bdev; 317 318 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;) 319 320 /* 321 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 322 * will be rejected. Instead look for a better place. 323 */ 324 }; 325 326 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 327 { 328 return container_of(dev, struct drm_i915_private, drm); 329 } 330 331 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) 332 { 333 struct drm_device *drm = dev_get_drvdata(kdev); 334 335 return drm ? to_i915(drm) : NULL; 336 } 337 338 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) 339 { 340 struct drm_device *drm = pci_get_drvdata(pdev); 341 342 return drm ? to_i915(drm) : NULL; 343 } 344 345 static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) 346 { 347 return i915->gt[0]; 348 } 349 350 #define INTEL_INFO(i915) ((i915)->__info) 351 #define RUNTIME_INFO(i915) (&(i915)->__runtime) 352 #define DRIVER_CAPS(i915) (&(i915)->caps) 353 354 #define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id) 355 356 #define IP_VER(ver, rel) ((ver) << 8 | (rel)) 357 358 #define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver) 359 #define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \ 360 RUNTIME_INFO(i915)->graphics.ip.rel) 361 #define IS_GRAPHICS_VER(i915, from, until) \ 362 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until)) 363 364 #define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver) 365 #define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \ 366 RUNTIME_INFO(i915)->media.ip.rel) 367 #define IS_MEDIA_VER(i915, from, until) \ 368 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until)) 369 370 #define INTEL_REVID(i915) (to_pci_dev((i915)->drm.dev)->revision) 371 372 #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step) 373 #define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step) 374 375 #define IS_GRAPHICS_STEP(__i915, since, until) \ 376 (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \ 377 INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until)) 378 379 #define IS_MEDIA_STEP(__i915, since, until) \ 380 (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \ 381 INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until)) 382 383 static __always_inline unsigned int 384 __platform_mask_index(const struct intel_runtime_info *info, 385 enum intel_platform p) 386 { 387 const unsigned int pbits = 388 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 389 390 /* Expand the platform_mask array if this fails. */ 391 BUILD_BUG_ON(INTEL_MAX_PLATFORMS > 392 pbits * ARRAY_SIZE(info->platform_mask)); 393 394 return p / pbits; 395 } 396 397 static __always_inline unsigned int 398 __platform_mask_bit(const struct intel_runtime_info *info, 399 enum intel_platform p) 400 { 401 const unsigned int pbits = 402 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 403 404 return p % pbits + INTEL_SUBPLATFORM_BITS; 405 } 406 407 static inline u32 408 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p) 409 { 410 const unsigned int pi = __platform_mask_index(info, p); 411 412 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK; 413 } 414 415 static __always_inline bool 416 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p) 417 { 418 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 419 const unsigned int pi = __platform_mask_index(info, p); 420 const unsigned int pb = __platform_mask_bit(info, p); 421 422 BUILD_BUG_ON(!__builtin_constant_p(p)); 423 424 return info->platform_mask[pi] & BIT(pb); 425 } 426 427 static __always_inline bool 428 IS_SUBPLATFORM(const struct drm_i915_private *i915, 429 enum intel_platform p, unsigned int s) 430 { 431 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 432 const unsigned int pi = __platform_mask_index(info, p); 433 const unsigned int pb = __platform_mask_bit(info, p); 434 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1; 435 const u32 mask = info->platform_mask[pi]; 436 437 BUILD_BUG_ON(!__builtin_constant_p(p)); 438 BUILD_BUG_ON(!__builtin_constant_p(s)); 439 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS); 440 441 /* Shift and test on the MSB position so sign flag can be used. */ 442 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); 443 } 444 445 #define IS_MOBILE(i915) (INTEL_INFO(i915)->is_mobile) 446 #define IS_DGFX(i915) (INTEL_INFO(i915)->is_dgfx) 447 448 #define IS_I830(i915) IS_PLATFORM(i915, INTEL_I830) 449 #define IS_I845G(i915) IS_PLATFORM(i915, INTEL_I845G) 450 #define IS_I85X(i915) IS_PLATFORM(i915, INTEL_I85X) 451 #define IS_I865G(i915) IS_PLATFORM(i915, INTEL_I865G) 452 #define IS_I915G(i915) IS_PLATFORM(i915, INTEL_I915G) 453 #define IS_I915GM(i915) IS_PLATFORM(i915, INTEL_I915GM) 454 #define IS_I945G(i915) IS_PLATFORM(i915, INTEL_I945G) 455 #define IS_I945GM(i915) IS_PLATFORM(i915, INTEL_I945GM) 456 #define IS_I965G(i915) IS_PLATFORM(i915, INTEL_I965G) 457 #define IS_I965GM(i915) IS_PLATFORM(i915, INTEL_I965GM) 458 #define IS_G45(i915) IS_PLATFORM(i915, INTEL_G45) 459 #define IS_GM45(i915) IS_PLATFORM(i915, INTEL_GM45) 460 #define IS_G4X(i915) (IS_G45(i915) || IS_GM45(i915)) 461 #define IS_PINEVIEW(i915) IS_PLATFORM(i915, INTEL_PINEVIEW) 462 #define IS_G33(i915) IS_PLATFORM(i915, INTEL_G33) 463 #define IS_IRONLAKE(i915) IS_PLATFORM(i915, INTEL_IRONLAKE) 464 #define IS_IRONLAKE_M(i915) \ 465 (IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915)) 466 #define IS_SANDYBRIDGE(i915) IS_PLATFORM(i915, INTEL_SANDYBRIDGE) 467 #define IS_IVYBRIDGE(i915) IS_PLATFORM(i915, INTEL_IVYBRIDGE) 468 #define IS_VALLEYVIEW(i915) IS_PLATFORM(i915, INTEL_VALLEYVIEW) 469 #define IS_CHERRYVIEW(i915) IS_PLATFORM(i915, INTEL_CHERRYVIEW) 470 #define IS_HASWELL(i915) IS_PLATFORM(i915, INTEL_HASWELL) 471 #define IS_BROADWELL(i915) IS_PLATFORM(i915, INTEL_BROADWELL) 472 #define IS_SKYLAKE(i915) IS_PLATFORM(i915, INTEL_SKYLAKE) 473 #define IS_BROXTON(i915) IS_PLATFORM(i915, INTEL_BROXTON) 474 #define IS_KABYLAKE(i915) IS_PLATFORM(i915, INTEL_KABYLAKE) 475 #define IS_GEMINILAKE(i915) IS_PLATFORM(i915, INTEL_GEMINILAKE) 476 #define IS_COFFEELAKE(i915) IS_PLATFORM(i915, INTEL_COFFEELAKE) 477 #define IS_COMETLAKE(i915) IS_PLATFORM(i915, INTEL_COMETLAKE) 478 #define IS_ICELAKE(i915) IS_PLATFORM(i915, INTEL_ICELAKE) 479 #define IS_JASPERLAKE(i915) IS_PLATFORM(i915, INTEL_JASPERLAKE) 480 #define IS_ELKHARTLAKE(i915) IS_PLATFORM(i915, INTEL_ELKHARTLAKE) 481 #define IS_TIGERLAKE(i915) IS_PLATFORM(i915, INTEL_TIGERLAKE) 482 #define IS_ROCKETLAKE(i915) IS_PLATFORM(i915, INTEL_ROCKETLAKE) 483 #define IS_DG1(i915) IS_PLATFORM(i915, INTEL_DG1) 484 #define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S) 485 #define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P) 486 #define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2) 487 #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE) 488 489 #define IS_ARROWLAKE_H(i915) \ 490 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_H) 491 #define IS_ARROWLAKE_U(i915) \ 492 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_U) 493 #define IS_ARROWLAKE_S(i915) \ 494 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_S) 495 #define IS_DG2_G10(i915) \ 496 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10) 497 #define IS_DG2_G11(i915) \ 498 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11) 499 #define IS_DG2_G12(i915) \ 500 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12) 501 #define IS_DG2_D(i915) \ 502 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_D) 503 #define IS_RAPTORLAKE_S(i915) \ 504 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL) 505 #define IS_ALDERLAKE_P_N(i915) \ 506 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N) 507 #define IS_RAPTORLAKE_P(i915) \ 508 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL) 509 #define IS_RAPTORLAKE_U(i915) \ 510 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU) 511 #define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \ 512 (INTEL_DEVID(i915) & 0xFF00) == 0x0C00) 513 #define IS_BROADWELL_ULT(i915) \ 514 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) 515 #define IS_BROADWELL_ULX(i915) \ 516 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX) 517 #define IS_HASWELL_ULT(i915) \ 518 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) 519 /* ULX machines are also considered ULT. */ 520 #define IS_HASWELL_ULX(i915) \ 521 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) 522 #define IS_SKYLAKE_ULT(i915) \ 523 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) 524 #define IS_SKYLAKE_ULX(i915) \ 525 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) 526 #define IS_KABYLAKE_ULT(i915) \ 527 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) 528 #define IS_KABYLAKE_ULX(i915) \ 529 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) 530 #define IS_COFFEELAKE_ULT(i915) \ 531 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) 532 #define IS_COFFEELAKE_ULX(i915) \ 533 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX) 534 #define IS_COMETLAKE_ULT(i915) \ 535 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT) 536 #define IS_COMETLAKE_ULX(i915) \ 537 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX) 538 539 #define IS_ICL_WITH_PORT_F(i915) \ 540 IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) 541 542 #define IS_TIGERLAKE_UY(i915) \ 543 IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY) 544 545 #define IS_GEN9_LP(i915) (IS_BROXTON(i915) || IS_GEMINILAKE(i915)) 546 #define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_GEN9_LP(i915)) 547 548 #define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode) 549 550 /* 551 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution 552 * All later gens can run the final buffer from the ppgtt 553 */ 554 #define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7) 555 556 #define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc) 557 #define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop) 558 #define HAS_EDRAM(i915) ((i915)->edram_size_mb) 559 #define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6) 560 #define HAS_WT(i915) HAS_EDRAM(i915) 561 562 #define HWS_NEEDS_PHYSICAL(i915) (INTEL_INFO(i915)->hws_needs_physical) 563 564 #define HAS_LOGICAL_RING_CONTEXTS(i915) \ 565 (INTEL_INFO(i915)->has_logical_ring_contexts) 566 #define HAS_LOGICAL_RING_ELSQ(i915) \ 567 (INTEL_INFO(i915)->has_logical_ring_elsq) 568 569 #define HAS_EXECLISTS(i915) HAS_LOGICAL_RING_CONTEXTS(i915) 570 571 #define INTEL_PPGTT(i915) (RUNTIME_INFO(i915)->ppgtt_type) 572 #define HAS_PPGTT(i915) \ 573 (INTEL_PPGTT(i915) != INTEL_PPGTT_NONE) 574 #define HAS_FULL_PPGTT(i915) \ 575 (INTEL_PPGTT(i915) >= INTEL_PPGTT_FULL) 576 577 #define HAS_PAGE_SIZES(i915, sizes) ({ \ 578 GEM_BUG_ON((sizes) == 0); \ 579 ((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \ 580 }) 581 582 #define NEEDS_RC6_CTX_CORRUPTION_WA(i915) \ 583 (IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9) 584 585 /* WaRsDisableCoarsePowerGating:skl,cnl */ 586 #define NEEDS_WaRsDisableCoarsePowerGating(i915) \ 587 (IS_SKYLAKE(i915) && (INTEL_INFO(i915)->gt == 3 || INTEL_INFO(i915)->gt == 4)) 588 589 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 590 * rows, which changed the alignment requirements and fence programming. 591 */ 592 #define HAS_128_BYTE_Y_TILING(i915) (!IS_I915G(i915) && !IS_I915GM(i915)) 593 594 #define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6) 595 #define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p) 596 #define HAS_RC6pp(i915) (false) /* HW was never validated */ 597 598 #define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps) 599 600 #define HAS_PXP(i915) \ 601 (IS_ENABLED(CONFIG_DRM_I915_PXP) && INTEL_INFO(i915)->has_pxp) 602 603 #define HAS_HECI_PXP(i915) \ 604 (INTEL_INFO(i915)->has_heci_pxp) 605 606 #define HAS_HECI_GSCFI(i915) \ 607 (INTEL_INFO(i915)->has_heci_gscfi) 608 609 #define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915)) 610 611 #define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm) 612 #define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc) 613 614 #define HAS_OA_BPC_REPORTING(i915) \ 615 (INTEL_INFO(i915)->has_oa_bpc_reporting) 616 #define HAS_OA_SLICE_CONTRIB_LIMITS(i915) \ 617 (INTEL_INFO(i915)->has_oa_slice_contrib_limits) 618 #define HAS_OAM(i915) \ 619 (INTEL_INFO(i915)->has_oam) 620 621 /* 622 * Set this flag, when platform requires 64K GTT page sizes or larger for 623 * device local memory access. 624 */ 625 #define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages) 626 627 #define HAS_REGION(i915, id) (INTEL_INFO(i915)->memory_regions & BIT(id)) 628 #define HAS_LMEM(i915) HAS_REGION(i915, INTEL_REGION_LMEM_0) 629 630 #define HAS_EXTRA_GT_LIST(i915) (INTEL_INFO(i915)->extra_gt_list) 631 632 /* 633 * Platform has the dedicated compression control state for each lmem surfaces 634 * stored in lmem to support the 3D and media compression formats. 635 */ 636 #define HAS_FLAT_CCS(i915) (INTEL_INFO(i915)->has_flat_ccs) 637 638 #define HAS_GT_UC(i915) (INTEL_INFO(i915)->has_gt_uc) 639 640 #define HAS_POOLED_EU(i915) (RUNTIME_INFO(i915)->has_pooled_eu) 641 642 #define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs) 643 644 #define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id) 645 646 #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read) 647 648 /* DPF == dynamic parity feature */ 649 #define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf) 650 #define NUM_L3_SLICES(i915) (IS_HASWELL(i915) && INTEL_INFO(i915)->gt == 3 ? \ 651 2 : HAS_L3_DPF(i915)) 652 653 #define HAS_GUC_DEPRIVILEGE(i915) \ 654 (INTEL_INFO(i915)->has_guc_deprivilege) 655 656 #define HAS_GUC_TLB_INVALIDATION(i915) (INTEL_INFO(i915)->has_guc_tlb_invalidation) 657 658 #define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline) 659 660 #define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit) 661 662 #define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \ 663 GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) 664 665 #endif 666