1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include "i915_reg.h" 34 #include "intel_bios.h" 35 #include "intel_ringbuffer.h" 36 #include <linux/io-mapping.h> 37 #include <linux/i2c.h> 38 #include <drm/intel-gtt.h> 39 #include <linux/backlight.h> 40 41 /* General customization: 42 */ 43 44 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 45 46 #define DRIVER_NAME "i915" 47 #define DRIVER_DESC "Intel Graphics" 48 #define DRIVER_DATE "20080730" 49 50 enum pipe { 51 PIPE_A = 0, 52 PIPE_B, 53 PIPE_C, 54 I915_MAX_PIPES 55 }; 56 #define pipe_name(p) ((p) + 'A') 57 58 enum plane { 59 PLANE_A = 0, 60 PLANE_B, 61 PLANE_C, 62 }; 63 #define plane_name(p) ((p) + 'A') 64 65 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 66 67 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) 68 69 /* Interface history: 70 * 71 * 1.1: Original. 72 * 1.2: Add Power Management 73 * 1.3: Add vblank support 74 * 1.4: Fix cmdbuffer path, add heap destroy 75 * 1.5: Add vblank pipe configuration 76 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 77 * - Support vertical blank on secondary display pipe 78 */ 79 #define DRIVER_MAJOR 1 80 #define DRIVER_MINOR 6 81 #define DRIVER_PATCHLEVEL 0 82 83 #define WATCH_COHERENCY 0 84 #define WATCH_LISTS 0 85 86 #define I915_GEM_PHYS_CURSOR_0 1 87 #define I915_GEM_PHYS_CURSOR_1 2 88 #define I915_GEM_PHYS_OVERLAY_REGS 3 89 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 90 91 struct drm_i915_gem_phys_object { 92 int id; 93 struct page **page_list; 94 drm_dma_handle_t *handle; 95 struct drm_i915_gem_object *cur_obj; 96 }; 97 98 struct mem_block { 99 struct mem_block *next; 100 struct mem_block *prev; 101 int start; 102 int size; 103 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 104 }; 105 106 struct opregion_header; 107 struct opregion_acpi; 108 struct opregion_swsci; 109 struct opregion_asle; 110 111 struct intel_opregion { 112 struct opregion_header *header; 113 struct opregion_acpi *acpi; 114 struct opregion_swsci *swsci; 115 struct opregion_asle *asle; 116 void *vbt; 117 u32 __iomem *lid_state; 118 }; 119 #define OPREGION_SIZE (8*1024) 120 121 struct intel_overlay; 122 struct intel_overlay_error_state; 123 124 struct drm_i915_master_private { 125 drm_local_map_t *sarea; 126 struct _drm_i915_sarea *sarea_priv; 127 }; 128 #define I915_FENCE_REG_NONE -1 129 130 struct drm_i915_fence_reg { 131 struct list_head lru_list; 132 struct drm_i915_gem_object *obj; 133 uint32_t setup_seqno; 134 }; 135 136 struct sdvo_device_mapping { 137 u8 initialized; 138 u8 dvo_port; 139 u8 slave_addr; 140 u8 dvo_wiring; 141 u8 i2c_pin; 142 u8 ddc_pin; 143 }; 144 145 struct intel_display_error_state; 146 147 struct drm_i915_error_state { 148 u32 eir; 149 u32 pgtbl_er; 150 u32 pipestat[I915_MAX_PIPES]; 151 u32 ipeir; 152 u32 ipehr; 153 u32 instdone; 154 u32 acthd; 155 u32 error; /* gen6+ */ 156 u32 bcs_acthd; /* gen6+ blt engine */ 157 u32 bcs_ipehr; 158 u32 bcs_ipeir; 159 u32 bcs_instdone; 160 u32 bcs_seqno; 161 u32 vcs_acthd; /* gen6+ bsd engine */ 162 u32 vcs_ipehr; 163 u32 vcs_ipeir; 164 u32 vcs_instdone; 165 u32 vcs_seqno; 166 u32 instpm; 167 u32 instps; 168 u32 instdone1; 169 u32 seqno; 170 u64 bbaddr; 171 u64 fence[16]; 172 struct timeval time; 173 struct drm_i915_error_object { 174 int page_count; 175 u32 gtt_offset; 176 u32 *pages[0]; 177 } *ringbuffer[I915_NUM_RINGS], *batchbuffer[I915_NUM_RINGS]; 178 struct drm_i915_error_buffer { 179 u32 size; 180 u32 name; 181 u32 seqno; 182 u32 gtt_offset; 183 u32 read_domains; 184 u32 write_domain; 185 s32 fence_reg:5; 186 s32 pinned:2; 187 u32 tiling:2; 188 u32 dirty:1; 189 u32 purgeable:1; 190 u32 ring:4; 191 u32 cache_level:2; 192 } *active_bo, *pinned_bo; 193 u32 active_bo_count, pinned_bo_count; 194 struct intel_overlay_error_state *overlay; 195 struct intel_display_error_state *display; 196 }; 197 198 struct drm_i915_display_funcs { 199 void (*dpms)(struct drm_crtc *crtc, int mode); 200 bool (*fbc_enabled)(struct drm_device *dev); 201 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); 202 void (*disable_fbc)(struct drm_device *dev); 203 int (*get_display_clock_speed)(struct drm_device *dev); 204 int (*get_fifo_size)(struct drm_device *dev, int plane); 205 void (*update_wm)(struct drm_device *dev); 206 int (*crtc_mode_set)(struct drm_crtc *crtc, 207 struct drm_display_mode *mode, 208 struct drm_display_mode *adjusted_mode, 209 int x, int y, 210 struct drm_framebuffer *old_fb); 211 void (*write_eld)(struct drm_connector *connector, 212 struct drm_crtc *crtc); 213 void (*fdi_link_train)(struct drm_crtc *crtc); 214 void (*init_clock_gating)(struct drm_device *dev); 215 void (*init_pch_clock_gating)(struct drm_device *dev); 216 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 217 struct drm_framebuffer *fb, 218 struct drm_i915_gem_object *obj); 219 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, 220 int x, int y); 221 /* clock updates for mode set */ 222 /* cursor updates */ 223 /* render clock increase/decrease */ 224 /* display clock increase/decrease */ 225 /* pll clock increase/decrease */ 226 }; 227 228 struct intel_device_info { 229 u8 gen; 230 u8 is_mobile:1; 231 u8 is_i85x:1; 232 u8 is_i915g:1; 233 u8 is_i945gm:1; 234 u8 is_g33:1; 235 u8 need_gfx_hws:1; 236 u8 is_g4x:1; 237 u8 is_pineview:1; 238 u8 is_broadwater:1; 239 u8 is_crestline:1; 240 u8 is_ivybridge:1; 241 u8 has_fbc:1; 242 u8 has_pipe_cxsr:1; 243 u8 has_hotplug:1; 244 u8 cursor_needs_physical:1; 245 u8 has_overlay:1; 246 u8 overlay_needs_physical:1; 247 u8 supports_tv:1; 248 u8 has_bsd_ring:1; 249 u8 has_blt_ring:1; 250 }; 251 252 enum no_fbc_reason { 253 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 254 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ 255 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 256 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 257 FBC_BAD_PLANE, /* fbc not supported on plane */ 258 FBC_NOT_TILED, /* buffer not tiled */ 259 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 260 FBC_MODULE_PARAM, 261 }; 262 263 enum intel_pch { 264 PCH_IBX, /* Ibexpeak PCH */ 265 PCH_CPT, /* Cougarpoint PCH */ 266 }; 267 268 #define QUIRK_PIPEA_FORCE (1<<0) 269 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 270 271 struct intel_fbdev; 272 struct intel_fbc_work; 273 274 typedef struct drm_i915_private { 275 struct drm_device *dev; 276 277 const struct intel_device_info *info; 278 279 int has_gem; 280 int relative_constants_mode; 281 282 void __iomem *regs; 283 u32 gt_fifo_count; 284 285 struct intel_gmbus { 286 struct i2c_adapter adapter; 287 struct i2c_adapter *force_bit; 288 u32 reg0; 289 } *gmbus; 290 291 struct pci_dev *bridge_dev; 292 struct intel_ring_buffer ring[I915_NUM_RINGS]; 293 uint32_t next_seqno; 294 295 drm_dma_handle_t *status_page_dmah; 296 uint32_t counter; 297 drm_local_map_t hws_map; 298 struct drm_i915_gem_object *pwrctx; 299 struct drm_i915_gem_object *renderctx; 300 301 struct resource mch_res; 302 303 unsigned int cpp; 304 int back_offset; 305 int front_offset; 306 int current_page; 307 int page_flipping; 308 309 atomic_t irq_received; 310 311 /* protects the irq masks */ 312 spinlock_t irq_lock; 313 /** Cached value of IMR to avoid reads in updating the bitfield */ 314 u32 pipestat[2]; 315 u32 irq_mask; 316 u32 gt_irq_mask; 317 u32 pch_irq_mask; 318 319 u32 hotplug_supported_mask; 320 struct work_struct hotplug_work; 321 322 int tex_lru_log_granularity; 323 int allow_batchbuffer; 324 struct mem_block *agp_heap; 325 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 326 int vblank_pipe; 327 int num_pipe; 328 329 /* For hangcheck timer */ 330 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ 331 struct timer_list hangcheck_timer; 332 int hangcheck_count; 333 uint32_t last_acthd; 334 uint32_t last_instdone; 335 uint32_t last_instdone1; 336 337 unsigned long cfb_size; 338 unsigned int cfb_fb; 339 enum plane cfb_plane; 340 int cfb_y; 341 struct intel_fbc_work *fbc_work; 342 343 struct intel_opregion opregion; 344 345 /* overlay */ 346 struct intel_overlay *overlay; 347 348 /* LVDS info */ 349 int backlight_level; /* restore backlight to this value */ 350 bool backlight_enabled; 351 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 352 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 353 354 /* Feature bits from the VBIOS */ 355 unsigned int int_tv_support:1; 356 unsigned int lvds_dither:1; 357 unsigned int lvds_vbt:1; 358 unsigned int int_crt_support:1; 359 unsigned int lvds_use_ssc:1; 360 unsigned int display_clock_mode:1; 361 int lvds_ssc_freq; 362 struct { 363 int rate; 364 int lanes; 365 int preemphasis; 366 int vswing; 367 368 bool initialized; 369 bool support; 370 int bpp; 371 struct edp_power_seq pps; 372 } edp; 373 bool no_aux_handshake; 374 375 struct notifier_block lid_notifier; 376 377 int crt_ddc_pin; 378 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ 379 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 380 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 381 382 unsigned int fsb_freq, mem_freq, is_ddr3; 383 384 spinlock_t error_lock; 385 struct drm_i915_error_state *first_error; 386 struct work_struct error_work; 387 struct completion error_completion; 388 struct workqueue_struct *wq; 389 390 /* Display functions */ 391 struct drm_i915_display_funcs display; 392 393 /* PCH chipset type */ 394 enum intel_pch pch_type; 395 396 unsigned long quirks; 397 398 /* Register state */ 399 bool modeset_on_lid; 400 u8 saveLBB; 401 u32 saveDSPACNTR; 402 u32 saveDSPBCNTR; 403 u32 saveDSPARB; 404 u32 saveHWS; 405 u32 savePIPEACONF; 406 u32 savePIPEBCONF; 407 u32 savePIPEASRC; 408 u32 savePIPEBSRC; 409 u32 saveFPA0; 410 u32 saveFPA1; 411 u32 saveDPLL_A; 412 u32 saveDPLL_A_MD; 413 u32 saveHTOTAL_A; 414 u32 saveHBLANK_A; 415 u32 saveHSYNC_A; 416 u32 saveVTOTAL_A; 417 u32 saveVBLANK_A; 418 u32 saveVSYNC_A; 419 u32 saveBCLRPAT_A; 420 u32 saveTRANSACONF; 421 u32 saveTRANS_HTOTAL_A; 422 u32 saveTRANS_HBLANK_A; 423 u32 saveTRANS_HSYNC_A; 424 u32 saveTRANS_VTOTAL_A; 425 u32 saveTRANS_VBLANK_A; 426 u32 saveTRANS_VSYNC_A; 427 u32 savePIPEASTAT; 428 u32 saveDSPASTRIDE; 429 u32 saveDSPASIZE; 430 u32 saveDSPAPOS; 431 u32 saveDSPAADDR; 432 u32 saveDSPASURF; 433 u32 saveDSPATILEOFF; 434 u32 savePFIT_PGM_RATIOS; 435 u32 saveBLC_HIST_CTL; 436 u32 saveBLC_PWM_CTL; 437 u32 saveBLC_PWM_CTL2; 438 u32 saveBLC_CPU_PWM_CTL; 439 u32 saveBLC_CPU_PWM_CTL2; 440 u32 saveFPB0; 441 u32 saveFPB1; 442 u32 saveDPLL_B; 443 u32 saveDPLL_B_MD; 444 u32 saveHTOTAL_B; 445 u32 saveHBLANK_B; 446 u32 saveHSYNC_B; 447 u32 saveVTOTAL_B; 448 u32 saveVBLANK_B; 449 u32 saveVSYNC_B; 450 u32 saveBCLRPAT_B; 451 u32 saveTRANSBCONF; 452 u32 saveTRANS_HTOTAL_B; 453 u32 saveTRANS_HBLANK_B; 454 u32 saveTRANS_HSYNC_B; 455 u32 saveTRANS_VTOTAL_B; 456 u32 saveTRANS_VBLANK_B; 457 u32 saveTRANS_VSYNC_B; 458 u32 savePIPEBSTAT; 459 u32 saveDSPBSTRIDE; 460 u32 saveDSPBSIZE; 461 u32 saveDSPBPOS; 462 u32 saveDSPBADDR; 463 u32 saveDSPBSURF; 464 u32 saveDSPBTILEOFF; 465 u32 saveVGA0; 466 u32 saveVGA1; 467 u32 saveVGA_PD; 468 u32 saveVGACNTRL; 469 u32 saveADPA; 470 u32 saveLVDS; 471 u32 savePP_ON_DELAYS; 472 u32 savePP_OFF_DELAYS; 473 u32 saveDVOA; 474 u32 saveDVOB; 475 u32 saveDVOC; 476 u32 savePP_ON; 477 u32 savePP_OFF; 478 u32 savePP_CONTROL; 479 u32 savePP_DIVISOR; 480 u32 savePFIT_CONTROL; 481 u32 save_palette_a[256]; 482 u32 save_palette_b[256]; 483 u32 saveDPFC_CB_BASE; 484 u32 saveFBC_CFB_BASE; 485 u32 saveFBC_LL_BASE; 486 u32 saveFBC_CONTROL; 487 u32 saveFBC_CONTROL2; 488 u32 saveIER; 489 u32 saveIIR; 490 u32 saveIMR; 491 u32 saveDEIER; 492 u32 saveDEIMR; 493 u32 saveGTIER; 494 u32 saveGTIMR; 495 u32 saveFDI_RXA_IMR; 496 u32 saveFDI_RXB_IMR; 497 u32 saveCACHE_MODE_0; 498 u32 saveMI_ARB_STATE; 499 u32 saveSWF0[16]; 500 u32 saveSWF1[16]; 501 u32 saveSWF2[3]; 502 u8 saveMSR; 503 u8 saveSR[8]; 504 u8 saveGR[25]; 505 u8 saveAR_INDEX; 506 u8 saveAR[21]; 507 u8 saveDACMASK; 508 u8 saveCR[37]; 509 uint64_t saveFENCE[16]; 510 u32 saveCURACNTR; 511 u32 saveCURAPOS; 512 u32 saveCURABASE; 513 u32 saveCURBCNTR; 514 u32 saveCURBPOS; 515 u32 saveCURBBASE; 516 u32 saveCURSIZE; 517 u32 saveDP_B; 518 u32 saveDP_C; 519 u32 saveDP_D; 520 u32 savePIPEA_GMCH_DATA_M; 521 u32 savePIPEB_GMCH_DATA_M; 522 u32 savePIPEA_GMCH_DATA_N; 523 u32 savePIPEB_GMCH_DATA_N; 524 u32 savePIPEA_DP_LINK_M; 525 u32 savePIPEB_DP_LINK_M; 526 u32 savePIPEA_DP_LINK_N; 527 u32 savePIPEB_DP_LINK_N; 528 u32 saveFDI_RXA_CTL; 529 u32 saveFDI_TXA_CTL; 530 u32 saveFDI_RXB_CTL; 531 u32 saveFDI_TXB_CTL; 532 u32 savePFA_CTL_1; 533 u32 savePFB_CTL_1; 534 u32 savePFA_WIN_SZ; 535 u32 savePFB_WIN_SZ; 536 u32 savePFA_WIN_POS; 537 u32 savePFB_WIN_POS; 538 u32 savePCH_DREF_CONTROL; 539 u32 saveDISP_ARB_CTL; 540 u32 savePIPEA_DATA_M1; 541 u32 savePIPEA_DATA_N1; 542 u32 savePIPEA_LINK_M1; 543 u32 savePIPEA_LINK_N1; 544 u32 savePIPEB_DATA_M1; 545 u32 savePIPEB_DATA_N1; 546 u32 savePIPEB_LINK_M1; 547 u32 savePIPEB_LINK_N1; 548 u32 saveMCHBAR_RENDER_STANDBY; 549 u32 savePCH_PORT_HOTPLUG; 550 551 struct { 552 /** Bridge to intel-gtt-ko */ 553 const struct intel_gtt *gtt; 554 /** Memory allocator for GTT stolen memory */ 555 struct drm_mm stolen; 556 /** Memory allocator for GTT */ 557 struct drm_mm gtt_space; 558 /** List of all objects in gtt_space. Used to restore gtt 559 * mappings on resume */ 560 struct list_head gtt_list; 561 562 /** Usable portion of the GTT for GEM */ 563 unsigned long gtt_start; 564 unsigned long gtt_mappable_end; 565 unsigned long gtt_end; 566 567 struct io_mapping *gtt_mapping; 568 int gtt_mtrr; 569 570 struct shrinker inactive_shrinker; 571 572 /** 573 * List of objects currently involved in rendering. 574 * 575 * Includes buffers having the contents of their GPU caches 576 * flushed, not necessarily primitives. last_rendering_seqno 577 * represents when the rendering involved will be completed. 578 * 579 * A reference is held on the buffer while on this list. 580 */ 581 struct list_head active_list; 582 583 /** 584 * List of objects which are not in the ringbuffer but which 585 * still have a write_domain which needs to be flushed before 586 * unbinding. 587 * 588 * last_rendering_seqno is 0 while an object is in this list. 589 * 590 * A reference is held on the buffer while on this list. 591 */ 592 struct list_head flushing_list; 593 594 /** 595 * LRU list of objects which are not in the ringbuffer and 596 * are ready to unbind, but are still in the GTT. 597 * 598 * last_rendering_seqno is 0 while an object is in this list. 599 * 600 * A reference is not held on the buffer while on this list, 601 * as merely being GTT-bound shouldn't prevent its being 602 * freed, and we'll pull it off the list in the free path. 603 */ 604 struct list_head inactive_list; 605 606 /** 607 * LRU list of objects which are not in the ringbuffer but 608 * are still pinned in the GTT. 609 */ 610 struct list_head pinned_list; 611 612 /** LRU list of objects with fence regs on them. */ 613 struct list_head fence_list; 614 615 /** 616 * List of objects currently pending being freed. 617 * 618 * These objects are no longer in use, but due to a signal 619 * we were prevented from freeing them at the appointed time. 620 */ 621 struct list_head deferred_free_list; 622 623 /** 624 * We leave the user IRQ off as much as possible, 625 * but this means that requests will finish and never 626 * be retired once the system goes idle. Set a timer to 627 * fire periodically while the ring is running. When it 628 * fires, go retire requests. 629 */ 630 struct delayed_work retire_work; 631 632 /** 633 * Are we in a non-interruptible section of code like 634 * modesetting? 635 */ 636 bool interruptible; 637 638 /** 639 * Flag if the X Server, and thus DRM, is not currently in 640 * control of the device. 641 * 642 * This is set between LeaveVT and EnterVT. It needs to be 643 * replaced with a semaphore. It also needs to be 644 * transitioned away from for kernel modesetting. 645 */ 646 int suspended; 647 648 /** 649 * Flag if the hardware appears to be wedged. 650 * 651 * This is set when attempts to idle the device timeout. 652 * It prevents command submission from occurring and makes 653 * every pending request fail 654 */ 655 atomic_t wedged; 656 657 /** Bit 6 swizzling required for X tiling */ 658 uint32_t bit_6_swizzle_x; 659 /** Bit 6 swizzling required for Y tiling */ 660 uint32_t bit_6_swizzle_y; 661 662 /* storage for physical objects */ 663 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 664 665 /* accounting, useful for userland debugging */ 666 size_t gtt_total; 667 size_t mappable_gtt_total; 668 size_t object_memory; 669 u32 object_count; 670 } mm; 671 struct sdvo_device_mapping sdvo_mappings[2]; 672 /* indicate whether the LVDS_BORDER should be enabled or not */ 673 unsigned int lvds_border_bits; 674 /* Panel fitter placement and size for Ironlake+ */ 675 u32 pch_pf_pos, pch_pf_size; 676 677 struct drm_crtc *plane_to_crtc_mapping[3]; 678 struct drm_crtc *pipe_to_crtc_mapping[3]; 679 wait_queue_head_t pending_flip_queue; 680 bool flip_pending_is_done; 681 682 /* Reclocking support */ 683 bool render_reclock_avail; 684 bool lvds_downclock_avail; 685 /* indicates the reduced downclock for LVDS*/ 686 int lvds_downclock; 687 struct work_struct idle_work; 688 struct timer_list idle_timer; 689 bool busy; 690 u16 orig_clock; 691 int child_dev_num; 692 struct child_device_config *child_dev; 693 struct drm_connector *int_lvds_connector; 694 struct drm_connector *int_edp_connector; 695 696 bool mchbar_need_disable; 697 698 struct work_struct rps_work; 699 spinlock_t rps_lock; 700 u32 pm_iir; 701 702 u8 cur_delay; 703 u8 min_delay; 704 u8 max_delay; 705 u8 fmax; 706 u8 fstart; 707 708 u64 last_count1; 709 unsigned long last_time1; 710 u64 last_count2; 711 struct timespec last_time2; 712 unsigned long gfx_power; 713 int c_m; 714 int r_t; 715 u8 corr; 716 spinlock_t *mchdev_lock; 717 718 enum no_fbc_reason no_fbc_reason; 719 720 struct drm_mm_node *compressed_fb; 721 struct drm_mm_node *compressed_llb; 722 723 unsigned long last_gpu_reset; 724 725 /* list of fbdev register on this device */ 726 struct intel_fbdev *fbdev; 727 728 struct backlight_device *backlight; 729 730 struct drm_property *broadcast_rgb_property; 731 struct drm_property *force_audio_property; 732 733 atomic_t forcewake_count; 734 } drm_i915_private_t; 735 736 enum i915_cache_level { 737 I915_CACHE_NONE, 738 I915_CACHE_LLC, 739 I915_CACHE_LLC_MLC, /* gen6+ */ 740 }; 741 742 struct drm_i915_gem_object { 743 struct drm_gem_object base; 744 745 /** Current space allocated to this object in the GTT, if any. */ 746 struct drm_mm_node *gtt_space; 747 struct list_head gtt_list; 748 749 /** This object's place on the active/flushing/inactive lists */ 750 struct list_head ring_list; 751 struct list_head mm_list; 752 /** This object's place on GPU write list */ 753 struct list_head gpu_write_list; 754 /** This object's place in the batchbuffer or on the eviction list */ 755 struct list_head exec_list; 756 757 /** 758 * This is set if the object is on the active or flushing lists 759 * (has pending rendering), and is not set if it's on inactive (ready 760 * to be unbound). 761 */ 762 unsigned int active:1; 763 764 /** 765 * This is set if the object has been written to since last bound 766 * to the GTT 767 */ 768 unsigned int dirty:1; 769 770 /** 771 * This is set if the object has been written to since the last 772 * GPU flush. 773 */ 774 unsigned int pending_gpu_write:1; 775 776 /** 777 * Fence register bits (if any) for this object. Will be set 778 * as needed when mapped into the GTT. 779 * Protected by dev->struct_mutex. 780 * 781 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE) 782 */ 783 signed int fence_reg:5; 784 785 /** 786 * Advice: are the backing pages purgeable? 787 */ 788 unsigned int madv:2; 789 790 /** 791 * Current tiling mode for the object. 792 */ 793 unsigned int tiling_mode:2; 794 unsigned int tiling_changed:1; 795 796 /** How many users have pinned this object in GTT space. The following 797 * users can each hold at most one reference: pwrite/pread, pin_ioctl 798 * (via user_pin_count), execbuffer (objects are not allowed multiple 799 * times for the same batchbuffer), and the framebuffer code. When 800 * switching/pageflipping, the framebuffer code has at most two buffers 801 * pinned per crtc. 802 * 803 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 804 * bits with absolutely no headroom. So use 4 bits. */ 805 unsigned int pin_count:4; 806 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 807 808 /** 809 * Is the object at the current location in the gtt mappable and 810 * fenceable? Used to avoid costly recalculations. 811 */ 812 unsigned int map_and_fenceable:1; 813 814 /** 815 * Whether the current gtt mapping needs to be mappable (and isn't just 816 * mappable by accident). Track pin and fault separate for a more 817 * accurate mappable working set. 818 */ 819 unsigned int fault_mappable:1; 820 unsigned int pin_mappable:1; 821 822 /* 823 * Is the GPU currently using a fence to access this buffer, 824 */ 825 unsigned int pending_fenced_gpu_access:1; 826 unsigned int fenced_gpu_access:1; 827 828 unsigned int cache_level:2; 829 830 struct page **pages; 831 832 /** 833 * DMAR support 834 */ 835 struct scatterlist *sg_list; 836 int num_sg; 837 838 /** 839 * Used for performing relocations during execbuffer insertion. 840 */ 841 struct hlist_node exec_node; 842 unsigned long exec_handle; 843 struct drm_i915_gem_exec_object2 *exec_entry; 844 845 /** 846 * Current offset of the object in GTT space. 847 * 848 * This is the same as gtt_space->start 849 */ 850 uint32_t gtt_offset; 851 852 /** Breadcrumb of last rendering to the buffer. */ 853 uint32_t last_rendering_seqno; 854 struct intel_ring_buffer *ring; 855 856 /** Breadcrumb of last fenced GPU access to the buffer. */ 857 uint32_t last_fenced_seqno; 858 struct intel_ring_buffer *last_fenced_ring; 859 860 /** Current tiling stride for the object, if it's tiled. */ 861 uint32_t stride; 862 863 /** Record of address bit 17 of each page at last unbind. */ 864 unsigned long *bit_17; 865 866 867 /** 868 * If present, while GEM_DOMAIN_CPU is in the read domain this array 869 * flags which individual pages are valid. 870 */ 871 uint8_t *page_cpu_valid; 872 873 /** User space pin count and filp owning the pin */ 874 uint32_t user_pin_count; 875 struct drm_file *pin_filp; 876 877 /** for phy allocated objects */ 878 struct drm_i915_gem_phys_object *phys_obj; 879 880 /** 881 * Number of crtcs where this object is currently the fb, but 882 * will be page flipped away on the next vblank. When it 883 * reaches 0, dev_priv->pending_flip_queue will be woken up. 884 */ 885 atomic_t pending_flip; 886 }; 887 888 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 889 890 /** 891 * Request queue structure. 892 * 893 * The request queue allows us to note sequence numbers that have been emitted 894 * and may be associated with active buffers to be retired. 895 * 896 * By keeping this list, we can avoid having to do questionable 897 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 898 * an emission time with seqnos for tracking how far ahead of the GPU we are. 899 */ 900 struct drm_i915_gem_request { 901 /** On Which ring this request was generated */ 902 struct intel_ring_buffer *ring; 903 904 /** GEM sequence number associated with this request. */ 905 uint32_t seqno; 906 907 /** Time at which this request was emitted, in jiffies. */ 908 unsigned long emitted_jiffies; 909 910 /** global list entry for this request */ 911 struct list_head list; 912 913 struct drm_i915_file_private *file_priv; 914 /** file_priv list entry for this request */ 915 struct list_head client_list; 916 }; 917 918 struct drm_i915_file_private { 919 struct { 920 struct spinlock lock; 921 struct list_head request_list; 922 } mm; 923 }; 924 925 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) 926 927 #define IS_I830(dev) ((dev)->pci_device == 0x3577) 928 #define IS_845G(dev) ((dev)->pci_device == 0x2562) 929 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 930 #define IS_I865G(dev) ((dev)->pci_device == 0x2572) 931 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 932 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 933 #define IS_I945G(dev) ((dev)->pci_device == 0x2772) 934 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 935 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 936 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 937 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 938 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 939 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) 940 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) 941 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 942 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 943 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) 944 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 945 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 946 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 947 948 /* 949 * The genX designation typically refers to the render engine, so render 950 * capability related checks should use IS_GEN, while display and other checks 951 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular 952 * chips, etc.). 953 */ 954 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 955 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 956 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 957 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 958 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 959 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 960 961 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) 962 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) 963 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 964 965 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 966 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 967 968 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 969 * rows, which changed the alignment requirements and fence programming. 970 */ 971 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 972 IS_I915GM(dev))) 973 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 974 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 975 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 976 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) 977 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 978 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 979 /* dsparb controlled by hw only */ 980 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 981 982 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 983 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 984 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 985 986 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) 987 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) 988 989 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) 990 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 991 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 992 993 #include "i915_trace.h" 994 995 extern struct drm_ioctl_desc i915_ioctls[]; 996 extern int i915_max_ioctl; 997 extern unsigned int i915_fbpercrtc __always_unused; 998 extern int i915_panel_ignore_lid __read_mostly; 999 extern unsigned int i915_powersave __read_mostly; 1000 extern unsigned int i915_semaphores __read_mostly; 1001 extern unsigned int i915_lvds_downclock __read_mostly; 1002 extern unsigned int i915_panel_use_ssc __read_mostly; 1003 extern int i915_vbt_sdvo_panel_type __read_mostly; 1004 extern unsigned int i915_enable_rc6 __read_mostly; 1005 extern unsigned int i915_enable_fbc __read_mostly; 1006 extern bool i915_enable_hangcheck __read_mostly; 1007 1008 extern int i915_suspend(struct drm_device *dev, pm_message_t state); 1009 extern int i915_resume(struct drm_device *dev); 1010 extern int i915_master_create(struct drm_device *dev, struct drm_master *master); 1011 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 1012 1013 /* i915_dma.c */ 1014 extern void i915_kernel_lost_context(struct drm_device * dev); 1015 extern int i915_driver_load(struct drm_device *, unsigned long flags); 1016 extern int i915_driver_unload(struct drm_device *); 1017 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 1018 extern void i915_driver_lastclose(struct drm_device * dev); 1019 extern void i915_driver_preclose(struct drm_device *dev, 1020 struct drm_file *file_priv); 1021 extern void i915_driver_postclose(struct drm_device *dev, 1022 struct drm_file *file_priv); 1023 extern int i915_driver_device_is_agp(struct drm_device * dev); 1024 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 1025 unsigned long arg); 1026 extern int i915_emit_box(struct drm_device *dev, 1027 struct drm_clip_rect *box, 1028 int DR1, int DR4); 1029 extern int i915_reset(struct drm_device *dev, u8 flags); 1030 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 1031 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 1032 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 1033 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); 1034 1035 1036 /* i915_irq.c */ 1037 void i915_hangcheck_elapsed(unsigned long data); 1038 void i915_handle_error(struct drm_device *dev, bool wedged); 1039 extern int i915_irq_emit(struct drm_device *dev, void *data, 1040 struct drm_file *file_priv); 1041 extern int i915_irq_wait(struct drm_device *dev, void *data, 1042 struct drm_file *file_priv); 1043 1044 extern void intel_irq_init(struct drm_device *dev); 1045 1046 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, 1047 struct drm_file *file_priv); 1048 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, 1049 struct drm_file *file_priv); 1050 extern int i915_vblank_swap(struct drm_device *dev, void *data, 1051 struct drm_file *file_priv); 1052 1053 void 1054 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1055 1056 void 1057 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1058 1059 void intel_enable_asle(struct drm_device *dev); 1060 1061 #ifdef CONFIG_DEBUG_FS 1062 extern void i915_destroy_error_state(struct drm_device *dev); 1063 #else 1064 #define i915_destroy_error_state(x) 1065 #endif 1066 1067 1068 /* i915_mem.c */ 1069 extern int i915_mem_alloc(struct drm_device *dev, void *data, 1070 struct drm_file *file_priv); 1071 extern int i915_mem_free(struct drm_device *dev, void *data, 1072 struct drm_file *file_priv); 1073 extern int i915_mem_init_heap(struct drm_device *dev, void *data, 1074 struct drm_file *file_priv); 1075 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, 1076 struct drm_file *file_priv); 1077 extern void i915_mem_takedown(struct mem_block **heap); 1078 extern void i915_mem_release(struct drm_device * dev, 1079 struct drm_file *file_priv, struct mem_block *heap); 1080 /* i915_gem.c */ 1081 int i915_gem_init_ioctl(struct drm_device *dev, void *data, 1082 struct drm_file *file_priv); 1083 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 1084 struct drm_file *file_priv); 1085 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 1086 struct drm_file *file_priv); 1087 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1088 struct drm_file *file_priv); 1089 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 1090 struct drm_file *file_priv); 1091 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 1092 struct drm_file *file_priv); 1093 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1094 struct drm_file *file_priv); 1095 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 1096 struct drm_file *file_priv); 1097 int i915_gem_execbuffer(struct drm_device *dev, void *data, 1098 struct drm_file *file_priv); 1099 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 1100 struct drm_file *file_priv); 1101 int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 1102 struct drm_file *file_priv); 1103 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 1104 struct drm_file *file_priv); 1105 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 1106 struct drm_file *file_priv); 1107 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 1108 struct drm_file *file_priv); 1109 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 1110 struct drm_file *file_priv); 1111 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 1112 struct drm_file *file_priv); 1113 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 1114 struct drm_file *file_priv); 1115 int i915_gem_set_tiling(struct drm_device *dev, void *data, 1116 struct drm_file *file_priv); 1117 int i915_gem_get_tiling(struct drm_device *dev, void *data, 1118 struct drm_file *file_priv); 1119 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 1120 struct drm_file *file_priv); 1121 void i915_gem_load(struct drm_device *dev); 1122 int i915_gem_init_object(struct drm_gem_object *obj); 1123 int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring, 1124 uint32_t invalidate_domains, 1125 uint32_t flush_domains); 1126 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 1127 size_t size); 1128 void i915_gem_free_object(struct drm_gem_object *obj); 1129 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, 1130 uint32_t alignment, 1131 bool map_and_fenceable); 1132 void i915_gem_object_unpin(struct drm_i915_gem_object *obj); 1133 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); 1134 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 1135 void i915_gem_lastclose(struct drm_device *dev); 1136 1137 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); 1138 int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj); 1139 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, 1140 struct intel_ring_buffer *ring, 1141 u32 seqno); 1142 1143 int i915_gem_dumb_create(struct drm_file *file_priv, 1144 struct drm_device *dev, 1145 struct drm_mode_create_dumb *args); 1146 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 1147 uint32_t handle, uint64_t *offset); 1148 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, 1149 uint32_t handle); 1150 /** 1151 * Returns true if seq1 is later than seq2. 1152 */ 1153 static inline bool 1154 i915_seqno_passed(uint32_t seq1, uint32_t seq2) 1155 { 1156 return (int32_t)(seq1 - seq2) >= 0; 1157 } 1158 1159 static inline u32 1160 i915_gem_next_request_seqno(struct intel_ring_buffer *ring) 1161 { 1162 drm_i915_private_t *dev_priv = ring->dev->dev_private; 1163 return ring->outstanding_lazy_request = dev_priv->next_seqno; 1164 } 1165 1166 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj, 1167 struct intel_ring_buffer *pipelined); 1168 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 1169 1170 void i915_gem_retire_requests(struct drm_device *dev); 1171 void i915_gem_reset(struct drm_device *dev); 1172 void i915_gem_clflush_object(struct drm_i915_gem_object *obj); 1173 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, 1174 uint32_t read_domains, 1175 uint32_t write_domain); 1176 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 1177 int __must_check i915_gem_init_ringbuffer(struct drm_device *dev); 1178 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 1179 void i915_gem_do_init(struct drm_device *dev, 1180 unsigned long start, 1181 unsigned long mappable_end, 1182 unsigned long end); 1183 int __must_check i915_gpu_idle(struct drm_device *dev); 1184 int __must_check i915_gem_idle(struct drm_device *dev); 1185 int __must_check i915_add_request(struct intel_ring_buffer *ring, 1186 struct drm_file *file, 1187 struct drm_i915_gem_request *request); 1188 int __must_check i915_wait_request(struct intel_ring_buffer *ring, 1189 uint32_t seqno); 1190 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 1191 int __must_check 1192 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 1193 bool write); 1194 int __must_check 1195 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 1196 u32 alignment, 1197 struct intel_ring_buffer *pipelined); 1198 int i915_gem_attach_phys_object(struct drm_device *dev, 1199 struct drm_i915_gem_object *obj, 1200 int id, 1201 int align); 1202 void i915_gem_detach_phys_object(struct drm_device *dev, 1203 struct drm_i915_gem_object *obj); 1204 void i915_gem_free_all_phys_object(struct drm_device *dev); 1205 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 1206 1207 uint32_t 1208 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, 1209 uint32_t size, 1210 int tiling_mode); 1211 1212 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1213 enum i915_cache_level cache_level); 1214 1215 /* i915_gem_gtt.c */ 1216 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 1217 int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj); 1218 void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj, 1219 enum i915_cache_level cache_level); 1220 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); 1221 1222 /* i915_gem_evict.c */ 1223 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, 1224 unsigned alignment, bool mappable); 1225 int __must_check i915_gem_evict_everything(struct drm_device *dev, 1226 bool purgeable_only); 1227 int __must_check i915_gem_evict_inactive(struct drm_device *dev, 1228 bool purgeable_only); 1229 1230 /* i915_gem_tiling.c */ 1231 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 1232 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 1233 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 1234 1235 /* i915_gem_debug.c */ 1236 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, 1237 const char *where, uint32_t mark); 1238 #if WATCH_LISTS 1239 int i915_verify_lists(struct drm_device *dev); 1240 #else 1241 #define i915_verify_lists(dev) 0 1242 #endif 1243 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, 1244 int handle); 1245 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, 1246 const char *where, uint32_t mark); 1247 1248 /* i915_debugfs.c */ 1249 int i915_debugfs_init(struct drm_minor *minor); 1250 void i915_debugfs_cleanup(struct drm_minor *minor); 1251 1252 /* i915_suspend.c */ 1253 extern int i915_save_state(struct drm_device *dev); 1254 extern int i915_restore_state(struct drm_device *dev); 1255 1256 /* i915_suspend.c */ 1257 extern int i915_save_state(struct drm_device *dev); 1258 extern int i915_restore_state(struct drm_device *dev); 1259 1260 /* intel_i2c.c */ 1261 extern int intel_setup_gmbus(struct drm_device *dev); 1262 extern void intel_teardown_gmbus(struct drm_device *dev); 1263 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); 1264 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); 1265 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 1266 { 1267 return container_of(adapter, struct intel_gmbus, adapter)->force_bit; 1268 } 1269 extern void intel_i2c_reset(struct drm_device *dev); 1270 1271 /* intel_opregion.c */ 1272 extern int intel_opregion_setup(struct drm_device *dev); 1273 #ifdef CONFIG_ACPI 1274 extern void intel_opregion_init(struct drm_device *dev); 1275 extern void intel_opregion_fini(struct drm_device *dev); 1276 extern void intel_opregion_asle_intr(struct drm_device *dev); 1277 extern void intel_opregion_gse_intr(struct drm_device *dev); 1278 extern void intel_opregion_enable_asle(struct drm_device *dev); 1279 #else 1280 static inline void intel_opregion_init(struct drm_device *dev) { return; } 1281 static inline void intel_opregion_fini(struct drm_device *dev) { return; } 1282 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } 1283 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } 1284 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } 1285 #endif 1286 1287 /* intel_acpi.c */ 1288 #ifdef CONFIG_ACPI 1289 extern void intel_register_dsm_handler(void); 1290 extern void intel_unregister_dsm_handler(void); 1291 #else 1292 static inline void intel_register_dsm_handler(void) { return; } 1293 static inline void intel_unregister_dsm_handler(void) { return; } 1294 #endif /* CONFIG_ACPI */ 1295 1296 /* modesetting */ 1297 extern void intel_modeset_init(struct drm_device *dev); 1298 extern void intel_modeset_gem_init(struct drm_device *dev); 1299 extern void intel_modeset_cleanup(struct drm_device *dev); 1300 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 1301 extern bool intel_fbc_enabled(struct drm_device *dev); 1302 extern void intel_disable_fbc(struct drm_device *dev); 1303 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 1304 extern void ironlake_init_pch_refclk(struct drm_device *dev); 1305 extern void ironlake_enable_rc6(struct drm_device *dev); 1306 extern void gen6_set_rps(struct drm_device *dev, u8 val); 1307 extern void intel_detect_pch(struct drm_device *dev); 1308 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 1309 1310 /* overlay */ 1311 #ifdef CONFIG_DEBUG_FS 1312 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); 1313 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); 1314 1315 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); 1316 extern void intel_display_print_error_state(struct seq_file *m, 1317 struct drm_device *dev, 1318 struct intel_display_error_state *error); 1319 #endif 1320 1321 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) 1322 1323 #define BEGIN_LP_RING(n) \ 1324 intel_ring_begin(LP_RING(dev_priv), (n)) 1325 1326 #define OUT_RING(x) \ 1327 intel_ring_emit(LP_RING(dev_priv), x) 1328 1329 #define ADVANCE_LP_RING() \ 1330 intel_ring_advance(LP_RING(dev_priv)) 1331 1332 /** 1333 * Lock test for when it's just for synchronization of ring access. 1334 * 1335 * In that case, we don't need to do it when GEM is initialized as nobody else 1336 * has access to the ring. 1337 */ 1338 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ 1339 if (LP_RING(dev->dev_private)->obj == NULL) \ 1340 LOCK_TEST_WITH_RETURN(dev, file); \ 1341 } while (0) 1342 1343 /* On SNB platform, before reading ring registers forcewake bit 1344 * must be set to prevent GT core from power down and stale values being 1345 * returned. 1346 */ 1347 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1348 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1349 void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); 1350 1351 /* We give fast paths for the really cool registers */ 1352 #define NEEDS_FORCE_WAKE(dev_priv, reg) \ 1353 (((dev_priv)->info->gen >= 6) && \ 1354 ((reg) < 0x40000) && \ 1355 ((reg) != FORCEWAKE)) 1356 1357 #define __i915_read(x, y) \ 1358 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); 1359 1360 __i915_read(8, b) 1361 __i915_read(16, w) 1362 __i915_read(32, l) 1363 __i915_read(64, q) 1364 #undef __i915_read 1365 1366 #define __i915_write(x, y) \ 1367 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); 1368 1369 __i915_write(8, b) 1370 __i915_write(16, w) 1371 __i915_write(32, l) 1372 __i915_write(64, q) 1373 #undef __i915_write 1374 1375 #define I915_READ8(reg) i915_read8(dev_priv, (reg)) 1376 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) 1377 1378 #define I915_READ16(reg) i915_read16(dev_priv, (reg)) 1379 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) 1380 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) 1381 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) 1382 1383 #define I915_READ(reg) i915_read32(dev_priv, (reg)) 1384 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) 1385 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) 1386 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) 1387 1388 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) 1389 #define I915_READ64(reg) i915_read64(dev_priv, (reg)) 1390 1391 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 1392 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 1393 1394 1395 #endif 1396