1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include "i915_reg.h" 34 #include "intel_bios.h" 35 #include "intel_ringbuffer.h" 36 #include <linux/io-mapping.h> 37 #include <linux/i2c.h> 38 #include <drm/intel-gtt.h> 39 #include <linux/backlight.h> 40 41 /* General customization: 42 */ 43 44 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 45 46 #define DRIVER_NAME "i915" 47 #define DRIVER_DESC "Intel Graphics" 48 #define DRIVER_DATE "20080730" 49 50 enum pipe { 51 PIPE_A = 0, 52 PIPE_B, 53 PIPE_C, 54 I915_MAX_PIPES 55 }; 56 #define pipe_name(p) ((p) + 'A') 57 58 enum plane { 59 PLANE_A = 0, 60 PLANE_B, 61 PLANE_C, 62 }; 63 #define plane_name(p) ((p) + 'A') 64 65 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 66 67 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) 68 69 /* Interface history: 70 * 71 * 1.1: Original. 72 * 1.2: Add Power Management 73 * 1.3: Add vblank support 74 * 1.4: Fix cmdbuffer path, add heap destroy 75 * 1.5: Add vblank pipe configuration 76 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 77 * - Support vertical blank on secondary display pipe 78 */ 79 #define DRIVER_MAJOR 1 80 #define DRIVER_MINOR 6 81 #define DRIVER_PATCHLEVEL 0 82 83 #define WATCH_COHERENCY 0 84 #define WATCH_LISTS 0 85 86 #define I915_GEM_PHYS_CURSOR_0 1 87 #define I915_GEM_PHYS_CURSOR_1 2 88 #define I915_GEM_PHYS_OVERLAY_REGS 3 89 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 90 91 struct drm_i915_gem_phys_object { 92 int id; 93 struct page **page_list; 94 drm_dma_handle_t *handle; 95 struct drm_i915_gem_object *cur_obj; 96 }; 97 98 struct mem_block { 99 struct mem_block *next; 100 struct mem_block *prev; 101 int start; 102 int size; 103 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 104 }; 105 106 struct opregion_header; 107 struct opregion_acpi; 108 struct opregion_swsci; 109 struct opregion_asle; 110 struct drm_i915_private; 111 112 struct intel_opregion { 113 struct opregion_header *header; 114 struct opregion_acpi *acpi; 115 struct opregion_swsci *swsci; 116 struct opregion_asle *asle; 117 void *vbt; 118 u32 __iomem *lid_state; 119 }; 120 #define OPREGION_SIZE (8*1024) 121 122 struct intel_overlay; 123 struct intel_overlay_error_state; 124 125 struct drm_i915_master_private { 126 drm_local_map_t *sarea; 127 struct _drm_i915_sarea *sarea_priv; 128 }; 129 #define I915_FENCE_REG_NONE -1 130 #define I915_MAX_NUM_FENCES 16 131 /* 16 fences + sign bit for FENCE_REG_NONE */ 132 #define I915_MAX_NUM_FENCE_BITS 5 133 134 struct drm_i915_fence_reg { 135 struct list_head lru_list; 136 struct drm_i915_gem_object *obj; 137 uint32_t setup_seqno; 138 }; 139 140 struct sdvo_device_mapping { 141 u8 initialized; 142 u8 dvo_port; 143 u8 slave_addr; 144 u8 dvo_wiring; 145 u8 i2c_pin; 146 u8 ddc_pin; 147 }; 148 149 struct intel_display_error_state; 150 151 struct drm_i915_error_state { 152 u32 eir; 153 u32 pgtbl_er; 154 u32 pipestat[I915_MAX_PIPES]; 155 u32 ipeir; 156 u32 ipehr; 157 u32 instdone; 158 u32 acthd; 159 u32 error; /* gen6+ */ 160 u32 bcs_acthd; /* gen6+ blt engine */ 161 u32 bcs_ipehr; 162 u32 bcs_ipeir; 163 u32 bcs_instdone; 164 u32 bcs_seqno; 165 u32 vcs_acthd; /* gen6+ bsd engine */ 166 u32 vcs_ipehr; 167 u32 vcs_ipeir; 168 u32 vcs_instdone; 169 u32 vcs_seqno; 170 u32 instpm; 171 u32 instps; 172 u32 instdone1; 173 u32 seqno; 174 u64 bbaddr; 175 u64 fence[I915_MAX_NUM_FENCES]; 176 struct timeval time; 177 struct drm_i915_error_object { 178 int page_count; 179 u32 gtt_offset; 180 u32 *pages[0]; 181 } *ringbuffer[I915_NUM_RINGS], *batchbuffer[I915_NUM_RINGS]; 182 struct drm_i915_error_buffer { 183 u32 size; 184 u32 name; 185 u32 seqno; 186 u32 gtt_offset; 187 u32 read_domains; 188 u32 write_domain; 189 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 190 s32 pinned:2; 191 u32 tiling:2; 192 u32 dirty:1; 193 u32 purgeable:1; 194 u32 ring:4; 195 u32 cache_level:2; 196 } *active_bo, *pinned_bo; 197 u32 active_bo_count, pinned_bo_count; 198 struct intel_overlay_error_state *overlay; 199 struct intel_display_error_state *display; 200 }; 201 202 struct drm_i915_display_funcs { 203 void (*dpms)(struct drm_crtc *crtc, int mode); 204 bool (*fbc_enabled)(struct drm_device *dev); 205 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); 206 void (*disable_fbc)(struct drm_device *dev); 207 int (*get_display_clock_speed)(struct drm_device *dev); 208 int (*get_fifo_size)(struct drm_device *dev, int plane); 209 void (*update_wm)(struct drm_device *dev); 210 void (*update_sprite_wm)(struct drm_device *dev, int pipe, 211 uint32_t sprite_width, int pixel_size); 212 int (*crtc_mode_set)(struct drm_crtc *crtc, 213 struct drm_display_mode *mode, 214 struct drm_display_mode *adjusted_mode, 215 int x, int y, 216 struct drm_framebuffer *old_fb); 217 void (*write_eld)(struct drm_connector *connector, 218 struct drm_crtc *crtc); 219 void (*fdi_link_train)(struct drm_crtc *crtc); 220 void (*init_clock_gating)(struct drm_device *dev); 221 void (*init_pch_clock_gating)(struct drm_device *dev); 222 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 223 struct drm_framebuffer *fb, 224 struct drm_i915_gem_object *obj); 225 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, 226 int x, int y); 227 void (*force_wake_get)(struct drm_i915_private *dev_priv); 228 void (*force_wake_put)(struct drm_i915_private *dev_priv); 229 /* clock updates for mode set */ 230 /* cursor updates */ 231 /* render clock increase/decrease */ 232 /* display clock increase/decrease */ 233 /* pll clock increase/decrease */ 234 }; 235 236 struct intel_device_info { 237 u8 gen; 238 u8 is_mobile:1; 239 u8 is_i85x:1; 240 u8 is_i915g:1; 241 u8 is_i945gm:1; 242 u8 is_g33:1; 243 u8 need_gfx_hws:1; 244 u8 is_g4x:1; 245 u8 is_pineview:1; 246 u8 is_broadwater:1; 247 u8 is_crestline:1; 248 u8 is_ivybridge:1; 249 u8 has_fbc:1; 250 u8 has_pipe_cxsr:1; 251 u8 has_hotplug:1; 252 u8 cursor_needs_physical:1; 253 u8 has_overlay:1; 254 u8 overlay_needs_physical:1; 255 u8 supports_tv:1; 256 u8 has_bsd_ring:1; 257 u8 has_blt_ring:1; 258 }; 259 260 enum no_fbc_reason { 261 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 262 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ 263 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 264 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 265 FBC_BAD_PLANE, /* fbc not supported on plane */ 266 FBC_NOT_TILED, /* buffer not tiled */ 267 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 268 FBC_MODULE_PARAM, 269 }; 270 271 enum intel_pch { 272 PCH_IBX, /* Ibexpeak PCH */ 273 PCH_CPT, /* Cougarpoint PCH */ 274 }; 275 276 #define QUIRK_PIPEA_FORCE (1<<0) 277 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 278 279 struct intel_fbdev; 280 struct intel_fbc_work; 281 282 typedef struct drm_i915_private { 283 struct drm_device *dev; 284 285 const struct intel_device_info *info; 286 287 int has_gem; 288 int relative_constants_mode; 289 290 void __iomem *regs; 291 u32 gt_fifo_count; 292 293 struct intel_gmbus { 294 struct i2c_adapter adapter; 295 struct i2c_adapter *force_bit; 296 u32 reg0; 297 } *gmbus; 298 299 struct pci_dev *bridge_dev; 300 struct intel_ring_buffer ring[I915_NUM_RINGS]; 301 uint32_t next_seqno; 302 303 drm_dma_handle_t *status_page_dmah; 304 uint32_t counter; 305 drm_local_map_t hws_map; 306 struct drm_i915_gem_object *pwrctx; 307 struct drm_i915_gem_object *renderctx; 308 309 struct resource mch_res; 310 311 unsigned int cpp; 312 int back_offset; 313 int front_offset; 314 int current_page; 315 int page_flipping; 316 317 atomic_t irq_received; 318 319 /* protects the irq masks */ 320 spinlock_t irq_lock; 321 /** Cached value of IMR to avoid reads in updating the bitfield */ 322 u32 pipestat[2]; 323 u32 irq_mask; 324 u32 gt_irq_mask; 325 u32 pch_irq_mask; 326 327 u32 hotplug_supported_mask; 328 struct work_struct hotplug_work; 329 330 int tex_lru_log_granularity; 331 int allow_batchbuffer; 332 struct mem_block *agp_heap; 333 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 334 int vblank_pipe; 335 int num_pipe; 336 337 /* For hangcheck timer */ 338 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ 339 struct timer_list hangcheck_timer; 340 int hangcheck_count; 341 uint32_t last_acthd; 342 uint32_t last_acthd_bsd; 343 uint32_t last_acthd_blt; 344 uint32_t last_instdone; 345 uint32_t last_instdone1; 346 347 unsigned long cfb_size; 348 unsigned int cfb_fb; 349 enum plane cfb_plane; 350 int cfb_y; 351 struct intel_fbc_work *fbc_work; 352 353 struct intel_opregion opregion; 354 355 /* overlay */ 356 struct intel_overlay *overlay; 357 bool sprite_scaling_enabled; 358 359 /* LVDS info */ 360 int backlight_level; /* restore backlight to this value */ 361 bool backlight_enabled; 362 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 363 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 364 365 /* Feature bits from the VBIOS */ 366 unsigned int int_tv_support:1; 367 unsigned int lvds_dither:1; 368 unsigned int lvds_vbt:1; 369 unsigned int int_crt_support:1; 370 unsigned int lvds_use_ssc:1; 371 unsigned int display_clock_mode:1; 372 int lvds_ssc_freq; 373 struct { 374 int rate; 375 int lanes; 376 int preemphasis; 377 int vswing; 378 379 bool initialized; 380 bool support; 381 int bpp; 382 struct edp_power_seq pps; 383 } edp; 384 bool no_aux_handshake; 385 386 struct notifier_block lid_notifier; 387 388 int crt_ddc_pin; 389 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 390 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 391 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 392 393 unsigned int fsb_freq, mem_freq, is_ddr3; 394 395 spinlock_t error_lock; 396 struct drm_i915_error_state *first_error; 397 struct work_struct error_work; 398 struct completion error_completion; 399 struct workqueue_struct *wq; 400 401 /* Display functions */ 402 struct drm_i915_display_funcs display; 403 404 /* PCH chipset type */ 405 enum intel_pch pch_type; 406 407 unsigned long quirks; 408 409 /* Register state */ 410 bool modeset_on_lid; 411 u8 saveLBB; 412 u32 saveDSPACNTR; 413 u32 saveDSPBCNTR; 414 u32 saveDSPARB; 415 u32 saveHWS; 416 u32 savePIPEACONF; 417 u32 savePIPEBCONF; 418 u32 savePIPEASRC; 419 u32 savePIPEBSRC; 420 u32 saveFPA0; 421 u32 saveFPA1; 422 u32 saveDPLL_A; 423 u32 saveDPLL_A_MD; 424 u32 saveHTOTAL_A; 425 u32 saveHBLANK_A; 426 u32 saveHSYNC_A; 427 u32 saveVTOTAL_A; 428 u32 saveVBLANK_A; 429 u32 saveVSYNC_A; 430 u32 saveBCLRPAT_A; 431 u32 saveTRANSACONF; 432 u32 saveTRANS_HTOTAL_A; 433 u32 saveTRANS_HBLANK_A; 434 u32 saveTRANS_HSYNC_A; 435 u32 saveTRANS_VTOTAL_A; 436 u32 saveTRANS_VBLANK_A; 437 u32 saveTRANS_VSYNC_A; 438 u32 savePIPEASTAT; 439 u32 saveDSPASTRIDE; 440 u32 saveDSPASIZE; 441 u32 saveDSPAPOS; 442 u32 saveDSPAADDR; 443 u32 saveDSPASURF; 444 u32 saveDSPATILEOFF; 445 u32 savePFIT_PGM_RATIOS; 446 u32 saveBLC_HIST_CTL; 447 u32 saveBLC_PWM_CTL; 448 u32 saveBLC_PWM_CTL2; 449 u32 saveBLC_CPU_PWM_CTL; 450 u32 saveBLC_CPU_PWM_CTL2; 451 u32 saveFPB0; 452 u32 saveFPB1; 453 u32 saveDPLL_B; 454 u32 saveDPLL_B_MD; 455 u32 saveHTOTAL_B; 456 u32 saveHBLANK_B; 457 u32 saveHSYNC_B; 458 u32 saveVTOTAL_B; 459 u32 saveVBLANK_B; 460 u32 saveVSYNC_B; 461 u32 saveBCLRPAT_B; 462 u32 saveTRANSBCONF; 463 u32 saveTRANS_HTOTAL_B; 464 u32 saveTRANS_HBLANK_B; 465 u32 saveTRANS_HSYNC_B; 466 u32 saveTRANS_VTOTAL_B; 467 u32 saveTRANS_VBLANK_B; 468 u32 saveTRANS_VSYNC_B; 469 u32 savePIPEBSTAT; 470 u32 saveDSPBSTRIDE; 471 u32 saveDSPBSIZE; 472 u32 saveDSPBPOS; 473 u32 saveDSPBADDR; 474 u32 saveDSPBSURF; 475 u32 saveDSPBTILEOFF; 476 u32 saveVGA0; 477 u32 saveVGA1; 478 u32 saveVGA_PD; 479 u32 saveVGACNTRL; 480 u32 saveADPA; 481 u32 saveLVDS; 482 u32 savePP_ON_DELAYS; 483 u32 savePP_OFF_DELAYS; 484 u32 saveDVOA; 485 u32 saveDVOB; 486 u32 saveDVOC; 487 u32 savePP_ON; 488 u32 savePP_OFF; 489 u32 savePP_CONTROL; 490 u32 savePP_DIVISOR; 491 u32 savePFIT_CONTROL; 492 u32 save_palette_a[256]; 493 u32 save_palette_b[256]; 494 u32 saveDPFC_CB_BASE; 495 u32 saveFBC_CFB_BASE; 496 u32 saveFBC_LL_BASE; 497 u32 saveFBC_CONTROL; 498 u32 saveFBC_CONTROL2; 499 u32 saveIER; 500 u32 saveIIR; 501 u32 saveIMR; 502 u32 saveDEIER; 503 u32 saveDEIMR; 504 u32 saveGTIER; 505 u32 saveGTIMR; 506 u32 saveFDI_RXA_IMR; 507 u32 saveFDI_RXB_IMR; 508 u32 saveCACHE_MODE_0; 509 u32 saveMI_ARB_STATE; 510 u32 saveSWF0[16]; 511 u32 saveSWF1[16]; 512 u32 saveSWF2[3]; 513 u8 saveMSR; 514 u8 saveSR[8]; 515 u8 saveGR[25]; 516 u8 saveAR_INDEX; 517 u8 saveAR[21]; 518 u8 saveDACMASK; 519 u8 saveCR[37]; 520 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 521 u32 saveCURACNTR; 522 u32 saveCURAPOS; 523 u32 saveCURABASE; 524 u32 saveCURBCNTR; 525 u32 saveCURBPOS; 526 u32 saveCURBBASE; 527 u32 saveCURSIZE; 528 u32 saveDP_B; 529 u32 saveDP_C; 530 u32 saveDP_D; 531 u32 savePIPEA_GMCH_DATA_M; 532 u32 savePIPEB_GMCH_DATA_M; 533 u32 savePIPEA_GMCH_DATA_N; 534 u32 savePIPEB_GMCH_DATA_N; 535 u32 savePIPEA_DP_LINK_M; 536 u32 savePIPEB_DP_LINK_M; 537 u32 savePIPEA_DP_LINK_N; 538 u32 savePIPEB_DP_LINK_N; 539 u32 saveFDI_RXA_CTL; 540 u32 saveFDI_TXA_CTL; 541 u32 saveFDI_RXB_CTL; 542 u32 saveFDI_TXB_CTL; 543 u32 savePFA_CTL_1; 544 u32 savePFB_CTL_1; 545 u32 savePFA_WIN_SZ; 546 u32 savePFB_WIN_SZ; 547 u32 savePFA_WIN_POS; 548 u32 savePFB_WIN_POS; 549 u32 savePCH_DREF_CONTROL; 550 u32 saveDISP_ARB_CTL; 551 u32 savePIPEA_DATA_M1; 552 u32 savePIPEA_DATA_N1; 553 u32 savePIPEA_LINK_M1; 554 u32 savePIPEA_LINK_N1; 555 u32 savePIPEB_DATA_M1; 556 u32 savePIPEB_DATA_N1; 557 u32 savePIPEB_LINK_M1; 558 u32 savePIPEB_LINK_N1; 559 u32 saveMCHBAR_RENDER_STANDBY; 560 u32 savePCH_PORT_HOTPLUG; 561 562 struct { 563 /** Bridge to intel-gtt-ko */ 564 const struct intel_gtt *gtt; 565 /** Memory allocator for GTT stolen memory */ 566 struct drm_mm stolen; 567 /** Memory allocator for GTT */ 568 struct drm_mm gtt_space; 569 /** List of all objects in gtt_space. Used to restore gtt 570 * mappings on resume */ 571 struct list_head gtt_list; 572 573 /** Usable portion of the GTT for GEM */ 574 unsigned long gtt_start; 575 unsigned long gtt_mappable_end; 576 unsigned long gtt_end; 577 578 struct io_mapping *gtt_mapping; 579 int gtt_mtrr; 580 581 struct shrinker inactive_shrinker; 582 583 /** 584 * List of objects currently involved in rendering. 585 * 586 * Includes buffers having the contents of their GPU caches 587 * flushed, not necessarily primitives. last_rendering_seqno 588 * represents when the rendering involved will be completed. 589 * 590 * A reference is held on the buffer while on this list. 591 */ 592 struct list_head active_list; 593 594 /** 595 * List of objects which are not in the ringbuffer but which 596 * still have a write_domain which needs to be flushed before 597 * unbinding. 598 * 599 * last_rendering_seqno is 0 while an object is in this list. 600 * 601 * A reference is held on the buffer while on this list. 602 */ 603 struct list_head flushing_list; 604 605 /** 606 * LRU list of objects which are not in the ringbuffer and 607 * are ready to unbind, but are still in the GTT. 608 * 609 * last_rendering_seqno is 0 while an object is in this list. 610 * 611 * A reference is not held on the buffer while on this list, 612 * as merely being GTT-bound shouldn't prevent its being 613 * freed, and we'll pull it off the list in the free path. 614 */ 615 struct list_head inactive_list; 616 617 /** 618 * LRU list of objects which are not in the ringbuffer but 619 * are still pinned in the GTT. 620 */ 621 struct list_head pinned_list; 622 623 /** LRU list of objects with fence regs on them. */ 624 struct list_head fence_list; 625 626 /** 627 * List of objects currently pending being freed. 628 * 629 * These objects are no longer in use, but due to a signal 630 * we were prevented from freeing them at the appointed time. 631 */ 632 struct list_head deferred_free_list; 633 634 /** 635 * We leave the user IRQ off as much as possible, 636 * but this means that requests will finish and never 637 * be retired once the system goes idle. Set a timer to 638 * fire periodically while the ring is running. When it 639 * fires, go retire requests. 640 */ 641 struct delayed_work retire_work; 642 643 /** 644 * Are we in a non-interruptible section of code like 645 * modesetting? 646 */ 647 bool interruptible; 648 649 /** 650 * Flag if the X Server, and thus DRM, is not currently in 651 * control of the device. 652 * 653 * This is set between LeaveVT and EnterVT. It needs to be 654 * replaced with a semaphore. It also needs to be 655 * transitioned away from for kernel modesetting. 656 */ 657 int suspended; 658 659 /** 660 * Flag if the hardware appears to be wedged. 661 * 662 * This is set when attempts to idle the device timeout. 663 * It prevents command submission from occurring and makes 664 * every pending request fail 665 */ 666 atomic_t wedged; 667 668 /** Bit 6 swizzling required for X tiling */ 669 uint32_t bit_6_swizzle_x; 670 /** Bit 6 swizzling required for Y tiling */ 671 uint32_t bit_6_swizzle_y; 672 673 /* storage for physical objects */ 674 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 675 676 /* accounting, useful for userland debugging */ 677 size_t gtt_total; 678 size_t mappable_gtt_total; 679 size_t object_memory; 680 u32 object_count; 681 } mm; 682 struct sdvo_device_mapping sdvo_mappings[2]; 683 /* indicate whether the LVDS_BORDER should be enabled or not */ 684 unsigned int lvds_border_bits; 685 /* Panel fitter placement and size for Ironlake+ */ 686 u32 pch_pf_pos, pch_pf_size; 687 688 struct drm_crtc *plane_to_crtc_mapping[3]; 689 struct drm_crtc *pipe_to_crtc_mapping[3]; 690 wait_queue_head_t pending_flip_queue; 691 bool flip_pending_is_done; 692 693 /* Reclocking support */ 694 bool render_reclock_avail; 695 bool lvds_downclock_avail; 696 /* indicates the reduced downclock for LVDS*/ 697 int lvds_downclock; 698 struct work_struct idle_work; 699 struct timer_list idle_timer; 700 bool busy; 701 u16 orig_clock; 702 int child_dev_num; 703 struct child_device_config *child_dev; 704 struct drm_connector *int_lvds_connector; 705 struct drm_connector *int_edp_connector; 706 707 bool mchbar_need_disable; 708 709 struct work_struct rps_work; 710 spinlock_t rps_lock; 711 u32 pm_iir; 712 713 u8 cur_delay; 714 u8 min_delay; 715 u8 max_delay; 716 u8 fmax; 717 u8 fstart; 718 719 u64 last_count1; 720 unsigned long last_time1; 721 unsigned long chipset_power; 722 u64 last_count2; 723 struct timespec last_time2; 724 unsigned long gfx_power; 725 int c_m; 726 int r_t; 727 u8 corr; 728 spinlock_t *mchdev_lock; 729 730 enum no_fbc_reason no_fbc_reason; 731 732 struct drm_mm_node *compressed_fb; 733 struct drm_mm_node *compressed_llb; 734 735 unsigned long last_gpu_reset; 736 737 /* list of fbdev register on this device */ 738 struct intel_fbdev *fbdev; 739 740 struct backlight_device *backlight; 741 742 struct drm_property *broadcast_rgb_property; 743 struct drm_property *force_audio_property; 744 745 atomic_t forcewake_count; 746 } drm_i915_private_t; 747 748 enum i915_cache_level { 749 I915_CACHE_NONE, 750 I915_CACHE_LLC, 751 I915_CACHE_LLC_MLC, /* gen6+ */ 752 }; 753 754 struct drm_i915_gem_object { 755 struct drm_gem_object base; 756 757 /** Current space allocated to this object in the GTT, if any. */ 758 struct drm_mm_node *gtt_space; 759 struct list_head gtt_list; 760 761 /** This object's place on the active/flushing/inactive lists */ 762 struct list_head ring_list; 763 struct list_head mm_list; 764 /** This object's place on GPU write list */ 765 struct list_head gpu_write_list; 766 /** This object's place in the batchbuffer or on the eviction list */ 767 struct list_head exec_list; 768 769 /** 770 * This is set if the object is on the active or flushing lists 771 * (has pending rendering), and is not set if it's on inactive (ready 772 * to be unbound). 773 */ 774 unsigned int active:1; 775 776 /** 777 * This is set if the object has been written to since last bound 778 * to the GTT 779 */ 780 unsigned int dirty:1; 781 782 /** 783 * This is set if the object has been written to since the last 784 * GPU flush. 785 */ 786 unsigned int pending_gpu_write:1; 787 788 /** 789 * Fence register bits (if any) for this object. Will be set 790 * as needed when mapped into the GTT. 791 * Protected by dev->struct_mutex. 792 */ 793 signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 794 795 /** 796 * Advice: are the backing pages purgeable? 797 */ 798 unsigned int madv:2; 799 800 /** 801 * Current tiling mode for the object. 802 */ 803 unsigned int tiling_mode:2; 804 unsigned int tiling_changed:1; 805 806 /** How many users have pinned this object in GTT space. The following 807 * users can each hold at most one reference: pwrite/pread, pin_ioctl 808 * (via user_pin_count), execbuffer (objects are not allowed multiple 809 * times for the same batchbuffer), and the framebuffer code. When 810 * switching/pageflipping, the framebuffer code has at most two buffers 811 * pinned per crtc. 812 * 813 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 814 * bits with absolutely no headroom. So use 4 bits. */ 815 unsigned int pin_count:4; 816 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 817 818 /** 819 * Is the object at the current location in the gtt mappable and 820 * fenceable? Used to avoid costly recalculations. 821 */ 822 unsigned int map_and_fenceable:1; 823 824 /** 825 * Whether the current gtt mapping needs to be mappable (and isn't just 826 * mappable by accident). Track pin and fault separate for a more 827 * accurate mappable working set. 828 */ 829 unsigned int fault_mappable:1; 830 unsigned int pin_mappable:1; 831 832 /* 833 * Is the GPU currently using a fence to access this buffer, 834 */ 835 unsigned int pending_fenced_gpu_access:1; 836 unsigned int fenced_gpu_access:1; 837 838 unsigned int cache_level:2; 839 840 struct page **pages; 841 842 /** 843 * DMAR support 844 */ 845 struct scatterlist *sg_list; 846 int num_sg; 847 848 /** 849 * Used for performing relocations during execbuffer insertion. 850 */ 851 struct hlist_node exec_node; 852 unsigned long exec_handle; 853 struct drm_i915_gem_exec_object2 *exec_entry; 854 855 /** 856 * Current offset of the object in GTT space. 857 * 858 * This is the same as gtt_space->start 859 */ 860 uint32_t gtt_offset; 861 862 /** Breadcrumb of last rendering to the buffer. */ 863 uint32_t last_rendering_seqno; 864 struct intel_ring_buffer *ring; 865 866 /** Breadcrumb of last fenced GPU access to the buffer. */ 867 uint32_t last_fenced_seqno; 868 struct intel_ring_buffer *last_fenced_ring; 869 870 /** Current tiling stride for the object, if it's tiled. */ 871 uint32_t stride; 872 873 /** Record of address bit 17 of each page at last unbind. */ 874 unsigned long *bit_17; 875 876 877 /** 878 * If present, while GEM_DOMAIN_CPU is in the read domain this array 879 * flags which individual pages are valid. 880 */ 881 uint8_t *page_cpu_valid; 882 883 /** User space pin count and filp owning the pin */ 884 uint32_t user_pin_count; 885 struct drm_file *pin_filp; 886 887 /** for phy allocated objects */ 888 struct drm_i915_gem_phys_object *phys_obj; 889 890 /** 891 * Number of crtcs where this object is currently the fb, but 892 * will be page flipped away on the next vblank. When it 893 * reaches 0, dev_priv->pending_flip_queue will be woken up. 894 */ 895 atomic_t pending_flip; 896 }; 897 898 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 899 900 /** 901 * Request queue structure. 902 * 903 * The request queue allows us to note sequence numbers that have been emitted 904 * and may be associated with active buffers to be retired. 905 * 906 * By keeping this list, we can avoid having to do questionable 907 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 908 * an emission time with seqnos for tracking how far ahead of the GPU we are. 909 */ 910 struct drm_i915_gem_request { 911 /** On Which ring this request was generated */ 912 struct intel_ring_buffer *ring; 913 914 /** GEM sequence number associated with this request. */ 915 uint32_t seqno; 916 917 /** Time at which this request was emitted, in jiffies. */ 918 unsigned long emitted_jiffies; 919 920 /** global list entry for this request */ 921 struct list_head list; 922 923 struct drm_i915_file_private *file_priv; 924 /** file_priv list entry for this request */ 925 struct list_head client_list; 926 }; 927 928 struct drm_i915_file_private { 929 struct { 930 struct spinlock lock; 931 struct list_head request_list; 932 } mm; 933 }; 934 935 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) 936 937 #define IS_I830(dev) ((dev)->pci_device == 0x3577) 938 #define IS_845G(dev) ((dev)->pci_device == 0x2562) 939 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 940 #define IS_I865G(dev) ((dev)->pci_device == 0x2572) 941 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 942 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 943 #define IS_I945G(dev) ((dev)->pci_device == 0x2772) 944 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 945 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 946 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 947 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 948 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 949 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) 950 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) 951 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 952 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 953 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) 954 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 955 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 956 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 957 958 /* 959 * The genX designation typically refers to the render engine, so render 960 * capability related checks should use IS_GEN, while display and other checks 961 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular 962 * chips, etc.). 963 */ 964 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 965 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 966 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 967 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 968 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 969 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 970 971 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) 972 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) 973 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 974 975 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 976 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 977 978 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 979 * rows, which changed the alignment requirements and fence programming. 980 */ 981 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 982 IS_I915GM(dev))) 983 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 984 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 985 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 986 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) 987 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 988 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 989 /* dsparb controlled by hw only */ 990 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 991 992 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 993 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 994 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 995 996 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) 997 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) 998 999 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) 1000 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1001 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 1002 1003 #include "i915_trace.h" 1004 1005 extern struct drm_ioctl_desc i915_ioctls[]; 1006 extern int i915_max_ioctl; 1007 extern unsigned int i915_fbpercrtc __always_unused; 1008 extern int i915_panel_ignore_lid __read_mostly; 1009 extern unsigned int i915_powersave __read_mostly; 1010 extern int i915_semaphores __read_mostly; 1011 extern unsigned int i915_lvds_downclock __read_mostly; 1012 extern int i915_panel_use_ssc __read_mostly; 1013 extern int i915_vbt_sdvo_panel_type __read_mostly; 1014 extern int i915_enable_rc6 __read_mostly; 1015 extern int i915_enable_fbc __read_mostly; 1016 extern bool i915_enable_hangcheck __read_mostly; 1017 1018 extern int i915_suspend(struct drm_device *dev, pm_message_t state); 1019 extern int i915_resume(struct drm_device *dev); 1020 extern int i915_master_create(struct drm_device *dev, struct drm_master *master); 1021 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 1022 1023 /* i915_dma.c */ 1024 extern void i915_kernel_lost_context(struct drm_device * dev); 1025 extern int i915_driver_load(struct drm_device *, unsigned long flags); 1026 extern int i915_driver_unload(struct drm_device *); 1027 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 1028 extern void i915_driver_lastclose(struct drm_device * dev); 1029 extern void i915_driver_preclose(struct drm_device *dev, 1030 struct drm_file *file_priv); 1031 extern void i915_driver_postclose(struct drm_device *dev, 1032 struct drm_file *file_priv); 1033 extern int i915_driver_device_is_agp(struct drm_device * dev); 1034 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 1035 unsigned long arg); 1036 extern int i915_emit_box(struct drm_device *dev, 1037 struct drm_clip_rect *box, 1038 int DR1, int DR4); 1039 extern int i915_reset(struct drm_device *dev, u8 flags); 1040 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 1041 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 1042 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 1043 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); 1044 1045 1046 /* i915_irq.c */ 1047 void i915_hangcheck_elapsed(unsigned long data); 1048 void i915_handle_error(struct drm_device *dev, bool wedged); 1049 extern int i915_irq_emit(struct drm_device *dev, void *data, 1050 struct drm_file *file_priv); 1051 extern int i915_irq_wait(struct drm_device *dev, void *data, 1052 struct drm_file *file_priv); 1053 1054 extern void intel_irq_init(struct drm_device *dev); 1055 1056 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, 1057 struct drm_file *file_priv); 1058 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, 1059 struct drm_file *file_priv); 1060 extern int i915_vblank_swap(struct drm_device *dev, void *data, 1061 struct drm_file *file_priv); 1062 1063 void 1064 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1065 1066 void 1067 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1068 1069 void intel_enable_asle(struct drm_device *dev); 1070 1071 #ifdef CONFIG_DEBUG_FS 1072 extern void i915_destroy_error_state(struct drm_device *dev); 1073 #else 1074 #define i915_destroy_error_state(x) 1075 #endif 1076 1077 1078 /* i915_mem.c */ 1079 extern int i915_mem_alloc(struct drm_device *dev, void *data, 1080 struct drm_file *file_priv); 1081 extern int i915_mem_free(struct drm_device *dev, void *data, 1082 struct drm_file *file_priv); 1083 extern int i915_mem_init_heap(struct drm_device *dev, void *data, 1084 struct drm_file *file_priv); 1085 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, 1086 struct drm_file *file_priv); 1087 extern void i915_mem_takedown(struct mem_block **heap); 1088 extern void i915_mem_release(struct drm_device * dev, 1089 struct drm_file *file_priv, struct mem_block *heap); 1090 /* i915_gem.c */ 1091 int i915_gem_init_ioctl(struct drm_device *dev, void *data, 1092 struct drm_file *file_priv); 1093 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 1094 struct drm_file *file_priv); 1095 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 1096 struct drm_file *file_priv); 1097 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1098 struct drm_file *file_priv); 1099 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 1100 struct drm_file *file_priv); 1101 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 1102 struct drm_file *file_priv); 1103 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1104 struct drm_file *file_priv); 1105 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 1106 struct drm_file *file_priv); 1107 int i915_gem_execbuffer(struct drm_device *dev, void *data, 1108 struct drm_file *file_priv); 1109 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 1110 struct drm_file *file_priv); 1111 int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 1112 struct drm_file *file_priv); 1113 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 1114 struct drm_file *file_priv); 1115 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 1116 struct drm_file *file_priv); 1117 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 1118 struct drm_file *file_priv); 1119 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 1120 struct drm_file *file_priv); 1121 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 1122 struct drm_file *file_priv); 1123 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 1124 struct drm_file *file_priv); 1125 int i915_gem_set_tiling(struct drm_device *dev, void *data, 1126 struct drm_file *file_priv); 1127 int i915_gem_get_tiling(struct drm_device *dev, void *data, 1128 struct drm_file *file_priv); 1129 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 1130 struct drm_file *file_priv); 1131 void i915_gem_load(struct drm_device *dev); 1132 int i915_gem_init_object(struct drm_gem_object *obj); 1133 int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring, 1134 uint32_t invalidate_domains, 1135 uint32_t flush_domains); 1136 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 1137 size_t size); 1138 void i915_gem_free_object(struct drm_gem_object *obj); 1139 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, 1140 uint32_t alignment, 1141 bool map_and_fenceable); 1142 void i915_gem_object_unpin(struct drm_i915_gem_object *obj); 1143 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); 1144 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 1145 void i915_gem_lastclose(struct drm_device *dev); 1146 1147 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); 1148 int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj); 1149 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, 1150 struct intel_ring_buffer *ring, 1151 u32 seqno); 1152 1153 int i915_gem_dumb_create(struct drm_file *file_priv, 1154 struct drm_device *dev, 1155 struct drm_mode_create_dumb *args); 1156 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 1157 uint32_t handle, uint64_t *offset); 1158 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, 1159 uint32_t handle); 1160 /** 1161 * Returns true if seq1 is later than seq2. 1162 */ 1163 static inline bool 1164 i915_seqno_passed(uint32_t seq1, uint32_t seq2) 1165 { 1166 return (int32_t)(seq1 - seq2) >= 0; 1167 } 1168 1169 static inline u32 1170 i915_gem_next_request_seqno(struct intel_ring_buffer *ring) 1171 { 1172 drm_i915_private_t *dev_priv = ring->dev->dev_private; 1173 return ring->outstanding_lazy_request = dev_priv->next_seqno; 1174 } 1175 1176 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj, 1177 struct intel_ring_buffer *pipelined); 1178 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 1179 1180 void i915_gem_retire_requests(struct drm_device *dev); 1181 void i915_gem_reset(struct drm_device *dev); 1182 void i915_gem_clflush_object(struct drm_i915_gem_object *obj); 1183 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, 1184 uint32_t read_domains, 1185 uint32_t write_domain); 1186 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 1187 int __must_check i915_gem_init_ringbuffer(struct drm_device *dev); 1188 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 1189 void i915_gem_do_init(struct drm_device *dev, 1190 unsigned long start, 1191 unsigned long mappable_end, 1192 unsigned long end); 1193 int __must_check i915_gpu_idle(struct drm_device *dev); 1194 int __must_check i915_gem_idle(struct drm_device *dev); 1195 int __must_check i915_add_request(struct intel_ring_buffer *ring, 1196 struct drm_file *file, 1197 struct drm_i915_gem_request *request); 1198 int __must_check i915_wait_request(struct intel_ring_buffer *ring, 1199 uint32_t seqno); 1200 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 1201 int __must_check 1202 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 1203 bool write); 1204 int __must_check 1205 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 1206 u32 alignment, 1207 struct intel_ring_buffer *pipelined); 1208 int i915_gem_attach_phys_object(struct drm_device *dev, 1209 struct drm_i915_gem_object *obj, 1210 int id, 1211 int align); 1212 void i915_gem_detach_phys_object(struct drm_device *dev, 1213 struct drm_i915_gem_object *obj); 1214 void i915_gem_free_all_phys_object(struct drm_device *dev); 1215 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 1216 1217 uint32_t 1218 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, 1219 uint32_t size, 1220 int tiling_mode); 1221 1222 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1223 enum i915_cache_level cache_level); 1224 1225 /* i915_gem_gtt.c */ 1226 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 1227 int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj); 1228 void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj, 1229 enum i915_cache_level cache_level); 1230 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); 1231 1232 /* i915_gem_evict.c */ 1233 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, 1234 unsigned alignment, bool mappable); 1235 int __must_check i915_gem_evict_everything(struct drm_device *dev, 1236 bool purgeable_only); 1237 int __must_check i915_gem_evict_inactive(struct drm_device *dev, 1238 bool purgeable_only); 1239 1240 /* i915_gem_tiling.c */ 1241 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 1242 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 1243 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 1244 1245 /* i915_gem_debug.c */ 1246 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, 1247 const char *where, uint32_t mark); 1248 #if WATCH_LISTS 1249 int i915_verify_lists(struct drm_device *dev); 1250 #else 1251 #define i915_verify_lists(dev) 0 1252 #endif 1253 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, 1254 int handle); 1255 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, 1256 const char *where, uint32_t mark); 1257 1258 /* i915_debugfs.c */ 1259 int i915_debugfs_init(struct drm_minor *minor); 1260 void i915_debugfs_cleanup(struct drm_minor *minor); 1261 1262 /* i915_suspend.c */ 1263 extern int i915_save_state(struct drm_device *dev); 1264 extern int i915_restore_state(struct drm_device *dev); 1265 1266 /* i915_suspend.c */ 1267 extern int i915_save_state(struct drm_device *dev); 1268 extern int i915_restore_state(struct drm_device *dev); 1269 1270 /* intel_i2c.c */ 1271 extern int intel_setup_gmbus(struct drm_device *dev); 1272 extern void intel_teardown_gmbus(struct drm_device *dev); 1273 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); 1274 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); 1275 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 1276 { 1277 return container_of(adapter, struct intel_gmbus, adapter)->force_bit; 1278 } 1279 extern void intel_i2c_reset(struct drm_device *dev); 1280 1281 /* intel_opregion.c */ 1282 extern int intel_opregion_setup(struct drm_device *dev); 1283 #ifdef CONFIG_ACPI 1284 extern void intel_opregion_init(struct drm_device *dev); 1285 extern void intel_opregion_fini(struct drm_device *dev); 1286 extern void intel_opregion_asle_intr(struct drm_device *dev); 1287 extern void intel_opregion_gse_intr(struct drm_device *dev); 1288 extern void intel_opregion_enable_asle(struct drm_device *dev); 1289 #else 1290 static inline void intel_opregion_init(struct drm_device *dev) { return; } 1291 static inline void intel_opregion_fini(struct drm_device *dev) { return; } 1292 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } 1293 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } 1294 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } 1295 #endif 1296 1297 /* intel_acpi.c */ 1298 #ifdef CONFIG_ACPI 1299 extern void intel_register_dsm_handler(void); 1300 extern void intel_unregister_dsm_handler(void); 1301 #else 1302 static inline void intel_register_dsm_handler(void) { return; } 1303 static inline void intel_unregister_dsm_handler(void) { return; } 1304 #endif /* CONFIG_ACPI */ 1305 1306 /* modesetting */ 1307 extern void intel_modeset_init(struct drm_device *dev); 1308 extern void intel_modeset_gem_init(struct drm_device *dev); 1309 extern void intel_modeset_cleanup(struct drm_device *dev); 1310 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 1311 extern bool intel_fbc_enabled(struct drm_device *dev); 1312 extern void intel_disable_fbc(struct drm_device *dev); 1313 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 1314 extern void ironlake_init_pch_refclk(struct drm_device *dev); 1315 extern void ironlake_enable_rc6(struct drm_device *dev); 1316 extern void gen6_set_rps(struct drm_device *dev, u8 val); 1317 extern void intel_detect_pch(struct drm_device *dev); 1318 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 1319 1320 extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1321 extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv); 1322 extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1323 extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv); 1324 1325 /* overlay */ 1326 #ifdef CONFIG_DEBUG_FS 1327 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); 1328 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); 1329 1330 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); 1331 extern void intel_display_print_error_state(struct seq_file *m, 1332 struct drm_device *dev, 1333 struct intel_display_error_state *error); 1334 #endif 1335 1336 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) 1337 1338 #define BEGIN_LP_RING(n) \ 1339 intel_ring_begin(LP_RING(dev_priv), (n)) 1340 1341 #define OUT_RING(x) \ 1342 intel_ring_emit(LP_RING(dev_priv), x) 1343 1344 #define ADVANCE_LP_RING() \ 1345 intel_ring_advance(LP_RING(dev_priv)) 1346 1347 /** 1348 * Lock test for when it's just for synchronization of ring access. 1349 * 1350 * In that case, we don't need to do it when GEM is initialized as nobody else 1351 * has access to the ring. 1352 */ 1353 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ 1354 if (LP_RING(dev->dev_private)->obj == NULL) \ 1355 LOCK_TEST_WITH_RETURN(dev, file); \ 1356 } while (0) 1357 1358 /* On SNB platform, before reading ring registers forcewake bit 1359 * must be set to prevent GT core from power down and stale values being 1360 * returned. 1361 */ 1362 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1363 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1364 void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); 1365 1366 /* We give fast paths for the really cool registers */ 1367 #define NEEDS_FORCE_WAKE(dev_priv, reg) \ 1368 (((dev_priv)->info->gen >= 6) && \ 1369 ((reg) < 0x40000) && \ 1370 ((reg) != FORCEWAKE)) 1371 1372 #define __i915_read(x, y) \ 1373 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); 1374 1375 __i915_read(8, b) 1376 __i915_read(16, w) 1377 __i915_read(32, l) 1378 __i915_read(64, q) 1379 #undef __i915_read 1380 1381 #define __i915_write(x, y) \ 1382 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); 1383 1384 __i915_write(8, b) 1385 __i915_write(16, w) 1386 __i915_write(32, l) 1387 __i915_write(64, q) 1388 #undef __i915_write 1389 1390 #define I915_READ8(reg) i915_read8(dev_priv, (reg)) 1391 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) 1392 1393 #define I915_READ16(reg) i915_read16(dev_priv, (reg)) 1394 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) 1395 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) 1396 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) 1397 1398 #define I915_READ(reg) i915_read32(dev_priv, (reg)) 1399 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) 1400 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) 1401 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) 1402 1403 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) 1404 #define I915_READ64(reg) i915_read64(dev_priv, (reg)) 1405 1406 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 1407 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 1408 1409 1410 #endif 1411