1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include "i915_reg.h" 34 #include "intel_bios.h" 35 #include "intel_ringbuffer.h" 36 #include <linux/io-mapping.h> 37 #include <linux/i2c.h> 38 #include <linux/i2c-algo-bit.h> 39 #include <drm/intel-gtt.h> 40 #include <linux/backlight.h> 41 #include <linux/intel-iommu.h> 42 #include <linux/kref.h> 43 44 /* General customization: 45 */ 46 47 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 48 49 #define DRIVER_NAME "i915" 50 #define DRIVER_DESC "Intel Graphics" 51 #define DRIVER_DATE "20080730" 52 53 enum pipe { 54 PIPE_A = 0, 55 PIPE_B, 56 PIPE_C, 57 I915_MAX_PIPES 58 }; 59 #define pipe_name(p) ((p) + 'A') 60 61 enum plane { 62 PLANE_A = 0, 63 PLANE_B, 64 PLANE_C, 65 }; 66 #define plane_name(p) ((p) + 'A') 67 68 enum port { 69 PORT_A = 0, 70 PORT_B, 71 PORT_C, 72 PORT_D, 73 PORT_E, 74 I915_MAX_PORTS 75 }; 76 #define port_name(p) ((p) + 'A') 77 78 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 79 80 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) 81 82 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 83 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 84 if ((intel_encoder)->base.crtc == (__crtc)) 85 86 struct intel_pch_pll { 87 int refcount; /* count of number of CRTCs sharing this PLL */ 88 int active; /* count of number of active CRTCs (i.e. DPMS on) */ 89 bool on; /* is the PLL actually active? Disabled during modeset */ 90 int pll_reg; 91 int fp0_reg; 92 int fp1_reg; 93 }; 94 #define I915_NUM_PLLS 2 95 96 /* Interface history: 97 * 98 * 1.1: Original. 99 * 1.2: Add Power Management 100 * 1.3: Add vblank support 101 * 1.4: Fix cmdbuffer path, add heap destroy 102 * 1.5: Add vblank pipe configuration 103 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 104 * - Support vertical blank on secondary display pipe 105 */ 106 #define DRIVER_MAJOR 1 107 #define DRIVER_MINOR 6 108 #define DRIVER_PATCHLEVEL 0 109 110 #define WATCH_COHERENCY 0 111 #define WATCH_LISTS 0 112 113 #define I915_GEM_PHYS_CURSOR_0 1 114 #define I915_GEM_PHYS_CURSOR_1 2 115 #define I915_GEM_PHYS_OVERLAY_REGS 3 116 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 117 118 struct drm_i915_gem_phys_object { 119 int id; 120 struct page **page_list; 121 drm_dma_handle_t *handle; 122 struct drm_i915_gem_object *cur_obj; 123 }; 124 125 struct mem_block { 126 struct mem_block *next; 127 struct mem_block *prev; 128 int start; 129 int size; 130 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 131 }; 132 133 struct opregion_header; 134 struct opregion_acpi; 135 struct opregion_swsci; 136 struct opregion_asle; 137 struct drm_i915_private; 138 139 struct intel_opregion { 140 struct opregion_header __iomem *header; 141 struct opregion_acpi __iomem *acpi; 142 struct opregion_swsci __iomem *swsci; 143 struct opregion_asle __iomem *asle; 144 void __iomem *vbt; 145 u32 __iomem *lid_state; 146 }; 147 #define OPREGION_SIZE (8*1024) 148 149 struct intel_overlay; 150 struct intel_overlay_error_state; 151 152 struct drm_i915_master_private { 153 drm_local_map_t *sarea; 154 struct _drm_i915_sarea *sarea_priv; 155 }; 156 #define I915_FENCE_REG_NONE -1 157 #define I915_MAX_NUM_FENCES 16 158 /* 16 fences + sign bit for FENCE_REG_NONE */ 159 #define I915_MAX_NUM_FENCE_BITS 5 160 161 struct drm_i915_fence_reg { 162 struct list_head lru_list; 163 struct drm_i915_gem_object *obj; 164 int pin_count; 165 }; 166 167 struct sdvo_device_mapping { 168 u8 initialized; 169 u8 dvo_port; 170 u8 slave_addr; 171 u8 dvo_wiring; 172 u8 i2c_pin; 173 u8 ddc_pin; 174 }; 175 176 struct intel_display_error_state; 177 178 struct drm_i915_error_state { 179 struct kref ref; 180 u32 eir; 181 u32 pgtbl_er; 182 u32 ier; 183 u32 ccid; 184 bool waiting[I915_NUM_RINGS]; 185 u32 pipestat[I915_MAX_PIPES]; 186 u32 tail[I915_NUM_RINGS]; 187 u32 head[I915_NUM_RINGS]; 188 u32 ipeir[I915_NUM_RINGS]; 189 u32 ipehr[I915_NUM_RINGS]; 190 u32 instdone[I915_NUM_RINGS]; 191 u32 acthd[I915_NUM_RINGS]; 192 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 193 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */ 194 /* our own tracking of ring head and tail */ 195 u32 cpu_ring_head[I915_NUM_RINGS]; 196 u32 cpu_ring_tail[I915_NUM_RINGS]; 197 u32 error; /* gen6+ */ 198 u32 instpm[I915_NUM_RINGS]; 199 u32 instps[I915_NUM_RINGS]; 200 u32 instdone1; 201 u32 seqno[I915_NUM_RINGS]; 202 u64 bbaddr; 203 u32 fault_reg[I915_NUM_RINGS]; 204 u32 done_reg; 205 u32 faddr[I915_NUM_RINGS]; 206 u64 fence[I915_MAX_NUM_FENCES]; 207 struct timeval time; 208 struct drm_i915_error_ring { 209 struct drm_i915_error_object { 210 int page_count; 211 u32 gtt_offset; 212 u32 *pages[0]; 213 } *ringbuffer, *batchbuffer; 214 struct drm_i915_error_request { 215 long jiffies; 216 u32 seqno; 217 u32 tail; 218 } *requests; 219 int num_requests; 220 } ring[I915_NUM_RINGS]; 221 struct drm_i915_error_buffer { 222 u32 size; 223 u32 name; 224 u32 seqno; 225 u32 gtt_offset; 226 u32 read_domains; 227 u32 write_domain; 228 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 229 s32 pinned:2; 230 u32 tiling:2; 231 u32 dirty:1; 232 u32 purgeable:1; 233 s32 ring:4; 234 u32 cache_level:2; 235 } *active_bo, *pinned_bo; 236 u32 active_bo_count, pinned_bo_count; 237 struct intel_overlay_error_state *overlay; 238 struct intel_display_error_state *display; 239 }; 240 241 struct drm_i915_display_funcs { 242 void (*dpms)(struct drm_crtc *crtc, int mode); 243 bool (*fbc_enabled)(struct drm_device *dev); 244 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); 245 void (*disable_fbc)(struct drm_device *dev); 246 int (*get_display_clock_speed)(struct drm_device *dev); 247 int (*get_fifo_size)(struct drm_device *dev, int plane); 248 void (*update_wm)(struct drm_device *dev); 249 void (*update_sprite_wm)(struct drm_device *dev, int pipe, 250 uint32_t sprite_width, int pixel_size); 251 void (*sanitize_pm)(struct drm_device *dev); 252 void (*update_linetime_wm)(struct drm_device *dev, int pipe, 253 struct drm_display_mode *mode); 254 int (*crtc_mode_set)(struct drm_crtc *crtc, 255 struct drm_display_mode *mode, 256 struct drm_display_mode *adjusted_mode, 257 int x, int y, 258 struct drm_framebuffer *old_fb); 259 void (*off)(struct drm_crtc *crtc); 260 void (*write_eld)(struct drm_connector *connector, 261 struct drm_crtc *crtc); 262 void (*fdi_link_train)(struct drm_crtc *crtc); 263 void (*init_clock_gating)(struct drm_device *dev); 264 void (*init_pch_clock_gating)(struct drm_device *dev); 265 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 266 struct drm_framebuffer *fb, 267 struct drm_i915_gem_object *obj); 268 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, 269 int x, int y); 270 /* clock updates for mode set */ 271 /* cursor updates */ 272 /* render clock increase/decrease */ 273 /* display clock increase/decrease */ 274 /* pll clock increase/decrease */ 275 }; 276 277 struct drm_i915_gt_funcs { 278 void (*force_wake_get)(struct drm_i915_private *dev_priv); 279 void (*force_wake_put)(struct drm_i915_private *dev_priv); 280 }; 281 282 struct intel_device_info { 283 u8 gen; 284 u8 is_mobile:1; 285 u8 is_i85x:1; 286 u8 is_i915g:1; 287 u8 is_i945gm:1; 288 u8 is_g33:1; 289 u8 need_gfx_hws:1; 290 u8 is_g4x:1; 291 u8 is_pineview:1; 292 u8 is_broadwater:1; 293 u8 is_crestline:1; 294 u8 is_ivybridge:1; 295 u8 is_valleyview:1; 296 u8 has_force_wake:1; 297 u8 is_haswell:1; 298 u8 has_fbc:1; 299 u8 has_pipe_cxsr:1; 300 u8 has_hotplug:1; 301 u8 cursor_needs_physical:1; 302 u8 has_overlay:1; 303 u8 overlay_needs_physical:1; 304 u8 supports_tv:1; 305 u8 has_bsd_ring:1; 306 u8 has_blt_ring:1; 307 u8 has_llc:1; 308 }; 309 310 #define I915_PPGTT_PD_ENTRIES 512 311 #define I915_PPGTT_PT_ENTRIES 1024 312 struct i915_hw_ppgtt { 313 unsigned num_pd_entries; 314 struct page **pt_pages; 315 uint32_t pd_offset; 316 dma_addr_t *pt_dma_addr; 317 dma_addr_t scratch_page_dma_addr; 318 }; 319 320 321 /* This must match up with the value previously used for execbuf2.rsvd1. */ 322 #define DEFAULT_CONTEXT_ID 0 323 struct i915_hw_context { 324 int id; 325 bool is_initialized; 326 struct drm_i915_file_private *file_priv; 327 struct intel_ring_buffer *ring; 328 struct drm_i915_gem_object *obj; 329 }; 330 331 enum no_fbc_reason { 332 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 333 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ 334 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 335 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 336 FBC_BAD_PLANE, /* fbc not supported on plane */ 337 FBC_NOT_TILED, /* buffer not tiled */ 338 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 339 FBC_MODULE_PARAM, 340 }; 341 342 enum intel_pch { 343 PCH_NONE = 0, /* No PCH present */ 344 PCH_IBX, /* Ibexpeak PCH */ 345 PCH_CPT, /* Cougarpoint PCH */ 346 PCH_LPT, /* Lynxpoint PCH */ 347 }; 348 349 #define QUIRK_PIPEA_FORCE (1<<0) 350 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 351 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 352 353 struct intel_fbdev; 354 struct intel_fbc_work; 355 356 struct intel_gmbus { 357 struct i2c_adapter adapter; 358 bool force_bit; 359 u32 reg0; 360 u32 gpio_reg; 361 struct i2c_algo_bit_data bit_algo; 362 struct drm_i915_private *dev_priv; 363 }; 364 365 typedef struct drm_i915_private { 366 struct drm_device *dev; 367 368 const struct intel_device_info *info; 369 370 int relative_constants_mode; 371 372 void __iomem *regs; 373 374 struct drm_i915_gt_funcs gt; 375 /** gt_fifo_count and the subsequent register write are synchronized 376 * with dev->struct_mutex. */ 377 unsigned gt_fifo_count; 378 /** forcewake_count is protected by gt_lock */ 379 unsigned forcewake_count; 380 /** gt_lock is also taken in irq contexts. */ 381 struct spinlock gt_lock; 382 383 struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; 384 385 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 386 * controller on different i2c buses. */ 387 struct mutex gmbus_mutex; 388 389 /** 390 * Base address of the gmbus and gpio block. 391 */ 392 uint32_t gpio_mmio_base; 393 394 struct pci_dev *bridge_dev; 395 struct intel_ring_buffer ring[I915_NUM_RINGS]; 396 uint32_t next_seqno; 397 398 drm_dma_handle_t *status_page_dmah; 399 uint32_t counter; 400 struct drm_i915_gem_object *pwrctx; 401 struct drm_i915_gem_object *renderctx; 402 403 struct resource mch_res; 404 405 unsigned int cpp; 406 int back_offset; 407 int front_offset; 408 int current_page; 409 int page_flipping; 410 411 atomic_t irq_received; 412 413 /* protects the irq masks */ 414 spinlock_t irq_lock; 415 416 /* DPIO indirect register protection */ 417 spinlock_t dpio_lock; 418 419 /** Cached value of IMR to avoid reads in updating the bitfield */ 420 u32 pipestat[2]; 421 u32 irq_mask; 422 u32 gt_irq_mask; 423 u32 pch_irq_mask; 424 425 u32 hotplug_supported_mask; 426 struct work_struct hotplug_work; 427 428 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 429 int num_pipe; 430 int num_pch_pll; 431 432 /* For hangcheck timer */ 433 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ 434 struct timer_list hangcheck_timer; 435 int hangcheck_count; 436 uint32_t last_acthd[I915_NUM_RINGS]; 437 uint32_t last_instdone; 438 uint32_t last_instdone1; 439 440 unsigned int stop_rings; 441 442 unsigned long cfb_size; 443 unsigned int cfb_fb; 444 enum plane cfb_plane; 445 int cfb_y; 446 struct intel_fbc_work *fbc_work; 447 448 struct intel_opregion opregion; 449 450 /* overlay */ 451 struct intel_overlay *overlay; 452 bool sprite_scaling_enabled; 453 454 /* LVDS info */ 455 int backlight_level; /* restore backlight to this value */ 456 bool backlight_enabled; 457 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 458 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 459 460 /* Feature bits from the VBIOS */ 461 unsigned int int_tv_support:1; 462 unsigned int lvds_dither:1; 463 unsigned int lvds_vbt:1; 464 unsigned int int_crt_support:1; 465 unsigned int lvds_use_ssc:1; 466 unsigned int display_clock_mode:1; 467 int lvds_ssc_freq; 468 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 469 unsigned int lvds_val; /* used for checking LVDS channel mode */ 470 struct { 471 int rate; 472 int lanes; 473 int preemphasis; 474 int vswing; 475 476 bool initialized; 477 bool support; 478 int bpp; 479 struct edp_power_seq pps; 480 } edp; 481 bool no_aux_handshake; 482 483 struct notifier_block lid_notifier; 484 485 int crt_ddc_pin; 486 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 487 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 488 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 489 490 unsigned int fsb_freq, mem_freq, is_ddr3; 491 492 spinlock_t error_lock; 493 /* Protected by dev->error_lock. */ 494 struct drm_i915_error_state *first_error; 495 struct work_struct error_work; 496 struct completion error_completion; 497 struct workqueue_struct *wq; 498 499 /* Display functions */ 500 struct drm_i915_display_funcs display; 501 502 /* PCH chipset type */ 503 enum intel_pch pch_type; 504 505 unsigned long quirks; 506 507 /* Register state */ 508 bool modeset_on_lid; 509 u8 saveLBB; 510 u32 saveDSPACNTR; 511 u32 saveDSPBCNTR; 512 u32 saveDSPARB; 513 u32 saveHWS; 514 u32 savePIPEACONF; 515 u32 savePIPEBCONF; 516 u32 savePIPEASRC; 517 u32 savePIPEBSRC; 518 u32 saveFPA0; 519 u32 saveFPA1; 520 u32 saveDPLL_A; 521 u32 saveDPLL_A_MD; 522 u32 saveHTOTAL_A; 523 u32 saveHBLANK_A; 524 u32 saveHSYNC_A; 525 u32 saveVTOTAL_A; 526 u32 saveVBLANK_A; 527 u32 saveVSYNC_A; 528 u32 saveBCLRPAT_A; 529 u32 saveTRANSACONF; 530 u32 saveTRANS_HTOTAL_A; 531 u32 saveTRANS_HBLANK_A; 532 u32 saveTRANS_HSYNC_A; 533 u32 saveTRANS_VTOTAL_A; 534 u32 saveTRANS_VBLANK_A; 535 u32 saveTRANS_VSYNC_A; 536 u32 savePIPEASTAT; 537 u32 saveDSPASTRIDE; 538 u32 saveDSPASIZE; 539 u32 saveDSPAPOS; 540 u32 saveDSPAADDR; 541 u32 saveDSPASURF; 542 u32 saveDSPATILEOFF; 543 u32 savePFIT_PGM_RATIOS; 544 u32 saveBLC_HIST_CTL; 545 u32 saveBLC_PWM_CTL; 546 u32 saveBLC_PWM_CTL2; 547 u32 saveBLC_CPU_PWM_CTL; 548 u32 saveBLC_CPU_PWM_CTL2; 549 u32 saveFPB0; 550 u32 saveFPB1; 551 u32 saveDPLL_B; 552 u32 saveDPLL_B_MD; 553 u32 saveHTOTAL_B; 554 u32 saveHBLANK_B; 555 u32 saveHSYNC_B; 556 u32 saveVTOTAL_B; 557 u32 saveVBLANK_B; 558 u32 saveVSYNC_B; 559 u32 saveBCLRPAT_B; 560 u32 saveTRANSBCONF; 561 u32 saveTRANS_HTOTAL_B; 562 u32 saveTRANS_HBLANK_B; 563 u32 saveTRANS_HSYNC_B; 564 u32 saveTRANS_VTOTAL_B; 565 u32 saveTRANS_VBLANK_B; 566 u32 saveTRANS_VSYNC_B; 567 u32 savePIPEBSTAT; 568 u32 saveDSPBSTRIDE; 569 u32 saveDSPBSIZE; 570 u32 saveDSPBPOS; 571 u32 saveDSPBADDR; 572 u32 saveDSPBSURF; 573 u32 saveDSPBTILEOFF; 574 u32 saveVGA0; 575 u32 saveVGA1; 576 u32 saveVGA_PD; 577 u32 saveVGACNTRL; 578 u32 saveADPA; 579 u32 saveLVDS; 580 u32 savePP_ON_DELAYS; 581 u32 savePP_OFF_DELAYS; 582 u32 saveDVOA; 583 u32 saveDVOB; 584 u32 saveDVOC; 585 u32 savePP_ON; 586 u32 savePP_OFF; 587 u32 savePP_CONTROL; 588 u32 savePP_DIVISOR; 589 u32 savePFIT_CONTROL; 590 u32 save_palette_a[256]; 591 u32 save_palette_b[256]; 592 u32 saveDPFC_CB_BASE; 593 u32 saveFBC_CFB_BASE; 594 u32 saveFBC_LL_BASE; 595 u32 saveFBC_CONTROL; 596 u32 saveFBC_CONTROL2; 597 u32 saveIER; 598 u32 saveIIR; 599 u32 saveIMR; 600 u32 saveDEIER; 601 u32 saveDEIMR; 602 u32 saveGTIER; 603 u32 saveGTIMR; 604 u32 saveFDI_RXA_IMR; 605 u32 saveFDI_RXB_IMR; 606 u32 saveCACHE_MODE_0; 607 u32 saveMI_ARB_STATE; 608 u32 saveSWF0[16]; 609 u32 saveSWF1[16]; 610 u32 saveSWF2[3]; 611 u8 saveMSR; 612 u8 saveSR[8]; 613 u8 saveGR[25]; 614 u8 saveAR_INDEX; 615 u8 saveAR[21]; 616 u8 saveDACMASK; 617 u8 saveCR[37]; 618 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 619 u32 saveCURACNTR; 620 u32 saveCURAPOS; 621 u32 saveCURABASE; 622 u32 saveCURBCNTR; 623 u32 saveCURBPOS; 624 u32 saveCURBBASE; 625 u32 saveCURSIZE; 626 u32 saveDP_B; 627 u32 saveDP_C; 628 u32 saveDP_D; 629 u32 savePIPEA_GMCH_DATA_M; 630 u32 savePIPEB_GMCH_DATA_M; 631 u32 savePIPEA_GMCH_DATA_N; 632 u32 savePIPEB_GMCH_DATA_N; 633 u32 savePIPEA_DP_LINK_M; 634 u32 savePIPEB_DP_LINK_M; 635 u32 savePIPEA_DP_LINK_N; 636 u32 savePIPEB_DP_LINK_N; 637 u32 saveFDI_RXA_CTL; 638 u32 saveFDI_TXA_CTL; 639 u32 saveFDI_RXB_CTL; 640 u32 saveFDI_TXB_CTL; 641 u32 savePFA_CTL_1; 642 u32 savePFB_CTL_1; 643 u32 savePFA_WIN_SZ; 644 u32 savePFB_WIN_SZ; 645 u32 savePFA_WIN_POS; 646 u32 savePFB_WIN_POS; 647 u32 savePCH_DREF_CONTROL; 648 u32 saveDISP_ARB_CTL; 649 u32 savePIPEA_DATA_M1; 650 u32 savePIPEA_DATA_N1; 651 u32 savePIPEA_LINK_M1; 652 u32 savePIPEA_LINK_N1; 653 u32 savePIPEB_DATA_M1; 654 u32 savePIPEB_DATA_N1; 655 u32 savePIPEB_LINK_M1; 656 u32 savePIPEB_LINK_N1; 657 u32 saveMCHBAR_RENDER_STANDBY; 658 u32 savePCH_PORT_HOTPLUG; 659 660 struct { 661 /** Bridge to intel-gtt-ko */ 662 const struct intel_gtt *gtt; 663 /** Memory allocator for GTT stolen memory */ 664 struct drm_mm stolen; 665 /** Memory allocator for GTT */ 666 struct drm_mm gtt_space; 667 /** List of all objects in gtt_space. Used to restore gtt 668 * mappings on resume */ 669 struct list_head gtt_list; 670 671 /** Usable portion of the GTT for GEM */ 672 unsigned long gtt_start; 673 unsigned long gtt_mappable_end; 674 unsigned long gtt_end; 675 676 struct io_mapping *gtt_mapping; 677 phys_addr_t gtt_base_addr; 678 int gtt_mtrr; 679 680 /** PPGTT used for aliasing the PPGTT with the GTT */ 681 struct i915_hw_ppgtt *aliasing_ppgtt; 682 683 u32 *l3_remap_info; 684 685 struct shrinker inactive_shrinker; 686 687 /** 688 * List of objects currently involved in rendering. 689 * 690 * Includes buffers having the contents of their GPU caches 691 * flushed, not necessarily primitives. last_rendering_seqno 692 * represents when the rendering involved will be completed. 693 * 694 * A reference is held on the buffer while on this list. 695 */ 696 struct list_head active_list; 697 698 /** 699 * List of objects which are not in the ringbuffer but which 700 * still have a write_domain which needs to be flushed before 701 * unbinding. 702 * 703 * last_rendering_seqno is 0 while an object is in this list. 704 * 705 * A reference is held on the buffer while on this list. 706 */ 707 struct list_head flushing_list; 708 709 /** 710 * LRU list of objects which are not in the ringbuffer and 711 * are ready to unbind, but are still in the GTT. 712 * 713 * last_rendering_seqno is 0 while an object is in this list. 714 * 715 * A reference is not held on the buffer while on this list, 716 * as merely being GTT-bound shouldn't prevent its being 717 * freed, and we'll pull it off the list in the free path. 718 */ 719 struct list_head inactive_list; 720 721 /** LRU list of objects with fence regs on them. */ 722 struct list_head fence_list; 723 724 /** 725 * We leave the user IRQ off as much as possible, 726 * but this means that requests will finish and never 727 * be retired once the system goes idle. Set a timer to 728 * fire periodically while the ring is running. When it 729 * fires, go retire requests. 730 */ 731 struct delayed_work retire_work; 732 733 /** 734 * Are we in a non-interruptible section of code like 735 * modesetting? 736 */ 737 bool interruptible; 738 739 /** 740 * Flag if the X Server, and thus DRM, is not currently in 741 * control of the device. 742 * 743 * This is set between LeaveVT and EnterVT. It needs to be 744 * replaced with a semaphore. It also needs to be 745 * transitioned away from for kernel modesetting. 746 */ 747 int suspended; 748 749 /** 750 * Flag if the hardware appears to be wedged. 751 * 752 * This is set when attempts to idle the device timeout. 753 * It prevents command submission from occurring and makes 754 * every pending request fail 755 */ 756 atomic_t wedged; 757 758 /** Bit 6 swizzling required for X tiling */ 759 uint32_t bit_6_swizzle_x; 760 /** Bit 6 swizzling required for Y tiling */ 761 uint32_t bit_6_swizzle_y; 762 763 /* storage for physical objects */ 764 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 765 766 /* accounting, useful for userland debugging */ 767 size_t gtt_total; 768 size_t mappable_gtt_total; 769 size_t object_memory; 770 u32 object_count; 771 } mm; 772 773 /* Old dri1 support infrastructure, beware the dragons ya fools entering 774 * here! */ 775 struct { 776 unsigned allow_batchbuffer : 1; 777 u32 __iomem *gfx_hws_cpu_addr; 778 } dri1; 779 780 /* Kernel Modesetting */ 781 782 struct sdvo_device_mapping sdvo_mappings[2]; 783 /* indicate whether the LVDS_BORDER should be enabled or not */ 784 unsigned int lvds_border_bits; 785 /* Panel fitter placement and size for Ironlake+ */ 786 u32 pch_pf_pos, pch_pf_size; 787 788 struct drm_crtc *plane_to_crtc_mapping[3]; 789 struct drm_crtc *pipe_to_crtc_mapping[3]; 790 wait_queue_head_t pending_flip_queue; 791 792 struct intel_pch_pll pch_plls[I915_NUM_PLLS]; 793 794 /* Reclocking support */ 795 bool render_reclock_avail; 796 bool lvds_downclock_avail; 797 /* indicates the reduced downclock for LVDS*/ 798 int lvds_downclock; 799 struct work_struct idle_work; 800 struct timer_list idle_timer; 801 bool busy; 802 u16 orig_clock; 803 int child_dev_num; 804 struct child_device_config *child_dev; 805 struct drm_connector *int_lvds_connector; 806 struct drm_connector *int_edp_connector; 807 808 bool mchbar_need_disable; 809 810 struct work_struct rps_work; 811 spinlock_t rps_lock; 812 u32 pm_iir; 813 814 u8 cur_delay; 815 u8 min_delay; 816 u8 max_delay; 817 u8 fmax; 818 u8 fstart; 819 820 u64 last_count1; 821 unsigned long last_time1; 822 unsigned long chipset_power; 823 u64 last_count2; 824 struct timespec last_time2; 825 unsigned long gfx_power; 826 int c_m; 827 int r_t; 828 u8 corr; 829 spinlock_t *mchdev_lock; 830 831 enum no_fbc_reason no_fbc_reason; 832 833 struct drm_mm_node *compressed_fb; 834 struct drm_mm_node *compressed_llb; 835 836 unsigned long last_gpu_reset; 837 838 /* list of fbdev register on this device */ 839 struct intel_fbdev *fbdev; 840 841 struct backlight_device *backlight; 842 843 struct drm_property *broadcast_rgb_property; 844 struct drm_property *force_audio_property; 845 846 struct work_struct parity_error_work; 847 bool hw_contexts_disabled; 848 uint32_t hw_context_size; 849 } drm_i915_private_t; 850 851 /* Iterate over initialised rings */ 852 #define for_each_ring(ring__, dev_priv__, i__) \ 853 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ 854 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) 855 856 enum hdmi_force_audio { 857 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 858 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 859 HDMI_AUDIO_AUTO, /* trust EDID */ 860 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 861 }; 862 863 enum i915_cache_level { 864 I915_CACHE_NONE, 865 I915_CACHE_LLC, 866 I915_CACHE_LLC_MLC, /* gen6+ */ 867 }; 868 869 struct drm_i915_gem_object { 870 struct drm_gem_object base; 871 872 /** Current space allocated to this object in the GTT, if any. */ 873 struct drm_mm_node *gtt_space; 874 struct list_head gtt_list; 875 876 /** This object's place on the active/flushing/inactive lists */ 877 struct list_head ring_list; 878 struct list_head mm_list; 879 /** This object's place on GPU write list */ 880 struct list_head gpu_write_list; 881 /** This object's place in the batchbuffer or on the eviction list */ 882 struct list_head exec_list; 883 884 /** 885 * This is set if the object is on the active or flushing lists 886 * (has pending rendering), and is not set if it's on inactive (ready 887 * to be unbound). 888 */ 889 unsigned int active:1; 890 891 /** 892 * This is set if the object has been written to since last bound 893 * to the GTT 894 */ 895 unsigned int dirty:1; 896 897 /** 898 * This is set if the object has been written to since the last 899 * GPU flush. 900 */ 901 unsigned int pending_gpu_write:1; 902 903 /** 904 * Fence register bits (if any) for this object. Will be set 905 * as needed when mapped into the GTT. 906 * Protected by dev->struct_mutex. 907 */ 908 signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 909 910 /** 911 * Advice: are the backing pages purgeable? 912 */ 913 unsigned int madv:2; 914 915 /** 916 * Current tiling mode for the object. 917 */ 918 unsigned int tiling_mode:2; 919 /** 920 * Whether the tiling parameters for the currently associated fence 921 * register have changed. Note that for the purposes of tracking 922 * tiling changes we also treat the unfenced register, the register 923 * slot that the object occupies whilst it executes a fenced 924 * command (such as BLT on gen2/3), as a "fence". 925 */ 926 unsigned int fence_dirty:1; 927 928 /** How many users have pinned this object in GTT space. The following 929 * users can each hold at most one reference: pwrite/pread, pin_ioctl 930 * (via user_pin_count), execbuffer (objects are not allowed multiple 931 * times for the same batchbuffer), and the framebuffer code. When 932 * switching/pageflipping, the framebuffer code has at most two buffers 933 * pinned per crtc. 934 * 935 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 936 * bits with absolutely no headroom. So use 4 bits. */ 937 unsigned int pin_count:4; 938 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 939 940 /** 941 * Is the object at the current location in the gtt mappable and 942 * fenceable? Used to avoid costly recalculations. 943 */ 944 unsigned int map_and_fenceable:1; 945 946 /** 947 * Whether the current gtt mapping needs to be mappable (and isn't just 948 * mappable by accident). Track pin and fault separate for a more 949 * accurate mappable working set. 950 */ 951 unsigned int fault_mappable:1; 952 unsigned int pin_mappable:1; 953 954 /* 955 * Is the GPU currently using a fence to access this buffer, 956 */ 957 unsigned int pending_fenced_gpu_access:1; 958 unsigned int fenced_gpu_access:1; 959 960 unsigned int cache_level:2; 961 962 unsigned int has_aliasing_ppgtt_mapping:1; 963 unsigned int has_global_gtt_mapping:1; 964 965 struct page **pages; 966 967 /** 968 * DMAR support 969 */ 970 struct scatterlist *sg_list; 971 int num_sg; 972 973 /* prime dma-buf support */ 974 struct sg_table *sg_table; 975 void *dma_buf_vmapping; 976 int vmapping_count; 977 978 /** 979 * Used for performing relocations during execbuffer insertion. 980 */ 981 struct hlist_node exec_node; 982 unsigned long exec_handle; 983 struct drm_i915_gem_exec_object2 *exec_entry; 984 985 /** 986 * Current offset of the object in GTT space. 987 * 988 * This is the same as gtt_space->start 989 */ 990 uint32_t gtt_offset; 991 992 struct intel_ring_buffer *ring; 993 994 /** Breadcrumb of last rendering to the buffer. */ 995 uint32_t last_rendering_seqno; 996 /** Breadcrumb of last fenced GPU access to the buffer. */ 997 uint32_t last_fenced_seqno; 998 999 /** Current tiling stride for the object, if it's tiled. */ 1000 uint32_t stride; 1001 1002 /** Record of address bit 17 of each page at last unbind. */ 1003 unsigned long *bit_17; 1004 1005 /** User space pin count and filp owning the pin */ 1006 uint32_t user_pin_count; 1007 struct drm_file *pin_filp; 1008 1009 /** for phy allocated objects */ 1010 struct drm_i915_gem_phys_object *phys_obj; 1011 1012 /** 1013 * Number of crtcs where this object is currently the fb, but 1014 * will be page flipped away on the next vblank. When it 1015 * reaches 0, dev_priv->pending_flip_queue will be woken up. 1016 */ 1017 atomic_t pending_flip; 1018 }; 1019 1020 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 1021 1022 /** 1023 * Request queue structure. 1024 * 1025 * The request queue allows us to note sequence numbers that have been emitted 1026 * and may be associated with active buffers to be retired. 1027 * 1028 * By keeping this list, we can avoid having to do questionable 1029 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 1030 * an emission time with seqnos for tracking how far ahead of the GPU we are. 1031 */ 1032 struct drm_i915_gem_request { 1033 /** On Which ring this request was generated */ 1034 struct intel_ring_buffer *ring; 1035 1036 /** GEM sequence number associated with this request. */ 1037 uint32_t seqno; 1038 1039 /** Postion in the ringbuffer of the end of the request */ 1040 u32 tail; 1041 1042 /** Time at which this request was emitted, in jiffies. */ 1043 unsigned long emitted_jiffies; 1044 1045 /** global list entry for this request */ 1046 struct list_head list; 1047 1048 struct drm_i915_file_private *file_priv; 1049 /** file_priv list entry for this request */ 1050 struct list_head client_list; 1051 }; 1052 1053 struct drm_i915_file_private { 1054 struct { 1055 struct spinlock lock; 1056 struct list_head request_list; 1057 } mm; 1058 struct idr context_idr; 1059 }; 1060 1061 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) 1062 1063 #define IS_I830(dev) ((dev)->pci_device == 0x3577) 1064 #define IS_845G(dev) ((dev)->pci_device == 0x2562) 1065 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 1066 #define IS_I865G(dev) ((dev)->pci_device == 0x2572) 1067 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1068 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 1069 #define IS_I945G(dev) ((dev)->pci_device == 0x2772) 1070 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 1071 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 1072 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 1073 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 1074 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 1075 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) 1076 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) 1077 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 1078 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 1079 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) 1080 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 1081 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 1082 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) 1083 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) 1084 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1085 1086 /* 1087 * The genX designation typically refers to the render engine, so render 1088 * capability related checks should use IS_GEN, while display and other checks 1089 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular 1090 * chips, etc.). 1091 */ 1092 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 1093 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 1094 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 1095 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 1096 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 1097 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 1098 1099 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) 1100 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) 1101 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 1102 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1103 1104 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) 1105 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev)) 1106 1107 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 1108 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 1109 1110 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1111 * rows, which changed the alignment requirements and fence programming. 1112 */ 1113 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 1114 IS_I915GM(dev))) 1115 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 1116 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1117 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1118 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) 1119 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 1120 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 1121 /* dsparb controlled by hw only */ 1122 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 1123 1124 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 1125 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 1126 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 1127 1128 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) 1129 1130 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) 1131 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) 1132 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1133 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 1134 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) 1135 1136 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake) 1137 1138 #include "i915_trace.h" 1139 1140 /** 1141 * RC6 is a special power stage which allows the GPU to enter an very 1142 * low-voltage mode when idle, using down to 0V while at this stage. This 1143 * stage is entered automatically when the GPU is idle when RC6 support is 1144 * enabled, and as soon as new workload arises GPU wakes up automatically as well. 1145 * 1146 * There are different RC6 modes available in Intel GPU, which differentiate 1147 * among each other with the latency required to enter and leave RC6 and 1148 * voltage consumed by the GPU in different states. 1149 * 1150 * The combination of the following flags define which states GPU is allowed 1151 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 1152 * RC6pp is deepest RC6. Their support by hardware varies according to the 1153 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 1154 * which brings the most power savings; deeper states save more power, but 1155 * require higher latency to switch to and wake up. 1156 */ 1157 #define INTEL_RC6_ENABLE (1<<0) 1158 #define INTEL_RC6p_ENABLE (1<<1) 1159 #define INTEL_RC6pp_ENABLE (1<<2) 1160 1161 extern struct drm_ioctl_desc i915_ioctls[]; 1162 extern int i915_max_ioctl; 1163 extern unsigned int i915_fbpercrtc __always_unused; 1164 extern int i915_panel_ignore_lid __read_mostly; 1165 extern unsigned int i915_powersave __read_mostly; 1166 extern int i915_semaphores __read_mostly; 1167 extern unsigned int i915_lvds_downclock __read_mostly; 1168 extern int i915_lvds_channel_mode __read_mostly; 1169 extern int i915_panel_use_ssc __read_mostly; 1170 extern int i915_vbt_sdvo_panel_type __read_mostly; 1171 extern int i915_enable_rc6 __read_mostly; 1172 extern int i915_enable_fbc __read_mostly; 1173 extern bool i915_enable_hangcheck __read_mostly; 1174 extern int i915_enable_ppgtt __read_mostly; 1175 1176 extern int i915_suspend(struct drm_device *dev, pm_message_t state); 1177 extern int i915_resume(struct drm_device *dev); 1178 extern int i915_master_create(struct drm_device *dev, struct drm_master *master); 1179 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 1180 1181 /* i915_dma.c */ 1182 void i915_update_dri1_breadcrumb(struct drm_device *dev); 1183 extern void i915_kernel_lost_context(struct drm_device * dev); 1184 extern int i915_driver_load(struct drm_device *, unsigned long flags); 1185 extern int i915_driver_unload(struct drm_device *); 1186 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 1187 extern void i915_driver_lastclose(struct drm_device * dev); 1188 extern void i915_driver_preclose(struct drm_device *dev, 1189 struct drm_file *file_priv); 1190 extern void i915_driver_postclose(struct drm_device *dev, 1191 struct drm_file *file_priv); 1192 extern int i915_driver_device_is_agp(struct drm_device * dev); 1193 #ifdef CONFIG_COMPAT 1194 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 1195 unsigned long arg); 1196 #endif 1197 extern int i915_emit_box(struct drm_device *dev, 1198 struct drm_clip_rect *box, 1199 int DR1, int DR4); 1200 extern int intel_gpu_reset(struct drm_device *dev); 1201 extern int i915_reset(struct drm_device *dev); 1202 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 1203 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 1204 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 1205 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); 1206 1207 1208 /* i915_irq.c */ 1209 void i915_hangcheck_elapsed(unsigned long data); 1210 void i915_handle_error(struct drm_device *dev, bool wedged); 1211 1212 extern void intel_irq_init(struct drm_device *dev); 1213 extern void intel_gt_init(struct drm_device *dev); 1214 1215 void i915_error_state_free(struct kref *error_ref); 1216 1217 void 1218 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1219 1220 void 1221 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1222 1223 void intel_enable_asle(struct drm_device *dev); 1224 1225 #ifdef CONFIG_DEBUG_FS 1226 extern void i915_destroy_error_state(struct drm_device *dev); 1227 #else 1228 #define i915_destroy_error_state(x) 1229 #endif 1230 1231 1232 /* i915_gem.c */ 1233 int i915_gem_init_ioctl(struct drm_device *dev, void *data, 1234 struct drm_file *file_priv); 1235 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 1236 struct drm_file *file_priv); 1237 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 1238 struct drm_file *file_priv); 1239 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1240 struct drm_file *file_priv); 1241 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 1242 struct drm_file *file_priv); 1243 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 1244 struct drm_file *file_priv); 1245 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1246 struct drm_file *file_priv); 1247 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 1248 struct drm_file *file_priv); 1249 int i915_gem_execbuffer(struct drm_device *dev, void *data, 1250 struct drm_file *file_priv); 1251 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 1252 struct drm_file *file_priv); 1253 int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 1254 struct drm_file *file_priv); 1255 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 1256 struct drm_file *file_priv); 1257 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 1258 struct drm_file *file_priv); 1259 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 1260 struct drm_file *file_priv); 1261 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 1262 struct drm_file *file_priv); 1263 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 1264 struct drm_file *file_priv); 1265 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 1266 struct drm_file *file_priv); 1267 int i915_gem_set_tiling(struct drm_device *dev, void *data, 1268 struct drm_file *file_priv); 1269 int i915_gem_get_tiling(struct drm_device *dev, void *data, 1270 struct drm_file *file_priv); 1271 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 1272 struct drm_file *file_priv); 1273 int i915_gem_wait_ioctl(struct drm_device *dev, void *data, 1274 struct drm_file *file_priv); 1275 void i915_gem_load(struct drm_device *dev); 1276 int i915_gem_init_object(struct drm_gem_object *obj); 1277 int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring, 1278 uint32_t invalidate_domains, 1279 uint32_t flush_domains); 1280 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 1281 size_t size); 1282 void i915_gem_free_object(struct drm_gem_object *obj); 1283 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, 1284 uint32_t alignment, 1285 bool map_and_fenceable); 1286 void i915_gem_object_unpin(struct drm_i915_gem_object *obj); 1287 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); 1288 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 1289 void i915_gem_lastclose(struct drm_device *dev); 1290 1291 int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, 1292 gfp_t gfpmask); 1293 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); 1294 int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj); 1295 int i915_gem_object_sync(struct drm_i915_gem_object *obj, 1296 struct intel_ring_buffer *to); 1297 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, 1298 struct intel_ring_buffer *ring, 1299 u32 seqno); 1300 1301 int i915_gem_dumb_create(struct drm_file *file_priv, 1302 struct drm_device *dev, 1303 struct drm_mode_create_dumb *args); 1304 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 1305 uint32_t handle, uint64_t *offset); 1306 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, 1307 uint32_t handle); 1308 /** 1309 * Returns true if seq1 is later than seq2. 1310 */ 1311 static inline bool 1312 i915_seqno_passed(uint32_t seq1, uint32_t seq2) 1313 { 1314 return (int32_t)(seq1 - seq2) >= 0; 1315 } 1316 1317 u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring); 1318 1319 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); 1320 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 1321 1322 static inline bool 1323 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) 1324 { 1325 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1326 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1327 dev_priv->fence_regs[obj->fence_reg].pin_count++; 1328 return true; 1329 } else 1330 return false; 1331 } 1332 1333 static inline void 1334 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) 1335 { 1336 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1337 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1338 dev_priv->fence_regs[obj->fence_reg].pin_count--; 1339 } 1340 } 1341 1342 void i915_gem_retire_requests(struct drm_device *dev); 1343 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); 1344 int __must_check i915_gem_check_wedge(struct drm_i915_private *dev_priv, 1345 bool interruptible); 1346 1347 void i915_gem_reset(struct drm_device *dev); 1348 void i915_gem_clflush_object(struct drm_i915_gem_object *obj); 1349 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, 1350 uint32_t read_domains, 1351 uint32_t write_domain); 1352 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 1353 int __must_check i915_gem_init(struct drm_device *dev); 1354 int __must_check i915_gem_init_hw(struct drm_device *dev); 1355 void i915_gem_l3_remap(struct drm_device *dev); 1356 void i915_gem_init_swizzling(struct drm_device *dev); 1357 void i915_gem_init_ppgtt(struct drm_device *dev); 1358 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 1359 int __must_check i915_gpu_idle(struct drm_device *dev); 1360 int __must_check i915_gem_idle(struct drm_device *dev); 1361 int __must_check i915_add_request(struct intel_ring_buffer *ring, 1362 struct drm_file *file, 1363 struct drm_i915_gem_request *request); 1364 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, 1365 uint32_t seqno); 1366 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 1367 int __must_check 1368 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 1369 bool write); 1370 int __must_check 1371 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); 1372 int __must_check 1373 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 1374 u32 alignment, 1375 struct intel_ring_buffer *pipelined); 1376 int i915_gem_attach_phys_object(struct drm_device *dev, 1377 struct drm_i915_gem_object *obj, 1378 int id, 1379 int align); 1380 void i915_gem_detach_phys_object(struct drm_device *dev, 1381 struct drm_i915_gem_object *obj); 1382 void i915_gem_free_all_phys_object(struct drm_device *dev); 1383 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 1384 1385 uint32_t 1386 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, 1387 uint32_t size, 1388 int tiling_mode); 1389 1390 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1391 enum i915_cache_level cache_level); 1392 1393 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 1394 struct dma_buf *dma_buf); 1395 1396 struct dma_buf *i915_gem_prime_export(struct drm_device *dev, 1397 struct drm_gem_object *gem_obj, int flags); 1398 1399 /* i915_gem_context.c */ 1400 void i915_gem_context_init(struct drm_device *dev); 1401 void i915_gem_context_fini(struct drm_device *dev); 1402 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); 1403 int i915_switch_context(struct intel_ring_buffer *ring, 1404 struct drm_file *file, int to_id); 1405 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 1406 struct drm_file *file); 1407 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, 1408 struct drm_file *file); 1409 1410 /* i915_gem_gtt.c */ 1411 int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev); 1412 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); 1413 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, 1414 struct drm_i915_gem_object *obj, 1415 enum i915_cache_level cache_level); 1416 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, 1417 struct drm_i915_gem_object *obj); 1418 1419 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 1420 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); 1421 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, 1422 enum i915_cache_level cache_level); 1423 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); 1424 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); 1425 void i915_gem_init_global_gtt(struct drm_device *dev, 1426 unsigned long start, 1427 unsigned long mappable_end, 1428 unsigned long end); 1429 1430 /* i915_gem_evict.c */ 1431 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, 1432 unsigned alignment, bool mappable); 1433 int i915_gem_evict_everything(struct drm_device *dev, bool purgeable_only); 1434 1435 /* i915_gem_stolen.c */ 1436 int i915_gem_init_stolen(struct drm_device *dev); 1437 void i915_gem_cleanup_stolen(struct drm_device *dev); 1438 1439 /* i915_gem_tiling.c */ 1440 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 1441 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 1442 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 1443 1444 /* i915_gem_debug.c */ 1445 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, 1446 const char *where, uint32_t mark); 1447 #if WATCH_LISTS 1448 int i915_verify_lists(struct drm_device *dev); 1449 #else 1450 #define i915_verify_lists(dev) 0 1451 #endif 1452 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, 1453 int handle); 1454 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, 1455 const char *where, uint32_t mark); 1456 1457 /* i915_debugfs.c */ 1458 int i915_debugfs_init(struct drm_minor *minor); 1459 void i915_debugfs_cleanup(struct drm_minor *minor); 1460 1461 /* i915_suspend.c */ 1462 extern int i915_save_state(struct drm_device *dev); 1463 extern int i915_restore_state(struct drm_device *dev); 1464 1465 /* i915_suspend.c */ 1466 extern int i915_save_state(struct drm_device *dev); 1467 extern int i915_restore_state(struct drm_device *dev); 1468 1469 /* i915_sysfs.c */ 1470 void i915_setup_sysfs(struct drm_device *dev_priv); 1471 void i915_teardown_sysfs(struct drm_device *dev_priv); 1472 1473 /* intel_i2c.c */ 1474 extern int intel_setup_gmbus(struct drm_device *dev); 1475 extern void intel_teardown_gmbus(struct drm_device *dev); 1476 extern inline bool intel_gmbus_is_port_valid(unsigned port) 1477 { 1478 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); 1479 } 1480 1481 extern struct i2c_adapter *intel_gmbus_get_adapter( 1482 struct drm_i915_private *dev_priv, unsigned port); 1483 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); 1484 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); 1485 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 1486 { 1487 return container_of(adapter, struct intel_gmbus, adapter)->force_bit; 1488 } 1489 extern void intel_i2c_reset(struct drm_device *dev); 1490 1491 /* intel_opregion.c */ 1492 extern int intel_opregion_setup(struct drm_device *dev); 1493 #ifdef CONFIG_ACPI 1494 extern void intel_opregion_init(struct drm_device *dev); 1495 extern void intel_opregion_fini(struct drm_device *dev); 1496 extern void intel_opregion_asle_intr(struct drm_device *dev); 1497 extern void intel_opregion_gse_intr(struct drm_device *dev); 1498 extern void intel_opregion_enable_asle(struct drm_device *dev); 1499 #else 1500 static inline void intel_opregion_init(struct drm_device *dev) { return; } 1501 static inline void intel_opregion_fini(struct drm_device *dev) { return; } 1502 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } 1503 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } 1504 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } 1505 #endif 1506 1507 /* intel_acpi.c */ 1508 #ifdef CONFIG_ACPI 1509 extern void intel_register_dsm_handler(void); 1510 extern void intel_unregister_dsm_handler(void); 1511 #else 1512 static inline void intel_register_dsm_handler(void) { return; } 1513 static inline void intel_unregister_dsm_handler(void) { return; } 1514 #endif /* CONFIG_ACPI */ 1515 1516 /* modesetting */ 1517 extern void intel_modeset_init_hw(struct drm_device *dev); 1518 extern void intel_modeset_init(struct drm_device *dev); 1519 extern void intel_modeset_gem_init(struct drm_device *dev); 1520 extern void intel_modeset_cleanup(struct drm_device *dev); 1521 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 1522 extern bool intel_fbc_enabled(struct drm_device *dev); 1523 extern void intel_disable_fbc(struct drm_device *dev); 1524 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 1525 extern void ironlake_init_pch_refclk(struct drm_device *dev); 1526 extern void gen6_set_rps(struct drm_device *dev, u8 val); 1527 extern void intel_detect_pch(struct drm_device *dev); 1528 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 1529 extern int intel_enable_rc6(const struct drm_device *dev); 1530 1531 extern bool i915_semaphore_is_enabled(struct drm_device *dev); 1532 1533 /* overlay */ 1534 #ifdef CONFIG_DEBUG_FS 1535 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); 1536 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); 1537 1538 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); 1539 extern void intel_display_print_error_state(struct seq_file *m, 1540 struct drm_device *dev, 1541 struct intel_display_error_state *error); 1542 #endif 1543 1544 /* On SNB platform, before reading ring registers forcewake bit 1545 * must be set to prevent GT core from power down and stale values being 1546 * returned. 1547 */ 1548 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1549 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1550 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); 1551 1552 #define __i915_read(x, y) \ 1553 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); 1554 1555 __i915_read(8, b) 1556 __i915_read(16, w) 1557 __i915_read(32, l) 1558 __i915_read(64, q) 1559 #undef __i915_read 1560 1561 #define __i915_write(x, y) \ 1562 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); 1563 1564 __i915_write(8, b) 1565 __i915_write(16, w) 1566 __i915_write(32, l) 1567 __i915_write(64, q) 1568 #undef __i915_write 1569 1570 #define I915_READ8(reg) i915_read8(dev_priv, (reg)) 1571 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) 1572 1573 #define I915_READ16(reg) i915_read16(dev_priv, (reg)) 1574 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) 1575 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) 1576 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) 1577 1578 #define I915_READ(reg) i915_read32(dev_priv, (reg)) 1579 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) 1580 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) 1581 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) 1582 1583 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) 1584 #define I915_READ64(reg) i915_read64(dev_priv, (reg)) 1585 1586 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 1587 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 1588 1589 1590 #endif 1591