1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 35 #include <linux/pci.h> 36 #include <linux/pm_qos.h> 37 38 #include <drm/ttm/ttm_device.h> 39 40 #include "gem/i915_gem_context_types.h" 41 #include "gem/i915_gem_shrinker.h" 42 #include "gem/i915_gem_stolen.h" 43 44 #include "gt/intel_engine.h" 45 #include "gt/intel_gt_types.h" 46 #include "gt/intel_region_lmem.h" 47 #include "gt/intel_workarounds.h" 48 #include "gt/uc/intel_uc.h" 49 50 #include "i915_drm_client.h" 51 #include "i915_gem.h" 52 #include "i915_gpu_error.h" 53 #include "i915_params.h" 54 #include "i915_perf_types.h" 55 #include "i915_scheduler.h" 56 #include "i915_utils.h" 57 #include "intel_device_info.h" 58 #include "intel_memory_region.h" 59 #include "intel_runtime_pm.h" 60 #include "intel_step.h" 61 #include "intel_uncore.h" 62 63 struct dram_info; 64 struct drm_i915_clock_gating_funcs; 65 struct intel_display; 66 struct intel_pxp; 67 struct vlv_s0ix_state; 68 69 /* Data Stolen Memory (DSM) aka "i915 stolen memory" */ 70 struct i915_dsm { 71 /* 72 * The start and end of DSM which we can optionally use to create GEM 73 * objects backed by stolen memory. 74 * 75 * Note that usable_size tells us exactly how much of this we are 76 * actually allowed to use, given that some portion of it is in fact 77 * reserved for use by hardware functions. 78 */ 79 struct resource stolen; 80 81 /* 82 * Reserved portion of DSM. 83 */ 84 struct resource reserved; 85 86 /* 87 * Total size minus reserved ranges. 88 * 89 * DSM is segmented in hardware with different portions offlimits to 90 * certain functions. 91 * 92 * The drm_mm is initialised to the total accessible range, as found 93 * from the PCI config. On Broadwell+, this is further restricted to 94 * avoid the first page! The upper end of DSM is reserved for hardware 95 * functions and similarly removed from the accessible range. 96 */ 97 resource_size_t usable_size; 98 }; 99 100 #define MAX_L3_SLICES 2 101 struct intel_l3_parity { 102 u32 *remap_info[MAX_L3_SLICES]; 103 struct work_struct error_work; 104 int which_slice; 105 }; 106 107 struct i915_gem_mm { 108 /* 109 * Shortcut for the stolen region. This points to either 110 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or 111 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't 112 * support stolen. 113 */ 114 struct intel_memory_region *stolen_region; 115 /** Memory allocator for GTT stolen memory */ 116 struct drm_mm stolen; 117 /** Protects the usage of the GTT stolen memory allocator. This is 118 * always the inner lock when overlapping with struct_mutex. */ 119 struct mutex stolen_lock; 120 121 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ 122 spinlock_t obj_lock; 123 124 /** 125 * List of objects which are purgeable. 126 */ 127 struct list_head purge_list; 128 129 /** 130 * List of objects which have allocated pages and are shrinkable. 131 */ 132 struct list_head shrink_list; 133 134 /** 135 * List of objects which are pending destruction. 136 */ 137 struct llist_head free_list; 138 struct work_struct free_work; 139 /** 140 * Count of objects pending destructions. Used to skip needlessly 141 * waiting on an RCU barrier if no objects are waiting to be freed. 142 */ 143 atomic_t free_count; 144 145 /** 146 * tmpfs instance used for shmem backed objects 147 */ 148 struct vfsmount *gemfs; 149 150 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN]; 151 152 struct notifier_block oom_notifier; 153 struct notifier_block vmap_notifier; 154 struct shrinker *shrinker; 155 156 /* shrinker accounting, also useful for userland debugging */ 157 u64 shrink_memory; 158 u32 shrink_count; 159 }; 160 161 struct i915_virtual_gpu { 162 struct mutex lock; /* serialises sending of g2v_notify command pkts */ 163 bool active; 164 u32 caps; 165 u32 *initial_mmio; 166 u8 *initial_cfg_space; 167 struct list_head entry; 168 }; 169 170 struct i915_selftest_stash { 171 atomic_t counter; 172 struct ida mock_region_instances; 173 }; 174 175 struct drm_i915_private { 176 struct drm_device drm; 177 178 struct intel_display *display; 179 180 /* FIXME: Device release actions should all be moved to drmm_ */ 181 bool do_release; 182 183 /* i915 device parameters */ 184 struct i915_params params; 185 186 const struct intel_device_info *__info; /* Use INTEL_INFO() to access. */ 187 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ 188 struct intel_driver_caps caps; 189 190 struct i915_dsm dsm; 191 192 struct intel_uncore uncore; 193 struct intel_uncore_mmio_debug mmio_debug; 194 195 struct i915_virtual_gpu vgpu; 196 197 struct intel_gvt *gvt; 198 199 struct { 200 struct pci_dev *pdev; 201 struct resource mch_res; 202 bool mchbar_need_disable; 203 } gmch; 204 205 /* 206 * Chaining user engines happens in multiple stages, starting with a 207 * simple lock-less linked list created by intel_engine_add_user(), 208 * which later gets sorted and converted to an intermediate regular 209 * list, just to be converted once again to its final rb tree structure 210 * in intel_engines_driver_register(). 211 * 212 * Make sure to use the right iterator helper, depending on if the code 213 * in question runs before or after intel_engines_driver_register() -- 214 * for_each_uabi_engine() can only be used afterwards! 215 */ 216 union { 217 struct llist_head uabi_engines_llist; 218 struct list_head uabi_engines_list; 219 struct rb_root uabi_engines; 220 }; 221 unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1]; 222 223 bool irqs_enabled; 224 225 /* VLV/CHV IOSF sideband */ 226 struct { 227 struct mutex lock; /* protect sideband access */ 228 unsigned long locked_unit_mask; 229 struct pm_qos_request qos; 230 } vlv_iosf_sb; 231 232 /* Sideband mailbox protection */ 233 struct mutex sb_lock; 234 235 /** Cached value of IMR to avoid reads in updating the bitfield */ 236 u32 irq_mask; 237 238 bool preserve_bios_swizzle; 239 240 unsigned int fsb_freq, mem_freq, is_ddr3; 241 242 unsigned int hpll_freq; 243 unsigned int czclk_freq; 244 245 /** 246 * wq - Driver workqueue for GEM. 247 * 248 * NOTE: Work items scheduled here are not allowed to grab any modeset 249 * locks, for otherwise the flushing done in the pageflip code will 250 * result in deadlocks. 251 */ 252 struct workqueue_struct *wq; 253 254 /** 255 * unordered_wq - internal workqueue for unordered work 256 * 257 * This workqueue should be used for all unordered work 258 * scheduling within i915, which used to be scheduled on the 259 * system_wq before moving to a driver instance due 260 * deprecation of flush_scheduled_work(). 261 */ 262 struct workqueue_struct *unordered_wq; 263 264 /* pm private clock gating functions */ 265 const struct drm_i915_clock_gating_funcs *clock_gating_funcs; 266 267 unsigned long gem_quirks; 268 269 struct i915_gem_mm mm; 270 271 struct intel_l3_parity l3_parity; 272 273 /* 274 * edram size in MB. 275 * Cannot be determined by PCIID. You must always read a register. 276 */ 277 u32 edram_size_mb; 278 279 struct i915_gpu_error gpu_error; 280 281 u32 suspend_count; 282 struct vlv_s0ix_state *vlv_s0ix_state; 283 284 const struct dram_info *dram_info; 285 286 struct intel_runtime_pm runtime_pm; 287 288 struct i915_perf perf; 289 290 struct i915_hwmon *hwmon; 291 292 struct intel_gt *gt[I915_MAX_GT]; 293 294 struct kobject *sysfs_gt; 295 296 /* Quick lookup of media GT (current platforms only have one) */ 297 struct intel_gt *media_gt; 298 299 struct { 300 struct i915_gem_contexts { 301 spinlock_t lock; /* locks list */ 302 struct list_head list; 303 } contexts; 304 305 /* 306 * We replace the local file with a global mappings as the 307 * backing storage for the mmap is on the device and not 308 * on the struct file, and we do not want to prolong the 309 * lifetime of the local fd. To minimise the number of 310 * anonymous inodes we create, we use a global singleton to 311 * share the global mapping. 312 */ 313 struct file *mmap_singleton; 314 } gem; 315 316 struct intel_pxp *pxp; 317 318 struct i915_pmu pmu; 319 320 /* The TTM device structure. */ 321 struct ttm_device bdev; 322 323 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;) 324 325 /* 326 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 327 * will be rejected. Instead look for a better place. 328 */ 329 }; 330 331 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 332 { 333 return container_of(dev, struct drm_i915_private, drm); 334 } 335 336 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) 337 { 338 struct drm_device *drm = dev_get_drvdata(kdev); 339 340 return drm ? to_i915(drm) : NULL; 341 } 342 343 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) 344 { 345 struct drm_device *drm = pci_get_drvdata(pdev); 346 347 return drm ? to_i915(drm) : NULL; 348 } 349 350 static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) 351 { 352 return i915->gt[0]; 353 } 354 355 #define INTEL_INFO(i915) ((i915)->__info) 356 #define RUNTIME_INFO(i915) (&(i915)->__runtime) 357 #define DRIVER_CAPS(i915) (&(i915)->caps) 358 359 #define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id) 360 361 #define IP_VER(ver, rel) ((ver) << 8 | (rel)) 362 363 #define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver) 364 #define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \ 365 RUNTIME_INFO(i915)->graphics.ip.rel) 366 #define IS_GRAPHICS_VER(i915, from, until) \ 367 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until)) 368 369 #define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver) 370 #define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \ 371 RUNTIME_INFO(i915)->media.ip.rel) 372 #define IS_MEDIA_VER(i915, from, until) \ 373 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until)) 374 375 #define INTEL_REVID(i915) (to_pci_dev((i915)->drm.dev)->revision) 376 377 #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step) 378 #define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step) 379 380 #define IS_GRAPHICS_STEP(__i915, since, until) \ 381 (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \ 382 INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until)) 383 384 #define IS_MEDIA_STEP(__i915, since, until) \ 385 (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \ 386 INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until)) 387 388 static __always_inline unsigned int 389 __platform_mask_index(const struct intel_runtime_info *info, 390 enum intel_platform p) 391 { 392 const unsigned int pbits = 393 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 394 395 /* Expand the platform_mask array if this fails. */ 396 BUILD_BUG_ON(INTEL_MAX_PLATFORMS > 397 pbits * ARRAY_SIZE(info->platform_mask)); 398 399 return p / pbits; 400 } 401 402 static __always_inline unsigned int 403 __platform_mask_bit(const struct intel_runtime_info *info, 404 enum intel_platform p) 405 { 406 const unsigned int pbits = 407 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 408 409 return p % pbits + INTEL_SUBPLATFORM_BITS; 410 } 411 412 static inline u32 413 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p) 414 { 415 const unsigned int pi = __platform_mask_index(info, p); 416 417 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK; 418 } 419 420 static __always_inline bool 421 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p) 422 { 423 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 424 const unsigned int pi = __platform_mask_index(info, p); 425 const unsigned int pb = __platform_mask_bit(info, p); 426 427 BUILD_BUG_ON(!__builtin_constant_p(p)); 428 429 return info->platform_mask[pi] & BIT(pb); 430 } 431 432 static __always_inline bool 433 IS_SUBPLATFORM(const struct drm_i915_private *i915, 434 enum intel_platform p, unsigned int s) 435 { 436 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 437 const unsigned int pi = __platform_mask_index(info, p); 438 const unsigned int pb = __platform_mask_bit(info, p); 439 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1; 440 const u32 mask = info->platform_mask[pi]; 441 442 BUILD_BUG_ON(!__builtin_constant_p(p)); 443 BUILD_BUG_ON(!__builtin_constant_p(s)); 444 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS); 445 446 /* Shift and test on the MSB position so sign flag can be used. */ 447 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); 448 } 449 450 #define IS_MOBILE(i915) (INTEL_INFO(i915)->is_mobile) 451 #define IS_DGFX(i915) (INTEL_INFO(i915)->is_dgfx) 452 453 #define IS_I830(i915) IS_PLATFORM(i915, INTEL_I830) 454 #define IS_I845G(i915) IS_PLATFORM(i915, INTEL_I845G) 455 #define IS_I85X(i915) IS_PLATFORM(i915, INTEL_I85X) 456 #define IS_I865G(i915) IS_PLATFORM(i915, INTEL_I865G) 457 #define IS_I915G(i915) IS_PLATFORM(i915, INTEL_I915G) 458 #define IS_I915GM(i915) IS_PLATFORM(i915, INTEL_I915GM) 459 #define IS_I945G(i915) IS_PLATFORM(i915, INTEL_I945G) 460 #define IS_I945GM(i915) IS_PLATFORM(i915, INTEL_I945GM) 461 #define IS_I965G(i915) IS_PLATFORM(i915, INTEL_I965G) 462 #define IS_I965GM(i915) IS_PLATFORM(i915, INTEL_I965GM) 463 #define IS_G45(i915) IS_PLATFORM(i915, INTEL_G45) 464 #define IS_GM45(i915) IS_PLATFORM(i915, INTEL_GM45) 465 #define IS_G4X(i915) (IS_G45(i915) || IS_GM45(i915)) 466 #define IS_PINEVIEW(i915) IS_PLATFORM(i915, INTEL_PINEVIEW) 467 #define IS_G33(i915) IS_PLATFORM(i915, INTEL_G33) 468 #define IS_IRONLAKE(i915) IS_PLATFORM(i915, INTEL_IRONLAKE) 469 #define IS_IRONLAKE_M(i915) \ 470 (IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915)) 471 #define IS_SANDYBRIDGE(i915) IS_PLATFORM(i915, INTEL_SANDYBRIDGE) 472 #define IS_IVYBRIDGE(i915) IS_PLATFORM(i915, INTEL_IVYBRIDGE) 473 #define IS_VALLEYVIEW(i915) IS_PLATFORM(i915, INTEL_VALLEYVIEW) 474 #define IS_CHERRYVIEW(i915) IS_PLATFORM(i915, INTEL_CHERRYVIEW) 475 #define IS_HASWELL(i915) IS_PLATFORM(i915, INTEL_HASWELL) 476 #define IS_BROADWELL(i915) IS_PLATFORM(i915, INTEL_BROADWELL) 477 #define IS_SKYLAKE(i915) IS_PLATFORM(i915, INTEL_SKYLAKE) 478 #define IS_BROXTON(i915) IS_PLATFORM(i915, INTEL_BROXTON) 479 #define IS_KABYLAKE(i915) IS_PLATFORM(i915, INTEL_KABYLAKE) 480 #define IS_GEMINILAKE(i915) IS_PLATFORM(i915, INTEL_GEMINILAKE) 481 #define IS_COFFEELAKE(i915) IS_PLATFORM(i915, INTEL_COFFEELAKE) 482 #define IS_COMETLAKE(i915) IS_PLATFORM(i915, INTEL_COMETLAKE) 483 #define IS_ICELAKE(i915) IS_PLATFORM(i915, INTEL_ICELAKE) 484 #define IS_JASPERLAKE(i915) IS_PLATFORM(i915, INTEL_JASPERLAKE) 485 #define IS_ELKHARTLAKE(i915) IS_PLATFORM(i915, INTEL_ELKHARTLAKE) 486 #define IS_TIGERLAKE(i915) IS_PLATFORM(i915, INTEL_TIGERLAKE) 487 #define IS_ROCKETLAKE(i915) IS_PLATFORM(i915, INTEL_ROCKETLAKE) 488 #define IS_DG1(i915) IS_PLATFORM(i915, INTEL_DG1) 489 #define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S) 490 #define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P) 491 #define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2) 492 #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE) 493 /* 494 * Display code shared by i915 and Xe relies on macros like IS_LUNARLAKE, 495 * so we need to define these even on platforms that the i915 base driver 496 * doesn't support. Ensure the parameter is used in the definition to 497 * avoid 'unused variable' warnings when compiling the shared display code 498 * for i915. 499 */ 500 #define IS_LUNARLAKE(i915) (0 && i915) 501 #define IS_BATTLEMAGE(i915) (0 && i915) 502 #define IS_PANTHERLAKE(i915) (0 && i915) 503 504 #define IS_ARROWLAKE_H(i915) \ 505 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_H) 506 #define IS_ARROWLAKE_U(i915) \ 507 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_U) 508 #define IS_ARROWLAKE_S(i915) \ 509 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_S) 510 #define IS_DG2_G10(i915) \ 511 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10) 512 #define IS_DG2_G11(i915) \ 513 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11) 514 #define IS_DG2_G12(i915) \ 515 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12) 516 #define IS_DG2_D(i915) \ 517 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_D) 518 #define IS_RAPTORLAKE_S(i915) \ 519 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL) 520 #define IS_ALDERLAKE_P_N(i915) \ 521 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N) 522 #define IS_RAPTORLAKE_P(i915) \ 523 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL) 524 #define IS_RAPTORLAKE_U(i915) \ 525 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU) 526 #define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \ 527 (INTEL_DEVID(i915) & 0xFF00) == 0x0C00) 528 #define IS_BROADWELL_ULT(i915) \ 529 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) 530 #define IS_BROADWELL_ULX(i915) \ 531 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX) 532 #define IS_HASWELL_ULT(i915) \ 533 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) 534 /* ULX machines are also considered ULT. */ 535 #define IS_HASWELL_ULX(i915) \ 536 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) 537 #define IS_SKYLAKE_ULT(i915) \ 538 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) 539 #define IS_SKYLAKE_ULX(i915) \ 540 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) 541 #define IS_KABYLAKE_ULT(i915) \ 542 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) 543 #define IS_KABYLAKE_ULX(i915) \ 544 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) 545 #define IS_COFFEELAKE_ULT(i915) \ 546 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) 547 #define IS_COFFEELAKE_ULX(i915) \ 548 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX) 549 #define IS_COMETLAKE_ULT(i915) \ 550 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT) 551 #define IS_COMETLAKE_ULX(i915) \ 552 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX) 553 554 #define IS_ICL_WITH_PORT_F(i915) \ 555 IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) 556 557 #define IS_TIGERLAKE_UY(i915) \ 558 IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY) 559 560 #define IS_GEN9_LP(i915) (IS_BROXTON(i915) || IS_GEMINILAKE(i915)) 561 #define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_GEN9_LP(i915)) 562 563 #define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode) 564 565 /* 566 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution 567 * All later gens can run the final buffer from the ppgtt 568 */ 569 #define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7) 570 571 #define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc) 572 #define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop) 573 #define HAS_EDRAM(i915) ((i915)->edram_size_mb) 574 #define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6) 575 #define HAS_WT(i915) HAS_EDRAM(i915) 576 577 #define HWS_NEEDS_PHYSICAL(i915) (INTEL_INFO(i915)->hws_needs_physical) 578 579 #define HAS_LOGICAL_RING_CONTEXTS(i915) \ 580 (INTEL_INFO(i915)->has_logical_ring_contexts) 581 #define HAS_LOGICAL_RING_ELSQ(i915) \ 582 (INTEL_INFO(i915)->has_logical_ring_elsq) 583 584 #define HAS_EXECLISTS(i915) HAS_LOGICAL_RING_CONTEXTS(i915) 585 586 #define INTEL_PPGTT(i915) (RUNTIME_INFO(i915)->ppgtt_type) 587 #define HAS_PPGTT(i915) \ 588 (INTEL_PPGTT(i915) != INTEL_PPGTT_NONE) 589 #define HAS_FULL_PPGTT(i915) \ 590 (INTEL_PPGTT(i915) >= INTEL_PPGTT_FULL) 591 592 #define HAS_PAGE_SIZES(i915, sizes) ({ \ 593 GEM_BUG_ON((sizes) == 0); \ 594 ((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \ 595 }) 596 597 #define NEEDS_RC6_CTX_CORRUPTION_WA(i915) \ 598 (IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9) 599 600 /* WaRsDisableCoarsePowerGating:skl,cnl */ 601 #define NEEDS_WaRsDisableCoarsePowerGating(i915) \ 602 (IS_SKYLAKE(i915) && (INTEL_INFO(i915)->gt == 3 || INTEL_INFO(i915)->gt == 4)) 603 604 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 605 * rows, which changed the alignment requirements and fence programming. 606 */ 607 #define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \ 608 !(IS_I915G(i915) || IS_I915GM(i915))) 609 610 #define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6) 611 #define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p) 612 #define HAS_RC6pp(i915) (false) /* HW was never validated */ 613 614 #define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps) 615 616 #define HAS_PXP(i915) \ 617 (IS_ENABLED(CONFIG_DRM_I915_PXP) && INTEL_INFO(i915)->has_pxp) 618 619 #define HAS_HECI_PXP(i915) \ 620 (INTEL_INFO(i915)->has_heci_pxp) 621 622 #define HAS_HECI_GSCFI(i915) \ 623 (INTEL_INFO(i915)->has_heci_gscfi) 624 625 #define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915)) 626 627 #define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm) 628 #define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc) 629 630 #define HAS_OA_BPC_REPORTING(i915) \ 631 (INTEL_INFO(i915)->has_oa_bpc_reporting) 632 #define HAS_OA_SLICE_CONTRIB_LIMITS(i915) \ 633 (INTEL_INFO(i915)->has_oa_slice_contrib_limits) 634 #define HAS_OAM(i915) \ 635 (INTEL_INFO(i915)->has_oam) 636 637 /* 638 * Set this flag, when platform requires 64K GTT page sizes or larger for 639 * device local memory access. 640 */ 641 #define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages) 642 643 #define HAS_REGION(i915, id) (INTEL_INFO(i915)->memory_regions & BIT(id)) 644 #define HAS_LMEM(i915) HAS_REGION(i915, INTEL_REGION_LMEM_0) 645 646 #define HAS_EXTRA_GT_LIST(i915) (INTEL_INFO(i915)->extra_gt_list) 647 648 /* 649 * Platform has the dedicated compression control state for each lmem surfaces 650 * stored in lmem to support the 3D and media compression formats. 651 */ 652 #define HAS_FLAT_CCS(i915) (INTEL_INFO(i915)->has_flat_ccs) 653 654 #define HAS_GT_UC(i915) (INTEL_INFO(i915)->has_gt_uc) 655 656 #define HAS_POOLED_EU(i915) (RUNTIME_INFO(i915)->has_pooled_eu) 657 658 #define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs) 659 660 #define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id) 661 662 #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read) 663 664 /* DPF == dynamic parity feature */ 665 #define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf) 666 #define NUM_L3_SLICES(i915) (IS_HASWELL(i915) && INTEL_INFO(i915)->gt == 3 ? \ 667 2 : HAS_L3_DPF(i915)) 668 669 #define HAS_GUC_DEPRIVILEGE(i915) \ 670 (INTEL_INFO(i915)->has_guc_deprivilege) 671 672 #define HAS_GUC_TLB_INVALIDATION(i915) (INTEL_INFO(i915)->has_guc_tlb_invalidation) 673 674 #define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline) 675 676 #define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit) 677 678 #define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \ 679 GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) 680 681 #endif 682