1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 35 #include <linux/pci.h> 36 #include <linux/pm_qos.h> 37 38 #include <drm/ttm/ttm_device.h> 39 40 #include "gem/i915_gem_context_types.h" 41 #include "gem/i915_gem_shrinker.h" 42 #include "gem/i915_gem_stolen.h" 43 44 #include "gt/intel_engine.h" 45 #include "gt/intel_gt_types.h" 46 #include "gt/intel_region_lmem.h" 47 #include "gt/intel_workarounds.h" 48 #include "gt/uc/intel_uc.h" 49 50 #include "i915_drm_client.h" 51 #include "i915_gem.h" 52 #include "i915_gpu_error.h" 53 #include "i915_params.h" 54 #include "i915_perf_types.h" 55 #include "i915_scheduler.h" 56 #include "i915_utils.h" 57 #include "intel_device_info.h" 58 #include "intel_memory_region.h" 59 #include "intel_runtime_pm.h" 60 #include "intel_step.h" 61 #include "intel_uncore.h" 62 63 struct dram_info; 64 struct drm_i915_clock_gating_funcs; 65 struct intel_display; 66 struct intel_pxp; 67 struct vlv_s0ix_state; 68 69 /* Data Stolen Memory (DSM) aka "i915 stolen memory" */ 70 struct i915_dsm { 71 /* 72 * The start and end of DSM which we can optionally use to create GEM 73 * objects backed by stolen memory. 74 * 75 * Note that usable_size tells us exactly how much of this we are 76 * actually allowed to use, given that some portion of it is in fact 77 * reserved for use by hardware functions. 78 */ 79 struct resource stolen; 80 81 /* 82 * Reserved portion of DSM. 83 */ 84 struct resource reserved; 85 86 /* 87 * Total size minus reserved ranges. 88 * 89 * DSM is segmented in hardware with different portions offlimits to 90 * certain functions. 91 * 92 * The drm_mm is initialised to the total accessible range, as found 93 * from the PCI config. On Broadwell+, this is further restricted to 94 * avoid the first page! The upper end of DSM is reserved for hardware 95 * functions and similarly removed from the accessible range. 96 */ 97 resource_size_t usable_size; 98 }; 99 100 #define MAX_L3_SLICES 2 101 struct intel_l3_parity { 102 u32 *remap_info[MAX_L3_SLICES]; 103 struct work_struct error_work; 104 int which_slice; 105 }; 106 107 struct i915_gem_mm { 108 /* 109 * Shortcut for the stolen region. This points to either 110 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or 111 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't 112 * support stolen. 113 */ 114 struct intel_memory_region *stolen_region; 115 /** Memory allocator for GTT stolen memory */ 116 struct drm_mm stolen; 117 /** Protects the usage of the GTT stolen memory allocator. This is 118 * always the inner lock when overlapping with struct_mutex. */ 119 struct mutex stolen_lock; 120 121 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ 122 spinlock_t obj_lock; 123 124 /** 125 * List of objects which are purgeable. 126 */ 127 struct list_head purge_list; 128 129 /** 130 * List of objects which have allocated pages and are shrinkable. 131 */ 132 struct list_head shrink_list; 133 134 /** 135 * List of objects which are pending destruction. 136 */ 137 struct llist_head free_list; 138 struct work_struct free_work; 139 /** 140 * Count of objects pending destructions. Used to skip needlessly 141 * waiting on an RCU barrier if no objects are waiting to be freed. 142 */ 143 atomic_t free_count; 144 145 /** 146 * tmpfs instance used for shmem backed objects 147 */ 148 struct vfsmount *gemfs; 149 150 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN]; 151 152 struct notifier_block oom_notifier; 153 struct notifier_block vmap_notifier; 154 struct shrinker *shrinker; 155 156 /* shrinker accounting, also useful for userland debugging */ 157 u64 shrink_memory; 158 u32 shrink_count; 159 }; 160 161 struct i915_virtual_gpu { 162 struct mutex lock; /* serialises sending of g2v_notify command pkts */ 163 bool active; 164 u32 caps; 165 u32 *initial_mmio; 166 u8 *initial_cfg_space; 167 struct list_head entry; 168 }; 169 170 struct i915_selftest_stash { 171 atomic_t counter; 172 struct ida mock_region_instances; 173 }; 174 175 struct drm_i915_private { 176 struct drm_device drm; 177 178 struct intel_display *display; 179 180 /* FIXME: Device release actions should all be moved to drmm_ */ 181 bool do_release; 182 183 /* i915 device parameters */ 184 struct i915_params params; 185 186 const struct intel_device_info *__info; /* Use INTEL_INFO() to access. */ 187 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ 188 struct intel_driver_caps caps; 189 190 struct i915_dsm dsm; 191 192 struct intel_uncore uncore; 193 struct intel_uncore_mmio_debug mmio_debug; 194 195 struct i915_virtual_gpu vgpu; 196 197 struct intel_gvt *gvt; 198 199 struct { 200 struct pci_dev *pdev; 201 struct resource mch_res; 202 bool mchbar_need_disable; 203 } gmch; 204 205 /* 206 * Chaining user engines happens in multiple stages, starting with a 207 * simple lock-less linked list created by intel_engine_add_user(), 208 * which later gets sorted and converted to an intermediate regular 209 * list, just to be converted once again to its final rb tree structure 210 * in intel_engines_driver_register(). 211 * 212 * Make sure to use the right iterator helper, depending on if the code 213 * in question runs before or after intel_engines_driver_register() -- 214 * for_each_uabi_engine() can only be used afterwards! 215 */ 216 union { 217 struct llist_head uabi_engines_llist; 218 struct list_head uabi_engines_list; 219 struct rb_root uabi_engines; 220 }; 221 unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1]; 222 223 bool irqs_enabled; 224 225 /* VLV/CHV IOSF sideband */ 226 struct { 227 struct mutex lock; /* protect sideband access */ 228 unsigned long locked_unit_mask; 229 struct pm_qos_request qos; 230 } vlv_iosf_sb; 231 232 /* Sideband mailbox protection */ 233 struct mutex sb_lock; 234 235 /** Cached value of IMR to avoid reads in updating the bitfield */ 236 u32 irq_mask; 237 238 bool preserve_bios_swizzle; 239 240 unsigned int hpll_freq; 241 unsigned int czclk_freq; 242 243 /** 244 * wq - Driver workqueue for GEM. 245 * 246 * NOTE: Work items scheduled here are not allowed to grab any modeset 247 * locks, for otherwise the flushing done in the pageflip code will 248 * result in deadlocks. 249 */ 250 struct workqueue_struct *wq; 251 252 /** 253 * unordered_wq - internal workqueue for unordered work 254 * 255 * This workqueue should be used for all unordered work 256 * scheduling within i915, which used to be scheduled on the 257 * system_wq before moving to a driver instance due 258 * deprecation of flush_scheduled_work(). 259 */ 260 struct workqueue_struct *unordered_wq; 261 262 /* pm private clock gating functions */ 263 const struct drm_i915_clock_gating_funcs *clock_gating_funcs; 264 265 unsigned long gem_quirks; 266 267 struct i915_gem_mm mm; 268 269 struct intel_l3_parity l3_parity; 270 271 /* 272 * edram size in MB. 273 * Cannot be determined by PCIID. You must always read a register. 274 */ 275 u32 edram_size_mb; 276 277 struct i915_gpu_error gpu_error; 278 279 u32 suspend_count; 280 struct vlv_s0ix_state *vlv_s0ix_state; 281 282 const struct dram_info *dram_info; 283 284 struct intel_runtime_pm runtime_pm; 285 286 struct i915_perf perf; 287 288 struct i915_hwmon *hwmon; 289 290 struct intel_gt *gt[I915_MAX_GT]; 291 292 struct kobject *sysfs_gt; 293 294 /* Quick lookup of media GT (current platforms only have one) */ 295 struct intel_gt *media_gt; 296 297 struct { 298 struct i915_gem_contexts { 299 spinlock_t lock; /* locks list */ 300 struct list_head list; 301 } contexts; 302 303 /* 304 * We replace the local file with a global mappings as the 305 * backing storage for the mmap is on the device and not 306 * on the struct file, and we do not want to prolong the 307 * lifetime of the local fd. To minimise the number of 308 * anonymous inodes we create, we use a global singleton to 309 * share the global mapping. 310 */ 311 struct file *mmap_singleton; 312 } gem; 313 314 struct intel_pxp *pxp; 315 316 struct i915_pmu pmu; 317 318 /* The TTM device structure. */ 319 struct ttm_device bdev; 320 321 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;) 322 323 /* 324 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 325 * will be rejected. Instead look for a better place. 326 */ 327 }; 328 329 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 330 { 331 return container_of(dev, struct drm_i915_private, drm); 332 } 333 334 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) 335 { 336 struct drm_device *drm = dev_get_drvdata(kdev); 337 338 return drm ? to_i915(drm) : NULL; 339 } 340 341 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) 342 { 343 struct drm_device *drm = pci_get_drvdata(pdev); 344 345 return drm ? to_i915(drm) : NULL; 346 } 347 348 static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) 349 { 350 return i915->gt[0]; 351 } 352 353 #define INTEL_INFO(i915) ((i915)->__info) 354 #define RUNTIME_INFO(i915) (&(i915)->__runtime) 355 #define DRIVER_CAPS(i915) (&(i915)->caps) 356 357 #define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id) 358 359 #define IP_VER(ver, rel) ((ver) << 8 | (rel)) 360 361 #define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver) 362 #define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \ 363 RUNTIME_INFO(i915)->graphics.ip.rel) 364 #define IS_GRAPHICS_VER(i915, from, until) \ 365 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until)) 366 367 #define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver) 368 #define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \ 369 RUNTIME_INFO(i915)->media.ip.rel) 370 #define IS_MEDIA_VER(i915, from, until) \ 371 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until)) 372 373 #define INTEL_REVID(i915) (to_pci_dev((i915)->drm.dev)->revision) 374 375 #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step) 376 #define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step) 377 378 #define IS_GRAPHICS_STEP(__i915, since, until) \ 379 (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \ 380 INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until)) 381 382 #define IS_MEDIA_STEP(__i915, since, until) \ 383 (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \ 384 INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until)) 385 386 static __always_inline unsigned int 387 __platform_mask_index(const struct intel_runtime_info *info, 388 enum intel_platform p) 389 { 390 const unsigned int pbits = 391 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 392 393 /* Expand the platform_mask array if this fails. */ 394 BUILD_BUG_ON(INTEL_MAX_PLATFORMS > 395 pbits * ARRAY_SIZE(info->platform_mask)); 396 397 return p / pbits; 398 } 399 400 static __always_inline unsigned int 401 __platform_mask_bit(const struct intel_runtime_info *info, 402 enum intel_platform p) 403 { 404 const unsigned int pbits = 405 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 406 407 return p % pbits + INTEL_SUBPLATFORM_BITS; 408 } 409 410 static inline u32 411 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p) 412 { 413 const unsigned int pi = __platform_mask_index(info, p); 414 415 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK; 416 } 417 418 static __always_inline bool 419 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p) 420 { 421 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 422 const unsigned int pi = __platform_mask_index(info, p); 423 const unsigned int pb = __platform_mask_bit(info, p); 424 425 BUILD_BUG_ON(!__builtin_constant_p(p)); 426 427 return info->platform_mask[pi] & BIT(pb); 428 } 429 430 static __always_inline bool 431 IS_SUBPLATFORM(const struct drm_i915_private *i915, 432 enum intel_platform p, unsigned int s) 433 { 434 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 435 const unsigned int pi = __platform_mask_index(info, p); 436 const unsigned int pb = __platform_mask_bit(info, p); 437 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1; 438 const u32 mask = info->platform_mask[pi]; 439 440 BUILD_BUG_ON(!__builtin_constant_p(p)); 441 BUILD_BUG_ON(!__builtin_constant_p(s)); 442 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS); 443 444 /* Shift and test on the MSB position so sign flag can be used. */ 445 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); 446 } 447 448 #define IS_MOBILE(i915) (INTEL_INFO(i915)->is_mobile) 449 #define IS_DGFX(i915) (INTEL_INFO(i915)->is_dgfx) 450 451 #define IS_I830(i915) IS_PLATFORM(i915, INTEL_I830) 452 #define IS_I845G(i915) IS_PLATFORM(i915, INTEL_I845G) 453 #define IS_I85X(i915) IS_PLATFORM(i915, INTEL_I85X) 454 #define IS_I865G(i915) IS_PLATFORM(i915, INTEL_I865G) 455 #define IS_I915G(i915) IS_PLATFORM(i915, INTEL_I915G) 456 #define IS_I915GM(i915) IS_PLATFORM(i915, INTEL_I915GM) 457 #define IS_I945G(i915) IS_PLATFORM(i915, INTEL_I945G) 458 #define IS_I945GM(i915) IS_PLATFORM(i915, INTEL_I945GM) 459 #define IS_I965G(i915) IS_PLATFORM(i915, INTEL_I965G) 460 #define IS_I965GM(i915) IS_PLATFORM(i915, INTEL_I965GM) 461 #define IS_G45(i915) IS_PLATFORM(i915, INTEL_G45) 462 #define IS_GM45(i915) IS_PLATFORM(i915, INTEL_GM45) 463 #define IS_G4X(i915) (IS_G45(i915) || IS_GM45(i915)) 464 #define IS_PINEVIEW(i915) IS_PLATFORM(i915, INTEL_PINEVIEW) 465 #define IS_G33(i915) IS_PLATFORM(i915, INTEL_G33) 466 #define IS_IRONLAKE(i915) IS_PLATFORM(i915, INTEL_IRONLAKE) 467 #define IS_IRONLAKE_M(i915) \ 468 (IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915)) 469 #define IS_SANDYBRIDGE(i915) IS_PLATFORM(i915, INTEL_SANDYBRIDGE) 470 #define IS_IVYBRIDGE(i915) IS_PLATFORM(i915, INTEL_IVYBRIDGE) 471 #define IS_VALLEYVIEW(i915) IS_PLATFORM(i915, INTEL_VALLEYVIEW) 472 #define IS_CHERRYVIEW(i915) IS_PLATFORM(i915, INTEL_CHERRYVIEW) 473 #define IS_HASWELL(i915) IS_PLATFORM(i915, INTEL_HASWELL) 474 #define IS_BROADWELL(i915) IS_PLATFORM(i915, INTEL_BROADWELL) 475 #define IS_SKYLAKE(i915) IS_PLATFORM(i915, INTEL_SKYLAKE) 476 #define IS_BROXTON(i915) IS_PLATFORM(i915, INTEL_BROXTON) 477 #define IS_KABYLAKE(i915) IS_PLATFORM(i915, INTEL_KABYLAKE) 478 #define IS_GEMINILAKE(i915) IS_PLATFORM(i915, INTEL_GEMINILAKE) 479 #define IS_COFFEELAKE(i915) IS_PLATFORM(i915, INTEL_COFFEELAKE) 480 #define IS_COMETLAKE(i915) IS_PLATFORM(i915, INTEL_COMETLAKE) 481 #define IS_ICELAKE(i915) IS_PLATFORM(i915, INTEL_ICELAKE) 482 #define IS_JASPERLAKE(i915) IS_PLATFORM(i915, INTEL_JASPERLAKE) 483 #define IS_ELKHARTLAKE(i915) IS_PLATFORM(i915, INTEL_ELKHARTLAKE) 484 #define IS_TIGERLAKE(i915) IS_PLATFORM(i915, INTEL_TIGERLAKE) 485 #define IS_ROCKETLAKE(i915) IS_PLATFORM(i915, INTEL_ROCKETLAKE) 486 #define IS_DG1(i915) IS_PLATFORM(i915, INTEL_DG1) 487 #define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S) 488 #define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P) 489 #define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2) 490 #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE) 491 /* 492 * Display code shared by i915 and Xe relies on macros like IS_LUNARLAKE, 493 * so we need to define these even on platforms that the i915 base driver 494 * doesn't support. Ensure the parameter is used in the definition to 495 * avoid 'unused variable' warnings when compiling the shared display code 496 * for i915. 497 */ 498 #define IS_LUNARLAKE(i915) (0 && i915) 499 #define IS_BATTLEMAGE(i915) (0 && i915) 500 #define IS_PANTHERLAKE(i915) (0 && i915) 501 502 #define IS_ARROWLAKE_H(i915) \ 503 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_H) 504 #define IS_ARROWLAKE_U(i915) \ 505 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_U) 506 #define IS_ARROWLAKE_S(i915) \ 507 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_S) 508 #define IS_DG2_G10(i915) \ 509 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10) 510 #define IS_DG2_G11(i915) \ 511 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11) 512 #define IS_DG2_G12(i915) \ 513 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12) 514 #define IS_DG2_D(i915) \ 515 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_D) 516 #define IS_RAPTORLAKE_S(i915) \ 517 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL) 518 #define IS_ALDERLAKE_P_N(i915) \ 519 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N) 520 #define IS_RAPTORLAKE_P(i915) \ 521 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL) 522 #define IS_RAPTORLAKE_U(i915) \ 523 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU) 524 #define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \ 525 (INTEL_DEVID(i915) & 0xFF00) == 0x0C00) 526 #define IS_BROADWELL_ULT(i915) \ 527 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) 528 #define IS_BROADWELL_ULX(i915) \ 529 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX) 530 #define IS_HASWELL_ULT(i915) \ 531 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) 532 /* ULX machines are also considered ULT. */ 533 #define IS_HASWELL_ULX(i915) \ 534 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) 535 #define IS_SKYLAKE_ULT(i915) \ 536 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) 537 #define IS_SKYLAKE_ULX(i915) \ 538 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) 539 #define IS_KABYLAKE_ULT(i915) \ 540 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) 541 #define IS_KABYLAKE_ULX(i915) \ 542 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) 543 #define IS_COFFEELAKE_ULT(i915) \ 544 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) 545 #define IS_COFFEELAKE_ULX(i915) \ 546 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX) 547 #define IS_COMETLAKE_ULT(i915) \ 548 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT) 549 #define IS_COMETLAKE_ULX(i915) \ 550 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX) 551 552 #define IS_ICL_WITH_PORT_F(i915) \ 553 IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) 554 555 #define IS_TIGERLAKE_UY(i915) \ 556 IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY) 557 558 #define IS_GEN9_LP(i915) (IS_BROXTON(i915) || IS_GEMINILAKE(i915)) 559 #define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_GEN9_LP(i915)) 560 561 #define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode) 562 563 /* 564 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution 565 * All later gens can run the final buffer from the ppgtt 566 */ 567 #define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7) 568 569 #define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc) 570 #define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop) 571 #define HAS_EDRAM(i915) ((i915)->edram_size_mb) 572 #define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6) 573 #define HAS_WT(i915) HAS_EDRAM(i915) 574 575 #define HWS_NEEDS_PHYSICAL(i915) (INTEL_INFO(i915)->hws_needs_physical) 576 577 #define HAS_LOGICAL_RING_CONTEXTS(i915) \ 578 (INTEL_INFO(i915)->has_logical_ring_contexts) 579 #define HAS_LOGICAL_RING_ELSQ(i915) \ 580 (INTEL_INFO(i915)->has_logical_ring_elsq) 581 582 #define HAS_EXECLISTS(i915) HAS_LOGICAL_RING_CONTEXTS(i915) 583 584 #define INTEL_PPGTT(i915) (RUNTIME_INFO(i915)->ppgtt_type) 585 #define HAS_PPGTT(i915) \ 586 (INTEL_PPGTT(i915) != INTEL_PPGTT_NONE) 587 #define HAS_FULL_PPGTT(i915) \ 588 (INTEL_PPGTT(i915) >= INTEL_PPGTT_FULL) 589 590 #define HAS_PAGE_SIZES(i915, sizes) ({ \ 591 GEM_BUG_ON((sizes) == 0); \ 592 ((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \ 593 }) 594 595 #define NEEDS_RC6_CTX_CORRUPTION_WA(i915) \ 596 (IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9) 597 598 /* WaRsDisableCoarsePowerGating:skl,cnl */ 599 #define NEEDS_WaRsDisableCoarsePowerGating(i915) \ 600 (IS_SKYLAKE(i915) && (INTEL_INFO(i915)->gt == 3 || INTEL_INFO(i915)->gt == 4)) 601 602 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 603 * rows, which changed the alignment requirements and fence programming. 604 */ 605 #define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \ 606 !(IS_I915G(i915) || IS_I915GM(i915))) 607 608 #define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6) 609 #define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p) 610 #define HAS_RC6pp(i915) (false) /* HW was never validated */ 611 612 #define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps) 613 614 #define HAS_PXP(i915) \ 615 (IS_ENABLED(CONFIG_DRM_I915_PXP) && INTEL_INFO(i915)->has_pxp) 616 617 #define HAS_HECI_PXP(i915) \ 618 (INTEL_INFO(i915)->has_heci_pxp) 619 620 #define HAS_HECI_GSCFI(i915) \ 621 (INTEL_INFO(i915)->has_heci_gscfi) 622 623 #define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915)) 624 625 #define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm) 626 #define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc) 627 628 #define HAS_OA_BPC_REPORTING(i915) \ 629 (INTEL_INFO(i915)->has_oa_bpc_reporting) 630 #define HAS_OA_SLICE_CONTRIB_LIMITS(i915) \ 631 (INTEL_INFO(i915)->has_oa_slice_contrib_limits) 632 #define HAS_OAM(i915) \ 633 (INTEL_INFO(i915)->has_oam) 634 635 /* 636 * Set this flag, when platform requires 64K GTT page sizes or larger for 637 * device local memory access. 638 */ 639 #define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages) 640 641 #define HAS_REGION(i915, id) (INTEL_INFO(i915)->memory_regions & BIT(id)) 642 #define HAS_LMEM(i915) HAS_REGION(i915, INTEL_REGION_LMEM_0) 643 644 #define HAS_EXTRA_GT_LIST(i915) (INTEL_INFO(i915)->extra_gt_list) 645 646 /* 647 * Platform has the dedicated compression control state for each lmem surfaces 648 * stored in lmem to support the 3D and media compression formats. 649 */ 650 #define HAS_FLAT_CCS(i915) (INTEL_INFO(i915)->has_flat_ccs) 651 652 #define HAS_GT_UC(i915) (INTEL_INFO(i915)->has_gt_uc) 653 654 #define HAS_POOLED_EU(i915) (RUNTIME_INFO(i915)->has_pooled_eu) 655 656 #define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs) 657 658 #define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id) 659 660 #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read) 661 662 /* DPF == dynamic parity feature */ 663 #define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf) 664 #define NUM_L3_SLICES(i915) (IS_HASWELL(i915) && INTEL_INFO(i915)->gt == 3 ? \ 665 2 : HAS_L3_DPF(i915)) 666 667 #define HAS_GUC_DEPRIVILEGE(i915) \ 668 (INTEL_INFO(i915)->has_guc_deprivilege) 669 670 #define HAS_GUC_TLB_INVALIDATION(i915) (INTEL_INFO(i915)->has_guc_tlb_invalidation) 671 672 #define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline) 673 674 #define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit) 675 676 #define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \ 677 GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) 678 679 #endif 680