1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include "i915_reg.h" 34 #include "intel_bios.h" 35 #include "intel_ringbuffer.h" 36 #include <linux/io-mapping.h> 37 #include <linux/i2c.h> 38 #include <linux/i2c-algo-bit.h> 39 #include <drm/intel-gtt.h> 40 #include <linux/backlight.h> 41 #include <linux/intel-iommu.h> 42 #include <linux/kref.h> 43 44 /* General customization: 45 */ 46 47 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 48 49 #define DRIVER_NAME "i915" 50 #define DRIVER_DESC "Intel Graphics" 51 #define DRIVER_DATE "20080730" 52 53 enum pipe { 54 PIPE_A = 0, 55 PIPE_B, 56 PIPE_C, 57 I915_MAX_PIPES 58 }; 59 #define pipe_name(p) ((p) + 'A') 60 61 enum transcoder { 62 TRANSCODER_A = 0, 63 TRANSCODER_B, 64 TRANSCODER_C, 65 TRANSCODER_EDP = 0xF, 66 }; 67 #define transcoder_name(t) ((t) + 'A') 68 69 enum plane { 70 PLANE_A = 0, 71 PLANE_B, 72 PLANE_C, 73 }; 74 #define plane_name(p) ((p) + 'A') 75 76 enum port { 77 PORT_A = 0, 78 PORT_B, 79 PORT_C, 80 PORT_D, 81 PORT_E, 82 I915_MAX_PORTS 83 }; 84 #define port_name(p) ((p) + 'A') 85 86 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 87 88 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) 89 90 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 91 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 92 if ((intel_encoder)->base.crtc == (__crtc)) 93 94 struct intel_pch_pll { 95 int refcount; /* count of number of CRTCs sharing this PLL */ 96 int active; /* count of number of active CRTCs (i.e. DPMS on) */ 97 bool on; /* is the PLL actually active? Disabled during modeset */ 98 int pll_reg; 99 int fp0_reg; 100 int fp1_reg; 101 }; 102 #define I915_NUM_PLLS 2 103 104 struct intel_ddi_plls { 105 int spll_refcount; 106 int wrpll1_refcount; 107 int wrpll2_refcount; 108 }; 109 110 /* Interface history: 111 * 112 * 1.1: Original. 113 * 1.2: Add Power Management 114 * 1.3: Add vblank support 115 * 1.4: Fix cmdbuffer path, add heap destroy 116 * 1.5: Add vblank pipe configuration 117 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 118 * - Support vertical blank on secondary display pipe 119 */ 120 #define DRIVER_MAJOR 1 121 #define DRIVER_MINOR 6 122 #define DRIVER_PATCHLEVEL 0 123 124 #define WATCH_COHERENCY 0 125 #define WATCH_LISTS 0 126 #define WATCH_GTT 0 127 128 #define I915_GEM_PHYS_CURSOR_0 1 129 #define I915_GEM_PHYS_CURSOR_1 2 130 #define I915_GEM_PHYS_OVERLAY_REGS 3 131 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 132 133 struct drm_i915_gem_phys_object { 134 int id; 135 struct page **page_list; 136 drm_dma_handle_t *handle; 137 struct drm_i915_gem_object *cur_obj; 138 }; 139 140 struct opregion_header; 141 struct opregion_acpi; 142 struct opregion_swsci; 143 struct opregion_asle; 144 struct drm_i915_private; 145 146 struct intel_opregion { 147 struct opregion_header __iomem *header; 148 struct opregion_acpi __iomem *acpi; 149 struct opregion_swsci __iomem *swsci; 150 struct opregion_asle __iomem *asle; 151 void __iomem *vbt; 152 u32 __iomem *lid_state; 153 }; 154 #define OPREGION_SIZE (8*1024) 155 156 struct intel_overlay; 157 struct intel_overlay_error_state; 158 159 struct drm_i915_master_private { 160 drm_local_map_t *sarea; 161 struct _drm_i915_sarea *sarea_priv; 162 }; 163 #define I915_FENCE_REG_NONE -1 164 #define I915_MAX_NUM_FENCES 16 165 /* 16 fences + sign bit for FENCE_REG_NONE */ 166 #define I915_MAX_NUM_FENCE_BITS 5 167 168 struct drm_i915_fence_reg { 169 struct list_head lru_list; 170 struct drm_i915_gem_object *obj; 171 int pin_count; 172 }; 173 174 struct sdvo_device_mapping { 175 u8 initialized; 176 u8 dvo_port; 177 u8 slave_addr; 178 u8 dvo_wiring; 179 u8 i2c_pin; 180 u8 ddc_pin; 181 }; 182 183 struct intel_display_error_state; 184 185 struct drm_i915_error_state { 186 struct kref ref; 187 u32 eir; 188 u32 pgtbl_er; 189 u32 ier; 190 u32 ccid; 191 bool waiting[I915_NUM_RINGS]; 192 u32 pipestat[I915_MAX_PIPES]; 193 u32 tail[I915_NUM_RINGS]; 194 u32 head[I915_NUM_RINGS]; 195 u32 ipeir[I915_NUM_RINGS]; 196 u32 ipehr[I915_NUM_RINGS]; 197 u32 instdone[I915_NUM_RINGS]; 198 u32 acthd[I915_NUM_RINGS]; 199 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 200 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 201 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */ 202 /* our own tracking of ring head and tail */ 203 u32 cpu_ring_head[I915_NUM_RINGS]; 204 u32 cpu_ring_tail[I915_NUM_RINGS]; 205 u32 error; /* gen6+ */ 206 u32 err_int; /* gen7 */ 207 u32 instpm[I915_NUM_RINGS]; 208 u32 instps[I915_NUM_RINGS]; 209 u32 extra_instdone[I915_NUM_INSTDONE_REG]; 210 u32 seqno[I915_NUM_RINGS]; 211 u64 bbaddr; 212 u32 fault_reg[I915_NUM_RINGS]; 213 u32 done_reg; 214 u32 faddr[I915_NUM_RINGS]; 215 u64 fence[I915_MAX_NUM_FENCES]; 216 struct timeval time; 217 struct drm_i915_error_ring { 218 struct drm_i915_error_object { 219 int page_count; 220 u32 gtt_offset; 221 u32 *pages[0]; 222 } *ringbuffer, *batchbuffer; 223 struct drm_i915_error_request { 224 long jiffies; 225 u32 seqno; 226 u32 tail; 227 } *requests; 228 int num_requests; 229 } ring[I915_NUM_RINGS]; 230 struct drm_i915_error_buffer { 231 u32 size; 232 u32 name; 233 u32 rseqno, wseqno; 234 u32 gtt_offset; 235 u32 read_domains; 236 u32 write_domain; 237 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 238 s32 pinned:2; 239 u32 tiling:2; 240 u32 dirty:1; 241 u32 purgeable:1; 242 s32 ring:4; 243 u32 cache_level:2; 244 } *active_bo, *pinned_bo; 245 u32 active_bo_count, pinned_bo_count; 246 struct intel_overlay_error_state *overlay; 247 struct intel_display_error_state *display; 248 }; 249 250 struct drm_i915_display_funcs { 251 bool (*fbc_enabled)(struct drm_device *dev); 252 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); 253 void (*disable_fbc)(struct drm_device *dev); 254 int (*get_display_clock_speed)(struct drm_device *dev); 255 int (*get_fifo_size)(struct drm_device *dev, int plane); 256 void (*update_wm)(struct drm_device *dev); 257 void (*update_sprite_wm)(struct drm_device *dev, int pipe, 258 uint32_t sprite_width, int pixel_size); 259 void (*update_linetime_wm)(struct drm_device *dev, int pipe, 260 struct drm_display_mode *mode); 261 void (*modeset_global_resources)(struct drm_device *dev); 262 int (*crtc_mode_set)(struct drm_crtc *crtc, 263 struct drm_display_mode *mode, 264 struct drm_display_mode *adjusted_mode, 265 int x, int y, 266 struct drm_framebuffer *old_fb); 267 void (*crtc_enable)(struct drm_crtc *crtc); 268 void (*crtc_disable)(struct drm_crtc *crtc); 269 void (*off)(struct drm_crtc *crtc); 270 void (*write_eld)(struct drm_connector *connector, 271 struct drm_crtc *crtc); 272 void (*fdi_link_train)(struct drm_crtc *crtc); 273 void (*init_clock_gating)(struct drm_device *dev); 274 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 275 struct drm_framebuffer *fb, 276 struct drm_i915_gem_object *obj); 277 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, 278 int x, int y); 279 /* clock updates for mode set */ 280 /* cursor updates */ 281 /* render clock increase/decrease */ 282 /* display clock increase/decrease */ 283 /* pll clock increase/decrease */ 284 }; 285 286 struct drm_i915_gt_funcs { 287 void (*force_wake_get)(struct drm_i915_private *dev_priv); 288 void (*force_wake_put)(struct drm_i915_private *dev_priv); 289 }; 290 291 #define DEV_INFO_FLAGS \ 292 DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \ 293 DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \ 294 DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \ 295 DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \ 296 DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \ 297 DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \ 298 DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \ 299 DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \ 300 DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \ 301 DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \ 302 DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \ 303 DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \ 304 DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \ 305 DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \ 306 DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \ 307 DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \ 308 DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \ 309 DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \ 310 DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \ 311 DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \ 312 DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \ 313 DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \ 314 DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \ 315 DEV_INFO_FLAG(has_llc) 316 317 struct intel_device_info { 318 u8 gen; 319 u8 is_mobile:1; 320 u8 is_i85x:1; 321 u8 is_i915g:1; 322 u8 is_i945gm:1; 323 u8 is_g33:1; 324 u8 need_gfx_hws:1; 325 u8 is_g4x:1; 326 u8 is_pineview:1; 327 u8 is_broadwater:1; 328 u8 is_crestline:1; 329 u8 is_ivybridge:1; 330 u8 is_valleyview:1; 331 u8 has_force_wake:1; 332 u8 is_haswell:1; 333 u8 has_fbc:1; 334 u8 has_pipe_cxsr:1; 335 u8 has_hotplug:1; 336 u8 cursor_needs_physical:1; 337 u8 has_overlay:1; 338 u8 overlay_needs_physical:1; 339 u8 supports_tv:1; 340 u8 has_bsd_ring:1; 341 u8 has_blt_ring:1; 342 u8 has_llc:1; 343 }; 344 345 #define I915_PPGTT_PD_ENTRIES 512 346 #define I915_PPGTT_PT_ENTRIES 1024 347 struct i915_hw_ppgtt { 348 struct drm_device *dev; 349 unsigned num_pd_entries; 350 struct page **pt_pages; 351 uint32_t pd_offset; 352 dma_addr_t *pt_dma_addr; 353 dma_addr_t scratch_page_dma_addr; 354 }; 355 356 357 /* This must match up with the value previously used for execbuf2.rsvd1. */ 358 #define DEFAULT_CONTEXT_ID 0 359 struct i915_hw_context { 360 int id; 361 bool is_initialized; 362 struct drm_i915_file_private *file_priv; 363 struct intel_ring_buffer *ring; 364 struct drm_i915_gem_object *obj; 365 }; 366 367 enum no_fbc_reason { 368 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 369 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ 370 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 371 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 372 FBC_BAD_PLANE, /* fbc not supported on plane */ 373 FBC_NOT_TILED, /* buffer not tiled */ 374 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 375 FBC_MODULE_PARAM, 376 }; 377 378 enum intel_pch { 379 PCH_NONE = 0, /* No PCH present */ 380 PCH_IBX, /* Ibexpeak PCH */ 381 PCH_CPT, /* Cougarpoint PCH */ 382 PCH_LPT, /* Lynxpoint PCH */ 383 }; 384 385 enum intel_sbi_destination { 386 SBI_ICLK, 387 SBI_MPHY, 388 }; 389 390 #define QUIRK_PIPEA_FORCE (1<<0) 391 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 392 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 393 394 struct intel_fbdev; 395 struct intel_fbc_work; 396 397 struct intel_gmbus { 398 struct i2c_adapter adapter; 399 u32 force_bit; 400 u32 reg0; 401 u32 gpio_reg; 402 struct i2c_algo_bit_data bit_algo; 403 struct drm_i915_private *dev_priv; 404 }; 405 406 struct i915_suspend_saved_registers { 407 u8 saveLBB; 408 u32 saveDSPACNTR; 409 u32 saveDSPBCNTR; 410 u32 saveDSPARB; 411 u32 savePIPEACONF; 412 u32 savePIPEBCONF; 413 u32 savePIPEASRC; 414 u32 savePIPEBSRC; 415 u32 saveFPA0; 416 u32 saveFPA1; 417 u32 saveDPLL_A; 418 u32 saveDPLL_A_MD; 419 u32 saveHTOTAL_A; 420 u32 saveHBLANK_A; 421 u32 saveHSYNC_A; 422 u32 saveVTOTAL_A; 423 u32 saveVBLANK_A; 424 u32 saveVSYNC_A; 425 u32 saveBCLRPAT_A; 426 u32 saveTRANSACONF; 427 u32 saveTRANS_HTOTAL_A; 428 u32 saveTRANS_HBLANK_A; 429 u32 saveTRANS_HSYNC_A; 430 u32 saveTRANS_VTOTAL_A; 431 u32 saveTRANS_VBLANK_A; 432 u32 saveTRANS_VSYNC_A; 433 u32 savePIPEASTAT; 434 u32 saveDSPASTRIDE; 435 u32 saveDSPASIZE; 436 u32 saveDSPAPOS; 437 u32 saveDSPAADDR; 438 u32 saveDSPASURF; 439 u32 saveDSPATILEOFF; 440 u32 savePFIT_PGM_RATIOS; 441 u32 saveBLC_HIST_CTL; 442 u32 saveBLC_PWM_CTL; 443 u32 saveBLC_PWM_CTL2; 444 u32 saveBLC_CPU_PWM_CTL; 445 u32 saveBLC_CPU_PWM_CTL2; 446 u32 saveFPB0; 447 u32 saveFPB1; 448 u32 saveDPLL_B; 449 u32 saveDPLL_B_MD; 450 u32 saveHTOTAL_B; 451 u32 saveHBLANK_B; 452 u32 saveHSYNC_B; 453 u32 saveVTOTAL_B; 454 u32 saveVBLANK_B; 455 u32 saveVSYNC_B; 456 u32 saveBCLRPAT_B; 457 u32 saveTRANSBCONF; 458 u32 saveTRANS_HTOTAL_B; 459 u32 saveTRANS_HBLANK_B; 460 u32 saveTRANS_HSYNC_B; 461 u32 saveTRANS_VTOTAL_B; 462 u32 saveTRANS_VBLANK_B; 463 u32 saveTRANS_VSYNC_B; 464 u32 savePIPEBSTAT; 465 u32 saveDSPBSTRIDE; 466 u32 saveDSPBSIZE; 467 u32 saveDSPBPOS; 468 u32 saveDSPBADDR; 469 u32 saveDSPBSURF; 470 u32 saveDSPBTILEOFF; 471 u32 saveVGA0; 472 u32 saveVGA1; 473 u32 saveVGA_PD; 474 u32 saveVGACNTRL; 475 u32 saveADPA; 476 u32 saveLVDS; 477 u32 savePP_ON_DELAYS; 478 u32 savePP_OFF_DELAYS; 479 u32 saveDVOA; 480 u32 saveDVOB; 481 u32 saveDVOC; 482 u32 savePP_ON; 483 u32 savePP_OFF; 484 u32 savePP_CONTROL; 485 u32 savePP_DIVISOR; 486 u32 savePFIT_CONTROL; 487 u32 save_palette_a[256]; 488 u32 save_palette_b[256]; 489 u32 saveDPFC_CB_BASE; 490 u32 saveFBC_CFB_BASE; 491 u32 saveFBC_LL_BASE; 492 u32 saveFBC_CONTROL; 493 u32 saveFBC_CONTROL2; 494 u32 saveIER; 495 u32 saveIIR; 496 u32 saveIMR; 497 u32 saveDEIER; 498 u32 saveDEIMR; 499 u32 saveGTIER; 500 u32 saveGTIMR; 501 u32 saveFDI_RXA_IMR; 502 u32 saveFDI_RXB_IMR; 503 u32 saveCACHE_MODE_0; 504 u32 saveMI_ARB_STATE; 505 u32 saveSWF0[16]; 506 u32 saveSWF1[16]; 507 u32 saveSWF2[3]; 508 u8 saveMSR; 509 u8 saveSR[8]; 510 u8 saveGR[25]; 511 u8 saveAR_INDEX; 512 u8 saveAR[21]; 513 u8 saveDACMASK; 514 u8 saveCR[37]; 515 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 516 u32 saveCURACNTR; 517 u32 saveCURAPOS; 518 u32 saveCURABASE; 519 u32 saveCURBCNTR; 520 u32 saveCURBPOS; 521 u32 saveCURBBASE; 522 u32 saveCURSIZE; 523 u32 saveDP_B; 524 u32 saveDP_C; 525 u32 saveDP_D; 526 u32 savePIPEA_GMCH_DATA_M; 527 u32 savePIPEB_GMCH_DATA_M; 528 u32 savePIPEA_GMCH_DATA_N; 529 u32 savePIPEB_GMCH_DATA_N; 530 u32 savePIPEA_DP_LINK_M; 531 u32 savePIPEB_DP_LINK_M; 532 u32 savePIPEA_DP_LINK_N; 533 u32 savePIPEB_DP_LINK_N; 534 u32 saveFDI_RXA_CTL; 535 u32 saveFDI_TXA_CTL; 536 u32 saveFDI_RXB_CTL; 537 u32 saveFDI_TXB_CTL; 538 u32 savePFA_CTL_1; 539 u32 savePFB_CTL_1; 540 u32 savePFA_WIN_SZ; 541 u32 savePFB_WIN_SZ; 542 u32 savePFA_WIN_POS; 543 u32 savePFB_WIN_POS; 544 u32 savePCH_DREF_CONTROL; 545 u32 saveDISP_ARB_CTL; 546 u32 savePIPEA_DATA_M1; 547 u32 savePIPEA_DATA_N1; 548 u32 savePIPEA_LINK_M1; 549 u32 savePIPEA_LINK_N1; 550 u32 savePIPEB_DATA_M1; 551 u32 savePIPEB_DATA_N1; 552 u32 savePIPEB_LINK_M1; 553 u32 savePIPEB_LINK_N1; 554 u32 saveMCHBAR_RENDER_STANDBY; 555 u32 savePCH_PORT_HOTPLUG; 556 }; 557 558 struct intel_gen6_power_mgmt { 559 struct work_struct work; 560 u32 pm_iir; 561 /* lock - irqsave spinlock that protectects the work_struct and 562 * pm_iir. */ 563 spinlock_t lock; 564 565 /* The below variables an all the rps hw state are protected by 566 * dev->struct mutext. */ 567 u8 cur_delay; 568 u8 min_delay; 569 u8 max_delay; 570 571 struct delayed_work delayed_resume_work; 572 573 /* 574 * Protects RPS/RC6 register access and PCU communication. 575 * Must be taken after struct_mutex if nested. 576 */ 577 struct mutex hw_lock; 578 }; 579 580 struct intel_ilk_power_mgmt { 581 u8 cur_delay; 582 u8 min_delay; 583 u8 max_delay; 584 u8 fmax; 585 u8 fstart; 586 587 u64 last_count1; 588 unsigned long last_time1; 589 unsigned long chipset_power; 590 u64 last_count2; 591 struct timespec last_time2; 592 unsigned long gfx_power; 593 u8 corr; 594 595 int c_m; 596 int r_t; 597 598 struct drm_i915_gem_object *pwrctx; 599 struct drm_i915_gem_object *renderctx; 600 }; 601 602 struct i915_dri1_state { 603 unsigned allow_batchbuffer : 1; 604 u32 __iomem *gfx_hws_cpu_addr; 605 606 unsigned int cpp; 607 int back_offset; 608 int front_offset; 609 int current_page; 610 int page_flipping; 611 612 uint32_t counter; 613 }; 614 615 struct intel_l3_parity { 616 u32 *remap_info; 617 struct work_struct error_work; 618 }; 619 620 typedef struct drm_i915_private { 621 struct drm_device *dev; 622 623 const struct intel_device_info *info; 624 625 int relative_constants_mode; 626 627 void __iomem *regs; 628 629 struct drm_i915_gt_funcs gt; 630 /** gt_fifo_count and the subsequent register write are synchronized 631 * with dev->struct_mutex. */ 632 unsigned gt_fifo_count; 633 /** forcewake_count is protected by gt_lock */ 634 unsigned forcewake_count; 635 /** gt_lock is also taken in irq contexts. */ 636 struct spinlock gt_lock; 637 638 struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; 639 640 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 641 * controller on different i2c buses. */ 642 struct mutex gmbus_mutex; 643 644 /** 645 * Base address of the gmbus and gpio block. 646 */ 647 uint32_t gpio_mmio_base; 648 649 struct pci_dev *bridge_dev; 650 struct intel_ring_buffer ring[I915_NUM_RINGS]; 651 uint32_t next_seqno; 652 653 drm_dma_handle_t *status_page_dmah; 654 struct resource mch_res; 655 656 atomic_t irq_received; 657 658 /* protects the irq masks */ 659 spinlock_t irq_lock; 660 661 /* DPIO indirect register protection */ 662 spinlock_t dpio_lock; 663 664 /** Cached value of IMR to avoid reads in updating the bitfield */ 665 u32 pipestat[2]; 666 u32 irq_mask; 667 u32 gt_irq_mask; 668 u32 pch_irq_mask; 669 670 u32 hotplug_supported_mask; 671 struct work_struct hotplug_work; 672 673 int num_pipe; 674 int num_pch_pll; 675 676 /* For hangcheck timer */ 677 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ 678 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) 679 struct timer_list hangcheck_timer; 680 int hangcheck_count; 681 uint32_t last_acthd[I915_NUM_RINGS]; 682 uint32_t prev_instdone[I915_NUM_INSTDONE_REG]; 683 684 unsigned int stop_rings; 685 686 unsigned long cfb_size; 687 unsigned int cfb_fb; 688 enum plane cfb_plane; 689 int cfb_y; 690 struct intel_fbc_work *fbc_work; 691 692 struct intel_opregion opregion; 693 694 /* overlay */ 695 struct intel_overlay *overlay; 696 bool sprite_scaling_enabled; 697 698 /* LVDS info */ 699 int backlight_level; /* restore backlight to this value */ 700 bool backlight_enabled; 701 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 702 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 703 704 /* Feature bits from the VBIOS */ 705 unsigned int int_tv_support:1; 706 unsigned int lvds_dither:1; 707 unsigned int lvds_vbt:1; 708 unsigned int int_crt_support:1; 709 unsigned int lvds_use_ssc:1; 710 unsigned int display_clock_mode:1; 711 int lvds_ssc_freq; 712 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 713 unsigned int lvds_val; /* used for checking LVDS channel mode */ 714 struct { 715 int rate; 716 int lanes; 717 int preemphasis; 718 int vswing; 719 720 bool initialized; 721 bool support; 722 int bpp; 723 struct edp_power_seq pps; 724 } edp; 725 bool no_aux_handshake; 726 727 int crt_ddc_pin; 728 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 729 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 730 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 731 732 unsigned int fsb_freq, mem_freq, is_ddr3; 733 734 spinlock_t error_lock; 735 /* Protected by dev->error_lock. */ 736 struct drm_i915_error_state *first_error; 737 struct work_struct error_work; 738 struct completion error_completion; 739 struct workqueue_struct *wq; 740 741 /* Display functions */ 742 struct drm_i915_display_funcs display; 743 744 /* PCH chipset type */ 745 enum intel_pch pch_type; 746 unsigned short pch_id; 747 748 unsigned long quirks; 749 750 /* Register state */ 751 bool modeset_on_lid; 752 753 struct { 754 /** Bridge to intel-gtt-ko */ 755 struct intel_gtt *gtt; 756 /** Memory allocator for GTT stolen memory */ 757 struct drm_mm stolen; 758 /** Memory allocator for GTT */ 759 struct drm_mm gtt_space; 760 /** List of all objects in gtt_space. Used to restore gtt 761 * mappings on resume */ 762 struct list_head bound_list; 763 /** 764 * List of objects which are not bound to the GTT (thus 765 * are idle and not used by the GPU) but still have 766 * (presumably uncached) pages still attached. 767 */ 768 struct list_head unbound_list; 769 770 /** Usable portion of the GTT for GEM */ 771 unsigned long gtt_start; 772 unsigned long gtt_mappable_end; 773 unsigned long gtt_end; 774 775 struct io_mapping *gtt_mapping; 776 phys_addr_t gtt_base_addr; 777 int gtt_mtrr; 778 779 /** PPGTT used for aliasing the PPGTT with the GTT */ 780 struct i915_hw_ppgtt *aliasing_ppgtt; 781 782 struct shrinker inactive_shrinker; 783 bool shrinker_no_lock_stealing; 784 785 /** 786 * List of objects currently involved in rendering. 787 * 788 * Includes buffers having the contents of their GPU caches 789 * flushed, not necessarily primitives. last_rendering_seqno 790 * represents when the rendering involved will be completed. 791 * 792 * A reference is held on the buffer while on this list. 793 */ 794 struct list_head active_list; 795 796 /** 797 * LRU list of objects which are not in the ringbuffer and 798 * are ready to unbind, but are still in the GTT. 799 * 800 * last_rendering_seqno is 0 while an object is in this list. 801 * 802 * A reference is not held on the buffer while on this list, 803 * as merely being GTT-bound shouldn't prevent its being 804 * freed, and we'll pull it off the list in the free path. 805 */ 806 struct list_head inactive_list; 807 808 /** LRU list of objects with fence regs on them. */ 809 struct list_head fence_list; 810 811 /** 812 * We leave the user IRQ off as much as possible, 813 * but this means that requests will finish and never 814 * be retired once the system goes idle. Set a timer to 815 * fire periodically while the ring is running. When it 816 * fires, go retire requests. 817 */ 818 struct delayed_work retire_work; 819 820 /** 821 * Are we in a non-interruptible section of code like 822 * modesetting? 823 */ 824 bool interruptible; 825 826 /** 827 * Flag if the X Server, and thus DRM, is not currently in 828 * control of the device. 829 * 830 * This is set between LeaveVT and EnterVT. It needs to be 831 * replaced with a semaphore. It also needs to be 832 * transitioned away from for kernel modesetting. 833 */ 834 int suspended; 835 836 /** 837 * Flag if the hardware appears to be wedged. 838 * 839 * This is set when attempts to idle the device timeout. 840 * It prevents command submission from occurring and makes 841 * every pending request fail 842 */ 843 atomic_t wedged; 844 845 /** Bit 6 swizzling required for X tiling */ 846 uint32_t bit_6_swizzle_x; 847 /** Bit 6 swizzling required for Y tiling */ 848 uint32_t bit_6_swizzle_y; 849 850 /* storage for physical objects */ 851 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 852 853 /* accounting, useful for userland debugging */ 854 size_t gtt_total; 855 size_t mappable_gtt_total; 856 size_t object_memory; 857 u32 object_count; 858 } mm; 859 860 /* Kernel Modesetting */ 861 862 struct sdvo_device_mapping sdvo_mappings[2]; 863 /* indicate whether the LVDS_BORDER should be enabled or not */ 864 unsigned int lvds_border_bits; 865 /* Panel fitter placement and size for Ironlake+ */ 866 u32 pch_pf_pos, pch_pf_size; 867 868 struct drm_crtc *plane_to_crtc_mapping[3]; 869 struct drm_crtc *pipe_to_crtc_mapping[3]; 870 wait_queue_head_t pending_flip_queue; 871 872 struct intel_pch_pll pch_plls[I915_NUM_PLLS]; 873 struct intel_ddi_plls ddi_plls; 874 875 /* Reclocking support */ 876 bool render_reclock_avail; 877 bool lvds_downclock_avail; 878 /* indicates the reduced downclock for LVDS*/ 879 int lvds_downclock; 880 u16 orig_clock; 881 int child_dev_num; 882 struct child_device_config *child_dev; 883 884 bool mchbar_need_disable; 885 886 struct intel_l3_parity l3_parity; 887 888 /* gen6+ rps state */ 889 struct intel_gen6_power_mgmt rps; 890 891 /* ilk-only ips/rps state. Everything in here is protected by the global 892 * mchdev_lock in intel_pm.c */ 893 struct intel_ilk_power_mgmt ips; 894 895 enum no_fbc_reason no_fbc_reason; 896 897 struct drm_mm_node *compressed_fb; 898 struct drm_mm_node *compressed_llb; 899 900 unsigned long last_gpu_reset; 901 902 /* list of fbdev register on this device */ 903 struct intel_fbdev *fbdev; 904 905 /* 906 * The console may be contended at resume, but we don't 907 * want it to block on it. 908 */ 909 struct work_struct console_resume_work; 910 911 struct backlight_device *backlight; 912 913 struct drm_property *broadcast_rgb_property; 914 struct drm_property *force_audio_property; 915 916 bool hw_contexts_disabled; 917 uint32_t hw_context_size; 918 919 bool fdi_rx_polarity_reversed; 920 921 struct i915_suspend_saved_registers regfile; 922 923 /* Old dri1 support infrastructure, beware the dragons ya fools entering 924 * here! */ 925 struct i915_dri1_state dri1; 926 } drm_i915_private_t; 927 928 /* Iterate over initialised rings */ 929 #define for_each_ring(ring__, dev_priv__, i__) \ 930 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ 931 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) 932 933 enum hdmi_force_audio { 934 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 935 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 936 HDMI_AUDIO_AUTO, /* trust EDID */ 937 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 938 }; 939 940 enum i915_cache_level { 941 I915_CACHE_NONE = 0, 942 I915_CACHE_LLC, 943 I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */ 944 }; 945 946 struct drm_i915_gem_object_ops { 947 /* Interface between the GEM object and its backing storage. 948 * get_pages() is called once prior to the use of the associated set 949 * of pages before to binding them into the GTT, and put_pages() is 950 * called after we no longer need them. As we expect there to be 951 * associated cost with migrating pages between the backing storage 952 * and making them available for the GPU (e.g. clflush), we may hold 953 * onto the pages after they are no longer referenced by the GPU 954 * in case they may be used again shortly (for example migrating the 955 * pages to a different memory domain within the GTT). put_pages() 956 * will therefore most likely be called when the object itself is 957 * being released or under memory pressure (where we attempt to 958 * reap pages for the shrinker). 959 */ 960 int (*get_pages)(struct drm_i915_gem_object *); 961 void (*put_pages)(struct drm_i915_gem_object *); 962 }; 963 964 struct drm_i915_gem_object { 965 struct drm_gem_object base; 966 967 const struct drm_i915_gem_object_ops *ops; 968 969 /** Current space allocated to this object in the GTT, if any. */ 970 struct drm_mm_node *gtt_space; 971 struct list_head gtt_list; 972 973 /** This object's place on the active/inactive lists */ 974 struct list_head ring_list; 975 struct list_head mm_list; 976 /** This object's place in the batchbuffer or on the eviction list */ 977 struct list_head exec_list; 978 979 /** 980 * This is set if the object is on the active lists (has pending 981 * rendering and so a non-zero seqno), and is not set if it i s on 982 * inactive (ready to be unbound) list. 983 */ 984 unsigned int active:1; 985 986 /** 987 * This is set if the object has been written to since last bound 988 * to the GTT 989 */ 990 unsigned int dirty:1; 991 992 /** 993 * Fence register bits (if any) for this object. Will be set 994 * as needed when mapped into the GTT. 995 * Protected by dev->struct_mutex. 996 */ 997 signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 998 999 /** 1000 * Advice: are the backing pages purgeable? 1001 */ 1002 unsigned int madv:2; 1003 1004 /** 1005 * Current tiling mode for the object. 1006 */ 1007 unsigned int tiling_mode:2; 1008 /** 1009 * Whether the tiling parameters for the currently associated fence 1010 * register have changed. Note that for the purposes of tracking 1011 * tiling changes we also treat the unfenced register, the register 1012 * slot that the object occupies whilst it executes a fenced 1013 * command (such as BLT on gen2/3), as a "fence". 1014 */ 1015 unsigned int fence_dirty:1; 1016 1017 /** How many users have pinned this object in GTT space. The following 1018 * users can each hold at most one reference: pwrite/pread, pin_ioctl 1019 * (via user_pin_count), execbuffer (objects are not allowed multiple 1020 * times for the same batchbuffer), and the framebuffer code. When 1021 * switching/pageflipping, the framebuffer code has at most two buffers 1022 * pinned per crtc. 1023 * 1024 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 1025 * bits with absolutely no headroom. So use 4 bits. */ 1026 unsigned int pin_count:4; 1027 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 1028 1029 /** 1030 * Is the object at the current location in the gtt mappable and 1031 * fenceable? Used to avoid costly recalculations. 1032 */ 1033 unsigned int map_and_fenceable:1; 1034 1035 /** 1036 * Whether the current gtt mapping needs to be mappable (and isn't just 1037 * mappable by accident). Track pin and fault separate for a more 1038 * accurate mappable working set. 1039 */ 1040 unsigned int fault_mappable:1; 1041 unsigned int pin_mappable:1; 1042 1043 /* 1044 * Is the GPU currently using a fence to access this buffer, 1045 */ 1046 unsigned int pending_fenced_gpu_access:1; 1047 unsigned int fenced_gpu_access:1; 1048 1049 unsigned int cache_level:2; 1050 1051 unsigned int has_aliasing_ppgtt_mapping:1; 1052 unsigned int has_global_gtt_mapping:1; 1053 unsigned int has_dma_mapping:1; 1054 1055 struct sg_table *pages; 1056 int pages_pin_count; 1057 1058 /* prime dma-buf support */ 1059 void *dma_buf_vmapping; 1060 int vmapping_count; 1061 1062 /** 1063 * Used for performing relocations during execbuffer insertion. 1064 */ 1065 struct hlist_node exec_node; 1066 unsigned long exec_handle; 1067 struct drm_i915_gem_exec_object2 *exec_entry; 1068 1069 /** 1070 * Current offset of the object in GTT space. 1071 * 1072 * This is the same as gtt_space->start 1073 */ 1074 uint32_t gtt_offset; 1075 1076 struct intel_ring_buffer *ring; 1077 1078 /** Breadcrumb of last rendering to the buffer. */ 1079 uint32_t last_read_seqno; 1080 uint32_t last_write_seqno; 1081 /** Breadcrumb of last fenced GPU access to the buffer. */ 1082 uint32_t last_fenced_seqno; 1083 1084 /** Current tiling stride for the object, if it's tiled. */ 1085 uint32_t stride; 1086 1087 /** Record of address bit 17 of each page at last unbind. */ 1088 unsigned long *bit_17; 1089 1090 /** User space pin count and filp owning the pin */ 1091 uint32_t user_pin_count; 1092 struct drm_file *pin_filp; 1093 1094 /** for phy allocated objects */ 1095 struct drm_i915_gem_phys_object *phys_obj; 1096 1097 /** 1098 * Number of crtcs where this object is currently the fb, but 1099 * will be page flipped away on the next vblank. When it 1100 * reaches 0, dev_priv->pending_flip_queue will be woken up. 1101 */ 1102 atomic_t pending_flip; 1103 }; 1104 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base) 1105 1106 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 1107 1108 /** 1109 * Request queue structure. 1110 * 1111 * The request queue allows us to note sequence numbers that have been emitted 1112 * and may be associated with active buffers to be retired. 1113 * 1114 * By keeping this list, we can avoid having to do questionable 1115 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 1116 * an emission time with seqnos for tracking how far ahead of the GPU we are. 1117 */ 1118 struct drm_i915_gem_request { 1119 /** On Which ring this request was generated */ 1120 struct intel_ring_buffer *ring; 1121 1122 /** GEM sequence number associated with this request. */ 1123 uint32_t seqno; 1124 1125 /** Postion in the ringbuffer of the end of the request */ 1126 u32 tail; 1127 1128 /** Time at which this request was emitted, in jiffies. */ 1129 unsigned long emitted_jiffies; 1130 1131 /** global list entry for this request */ 1132 struct list_head list; 1133 1134 struct drm_i915_file_private *file_priv; 1135 /** file_priv list entry for this request */ 1136 struct list_head client_list; 1137 }; 1138 1139 struct drm_i915_file_private { 1140 struct { 1141 struct spinlock lock; 1142 struct list_head request_list; 1143 } mm; 1144 struct idr context_idr; 1145 }; 1146 1147 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) 1148 1149 #define IS_I830(dev) ((dev)->pci_device == 0x3577) 1150 #define IS_845G(dev) ((dev)->pci_device == 0x2562) 1151 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 1152 #define IS_I865G(dev) ((dev)->pci_device == 0x2572) 1153 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1154 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 1155 #define IS_I945G(dev) ((dev)->pci_device == 0x2772) 1156 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 1157 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 1158 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 1159 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 1160 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 1161 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) 1162 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) 1163 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 1164 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 1165 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) 1166 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 1167 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 1168 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \ 1169 (dev)->pci_device == 0x0152 || \ 1170 (dev)->pci_device == 0x015a) 1171 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \ 1172 (dev)->pci_device == 0x0106 || \ 1173 (dev)->pci_device == 0x010A) 1174 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) 1175 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) 1176 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1177 #define IS_ULT(dev) (IS_HASWELL(dev) && \ 1178 ((dev)->pci_device & 0xFF00) == 0x0A00) 1179 1180 /* 1181 * The genX designation typically refers to the render engine, so render 1182 * capability related checks should use IS_GEN, while display and other checks 1183 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular 1184 * chips, etc.). 1185 */ 1186 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 1187 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 1188 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 1189 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 1190 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 1191 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 1192 1193 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) 1194 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) 1195 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 1196 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1197 1198 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) 1199 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev)) 1200 1201 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 1202 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 1203 1204 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 1205 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) 1206 1207 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1208 * rows, which changed the alignment requirements and fence programming. 1209 */ 1210 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 1211 IS_I915GM(dev))) 1212 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 1213 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1214 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1215 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) 1216 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 1217 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 1218 /* dsparb controlled by hw only */ 1219 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 1220 1221 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 1222 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 1223 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 1224 1225 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) 1226 1227 #define INTEL_PCH_DEVICE_ID_MASK 0xff00 1228 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 1229 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 1230 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 1231 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 1232 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 1233 1234 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) 1235 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) 1236 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1237 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 1238 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) 1239 1240 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake) 1241 1242 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 1243 1244 #define GT_FREQUENCY_MULTIPLIER 50 1245 1246 #include "i915_trace.h" 1247 1248 /** 1249 * RC6 is a special power stage which allows the GPU to enter an very 1250 * low-voltage mode when idle, using down to 0V while at this stage. This 1251 * stage is entered automatically when the GPU is idle when RC6 support is 1252 * enabled, and as soon as new workload arises GPU wakes up automatically as well. 1253 * 1254 * There are different RC6 modes available in Intel GPU, which differentiate 1255 * among each other with the latency required to enter and leave RC6 and 1256 * voltage consumed by the GPU in different states. 1257 * 1258 * The combination of the following flags define which states GPU is allowed 1259 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 1260 * RC6pp is deepest RC6. Their support by hardware varies according to the 1261 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 1262 * which brings the most power savings; deeper states save more power, but 1263 * require higher latency to switch to and wake up. 1264 */ 1265 #define INTEL_RC6_ENABLE (1<<0) 1266 #define INTEL_RC6p_ENABLE (1<<1) 1267 #define INTEL_RC6pp_ENABLE (1<<2) 1268 1269 extern struct drm_ioctl_desc i915_ioctls[]; 1270 extern int i915_max_ioctl; 1271 extern unsigned int i915_fbpercrtc __always_unused; 1272 extern int i915_panel_ignore_lid __read_mostly; 1273 extern unsigned int i915_powersave __read_mostly; 1274 extern int i915_semaphores __read_mostly; 1275 extern unsigned int i915_lvds_downclock __read_mostly; 1276 extern int i915_lvds_channel_mode __read_mostly; 1277 extern int i915_panel_use_ssc __read_mostly; 1278 extern int i915_vbt_sdvo_panel_type __read_mostly; 1279 extern int i915_enable_rc6 __read_mostly; 1280 extern int i915_enable_fbc __read_mostly; 1281 extern bool i915_enable_hangcheck __read_mostly; 1282 extern int i915_enable_ppgtt __read_mostly; 1283 extern unsigned int i915_preliminary_hw_support __read_mostly; 1284 1285 extern int i915_suspend(struct drm_device *dev, pm_message_t state); 1286 extern int i915_resume(struct drm_device *dev); 1287 extern int i915_master_create(struct drm_device *dev, struct drm_master *master); 1288 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 1289 1290 /* i915_dma.c */ 1291 void i915_update_dri1_breadcrumb(struct drm_device *dev); 1292 extern void i915_kernel_lost_context(struct drm_device * dev); 1293 extern int i915_driver_load(struct drm_device *, unsigned long flags); 1294 extern int i915_driver_unload(struct drm_device *); 1295 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 1296 extern void i915_driver_lastclose(struct drm_device * dev); 1297 extern void i915_driver_preclose(struct drm_device *dev, 1298 struct drm_file *file_priv); 1299 extern void i915_driver_postclose(struct drm_device *dev, 1300 struct drm_file *file_priv); 1301 extern int i915_driver_device_is_agp(struct drm_device * dev); 1302 #ifdef CONFIG_COMPAT 1303 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 1304 unsigned long arg); 1305 #endif 1306 extern int i915_emit_box(struct drm_device *dev, 1307 struct drm_clip_rect *box, 1308 int DR1, int DR4); 1309 extern int intel_gpu_reset(struct drm_device *dev); 1310 extern int i915_reset(struct drm_device *dev); 1311 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 1312 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 1313 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 1314 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); 1315 1316 extern void intel_console_resume(struct work_struct *work); 1317 1318 /* i915_irq.c */ 1319 void i915_hangcheck_elapsed(unsigned long data); 1320 void i915_handle_error(struct drm_device *dev, bool wedged); 1321 1322 extern void intel_irq_init(struct drm_device *dev); 1323 extern void intel_gt_init(struct drm_device *dev); 1324 extern void intel_gt_reset(struct drm_device *dev); 1325 1326 void i915_error_state_free(struct kref *error_ref); 1327 1328 void 1329 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1330 1331 void 1332 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1333 1334 void intel_enable_asle(struct drm_device *dev); 1335 1336 #ifdef CONFIG_DEBUG_FS 1337 extern void i915_destroy_error_state(struct drm_device *dev); 1338 #else 1339 #define i915_destroy_error_state(x) 1340 #endif 1341 1342 1343 /* i915_gem.c */ 1344 int i915_gem_init_ioctl(struct drm_device *dev, void *data, 1345 struct drm_file *file_priv); 1346 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 1347 struct drm_file *file_priv); 1348 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 1349 struct drm_file *file_priv); 1350 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1351 struct drm_file *file_priv); 1352 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 1353 struct drm_file *file_priv); 1354 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 1355 struct drm_file *file_priv); 1356 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1357 struct drm_file *file_priv); 1358 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 1359 struct drm_file *file_priv); 1360 int i915_gem_execbuffer(struct drm_device *dev, void *data, 1361 struct drm_file *file_priv); 1362 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 1363 struct drm_file *file_priv); 1364 int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 1365 struct drm_file *file_priv); 1366 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 1367 struct drm_file *file_priv); 1368 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 1369 struct drm_file *file_priv); 1370 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, 1371 struct drm_file *file); 1372 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, 1373 struct drm_file *file); 1374 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 1375 struct drm_file *file_priv); 1376 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 1377 struct drm_file *file_priv); 1378 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 1379 struct drm_file *file_priv); 1380 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 1381 struct drm_file *file_priv); 1382 int i915_gem_set_tiling(struct drm_device *dev, void *data, 1383 struct drm_file *file_priv); 1384 int i915_gem_get_tiling(struct drm_device *dev, void *data, 1385 struct drm_file *file_priv); 1386 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 1387 struct drm_file *file_priv); 1388 int i915_gem_wait_ioctl(struct drm_device *dev, void *data, 1389 struct drm_file *file_priv); 1390 void i915_gem_load(struct drm_device *dev); 1391 int i915_gem_init_object(struct drm_gem_object *obj); 1392 void i915_gem_object_init(struct drm_i915_gem_object *obj, 1393 const struct drm_i915_gem_object_ops *ops); 1394 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 1395 size_t size); 1396 void i915_gem_free_object(struct drm_gem_object *obj); 1397 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, 1398 uint32_t alignment, 1399 bool map_and_fenceable, 1400 bool nonblocking); 1401 void i915_gem_object_unpin(struct drm_i915_gem_object *obj); 1402 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); 1403 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 1404 void i915_gem_lastclose(struct drm_device *dev); 1405 1406 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); 1407 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) 1408 { 1409 struct scatterlist *sg = obj->pages->sgl; 1410 int nents = obj->pages->nents; 1411 while (nents > SG_MAX_SINGLE_ALLOC) { 1412 if (n < SG_MAX_SINGLE_ALLOC - 1) 1413 break; 1414 1415 sg = sg_chain_ptr(sg + SG_MAX_SINGLE_ALLOC - 1); 1416 n -= SG_MAX_SINGLE_ALLOC - 1; 1417 nents -= SG_MAX_SINGLE_ALLOC - 1; 1418 } 1419 return sg_page(sg+n); 1420 } 1421 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) 1422 { 1423 BUG_ON(obj->pages == NULL); 1424 obj->pages_pin_count++; 1425 } 1426 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) 1427 { 1428 BUG_ON(obj->pages_pin_count == 0); 1429 obj->pages_pin_count--; 1430 } 1431 1432 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); 1433 int i915_gem_object_sync(struct drm_i915_gem_object *obj, 1434 struct intel_ring_buffer *to); 1435 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, 1436 struct intel_ring_buffer *ring); 1437 1438 int i915_gem_dumb_create(struct drm_file *file_priv, 1439 struct drm_device *dev, 1440 struct drm_mode_create_dumb *args); 1441 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 1442 uint32_t handle, uint64_t *offset); 1443 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, 1444 uint32_t handle); 1445 /** 1446 * Returns true if seq1 is later than seq2. 1447 */ 1448 static inline bool 1449 i915_seqno_passed(uint32_t seq1, uint32_t seq2) 1450 { 1451 return (int32_t)(seq1 - seq2) >= 0; 1452 } 1453 1454 extern int i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); 1455 1456 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); 1457 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 1458 1459 static inline bool 1460 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) 1461 { 1462 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1463 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1464 dev_priv->fence_regs[obj->fence_reg].pin_count++; 1465 return true; 1466 } else 1467 return false; 1468 } 1469 1470 static inline void 1471 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) 1472 { 1473 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1474 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1475 dev_priv->fence_regs[obj->fence_reg].pin_count--; 1476 } 1477 } 1478 1479 void i915_gem_retire_requests(struct drm_device *dev); 1480 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); 1481 int __must_check i915_gem_check_wedge(struct drm_i915_private *dev_priv, 1482 bool interruptible); 1483 1484 void i915_gem_reset(struct drm_device *dev); 1485 void i915_gem_clflush_object(struct drm_i915_gem_object *obj); 1486 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, 1487 uint32_t read_domains, 1488 uint32_t write_domain); 1489 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 1490 int __must_check i915_gem_init(struct drm_device *dev); 1491 int __must_check i915_gem_init_hw(struct drm_device *dev); 1492 void i915_gem_l3_remap(struct drm_device *dev); 1493 void i915_gem_init_swizzling(struct drm_device *dev); 1494 void i915_gem_init_ppgtt(struct drm_device *dev); 1495 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 1496 int __must_check i915_gpu_idle(struct drm_device *dev); 1497 int __must_check i915_gem_idle(struct drm_device *dev); 1498 int i915_add_request(struct intel_ring_buffer *ring, 1499 struct drm_file *file, 1500 u32 *seqno); 1501 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, 1502 uint32_t seqno); 1503 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 1504 int __must_check 1505 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 1506 bool write); 1507 int __must_check 1508 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); 1509 int __must_check 1510 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 1511 u32 alignment, 1512 struct intel_ring_buffer *pipelined); 1513 int i915_gem_attach_phys_object(struct drm_device *dev, 1514 struct drm_i915_gem_object *obj, 1515 int id, 1516 int align); 1517 void i915_gem_detach_phys_object(struct drm_device *dev, 1518 struct drm_i915_gem_object *obj); 1519 void i915_gem_free_all_phys_object(struct drm_device *dev); 1520 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 1521 1522 uint32_t 1523 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, 1524 uint32_t size, 1525 int tiling_mode); 1526 1527 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1528 enum i915_cache_level cache_level); 1529 1530 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 1531 struct dma_buf *dma_buf); 1532 1533 struct dma_buf *i915_gem_prime_export(struct drm_device *dev, 1534 struct drm_gem_object *gem_obj, int flags); 1535 1536 /* i915_gem_context.c */ 1537 void i915_gem_context_init(struct drm_device *dev); 1538 void i915_gem_context_fini(struct drm_device *dev); 1539 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); 1540 int i915_switch_context(struct intel_ring_buffer *ring, 1541 struct drm_file *file, int to_id); 1542 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 1543 struct drm_file *file); 1544 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, 1545 struct drm_file *file); 1546 1547 /* i915_gem_gtt.c */ 1548 int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev); 1549 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); 1550 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, 1551 struct drm_i915_gem_object *obj, 1552 enum i915_cache_level cache_level); 1553 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, 1554 struct drm_i915_gem_object *obj); 1555 1556 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 1557 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); 1558 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, 1559 enum i915_cache_level cache_level); 1560 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); 1561 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); 1562 void i915_gem_init_global_gtt(struct drm_device *dev, 1563 unsigned long start, 1564 unsigned long mappable_end, 1565 unsigned long end); 1566 int i915_gem_gtt_init(struct drm_device *dev); 1567 void i915_gem_gtt_fini(struct drm_device *dev); 1568 static inline void i915_gem_chipset_flush(struct drm_device *dev) 1569 { 1570 if (INTEL_INFO(dev)->gen < 6) 1571 intel_gtt_chipset_flush(); 1572 } 1573 1574 1575 /* i915_gem_evict.c */ 1576 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, 1577 unsigned alignment, 1578 unsigned cache_level, 1579 bool mappable, 1580 bool nonblock); 1581 int i915_gem_evict_everything(struct drm_device *dev); 1582 1583 /* i915_gem_stolen.c */ 1584 int i915_gem_init_stolen(struct drm_device *dev); 1585 void i915_gem_cleanup_stolen(struct drm_device *dev); 1586 1587 /* i915_gem_tiling.c */ 1588 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 1589 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 1590 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 1591 1592 /* i915_gem_debug.c */ 1593 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, 1594 const char *where, uint32_t mark); 1595 #if WATCH_LISTS 1596 int i915_verify_lists(struct drm_device *dev); 1597 #else 1598 #define i915_verify_lists(dev) 0 1599 #endif 1600 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, 1601 int handle); 1602 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, 1603 const char *where, uint32_t mark); 1604 1605 /* i915_debugfs.c */ 1606 int i915_debugfs_init(struct drm_minor *minor); 1607 void i915_debugfs_cleanup(struct drm_minor *minor); 1608 1609 /* i915_suspend.c */ 1610 extern int i915_save_state(struct drm_device *dev); 1611 extern int i915_restore_state(struct drm_device *dev); 1612 1613 /* i915_suspend.c */ 1614 extern int i915_save_state(struct drm_device *dev); 1615 extern int i915_restore_state(struct drm_device *dev); 1616 1617 /* i915_sysfs.c */ 1618 void i915_setup_sysfs(struct drm_device *dev_priv); 1619 void i915_teardown_sysfs(struct drm_device *dev_priv); 1620 1621 /* intel_i2c.c */ 1622 extern int intel_setup_gmbus(struct drm_device *dev); 1623 extern void intel_teardown_gmbus(struct drm_device *dev); 1624 extern inline bool intel_gmbus_is_port_valid(unsigned port) 1625 { 1626 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); 1627 } 1628 1629 extern struct i2c_adapter *intel_gmbus_get_adapter( 1630 struct drm_i915_private *dev_priv, unsigned port); 1631 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); 1632 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); 1633 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 1634 { 1635 return container_of(adapter, struct intel_gmbus, adapter)->force_bit; 1636 } 1637 extern void intel_i2c_reset(struct drm_device *dev); 1638 1639 /* intel_opregion.c */ 1640 extern int intel_opregion_setup(struct drm_device *dev); 1641 #ifdef CONFIG_ACPI 1642 extern void intel_opregion_init(struct drm_device *dev); 1643 extern void intel_opregion_fini(struct drm_device *dev); 1644 extern void intel_opregion_asle_intr(struct drm_device *dev); 1645 extern void intel_opregion_gse_intr(struct drm_device *dev); 1646 extern void intel_opregion_enable_asle(struct drm_device *dev); 1647 #else 1648 static inline void intel_opregion_init(struct drm_device *dev) { return; } 1649 static inline void intel_opregion_fini(struct drm_device *dev) { return; } 1650 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } 1651 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } 1652 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } 1653 #endif 1654 1655 /* intel_acpi.c */ 1656 #ifdef CONFIG_ACPI 1657 extern void intel_register_dsm_handler(void); 1658 extern void intel_unregister_dsm_handler(void); 1659 #else 1660 static inline void intel_register_dsm_handler(void) { return; } 1661 static inline void intel_unregister_dsm_handler(void) { return; } 1662 #endif /* CONFIG_ACPI */ 1663 1664 /* modesetting */ 1665 extern void intel_modeset_init_hw(struct drm_device *dev); 1666 extern void intel_modeset_init(struct drm_device *dev); 1667 extern void intel_modeset_gem_init(struct drm_device *dev); 1668 extern void intel_modeset_cleanup(struct drm_device *dev); 1669 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 1670 extern void intel_modeset_setup_hw_state(struct drm_device *dev, 1671 bool force_restore); 1672 extern bool intel_fbc_enabled(struct drm_device *dev); 1673 extern void intel_disable_fbc(struct drm_device *dev); 1674 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 1675 extern void intel_init_pch_refclk(struct drm_device *dev); 1676 extern void gen6_set_rps(struct drm_device *dev, u8 val); 1677 extern void intel_detect_pch(struct drm_device *dev); 1678 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 1679 extern int intel_enable_rc6(const struct drm_device *dev); 1680 1681 extern bool i915_semaphore_is_enabled(struct drm_device *dev); 1682 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 1683 struct drm_file *file); 1684 1685 /* overlay */ 1686 #ifdef CONFIG_DEBUG_FS 1687 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); 1688 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); 1689 1690 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); 1691 extern void intel_display_print_error_state(struct seq_file *m, 1692 struct drm_device *dev, 1693 struct intel_display_error_state *error); 1694 #endif 1695 1696 /* On SNB platform, before reading ring registers forcewake bit 1697 * must be set to prevent GT core from power down and stale values being 1698 * returned. 1699 */ 1700 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1701 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1702 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); 1703 1704 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); 1705 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); 1706 1707 #define __i915_read(x, y) \ 1708 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); 1709 1710 __i915_read(8, b) 1711 __i915_read(16, w) 1712 __i915_read(32, l) 1713 __i915_read(64, q) 1714 #undef __i915_read 1715 1716 #define __i915_write(x, y) \ 1717 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); 1718 1719 __i915_write(8, b) 1720 __i915_write(16, w) 1721 __i915_write(32, l) 1722 __i915_write(64, q) 1723 #undef __i915_write 1724 1725 #define I915_READ8(reg) i915_read8(dev_priv, (reg)) 1726 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) 1727 1728 #define I915_READ16(reg) i915_read16(dev_priv, (reg)) 1729 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) 1730 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) 1731 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) 1732 1733 #define I915_READ(reg) i915_read32(dev_priv, (reg)) 1734 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) 1735 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) 1736 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) 1737 1738 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) 1739 #define I915_READ64(reg) i915_read64(dev_priv, (reg)) 1740 1741 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 1742 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 1743 1744 1745 #endif 1746