1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 #include <uapi/drm/drm_fourcc.h> 35 36 #include <linux/io-mapping.h> 37 #include <linux/i2c.h> 38 #include <linux/i2c-algo-bit.h> 39 #include <linux/backlight.h> 40 #include <linux/hash.h> 41 #include <linux/intel-iommu.h> 42 #include <linux/kref.h> 43 #include <linux/mm_types.h> 44 #include <linux/perf_event.h> 45 #include <linux/pm_qos.h> 46 #include <linux/dma-resv.h> 47 #include <linux/shmem_fs.h> 48 #include <linux/stackdepot.h> 49 #include <linux/xarray.h> 50 51 #include <drm/intel-gtt.h> 52 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ 53 #include <drm/drm_gem.h> 54 #include <drm/drm_auth.h> 55 #include <drm/drm_cache.h> 56 #include <drm/drm_util.h> 57 #include <drm/drm_dsc.h> 58 #include <drm/drm_atomic.h> 59 #include <drm/drm_connector.h> 60 #include <drm/i915_mei_hdcp_interface.h> 61 62 #include "i915_fixed.h" 63 #include "i915_params.h" 64 #include "i915_reg.h" 65 #include "i915_utils.h" 66 67 #include "display/intel_bios.h" 68 #include "display/intel_display.h" 69 #include "display/intel_display_power.h" 70 #include "display/intel_dpll_mgr.h" 71 #include "display/intel_dsb.h" 72 #include "display/intel_frontbuffer.h" 73 #include "display/intel_global_state.h" 74 #include "display/intel_gmbus.h" 75 #include "display/intel_opregion.h" 76 77 #include "gem/i915_gem_context_types.h" 78 #include "gem/i915_gem_shrinker.h" 79 #include "gem/i915_gem_stolen.h" 80 81 #include "gt/intel_lrc.h" 82 #include "gt/intel_engine.h" 83 #include "gt/intel_gt_types.h" 84 #include "gt/intel_workarounds.h" 85 #include "gt/uc/intel_uc.h" 86 87 #include "intel_device_info.h" 88 #include "intel_pch.h" 89 #include "intel_runtime_pm.h" 90 #include "intel_memory_region.h" 91 #include "intel_uncore.h" 92 #include "intel_wakeref.h" 93 #include "intel_wopcm.h" 94 95 #include "i915_gem.h" 96 #include "i915_gem_fence_reg.h" 97 #include "i915_gem_gtt.h" 98 #include "i915_gpu_error.h" 99 #include "i915_perf_types.h" 100 #include "i915_request.h" 101 #include "i915_scheduler.h" 102 #include "gt/intel_timeline.h" 103 #include "i915_vma.h" 104 #include "i915_irq.h" 105 106 #include "intel_region_lmem.h" 107 108 #include "intel_gvt.h" 109 110 /* General customization: 111 */ 112 113 #define DRIVER_NAME "i915" 114 #define DRIVER_DESC "Intel Graphics" 115 #define DRIVER_DATE "20200225" 116 #define DRIVER_TIMESTAMP 1582656081 117 118 struct drm_i915_gem_object; 119 120 enum hpd_pin { 121 HPD_NONE = 0, 122 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 123 HPD_CRT, 124 HPD_SDVO_B, 125 HPD_SDVO_C, 126 HPD_PORT_A, 127 HPD_PORT_B, 128 HPD_PORT_C, 129 HPD_PORT_D, 130 HPD_PORT_E, 131 HPD_PORT_F, 132 HPD_PORT_G, 133 HPD_PORT_H, 134 HPD_PORT_I, 135 136 HPD_NUM_PINS 137 }; 138 139 #define for_each_hpd_pin(__pin) \ 140 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) 141 142 /* Threshold == 5 for long IRQs, 50 for short */ 143 #define HPD_STORM_DEFAULT_THRESHOLD 50 144 145 struct i915_hotplug { 146 struct delayed_work hotplug_work; 147 148 struct { 149 unsigned long last_jiffies; 150 int count; 151 enum { 152 HPD_ENABLED = 0, 153 HPD_DISABLED = 1, 154 HPD_MARK_DISABLED = 2 155 } state; 156 } stats[HPD_NUM_PINS]; 157 u32 event_bits; 158 u32 retry_bits; 159 struct delayed_work reenable_work; 160 161 u32 long_port_mask; 162 u32 short_port_mask; 163 struct work_struct dig_port_work; 164 165 struct work_struct poll_init_work; 166 bool poll_enabled; 167 168 unsigned int hpd_storm_threshold; 169 /* Whether or not to count short HPD IRQs in HPD storms */ 170 u8 hpd_short_storm_enabled; 171 172 /* 173 * if we get a HPD irq from DP and a HPD irq from non-DP 174 * the non-DP HPD could block the workqueue on a mode config 175 * mutex getting, that userspace may have taken. However 176 * userspace is waiting on the DP workqueue to run which is 177 * blocked behind the non-DP one. 178 */ 179 struct workqueue_struct *dp_wq; 180 }; 181 182 #define I915_GEM_GPU_DOMAINS \ 183 (I915_GEM_DOMAIN_RENDER | \ 184 I915_GEM_DOMAIN_SAMPLER | \ 185 I915_GEM_DOMAIN_COMMAND | \ 186 I915_GEM_DOMAIN_INSTRUCTION | \ 187 I915_GEM_DOMAIN_VERTEX) 188 189 struct drm_i915_private; 190 struct i915_mm_struct; 191 struct i915_mmu_object; 192 193 struct drm_i915_file_private { 194 struct drm_i915_private *dev_priv; 195 196 union { 197 struct drm_file *file; 198 struct rcu_head rcu; 199 }; 200 201 struct { 202 spinlock_t lock; 203 struct list_head request_list; 204 } mm; 205 206 struct xarray context_xa; 207 struct xarray vm_xa; 208 209 unsigned int bsd_engine; 210 211 /* 212 * Every context ban increments per client ban score. Also 213 * hangs in short succession increments ban score. If ban threshold 214 * is reached, client is considered banned and submitting more work 215 * will fail. This is a stop gap measure to limit the badly behaving 216 * clients access to gpu. Note that unbannable contexts never increment 217 * the client ban score. 218 */ 219 #define I915_CLIENT_SCORE_HANG_FAST 1 220 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ) 221 #define I915_CLIENT_SCORE_CONTEXT_BAN 3 222 #define I915_CLIENT_SCORE_BANNED 9 223 /** ban_score: Accumulated score of all ctx bans and fast hangs. */ 224 atomic_t ban_score; 225 unsigned long hang_timestamp; 226 }; 227 228 /* Interface history: 229 * 230 * 1.1: Original. 231 * 1.2: Add Power Management 232 * 1.3: Add vblank support 233 * 1.4: Fix cmdbuffer path, add heap destroy 234 * 1.5: Add vblank pipe configuration 235 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 236 * - Support vertical blank on secondary display pipe 237 */ 238 #define DRIVER_MAJOR 1 239 #define DRIVER_MINOR 6 240 #define DRIVER_PATCHLEVEL 0 241 242 struct intel_overlay; 243 struct intel_overlay_error_state; 244 245 struct sdvo_device_mapping { 246 u8 initialized; 247 u8 dvo_port; 248 u8 slave_addr; 249 u8 dvo_wiring; 250 u8 i2c_pin; 251 u8 ddc_pin; 252 }; 253 254 struct intel_connector; 255 struct intel_encoder; 256 struct intel_atomic_state; 257 struct intel_cdclk_config; 258 struct intel_cdclk_state; 259 struct intel_cdclk_vals; 260 struct intel_initial_plane_config; 261 struct intel_crtc; 262 struct intel_limit; 263 struct dpll; 264 265 struct drm_i915_display_funcs { 266 void (*get_cdclk)(struct drm_i915_private *dev_priv, 267 struct intel_cdclk_config *cdclk_config); 268 void (*set_cdclk)(struct drm_i915_private *dev_priv, 269 const struct intel_cdclk_config *cdclk_config, 270 enum pipe pipe); 271 int (*get_fifo_size)(struct drm_i915_private *dev_priv, 272 enum i9xx_plane_id i9xx_plane); 273 int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state); 274 int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state); 275 void (*initial_watermarks)(struct intel_atomic_state *state, 276 struct intel_crtc *crtc); 277 void (*atomic_update_watermarks)(struct intel_atomic_state *state, 278 struct intel_crtc *crtc); 279 void (*optimize_watermarks)(struct intel_atomic_state *state, 280 struct intel_crtc *crtc); 281 int (*compute_global_watermarks)(struct intel_atomic_state *state); 282 void (*update_wm)(struct intel_crtc *crtc); 283 int (*modeset_calc_cdclk)(struct intel_cdclk_state *state); 284 u8 (*calc_voltage_level)(int cdclk); 285 /* Returns the active state of the crtc, and if the crtc is active, 286 * fills out the pipe-config with the hw state. */ 287 bool (*get_pipe_config)(struct intel_crtc *, 288 struct intel_crtc_state *); 289 void (*get_initial_plane_config)(struct intel_crtc *, 290 struct intel_initial_plane_config *); 291 int (*crtc_compute_clock)(struct intel_crtc *crtc, 292 struct intel_crtc_state *crtc_state); 293 void (*crtc_enable)(struct intel_atomic_state *state, 294 struct intel_crtc *crtc); 295 void (*crtc_disable)(struct intel_atomic_state *state, 296 struct intel_crtc *crtc); 297 void (*commit_modeset_enables)(struct intel_atomic_state *state); 298 void (*commit_modeset_disables)(struct intel_atomic_state *state); 299 void (*audio_codec_enable)(struct intel_encoder *encoder, 300 const struct intel_crtc_state *crtc_state, 301 const struct drm_connector_state *conn_state); 302 void (*audio_codec_disable)(struct intel_encoder *encoder, 303 const struct intel_crtc_state *old_crtc_state, 304 const struct drm_connector_state *old_conn_state); 305 void (*fdi_link_train)(struct intel_crtc *crtc, 306 const struct intel_crtc_state *crtc_state); 307 void (*init_clock_gating)(struct drm_i915_private *dev_priv); 308 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); 309 /* clock updates for mode set */ 310 /* cursor updates */ 311 /* render clock increase/decrease */ 312 /* display clock increase/decrease */ 313 /* pll clock increase/decrease */ 314 315 int (*color_check)(struct intel_crtc_state *crtc_state); 316 /* 317 * Program double buffered color management registers during 318 * vblank evasion. The registers should then latch during the 319 * next vblank start, alongside any other double buffered registers 320 * involved with the same commit. 321 */ 322 void (*color_commit)(const struct intel_crtc_state *crtc_state); 323 /* 324 * Load LUTs (and other single buffered color management 325 * registers). Will (hopefully) be called during the vblank 326 * following the latching of any double buffered registers 327 * involved with the same commit. 328 */ 329 void (*load_luts)(const struct intel_crtc_state *crtc_state); 330 void (*read_luts)(struct intel_crtc_state *crtc_state); 331 }; 332 333 struct intel_csr { 334 struct work_struct work; 335 const char *fw_path; 336 u32 required_version; 337 u32 max_fw_size; /* bytes */ 338 u32 *dmc_payload; 339 u32 dmc_fw_size; /* dwords */ 340 u32 version; 341 u32 mmio_count; 342 i915_reg_t mmioaddr[20]; 343 u32 mmiodata[20]; 344 u32 dc_state; 345 u32 target_dc_state; 346 u32 allowed_dc_mask; 347 intel_wakeref_t wakeref; 348 }; 349 350 enum i915_cache_level { 351 I915_CACHE_NONE = 0, 352 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ 353 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc 354 caches, eg sampler/render caches, and the 355 large Last-Level-Cache. LLC is coherent with 356 the CPU, but L3 is only visible to the GPU. */ 357 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ 358 }; 359 360 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */ 361 362 struct intel_fbc { 363 /* This is always the inner lock when overlapping with struct_mutex and 364 * it's the outer lock when overlapping with stolen_lock. */ 365 struct mutex lock; 366 unsigned threshold; 367 unsigned int possible_framebuffer_bits; 368 unsigned int busy_bits; 369 struct intel_crtc *crtc; 370 371 struct drm_mm_node compressed_fb; 372 struct drm_mm_node *compressed_llb; 373 374 bool false_color; 375 376 bool active; 377 bool activated; 378 bool flip_pending; 379 380 bool underrun_detected; 381 struct work_struct underrun_work; 382 383 /* 384 * Due to the atomic rules we can't access some structures without the 385 * appropriate locking, so we cache information here in order to avoid 386 * these problems. 387 */ 388 struct intel_fbc_state_cache { 389 struct { 390 unsigned int mode_flags; 391 u32 hsw_bdw_pixel_rate; 392 } crtc; 393 394 struct { 395 unsigned int rotation; 396 int src_w; 397 int src_h; 398 bool visible; 399 /* 400 * Display surface base address adjustement for 401 * pageflips. Note that on gen4+ this only adjusts up 402 * to a tile, offsets within a tile are handled in 403 * the hw itself (with the TILEOFF register). 404 */ 405 int adjusted_x; 406 int adjusted_y; 407 408 int y; 409 410 u16 pixel_blend_mode; 411 } plane; 412 413 struct { 414 const struct drm_format_info *format; 415 unsigned int stride; 416 } fb; 417 u16 gen9_wa_cfb_stride; 418 s8 fence_id; 419 } state_cache; 420 421 /* 422 * This structure contains everything that's relevant to program the 423 * hardware registers. When we want to figure out if we need to disable 424 * and re-enable FBC for a new configuration we just check if there's 425 * something different in the struct. The genx_fbc_activate functions 426 * are supposed to read from it in order to program the registers. 427 */ 428 struct intel_fbc_reg_params { 429 struct { 430 enum pipe pipe; 431 enum i9xx_plane_id i9xx_plane; 432 unsigned int fence_y_offset; 433 } crtc; 434 435 struct { 436 const struct drm_format_info *format; 437 unsigned int stride; 438 } fb; 439 440 int cfb_size; 441 u16 gen9_wa_cfb_stride; 442 s8 fence_id; 443 bool plane_visible; 444 } params; 445 446 const char *no_fbc_reason; 447 }; 448 449 /* 450 * HIGH_RR is the highest eDP panel refresh rate read from EDID 451 * LOW_RR is the lowest eDP panel refresh rate found from EDID 452 * parsing for same resolution. 453 */ 454 enum drrs_refresh_rate_type { 455 DRRS_HIGH_RR, 456 DRRS_LOW_RR, 457 DRRS_MAX_RR, /* RR count */ 458 }; 459 460 enum drrs_support_type { 461 DRRS_NOT_SUPPORTED = 0, 462 STATIC_DRRS_SUPPORT = 1, 463 SEAMLESS_DRRS_SUPPORT = 2 464 }; 465 466 struct intel_dp; 467 struct i915_drrs { 468 struct mutex mutex; 469 struct delayed_work work; 470 struct intel_dp *dp; 471 unsigned busy_frontbuffer_bits; 472 enum drrs_refresh_rate_type refresh_rate_type; 473 enum drrs_support_type type; 474 }; 475 476 struct i915_psr { 477 struct mutex lock; 478 479 #define I915_PSR_DEBUG_MODE_MASK 0x0f 480 #define I915_PSR_DEBUG_DEFAULT 0x00 481 #define I915_PSR_DEBUG_DISABLE 0x01 482 #define I915_PSR_DEBUG_ENABLE 0x02 483 #define I915_PSR_DEBUG_FORCE_PSR1 0x03 484 #define I915_PSR_DEBUG_IRQ 0x10 485 486 u32 debug; 487 bool sink_support; 488 bool enabled; 489 struct intel_dp *dp; 490 enum pipe pipe; 491 enum transcoder transcoder; 492 bool active; 493 struct work_struct work; 494 unsigned busy_frontbuffer_bits; 495 bool sink_psr2_support; 496 bool link_standby; 497 bool colorimetry_support; 498 bool psr2_enabled; 499 u8 sink_sync_latency; 500 ktime_t last_entry_attempt; 501 ktime_t last_exit; 502 bool sink_not_reliable; 503 bool irq_aux_error; 504 u16 su_x_granularity; 505 bool dc3co_enabled; 506 u32 dc3co_exit_delay; 507 struct delayed_work dc3co_work; 508 bool force_mode_changed; 509 }; 510 511 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 512 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 513 #define QUIRK_BACKLIGHT_PRESENT (1<<3) 514 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) 515 #define QUIRK_INCREASE_T12_DELAY (1<<6) 516 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7) 517 518 struct intel_fbdev; 519 struct intel_fbc_work; 520 521 struct intel_gmbus { 522 struct i2c_adapter adapter; 523 #define GMBUS_FORCE_BIT_RETRY (1U << 31) 524 u32 force_bit; 525 u32 reg0; 526 i915_reg_t gpio_reg; 527 struct i2c_algo_bit_data bit_algo; 528 struct drm_i915_private *dev_priv; 529 }; 530 531 struct i915_suspend_saved_registers { 532 u32 saveDSPARB; 533 u32 saveFBC_CONTROL; 534 u32 saveCACHE_MODE_0; 535 u32 saveMI_ARB_STATE; 536 u32 saveSWF0[16]; 537 u32 saveSWF1[16]; 538 u32 saveSWF3[3]; 539 u64 saveFENCE[I915_MAX_NUM_FENCES]; 540 u32 savePCH_PORT_HOTPLUG; 541 u16 saveGCDGMBUS; 542 }; 543 544 struct vlv_s0ix_state; 545 546 #define MAX_L3_SLICES 2 547 struct intel_l3_parity { 548 u32 *remap_info[MAX_L3_SLICES]; 549 struct work_struct error_work; 550 int which_slice; 551 }; 552 553 struct i915_gem_mm { 554 /** Memory allocator for GTT stolen memory */ 555 struct drm_mm stolen; 556 /** Protects the usage of the GTT stolen memory allocator. This is 557 * always the inner lock when overlapping with struct_mutex. */ 558 struct mutex stolen_lock; 559 560 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ 561 spinlock_t obj_lock; 562 563 /** 564 * List of objects which are purgeable. 565 */ 566 struct list_head purge_list; 567 568 /** 569 * List of objects which have allocated pages and are shrinkable. 570 */ 571 struct list_head shrink_list; 572 573 /** 574 * List of objects which are pending destruction. 575 */ 576 struct llist_head free_list; 577 struct work_struct free_work; 578 /** 579 * Count of objects pending destructions. Used to skip needlessly 580 * waiting on an RCU barrier if no objects are waiting to be freed. 581 */ 582 atomic_t free_count; 583 584 /** 585 * Small stash of WC pages 586 */ 587 struct pagestash wc_stash; 588 589 /** 590 * tmpfs instance used for shmem backed objects 591 */ 592 struct vfsmount *gemfs; 593 594 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN]; 595 596 struct notifier_block oom_notifier; 597 struct notifier_block vmap_notifier; 598 struct shrinker shrinker; 599 600 /** 601 * Workqueue to fault in userptr pages, flushed by the execbuf 602 * when required but otherwise left to userspace to try again 603 * on EAGAIN. 604 */ 605 struct workqueue_struct *userptr_wq; 606 607 /* shrinker accounting, also useful for userland debugging */ 608 u64 shrink_memory; 609 u32 shrink_count; 610 }; 611 612 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */ 613 614 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */ 615 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */ 616 617 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */ 618 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */ 619 620 #define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */ 621 622 /* Amount of SAGV/QGV points, BSpec precisely defines this */ 623 #define I915_NUM_QGV_POINTS 8 624 625 struct ddi_vbt_port_info { 626 /* Non-NULL if port present. */ 627 const struct child_device_config *child; 628 629 int max_tmds_clock; 630 631 /* This is an index in the HDMI/DVI DDI buffer translation table. */ 632 u8 hdmi_level_shift; 633 u8 hdmi_level_shift_set:1; 634 635 u8 supports_dvi:1; 636 u8 supports_hdmi:1; 637 u8 supports_dp:1; 638 u8 supports_edp:1; 639 u8 supports_typec_usb:1; 640 u8 supports_tbt:1; 641 642 u8 alternate_aux_channel; 643 u8 alternate_ddc_pin; 644 645 u8 dp_boost_level; 646 u8 hdmi_boost_level; 647 int dp_max_link_rate; /* 0 for not limited by VBT */ 648 }; 649 650 enum psr_lines_to_wait { 651 PSR_0_LINES_TO_WAIT = 0, 652 PSR_1_LINE_TO_WAIT, 653 PSR_4_LINES_TO_WAIT, 654 PSR_8_LINES_TO_WAIT 655 }; 656 657 struct intel_vbt_data { 658 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 659 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 660 661 /* Feature bits */ 662 unsigned int int_tv_support:1; 663 unsigned int lvds_dither:1; 664 unsigned int int_crt_support:1; 665 unsigned int lvds_use_ssc:1; 666 unsigned int int_lvds_support:1; 667 unsigned int display_clock_mode:1; 668 unsigned int fdi_rx_polarity_inverted:1; 669 unsigned int panel_type:4; 670 int lvds_ssc_freq; 671 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 672 enum drm_panel_orientation orientation; 673 674 enum drrs_support_type drrs_type; 675 676 struct { 677 int rate; 678 int lanes; 679 int preemphasis; 680 int vswing; 681 bool low_vswing; 682 bool initialized; 683 int bpp; 684 struct edp_power_seq pps; 685 } edp; 686 687 struct { 688 bool enable; 689 bool full_link; 690 bool require_aux_wakeup; 691 int idle_frames; 692 enum psr_lines_to_wait lines_to_wait; 693 int tp1_wakeup_time_us; 694 int tp2_tp3_wakeup_time_us; 695 int psr2_tp2_tp3_wakeup_time_us; 696 } psr; 697 698 struct { 699 u16 pwm_freq_hz; 700 bool present; 701 bool active_low_pwm; 702 u8 min_brightness; /* min_brightness/255 of max */ 703 u8 controller; /* brightness controller number */ 704 enum intel_backlight_type type; 705 } backlight; 706 707 /* MIPI DSI */ 708 struct { 709 u16 panel_id; 710 struct mipi_config *config; 711 struct mipi_pps_data *pps; 712 u16 bl_ports; 713 u16 cabc_ports; 714 u8 seq_version; 715 u32 size; 716 u8 *data; 717 const u8 *sequence[MIPI_SEQ_MAX]; 718 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */ 719 enum drm_panel_orientation orientation; 720 } dsi; 721 722 int crt_ddc_pin; 723 724 struct list_head display_devices; 725 726 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; 727 struct sdvo_device_mapping sdvo_mappings[2]; 728 }; 729 730 enum intel_ddb_partitioning { 731 INTEL_DDB_PART_1_2, 732 INTEL_DDB_PART_5_6, /* IVB+ */ 733 }; 734 735 struct intel_wm_level { 736 bool enable; 737 u32 pri_val; 738 u32 spr_val; 739 u32 cur_val; 740 u32 fbc_val; 741 }; 742 743 struct ilk_wm_values { 744 u32 wm_pipe[3]; 745 u32 wm_lp[3]; 746 u32 wm_lp_spr[3]; 747 bool enable_fbc_wm; 748 enum intel_ddb_partitioning partitioning; 749 }; 750 751 struct g4x_pipe_wm { 752 u16 plane[I915_MAX_PLANES]; 753 u16 fbc; 754 }; 755 756 struct g4x_sr_wm { 757 u16 plane; 758 u16 cursor; 759 u16 fbc; 760 }; 761 762 struct vlv_wm_ddl_values { 763 u8 plane[I915_MAX_PLANES]; 764 }; 765 766 struct vlv_wm_values { 767 struct g4x_pipe_wm pipe[3]; 768 struct g4x_sr_wm sr; 769 struct vlv_wm_ddl_values ddl[3]; 770 u8 level; 771 bool cxsr; 772 }; 773 774 struct g4x_wm_values { 775 struct g4x_pipe_wm pipe[2]; 776 struct g4x_sr_wm sr; 777 struct g4x_sr_wm hpll; 778 bool cxsr; 779 bool hpll_en; 780 bool fbc_en; 781 }; 782 783 struct skl_ddb_entry { 784 u16 start, end; /* in number of blocks, 'end' is exclusive */ 785 }; 786 787 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry) 788 { 789 return entry->end - entry->start; 790 } 791 792 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, 793 const struct skl_ddb_entry *e2) 794 { 795 if (e1->start == e2->start && e1->end == e2->end) 796 return true; 797 798 return false; 799 } 800 801 struct skl_wm_level { 802 u16 min_ddb_alloc; 803 u16 plane_res_b; 804 u8 plane_res_l; 805 bool plane_en; 806 bool ignore_lines; 807 }; 808 809 /* Stores plane specific WM parameters */ 810 struct skl_wm_params { 811 bool x_tiled, y_tiled; 812 bool rc_surface; 813 bool is_planar; 814 u32 width; 815 u8 cpp; 816 u32 plane_pixel_rate; 817 u32 y_min_scanlines; 818 u32 plane_bytes_per_line; 819 uint_fixed_16_16_t plane_blocks_per_line; 820 uint_fixed_16_16_t y_tile_minimum; 821 u32 linetime_us; 822 u32 dbuf_block_size; 823 }; 824 825 enum intel_pipe_crc_source { 826 INTEL_PIPE_CRC_SOURCE_NONE, 827 INTEL_PIPE_CRC_SOURCE_PLANE1, 828 INTEL_PIPE_CRC_SOURCE_PLANE2, 829 INTEL_PIPE_CRC_SOURCE_PLANE3, 830 INTEL_PIPE_CRC_SOURCE_PLANE4, 831 INTEL_PIPE_CRC_SOURCE_PLANE5, 832 INTEL_PIPE_CRC_SOURCE_PLANE6, 833 INTEL_PIPE_CRC_SOURCE_PLANE7, 834 INTEL_PIPE_CRC_SOURCE_PIPE, 835 /* TV/DP on pre-gen5/vlv can't use the pipe source. */ 836 INTEL_PIPE_CRC_SOURCE_TV, 837 INTEL_PIPE_CRC_SOURCE_DP_B, 838 INTEL_PIPE_CRC_SOURCE_DP_C, 839 INTEL_PIPE_CRC_SOURCE_DP_D, 840 INTEL_PIPE_CRC_SOURCE_AUTO, 841 INTEL_PIPE_CRC_SOURCE_MAX, 842 }; 843 844 #define INTEL_PIPE_CRC_ENTRIES_NR 128 845 struct intel_pipe_crc { 846 spinlock_t lock; 847 int skipped; 848 enum intel_pipe_crc_source source; 849 }; 850 851 struct i915_frontbuffer_tracking { 852 spinlock_t lock; 853 854 /* 855 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 856 * scheduled flips. 857 */ 858 unsigned busy_bits; 859 unsigned flip_bits; 860 }; 861 862 struct i915_virtual_gpu { 863 struct mutex lock; /* serialises sending of g2v_notify command pkts */ 864 bool active; 865 u32 caps; 866 }; 867 868 /* used in computing the new watermarks state */ 869 struct intel_wm_config { 870 unsigned int num_pipes_active; 871 bool sprites_enabled; 872 bool sprites_scaled; 873 }; 874 875 struct intel_cdclk_config { 876 unsigned int cdclk, vco, ref, bypass; 877 u8 voltage_level; 878 }; 879 880 struct i915_selftest_stash { 881 atomic_t counter; 882 }; 883 884 struct drm_i915_private { 885 struct drm_device drm; 886 887 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */ 888 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ 889 struct intel_driver_caps caps; 890 891 /** 892 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and 893 * end of stolen which we can optionally use to create GEM objects 894 * backed by stolen memory. Note that stolen_usable_size tells us 895 * exactly how much of this we are actually allowed to use, given that 896 * some portion of it is in fact reserved for use by hardware functions. 897 */ 898 struct resource dsm; 899 /** 900 * Reseved portion of Data Stolen Memory 901 */ 902 struct resource dsm_reserved; 903 904 /* 905 * Stolen memory is segmented in hardware with different portions 906 * offlimits to certain functions. 907 * 908 * The drm_mm is initialised to the total accessible range, as found 909 * from the PCI config. On Broadwell+, this is further restricted to 910 * avoid the first page! The upper end of stolen memory is reserved for 911 * hardware functions and similarly removed from the accessible range. 912 */ 913 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */ 914 915 struct intel_uncore uncore; 916 struct intel_uncore_mmio_debug mmio_debug; 917 918 struct i915_virtual_gpu vgpu; 919 920 struct intel_gvt *gvt; 921 922 struct intel_wopcm wopcm; 923 924 struct intel_csr csr; 925 926 struct intel_gmbus gmbus[GMBUS_NUM_PINS]; 927 928 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 929 * controller on different i2c buses. */ 930 struct mutex gmbus_mutex; 931 932 /** 933 * Base address of where the gmbus and gpio blocks are located (either 934 * on PCH or on SoC for platforms without PCH). 935 */ 936 u32 gpio_mmio_base; 937 938 u32 hsw_psr_mmio_adjust; 939 940 /* MMIO base address for MIPI regs */ 941 u32 mipi_mmio_base; 942 943 u32 pps_mmio_base; 944 945 wait_queue_head_t gmbus_wait_queue; 946 947 struct pci_dev *bridge_dev; 948 949 struct intel_engine_cs *engine[I915_NUM_ENGINES]; 950 struct rb_root uabi_engines; 951 952 struct resource mch_res; 953 954 /* protects the irq masks */ 955 spinlock_t irq_lock; 956 957 bool display_irqs_enabled; 958 959 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ 960 struct pm_qos_request pm_qos; 961 962 /* Sideband mailbox protection */ 963 struct mutex sb_lock; 964 struct pm_qos_request sb_qos; 965 966 /** Cached value of IMR to avoid reads in updating the bitfield */ 967 union { 968 u32 irq_mask; 969 u32 de_irq_mask[I915_MAX_PIPES]; 970 }; 971 u32 pipestat_irq_mask[I915_MAX_PIPES]; 972 973 struct i915_hotplug hotplug; 974 struct intel_fbc fbc; 975 struct i915_drrs drrs; 976 struct intel_opregion opregion; 977 struct intel_vbt_data vbt; 978 979 bool preserve_bios_swizzle; 980 981 /* overlay */ 982 struct intel_overlay *overlay; 983 984 /* backlight registers and fields in struct intel_panel */ 985 struct mutex backlight_lock; 986 987 /* protects panel power sequencer state */ 988 struct mutex pps_mutex; 989 990 unsigned int fsb_freq, mem_freq, is_ddr3; 991 unsigned int skl_preferred_vco_freq; 992 unsigned int max_cdclk_freq; 993 994 unsigned int max_dotclk_freq; 995 unsigned int hpll_freq; 996 unsigned int fdi_pll_freq; 997 unsigned int czclk_freq; 998 999 struct { 1000 /* The current hardware cdclk configuration */ 1001 struct intel_cdclk_config hw; 1002 1003 /* cdclk, divider, and ratio table from bspec */ 1004 const struct intel_cdclk_vals *table; 1005 1006 struct intel_global_obj obj; 1007 } cdclk; 1008 1009 /** 1010 * wq - Driver workqueue for GEM. 1011 * 1012 * NOTE: Work items scheduled here are not allowed to grab any modeset 1013 * locks, for otherwise the flushing done in the pageflip code will 1014 * result in deadlocks. 1015 */ 1016 struct workqueue_struct *wq; 1017 1018 /* ordered wq for modesets */ 1019 struct workqueue_struct *modeset_wq; 1020 /* unbound hipri wq for page flips/plane updates */ 1021 struct workqueue_struct *flip_wq; 1022 1023 /* Display functions */ 1024 struct drm_i915_display_funcs display; 1025 1026 /* PCH chipset type */ 1027 enum intel_pch pch_type; 1028 unsigned short pch_id; 1029 1030 unsigned long quirks; 1031 1032 struct drm_atomic_state *modeset_restore_state; 1033 struct drm_modeset_acquire_ctx reset_ctx; 1034 1035 struct i915_ggtt ggtt; /* VM representing the global address space */ 1036 1037 struct i915_gem_mm mm; 1038 DECLARE_HASHTABLE(mm_structs, 7); 1039 struct mutex mm_lock; 1040 1041 /* Kernel Modesetting */ 1042 1043 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; 1044 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; 1045 1046 #ifdef CONFIG_DEBUG_FS 1047 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; 1048 #endif 1049 1050 /* dpll and cdclk state is protected by connection_mutex */ 1051 int num_shared_dpll; 1052 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 1053 const struct intel_dpll_mgr *dpll_mgr; 1054 1055 /* 1056 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll. 1057 * Must be global rather than per dpll, because on some platforms 1058 * plls share registers. 1059 */ 1060 struct mutex dpll_lock; 1061 1062 struct list_head global_obj_list; 1063 1064 /* 1065 * For reading active_pipes holding any crtc lock is 1066 * sufficient, for writing must hold all of them. 1067 */ 1068 u8 active_pipes; 1069 1070 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; 1071 1072 struct i915_wa_list gt_wa_list; 1073 1074 struct i915_frontbuffer_tracking fb_tracking; 1075 1076 struct intel_atomic_helper { 1077 struct llist_head free_list; 1078 struct work_struct free_work; 1079 } atomic_helper; 1080 1081 u16 orig_clock; 1082 1083 bool mchbar_need_disable; 1084 1085 struct intel_l3_parity l3_parity; 1086 1087 /* 1088 * edram size in MB. 1089 * Cannot be determined by PCIID. You must always read a register. 1090 */ 1091 u32 edram_size_mb; 1092 1093 struct i915_power_domains power_domains; 1094 1095 struct i915_psr psr; 1096 1097 struct i915_gpu_error gpu_error; 1098 1099 struct drm_i915_gem_object *vlv_pctx; 1100 1101 /* list of fbdev register on this device */ 1102 struct intel_fbdev *fbdev; 1103 struct work_struct fbdev_suspend_work; 1104 1105 struct drm_property *broadcast_rgb_property; 1106 struct drm_property *force_audio_property; 1107 1108 /* hda/i915 audio component */ 1109 struct i915_audio_component *audio_component; 1110 bool audio_component_registered; 1111 /** 1112 * av_mutex - mutex for audio/video sync 1113 * 1114 */ 1115 struct mutex av_mutex; 1116 int audio_power_refcount; 1117 u32 audio_freq_cntrl; 1118 1119 u32 fdi_rx_config; 1120 1121 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ 1122 u32 chv_phy_control; 1123 /* 1124 * Shadows for CHV DPLL_MD regs to keep the state 1125 * checker somewhat working in the presence hardware 1126 * crappiness (can't read out DPLL_MD for pipes B & C). 1127 */ 1128 u32 chv_dpll_md[I915_MAX_PIPES]; 1129 u32 bxt_phy_grc; 1130 1131 u32 suspend_count; 1132 bool power_domains_suspended; 1133 struct i915_suspend_saved_registers regfile; 1134 struct vlv_s0ix_state *vlv_s0ix_state; 1135 1136 enum { 1137 I915_SAGV_UNKNOWN = 0, 1138 I915_SAGV_DISABLED, 1139 I915_SAGV_ENABLED, 1140 I915_SAGV_NOT_CONTROLLED 1141 } sagv_status; 1142 1143 u32 sagv_block_time_us; 1144 1145 struct { 1146 /* 1147 * Raw watermark latency values: 1148 * in 0.1us units for WM0, 1149 * in 0.5us units for WM1+. 1150 */ 1151 /* primary */ 1152 u16 pri_latency[5]; 1153 /* sprite */ 1154 u16 spr_latency[5]; 1155 /* cursor */ 1156 u16 cur_latency[5]; 1157 /* 1158 * Raw watermark memory latency values 1159 * for SKL for all 8 levels 1160 * in 1us units. 1161 */ 1162 u16 skl_latency[8]; 1163 1164 /* current hardware state */ 1165 union { 1166 struct ilk_wm_values hw; 1167 struct vlv_wm_values vlv; 1168 struct g4x_wm_values g4x; 1169 }; 1170 1171 u8 max_level; 1172 1173 /* 1174 * Should be held around atomic WM register writing; also 1175 * protects * intel_crtc->wm.active and 1176 * crtc_state->wm.need_postvbl_update. 1177 */ 1178 struct mutex wm_mutex; 1179 1180 /* 1181 * Set during HW readout of watermarks/DDB. Some platforms 1182 * need to know when we're still using BIOS-provided values 1183 * (which we don't fully trust). 1184 */ 1185 bool distrust_bios_wm; 1186 } wm; 1187 1188 u8 enabled_dbuf_slices_mask; /* GEN11 has configurable 2 slices */ 1189 1190 struct dram_info { 1191 bool valid; 1192 bool is_16gb_dimm; 1193 u8 num_channels; 1194 u8 ranks; 1195 u32 bandwidth_kbps; 1196 bool symmetric_memory; 1197 enum intel_dram_type { 1198 INTEL_DRAM_UNKNOWN, 1199 INTEL_DRAM_DDR3, 1200 INTEL_DRAM_DDR4, 1201 INTEL_DRAM_LPDDR3, 1202 INTEL_DRAM_LPDDR4 1203 } type; 1204 } dram_info; 1205 1206 struct intel_bw_info { 1207 /* for each QGV point */ 1208 unsigned int deratedbw[I915_NUM_QGV_POINTS]; 1209 u8 num_qgv_points; 1210 u8 num_planes; 1211 } max_bw[6]; 1212 1213 struct intel_global_obj bw_obj; 1214 1215 struct intel_runtime_pm runtime_pm; 1216 1217 struct i915_perf perf; 1218 1219 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ 1220 struct intel_gt gt; 1221 1222 struct { 1223 struct i915_gem_contexts { 1224 spinlock_t lock; /* locks list */ 1225 struct list_head list; 1226 1227 struct llist_head free_list; 1228 struct work_struct free_work; 1229 } contexts; 1230 1231 /* 1232 * We replace the local file with a global mappings as the 1233 * backing storage for the mmap is on the device and not 1234 * on the struct file, and we do not want to prolong the 1235 * lifetime of the local fd. To minimise the number of 1236 * anonymous inodes we create, we use a global singleton to 1237 * share the global mapping. 1238 */ 1239 struct file *mmap_singleton; 1240 } gem; 1241 1242 u8 pch_ssc_use; 1243 1244 /* For i915gm/i945gm vblank irq workaround */ 1245 u8 vblank_enabled; 1246 1247 /* perform PHY state sanity checks? */ 1248 bool chv_phy_assert[2]; 1249 1250 bool ipc_enabled; 1251 1252 /* Used to save the pipe-to-encoder mapping for audio */ 1253 struct intel_encoder *av_enc_map[I915_MAX_PIPES]; 1254 1255 /* necessary resource sharing with HDMI LPE audio driver. */ 1256 struct { 1257 struct platform_device *platdev; 1258 int irq; 1259 } lpe_audio; 1260 1261 struct i915_pmu pmu; 1262 1263 struct i915_hdcp_comp_master *hdcp_master; 1264 bool hdcp_comp_added; 1265 1266 /* Mutex to protect the above hdcp component related values. */ 1267 struct mutex hdcp_comp_mutex; 1268 1269 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;) 1270 1271 /* 1272 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 1273 * will be rejected. Instead look for a better place. 1274 */ 1275 }; 1276 1277 struct dram_dimm_info { 1278 u8 size, width, ranks; 1279 }; 1280 1281 struct dram_channel_info { 1282 struct dram_dimm_info dimm_l, dimm_s; 1283 u8 ranks; 1284 bool is_16gb_dimm; 1285 }; 1286 1287 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 1288 { 1289 return container_of(dev, struct drm_i915_private, drm); 1290 } 1291 1292 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) 1293 { 1294 return dev_get_drvdata(kdev); 1295 } 1296 1297 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) 1298 { 1299 return pci_get_drvdata(pdev); 1300 } 1301 1302 /* Simple iterator over all initialised engines */ 1303 #define for_each_engine(engine__, dev_priv__, id__) \ 1304 for ((id__) = 0; \ 1305 (id__) < I915_NUM_ENGINES; \ 1306 (id__)++) \ 1307 for_each_if ((engine__) = (dev_priv__)->engine[(id__)]) 1308 1309 /* Iterator over subset of engines selected by mask */ 1310 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \ 1311 for ((tmp__) = (mask__) & INTEL_INFO((gt__)->i915)->engine_mask; \ 1312 (tmp__) ? \ 1313 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \ 1314 0;) 1315 1316 #define rb_to_uabi_engine(rb) \ 1317 rb_entry_safe(rb, struct intel_engine_cs, uabi_node) 1318 1319 #define for_each_uabi_engine(engine__, i915__) \ 1320 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\ 1321 (engine__); \ 1322 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 1323 1324 #define I915_GTT_OFFSET_NONE ((u32)-1) 1325 1326 /* 1327 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is 1328 * considered to be the frontbuffer for the given plane interface-wise. This 1329 * doesn't mean that the hw necessarily already scans it out, but that any 1330 * rendering (by the cpu or gpu) will land in the frontbuffer eventually. 1331 * 1332 * We have one bit per pipe and per scanout plane type. 1333 */ 1334 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 1335 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \ 1336 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \ 1337 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \ 1338 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \ 1339 }) 1340 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ 1341 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) 1342 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ 1343 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \ 1344 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) 1345 1346 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info) 1347 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) 1348 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) 1349 1350 #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen) 1351 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id) 1352 1353 #define REVID_FOREVER 0xff 1354 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) 1355 1356 #define INTEL_GEN_MASK(s, e) ( \ 1357 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \ 1358 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \ 1359 GENMASK((e) - 1, (s) - 1)) 1360 1361 /* Returns true if Gen is in inclusive range [Start, End] */ 1362 #define IS_GEN_RANGE(dev_priv, s, e) \ 1363 (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e)))) 1364 1365 #define IS_GEN(dev_priv, n) \ 1366 (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \ 1367 INTEL_INFO(dev_priv)->gen == (n)) 1368 1369 #define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb) 1370 1371 /* 1372 * Return true if revision is in range [since,until] inclusive. 1373 * 1374 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. 1375 */ 1376 #define IS_REVID(p, since, until) \ 1377 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) 1378 1379 static __always_inline unsigned int 1380 __platform_mask_index(const struct intel_runtime_info *info, 1381 enum intel_platform p) 1382 { 1383 const unsigned int pbits = 1384 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 1385 1386 /* Expand the platform_mask array if this fails. */ 1387 BUILD_BUG_ON(INTEL_MAX_PLATFORMS > 1388 pbits * ARRAY_SIZE(info->platform_mask)); 1389 1390 return p / pbits; 1391 } 1392 1393 static __always_inline unsigned int 1394 __platform_mask_bit(const struct intel_runtime_info *info, 1395 enum intel_platform p) 1396 { 1397 const unsigned int pbits = 1398 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 1399 1400 return p % pbits + INTEL_SUBPLATFORM_BITS; 1401 } 1402 1403 static inline u32 1404 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p) 1405 { 1406 const unsigned int pi = __platform_mask_index(info, p); 1407 1408 return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS; 1409 } 1410 1411 static __always_inline bool 1412 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p) 1413 { 1414 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 1415 const unsigned int pi = __platform_mask_index(info, p); 1416 const unsigned int pb = __platform_mask_bit(info, p); 1417 1418 BUILD_BUG_ON(!__builtin_constant_p(p)); 1419 1420 return info->platform_mask[pi] & BIT(pb); 1421 } 1422 1423 static __always_inline bool 1424 IS_SUBPLATFORM(const struct drm_i915_private *i915, 1425 enum intel_platform p, unsigned int s) 1426 { 1427 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 1428 const unsigned int pi = __platform_mask_index(info, p); 1429 const unsigned int pb = __platform_mask_bit(info, p); 1430 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1; 1431 const u32 mask = info->platform_mask[pi]; 1432 1433 BUILD_BUG_ON(!__builtin_constant_p(p)); 1434 BUILD_BUG_ON(!__builtin_constant_p(s)); 1435 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS); 1436 1437 /* Shift and test on the MSB position so sign flag can be used. */ 1438 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); 1439 } 1440 1441 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile) 1442 #define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx) 1443 1444 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) 1445 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) 1446 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) 1447 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) 1448 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) 1449 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM) 1450 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) 1451 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM) 1452 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) 1453 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM) 1454 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) 1455 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) 1456 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) 1457 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) 1458 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) 1459 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE) 1460 #define IS_IRONLAKE_M(dev_priv) \ 1461 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv)) 1462 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) 1463 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ 1464 INTEL_INFO(dev_priv)->gt == 1) 1465 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) 1466 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) 1467 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) 1468 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) 1469 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) 1470 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) 1471 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) 1472 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) 1473 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) 1474 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) 1475 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) 1476 #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) 1477 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) 1478 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ 1479 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) 1480 #define IS_BDW_ULT(dev_priv) \ 1481 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) 1482 #define IS_BDW_ULX(dev_priv) \ 1483 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX) 1484 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ 1485 INTEL_INFO(dev_priv)->gt == 3) 1486 #define IS_HSW_ULT(dev_priv) \ 1487 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) 1488 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ 1489 INTEL_INFO(dev_priv)->gt == 3) 1490 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \ 1491 INTEL_INFO(dev_priv)->gt == 1) 1492 /* ULX machines are also considered ULT. */ 1493 #define IS_HSW_ULX(dev_priv) \ 1494 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) 1495 #define IS_SKL_ULT(dev_priv) \ 1496 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) 1497 #define IS_SKL_ULX(dev_priv) \ 1498 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) 1499 #define IS_KBL_ULT(dev_priv) \ 1500 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) 1501 #define IS_KBL_ULX(dev_priv) \ 1502 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) 1503 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1504 INTEL_INFO(dev_priv)->gt == 2) 1505 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1506 INTEL_INFO(dev_priv)->gt == 3) 1507 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1508 INTEL_INFO(dev_priv)->gt == 4) 1509 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ 1510 INTEL_INFO(dev_priv)->gt == 2) 1511 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ 1512 INTEL_INFO(dev_priv)->gt == 3) 1513 #define IS_CFL_ULT(dev_priv) \ 1514 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) 1515 #define IS_CFL_ULX(dev_priv) \ 1516 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX) 1517 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 1518 INTEL_INFO(dev_priv)->gt == 2) 1519 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 1520 INTEL_INFO(dev_priv)->gt == 3) 1521 #define IS_CNL_WITH_PORT_F(dev_priv) \ 1522 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF) 1523 #define IS_ICL_WITH_PORT_F(dev_priv) \ 1524 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) 1525 1526 #define SKL_REVID_A0 0x0 1527 #define SKL_REVID_B0 0x1 1528 #define SKL_REVID_C0 0x2 1529 #define SKL_REVID_D0 0x3 1530 #define SKL_REVID_E0 0x4 1531 #define SKL_REVID_F0 0x5 1532 #define SKL_REVID_G0 0x6 1533 #define SKL_REVID_H0 0x7 1534 1535 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) 1536 1537 #define BXT_REVID_A0 0x0 1538 #define BXT_REVID_A1 0x1 1539 #define BXT_REVID_B0 0x3 1540 #define BXT_REVID_B_LAST 0x8 1541 #define BXT_REVID_C0 0x9 1542 1543 #define IS_BXT_REVID(dev_priv, since, until) \ 1544 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until)) 1545 1546 #define KBL_REVID_A0 0x0 1547 #define KBL_REVID_B0 0x1 1548 #define KBL_REVID_C0 0x2 1549 #define KBL_REVID_D0 0x3 1550 #define KBL_REVID_E0 0x4 1551 1552 #define IS_KBL_REVID(dev_priv, since, until) \ 1553 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until)) 1554 1555 #define GLK_REVID_A0 0x0 1556 #define GLK_REVID_A1 0x1 1557 1558 #define IS_GLK_REVID(dev_priv, since, until) \ 1559 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until)) 1560 1561 #define CNL_REVID_A0 0x0 1562 #define CNL_REVID_B0 0x1 1563 #define CNL_REVID_C0 0x2 1564 1565 #define IS_CNL_REVID(p, since, until) \ 1566 (IS_CANNONLAKE(p) && IS_REVID(p, since, until)) 1567 1568 #define ICL_REVID_A0 0x0 1569 #define ICL_REVID_A2 0x1 1570 #define ICL_REVID_B0 0x3 1571 #define ICL_REVID_B2 0x4 1572 #define ICL_REVID_C0 0x5 1573 1574 #define IS_ICL_REVID(p, since, until) \ 1575 (IS_ICELAKE(p) && IS_REVID(p, since, until)) 1576 1577 #define TGL_REVID_A0 0x0 1578 1579 #define IS_TGL_REVID(p, since, until) \ 1580 (IS_TIGERLAKE(p) && IS_REVID(p, since, until)) 1581 1582 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) 1583 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) 1584 #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) 1585 1586 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id)) 1587 1588 #define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({ \ 1589 unsigned int first__ = (first); \ 1590 unsigned int count__ = (count); \ 1591 (INTEL_INFO(dev_priv)->engine_mask & \ 1592 GENMASK(first__ + count__ - 1, first__)) >> first__; \ 1593 }) 1594 #define VDBOX_MASK(dev_priv) \ 1595 ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS) 1596 #define VEBOX_MASK(dev_priv) \ 1597 ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS) 1598 1599 /* 1600 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution 1601 * All later gens can run the final buffer from the ppgtt 1602 */ 1603 #define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7) 1604 1605 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) 1606 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) 1607 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb) 1608 #define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6) 1609 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \ 1610 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv)) 1611 1612 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical) 1613 1614 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ 1615 (INTEL_INFO(dev_priv)->has_logical_ring_contexts) 1616 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \ 1617 (INTEL_INFO(dev_priv)->has_logical_ring_elsq) 1618 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \ 1619 (INTEL_INFO(dev_priv)->has_logical_ring_preemption) 1620 1621 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) 1622 1623 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type) 1624 #define HAS_PPGTT(dev_priv) \ 1625 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE) 1626 #define HAS_FULL_PPGTT(dev_priv) \ 1627 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL) 1628 1629 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \ 1630 GEM_BUG_ON((sizes) == 0); \ 1631 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \ 1632 }) 1633 1634 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay) 1635 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ 1636 (INTEL_INFO(dev_priv)->display.overlay_needs_physical) 1637 1638 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 1639 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) 1640 1641 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \ 1642 (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9)) 1643 1644 /* WaRsDisableCoarsePowerGating:skl,cnl */ 1645 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ 1646 (IS_CANNONLAKE(dev_priv) || \ 1647 IS_SKL_GT3(dev_priv) || \ 1648 IS_SKL_GT4(dev_priv)) 1649 1650 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4) 1651 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \ 1652 IS_GEMINILAKE(dev_priv) || \ 1653 IS_KABYLAKE(dev_priv)) 1654 1655 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1656 * rows, which changed the alignment requirements and fence programming. 1657 */ 1658 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \ 1659 !(IS_I915G(dev_priv) || \ 1660 IS_I915GM(dev_priv))) 1661 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv) 1662 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug) 1663 1664 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) 1665 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc) 1666 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7) 1667 1668 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) 1669 1670 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) 1671 1672 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) 1673 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg) 1674 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) 1675 #define HAS_TRANSCODER_EDP(dev_priv) (INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_EDP] != 0) 1676 1677 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) 1678 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p) 1679 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ 1680 1681 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps) 1682 1683 #define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr) 1684 1685 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm) 1686 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc) 1687 1688 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc) 1689 1690 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i)) 1691 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM) 1692 1693 #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc) 1694 1695 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu) 1696 1697 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs) 1698 1699 1700 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch) 1701 1702 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9) 1703 1704 /* DPF == dynamic parity feature */ 1705 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf) 1706 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ 1707 2 : HAS_L3_DPF(dev_priv)) 1708 1709 #define GT_FREQUENCY_MULTIPLIER 50 1710 #define GEN9_FREQ_SCALER 3 1711 1712 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask)) 1713 1714 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0) 1715 1716 /* Only valid when HAS_DISPLAY() is true */ 1717 #define INTEL_DISPLAY_ENABLED(dev_priv) (WARN_ON(!HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display) 1718 1719 static inline bool intel_vtd_active(void) 1720 { 1721 #ifdef CONFIG_INTEL_IOMMU 1722 if (intel_iommu_gfx_mapped) 1723 return true; 1724 #endif 1725 return false; 1726 } 1727 1728 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) 1729 { 1730 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active(); 1731 } 1732 1733 static inline bool 1734 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv) 1735 { 1736 return IS_BROXTON(dev_priv) && intel_vtd_active(); 1737 } 1738 1739 /* i915_drv.c */ 1740 #ifdef CONFIG_COMPAT 1741 long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); 1742 #else 1743 #define i915_compat_ioctl NULL 1744 #endif 1745 extern const struct dev_pm_ops i915_pm_ops; 1746 1747 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent); 1748 void i915_driver_remove(struct drm_i915_private *i915); 1749 1750 int i915_resume_switcheroo(struct drm_i915_private *i915); 1751 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state); 1752 1753 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv) 1754 { 1755 return dev_priv->gvt; 1756 } 1757 1758 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv) 1759 { 1760 return dev_priv->vgpu.active; 1761 } 1762 1763 int i915_getparam_ioctl(struct drm_device *dev, void *data, 1764 struct drm_file *file_priv); 1765 1766 /* i915_gem.c */ 1767 int i915_gem_init_userptr(struct drm_i915_private *dev_priv); 1768 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv); 1769 void i915_gem_init_early(struct drm_i915_private *dev_priv); 1770 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv); 1771 int i915_gem_freeze(struct drm_i915_private *dev_priv); 1772 int i915_gem_freeze_late(struct drm_i915_private *dev_priv); 1773 1774 struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915); 1775 1776 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915) 1777 { 1778 /* 1779 * A single pass should suffice to release all the freed objects (along 1780 * most call paths) , but be a little more paranoid in that freeing 1781 * the objects does take a little amount of time, during which the rcu 1782 * callbacks could have added new objects into the freed list, and 1783 * armed the work again. 1784 */ 1785 while (atomic_read(&i915->mm.free_count)) { 1786 flush_work(&i915->mm.free_work); 1787 rcu_barrier(); 1788 } 1789 } 1790 1791 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915) 1792 { 1793 /* 1794 * Similar to objects above (see i915_gem_drain_freed-objects), in 1795 * general we have workers that are armed by RCU and then rearm 1796 * themselves in their callbacks. To be paranoid, we need to 1797 * drain the workqueue a second time after waiting for the RCU 1798 * grace period so that we catch work queued via RCU from the first 1799 * pass. As neither drain_workqueue() nor flush_workqueue() report 1800 * a result, we make an assumption that we only don't require more 1801 * than 3 passes to catch all _recursive_ RCU delayed work. 1802 * 1803 */ 1804 int pass = 3; 1805 do { 1806 flush_workqueue(i915->wq); 1807 rcu_barrier(); 1808 i915_gem_drain_freed_objects(i915); 1809 } while (--pass); 1810 drain_workqueue(i915->wq); 1811 } 1812 1813 struct i915_vma * __must_check 1814 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, 1815 const struct i915_ggtt_view *view, 1816 u64 size, 1817 u64 alignment, 1818 u64 flags); 1819 1820 int i915_gem_object_unbind(struct drm_i915_gem_object *obj, 1821 unsigned long flags); 1822 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0) 1823 #define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1) 1824 1825 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv); 1826 1827 static inline int __must_check 1828 i915_mutex_lock_interruptible(struct drm_device *dev) 1829 { 1830 return mutex_lock_interruptible(&dev->struct_mutex); 1831 } 1832 1833 int i915_gem_dumb_create(struct drm_file *file_priv, 1834 struct drm_device *dev, 1835 struct drm_mode_create_dumb *args); 1836 1837 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno); 1838 1839 static inline u32 i915_reset_count(struct i915_gpu_error *error) 1840 { 1841 return atomic_read(&error->reset_count); 1842 } 1843 1844 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error, 1845 const struct intel_engine_cs *engine) 1846 { 1847 return atomic_read(&error->reset_engine_count[engine->uabi_class]); 1848 } 1849 1850 int __must_check i915_gem_init(struct drm_i915_private *dev_priv); 1851 void i915_gem_driver_register(struct drm_i915_private *i915); 1852 void i915_gem_driver_unregister(struct drm_i915_private *i915); 1853 void i915_gem_driver_remove(struct drm_i915_private *dev_priv); 1854 void i915_gem_driver_release(struct drm_i915_private *dev_priv); 1855 void i915_gem_suspend(struct drm_i915_private *dev_priv); 1856 void i915_gem_suspend_late(struct drm_i915_private *dev_priv); 1857 void i915_gem_resume(struct drm_i915_private *dev_priv); 1858 1859 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file); 1860 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 1861 1862 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1863 enum i915_cache_level cache_level); 1864 1865 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 1866 struct dma_buf *dma_buf); 1867 1868 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags); 1869 1870 static inline struct i915_gem_context * 1871 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id) 1872 { 1873 return xa_load(&file_priv->context_xa, id); 1874 } 1875 1876 static inline struct i915_gem_context * 1877 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id) 1878 { 1879 struct i915_gem_context *ctx; 1880 1881 rcu_read_lock(); 1882 ctx = __i915_gem_context_lookup_rcu(file_priv, id); 1883 if (ctx && !kref_get_unless_zero(&ctx->ref)) 1884 ctx = NULL; 1885 rcu_read_unlock(); 1886 1887 return ctx; 1888 } 1889 1890 /* i915_gem_evict.c */ 1891 int __must_check i915_gem_evict_something(struct i915_address_space *vm, 1892 u64 min_size, u64 alignment, 1893 unsigned long color, 1894 u64 start, u64 end, 1895 unsigned flags); 1896 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm, 1897 struct drm_mm_node *node, 1898 unsigned int flags); 1899 int i915_gem_evict_vm(struct i915_address_space *vm); 1900 1901 /* i915_gem_internal.c */ 1902 struct drm_i915_gem_object * 1903 i915_gem_object_create_internal(struct drm_i915_private *dev_priv, 1904 phys_addr_t size); 1905 1906 /* i915_gem_tiling.c */ 1907 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 1908 { 1909 struct drm_i915_private *i915 = to_i915(obj->base.dev); 1910 1911 return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 1912 i915_gem_object_is_tiled(obj); 1913 } 1914 1915 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size, 1916 unsigned int tiling, unsigned int stride); 1917 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size, 1918 unsigned int tiling, unsigned int stride); 1919 1920 const char *i915_cache_level_str(struct drm_i915_private *i915, int type); 1921 1922 /* i915_cmd_parser.c */ 1923 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); 1924 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine); 1925 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine); 1926 int intel_engine_cmd_parser(struct intel_engine_cs *engine, 1927 struct i915_vma *batch, 1928 u32 batch_offset, 1929 u32 batch_length, 1930 struct i915_vma *shadow, 1931 bool trampoline); 1932 #define I915_CMD_PARSER_TRAMPOLINE_SIZE 8 1933 1934 /* intel_device_info.c */ 1935 static inline struct intel_device_info * 1936 mkwrite_device_info(struct drm_i915_private *dev_priv) 1937 { 1938 return (struct intel_device_info *)INTEL_INFO(dev_priv); 1939 } 1940 1941 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 1942 struct drm_file *file); 1943 1944 #define __I915_REG_OP(op__, dev_priv__, ...) \ 1945 intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__) 1946 1947 #define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__)) 1948 #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__)) 1949 1950 #define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__)) 1951 1952 /* These are untraced mmio-accessors that are only valid to be used inside 1953 * critical sections, such as inside IRQ handlers, where forcewake is explicitly 1954 * controlled. 1955 * 1956 * Think twice, and think again, before using these. 1957 * 1958 * As an example, these accessors can possibly be used between: 1959 * 1960 * spin_lock_irq(&dev_priv->uncore.lock); 1961 * intel_uncore_forcewake_get__locked(); 1962 * 1963 * and 1964 * 1965 * intel_uncore_forcewake_put__locked(); 1966 * spin_unlock_irq(&dev_priv->uncore.lock); 1967 * 1968 * 1969 * Note: some registers may not need forcewake held, so 1970 * intel_uncore_forcewake_{get,put} can be omitted, see 1971 * intel_uncore_forcewake_for_reg(). 1972 * 1973 * Certain architectures will die if the same cacheline is concurrently accessed 1974 * by different clients (e.g. on Ivybridge). Access to registers should 1975 * therefore generally be serialised, by either the dev_priv->uncore.lock or 1976 * a more localised lock guarding all access to that bank of registers. 1977 */ 1978 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__)) 1979 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__)) 1980 1981 /* i915_mm.c */ 1982 int remap_io_mapping(struct vm_area_struct *vma, 1983 unsigned long addr, unsigned long pfn, unsigned long size, 1984 struct io_mapping *iomap); 1985 int remap_io_sg(struct vm_area_struct *vma, 1986 unsigned long addr, unsigned long size, 1987 struct scatterlist *sgl, resource_size_t iobase); 1988 1989 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915) 1990 { 1991 if (INTEL_GEN(i915) >= 10) 1992 return CNL_HWS_CSB_WRITE_INDEX; 1993 else 1994 return I915_HWS_CSB_WRITE_INDEX; 1995 } 1996 1997 static inline enum i915_map_type 1998 i915_coherent_map_type(struct drm_i915_private *i915) 1999 { 2000 return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC; 2001 } 2002 2003 #endif 2004