1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 #include <uapi/drm/drm_fourcc.h> 35 36 #include <linux/io-mapping.h> 37 #include <linux/i2c.h> 38 #include <linux/i2c-algo-bit.h> 39 #include <linux/backlight.h> 40 #include <linux/hash.h> 41 #include <linux/intel-iommu.h> 42 #include <linux/kref.h> 43 #include <linux/mm_types.h> 44 #include <linux/perf_event.h> 45 #include <linux/pm_qos.h> 46 #include <linux/dma-resv.h> 47 #include <linux/shmem_fs.h> 48 #include <linux/stackdepot.h> 49 50 #include <drm/intel-gtt.h> 51 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ 52 #include <drm/drm_gem.h> 53 #include <drm/drm_auth.h> 54 #include <drm/drm_cache.h> 55 #include <drm/drm_util.h> 56 #include <drm/drm_dsc.h> 57 #include <drm/drm_atomic.h> 58 #include <drm/drm_connector.h> 59 #include <drm/i915_mei_hdcp_interface.h> 60 61 #include "i915_fixed.h" 62 #include "i915_params.h" 63 #include "i915_reg.h" 64 #include "i915_utils.h" 65 66 #include "display/intel_bios.h" 67 #include "display/intel_display.h" 68 #include "display/intel_display_power.h" 69 #include "display/intel_dpll_mgr.h" 70 #include "display/intel_frontbuffer.h" 71 #include "display/intel_gmbus.h" 72 #include "display/intel_opregion.h" 73 74 #include "gem/i915_gem_context_types.h" 75 #include "gem/i915_gem_shrinker.h" 76 #include "gem/i915_gem_stolen.h" 77 78 #include "gt/intel_lrc.h" 79 #include "gt/intel_engine.h" 80 #include "gt/intel_gt_types.h" 81 #include "gt/intel_workarounds.h" 82 #include "gt/uc/intel_uc.h" 83 84 #include "intel_device_info.h" 85 #include "intel_pch.h" 86 #include "intel_runtime_pm.h" 87 #include "intel_uncore.h" 88 #include "intel_wakeref.h" 89 #include "intel_wopcm.h" 90 91 #include "i915_gem.h" 92 #include "i915_gem_fence_reg.h" 93 #include "i915_gem_gtt.h" 94 #include "i915_gpu_error.h" 95 #include "i915_request.h" 96 #include "i915_scheduler.h" 97 #include "gt/intel_timeline.h" 98 #include "i915_vma.h" 99 #include "i915_irq.h" 100 101 #include "intel_gvt.h" 102 103 /* General customization: 104 */ 105 106 #define DRIVER_NAME "i915" 107 #define DRIVER_DESC "Intel Graphics" 108 #define DRIVER_DATE "20190822" 109 #define DRIVER_TIMESTAMP 1566477988 110 111 struct drm_i915_gem_object; 112 113 enum hpd_pin { 114 HPD_NONE = 0, 115 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 116 HPD_CRT, 117 HPD_SDVO_B, 118 HPD_SDVO_C, 119 HPD_PORT_A, 120 HPD_PORT_B, 121 HPD_PORT_C, 122 HPD_PORT_D, 123 HPD_PORT_E, 124 HPD_PORT_F, 125 HPD_PORT_G, 126 HPD_PORT_H, 127 HPD_PORT_I, 128 129 HPD_NUM_PINS 130 }; 131 132 #define for_each_hpd_pin(__pin) \ 133 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) 134 135 /* Threshold == 5 for long IRQs, 50 for short */ 136 #define HPD_STORM_DEFAULT_THRESHOLD 50 137 138 struct i915_hotplug { 139 struct delayed_work hotplug_work; 140 141 struct { 142 unsigned long last_jiffies; 143 int count; 144 enum { 145 HPD_ENABLED = 0, 146 HPD_DISABLED = 1, 147 HPD_MARK_DISABLED = 2 148 } state; 149 } stats[HPD_NUM_PINS]; 150 u32 event_bits; 151 u32 retry_bits; 152 struct delayed_work reenable_work; 153 154 u32 long_port_mask; 155 u32 short_port_mask; 156 struct work_struct dig_port_work; 157 158 struct work_struct poll_init_work; 159 bool poll_enabled; 160 161 unsigned int hpd_storm_threshold; 162 /* Whether or not to count short HPD IRQs in HPD storms */ 163 u8 hpd_short_storm_enabled; 164 165 /* 166 * if we get a HPD irq from DP and a HPD irq from non-DP 167 * the non-DP HPD could block the workqueue on a mode config 168 * mutex getting, that userspace may have taken. However 169 * userspace is waiting on the DP workqueue to run which is 170 * blocked behind the non-DP one. 171 */ 172 struct workqueue_struct *dp_wq; 173 }; 174 175 #define I915_GEM_GPU_DOMAINS \ 176 (I915_GEM_DOMAIN_RENDER | \ 177 I915_GEM_DOMAIN_SAMPLER | \ 178 I915_GEM_DOMAIN_COMMAND | \ 179 I915_GEM_DOMAIN_INSTRUCTION | \ 180 I915_GEM_DOMAIN_VERTEX) 181 182 struct drm_i915_private; 183 struct i915_mm_struct; 184 struct i915_mmu_object; 185 186 struct drm_i915_file_private { 187 struct drm_i915_private *dev_priv; 188 struct drm_file *file; 189 190 struct { 191 spinlock_t lock; 192 struct list_head request_list; 193 } mm; 194 195 struct idr context_idr; 196 struct mutex context_idr_lock; /* guards context_idr */ 197 198 struct idr vm_idr; 199 struct mutex vm_idr_lock; /* guards vm_idr */ 200 201 unsigned int bsd_engine; 202 203 /* 204 * Every context ban increments per client ban score. Also 205 * hangs in short succession increments ban score. If ban threshold 206 * is reached, client is considered banned and submitting more work 207 * will fail. This is a stop gap measure to limit the badly behaving 208 * clients access to gpu. Note that unbannable contexts never increment 209 * the client ban score. 210 */ 211 #define I915_CLIENT_SCORE_HANG_FAST 1 212 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ) 213 #define I915_CLIENT_SCORE_CONTEXT_BAN 3 214 #define I915_CLIENT_SCORE_BANNED 9 215 /** ban_score: Accumulated score of all ctx bans and fast hangs. */ 216 atomic_t ban_score; 217 unsigned long hang_timestamp; 218 }; 219 220 /* Interface history: 221 * 222 * 1.1: Original. 223 * 1.2: Add Power Management 224 * 1.3: Add vblank support 225 * 1.4: Fix cmdbuffer path, add heap destroy 226 * 1.5: Add vblank pipe configuration 227 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 228 * - Support vertical blank on secondary display pipe 229 */ 230 #define DRIVER_MAJOR 1 231 #define DRIVER_MINOR 6 232 #define DRIVER_PATCHLEVEL 0 233 234 struct intel_overlay; 235 struct intel_overlay_error_state; 236 237 struct sdvo_device_mapping { 238 u8 initialized; 239 u8 dvo_port; 240 u8 slave_addr; 241 u8 dvo_wiring; 242 u8 i2c_pin; 243 u8 ddc_pin; 244 }; 245 246 struct intel_connector; 247 struct intel_encoder; 248 struct intel_atomic_state; 249 struct intel_crtc_state; 250 struct intel_initial_plane_config; 251 struct intel_crtc; 252 struct intel_limit; 253 struct dpll; 254 struct intel_cdclk_state; 255 256 struct drm_i915_display_funcs { 257 void (*get_cdclk)(struct drm_i915_private *dev_priv, 258 struct intel_cdclk_state *cdclk_state); 259 void (*set_cdclk)(struct drm_i915_private *dev_priv, 260 const struct intel_cdclk_state *cdclk_state, 261 enum pipe pipe); 262 int (*get_fifo_size)(struct drm_i915_private *dev_priv, 263 enum i9xx_plane_id i9xx_plane); 264 int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state); 265 int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state); 266 void (*initial_watermarks)(struct intel_atomic_state *state, 267 struct intel_crtc_state *crtc_state); 268 void (*atomic_update_watermarks)(struct intel_atomic_state *state, 269 struct intel_crtc_state *crtc_state); 270 void (*optimize_watermarks)(struct intel_atomic_state *state, 271 struct intel_crtc_state *crtc_state); 272 int (*compute_global_watermarks)(struct intel_atomic_state *state); 273 void (*update_wm)(struct intel_crtc *crtc); 274 int (*modeset_calc_cdclk)(struct intel_atomic_state *state); 275 /* Returns the active state of the crtc, and if the crtc is active, 276 * fills out the pipe-config with the hw state. */ 277 bool (*get_pipe_config)(struct intel_crtc *, 278 struct intel_crtc_state *); 279 void (*get_initial_plane_config)(struct intel_crtc *, 280 struct intel_initial_plane_config *); 281 int (*crtc_compute_clock)(struct intel_crtc *crtc, 282 struct intel_crtc_state *crtc_state); 283 void (*crtc_enable)(struct intel_crtc_state *pipe_config, 284 struct intel_atomic_state *old_state); 285 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state, 286 struct intel_atomic_state *old_state); 287 void (*update_crtcs)(struct intel_atomic_state *state); 288 void (*audio_codec_enable)(struct intel_encoder *encoder, 289 const struct intel_crtc_state *crtc_state, 290 const struct drm_connector_state *conn_state); 291 void (*audio_codec_disable)(struct intel_encoder *encoder, 292 const struct intel_crtc_state *old_crtc_state, 293 const struct drm_connector_state *old_conn_state); 294 void (*fdi_link_train)(struct intel_crtc *crtc, 295 const struct intel_crtc_state *crtc_state); 296 void (*init_clock_gating)(struct drm_i915_private *dev_priv); 297 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); 298 /* clock updates for mode set */ 299 /* cursor updates */ 300 /* render clock increase/decrease */ 301 /* display clock increase/decrease */ 302 /* pll clock increase/decrease */ 303 304 int (*color_check)(struct intel_crtc_state *crtc_state); 305 /* 306 * Program double buffered color management registers during 307 * vblank evasion. The registers should then latch during the 308 * next vblank start, alongside any other double buffered registers 309 * involved with the same commit. 310 */ 311 void (*color_commit)(const struct intel_crtc_state *crtc_state); 312 /* 313 * Load LUTs (and other single buffered color management 314 * registers). Will (hopefully) be called during the vblank 315 * following the latching of any double buffered registers 316 * involved with the same commit. 317 */ 318 void (*load_luts)(const struct intel_crtc_state *crtc_state); 319 void (*read_luts)(struct intel_crtc_state *crtc_state); 320 }; 321 322 struct intel_csr { 323 struct work_struct work; 324 const char *fw_path; 325 u32 required_version; 326 u32 max_fw_size; /* bytes */ 327 u32 *dmc_payload; 328 u32 dmc_fw_size; /* dwords */ 329 u32 version; 330 u32 mmio_count; 331 i915_reg_t mmioaddr[20]; 332 u32 mmiodata[20]; 333 u32 dc_state; 334 u32 allowed_dc_mask; 335 intel_wakeref_t wakeref; 336 }; 337 338 enum i915_cache_level { 339 I915_CACHE_NONE = 0, 340 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ 341 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc 342 caches, eg sampler/render caches, and the 343 large Last-Level-Cache. LLC is coherent with 344 the CPU, but L3 is only visible to the GPU. */ 345 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ 346 }; 347 348 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */ 349 350 struct intel_fbc { 351 /* This is always the inner lock when overlapping with struct_mutex and 352 * it's the outer lock when overlapping with stolen_lock. */ 353 struct mutex lock; 354 unsigned threshold; 355 unsigned int possible_framebuffer_bits; 356 unsigned int busy_bits; 357 unsigned int visible_pipes_mask; 358 struct intel_crtc *crtc; 359 360 struct drm_mm_node compressed_fb; 361 struct drm_mm_node *compressed_llb; 362 363 bool false_color; 364 365 bool enabled; 366 bool active; 367 bool flip_pending; 368 369 bool underrun_detected; 370 struct work_struct underrun_work; 371 372 /* 373 * Due to the atomic rules we can't access some structures without the 374 * appropriate locking, so we cache information here in order to avoid 375 * these problems. 376 */ 377 struct intel_fbc_state_cache { 378 struct i915_vma *vma; 379 unsigned long flags; 380 381 struct { 382 unsigned int mode_flags; 383 u32 hsw_bdw_pixel_rate; 384 } crtc; 385 386 struct { 387 unsigned int rotation; 388 int src_w; 389 int src_h; 390 bool visible; 391 /* 392 * Display surface base address adjustement for 393 * pageflips. Note that on gen4+ this only adjusts up 394 * to a tile, offsets within a tile are handled in 395 * the hw itself (with the TILEOFF register). 396 */ 397 int adjusted_x; 398 int adjusted_y; 399 400 int y; 401 402 u16 pixel_blend_mode; 403 } plane; 404 405 struct { 406 const struct drm_format_info *format; 407 unsigned int stride; 408 } fb; 409 } state_cache; 410 411 /* 412 * This structure contains everything that's relevant to program the 413 * hardware registers. When we want to figure out if we need to disable 414 * and re-enable FBC for a new configuration we just check if there's 415 * something different in the struct. The genx_fbc_activate functions 416 * are supposed to read from it in order to program the registers. 417 */ 418 struct intel_fbc_reg_params { 419 struct i915_vma *vma; 420 unsigned long flags; 421 422 struct { 423 enum pipe pipe; 424 enum i9xx_plane_id i9xx_plane; 425 unsigned int fence_y_offset; 426 } crtc; 427 428 struct { 429 const struct drm_format_info *format; 430 unsigned int stride; 431 } fb; 432 433 int cfb_size; 434 unsigned int gen9_wa_cfb_stride; 435 } params; 436 437 const char *no_fbc_reason; 438 }; 439 440 /* 441 * HIGH_RR is the highest eDP panel refresh rate read from EDID 442 * LOW_RR is the lowest eDP panel refresh rate found from EDID 443 * parsing for same resolution. 444 */ 445 enum drrs_refresh_rate_type { 446 DRRS_HIGH_RR, 447 DRRS_LOW_RR, 448 DRRS_MAX_RR, /* RR count */ 449 }; 450 451 enum drrs_support_type { 452 DRRS_NOT_SUPPORTED = 0, 453 STATIC_DRRS_SUPPORT = 1, 454 SEAMLESS_DRRS_SUPPORT = 2 455 }; 456 457 struct intel_dp; 458 struct i915_drrs { 459 struct mutex mutex; 460 struct delayed_work work; 461 struct intel_dp *dp; 462 unsigned busy_frontbuffer_bits; 463 enum drrs_refresh_rate_type refresh_rate_type; 464 enum drrs_support_type type; 465 }; 466 467 struct i915_psr { 468 struct mutex lock; 469 470 #define I915_PSR_DEBUG_MODE_MASK 0x0f 471 #define I915_PSR_DEBUG_DEFAULT 0x00 472 #define I915_PSR_DEBUG_DISABLE 0x01 473 #define I915_PSR_DEBUG_ENABLE 0x02 474 #define I915_PSR_DEBUG_FORCE_PSR1 0x03 475 #define I915_PSR_DEBUG_IRQ 0x10 476 477 u32 debug; 478 bool sink_support; 479 bool enabled; 480 struct intel_dp *dp; 481 enum pipe pipe; 482 bool active; 483 struct work_struct work; 484 unsigned busy_frontbuffer_bits; 485 bool sink_psr2_support; 486 bool link_standby; 487 bool colorimetry_support; 488 bool psr2_enabled; 489 u8 sink_sync_latency; 490 ktime_t last_entry_attempt; 491 ktime_t last_exit; 492 bool sink_not_reliable; 493 bool irq_aux_error; 494 u16 su_x_granularity; 495 }; 496 497 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 498 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 499 #define QUIRK_BACKLIGHT_PRESENT (1<<3) 500 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) 501 #define QUIRK_INCREASE_T12_DELAY (1<<6) 502 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7) 503 504 struct intel_fbdev; 505 struct intel_fbc_work; 506 507 struct intel_gmbus { 508 struct i2c_adapter adapter; 509 #define GMBUS_FORCE_BIT_RETRY (1U << 31) 510 u32 force_bit; 511 u32 reg0; 512 i915_reg_t gpio_reg; 513 struct i2c_algo_bit_data bit_algo; 514 struct drm_i915_private *dev_priv; 515 }; 516 517 struct i915_suspend_saved_registers { 518 u32 saveDSPARB; 519 u32 saveFBC_CONTROL; 520 u32 saveCACHE_MODE_0; 521 u32 saveMI_ARB_STATE; 522 u32 saveSWF0[16]; 523 u32 saveSWF1[16]; 524 u32 saveSWF3[3]; 525 u64 saveFENCE[I915_MAX_NUM_FENCES]; 526 u32 savePCH_PORT_HOTPLUG; 527 u16 saveGCDGMBUS; 528 }; 529 530 struct vlv_s0ix_state; 531 532 struct intel_rps_ei { 533 ktime_t ktime; 534 u32 render_c0; 535 u32 media_c0; 536 }; 537 538 struct intel_rps { 539 struct mutex lock; /* protects enabling and the worker */ 540 541 /* 542 * work, interrupts_enabled and pm_iir are protected by 543 * dev_priv->irq_lock 544 */ 545 struct work_struct work; 546 bool interrupts_enabled; 547 u32 pm_iir; 548 549 /* PM interrupt bits that should never be masked */ 550 u32 pm_intrmsk_mbz; 551 552 /* Frequencies are stored in potentially platform dependent multiples. 553 * In other words, *_freq needs to be multiplied by X to be interesting. 554 * Soft limits are those which are used for the dynamic reclocking done 555 * by the driver (raise frequencies under heavy loads, and lower for 556 * lighter loads). Hard limits are those imposed by the hardware. 557 * 558 * A distinction is made for overclocking, which is never enabled by 559 * default, and is considered to be above the hard limit if it's 560 * possible at all. 561 */ 562 u8 cur_freq; /* Current frequency (cached, may not == HW) */ 563 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ 564 u8 max_freq_softlimit; /* Max frequency permitted by the driver */ 565 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ 566 u8 min_freq; /* AKA RPn. Minimum frequency */ 567 u8 boost_freq; /* Frequency to request when wait boosting */ 568 u8 idle_freq; /* Frequency to request when we are idle */ 569 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ 570 u8 rp1_freq; /* "less than" RP0 power/freqency */ 571 u8 rp0_freq; /* Non-overclocked max frequency. */ 572 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */ 573 574 int last_adj; 575 576 struct { 577 struct mutex mutex; 578 579 enum { LOW_POWER, BETWEEN, HIGH_POWER } mode; 580 unsigned int interactive; 581 582 u8 up_threshold; /* Current %busy required to uplock */ 583 u8 down_threshold; /* Current %busy required to downclock */ 584 } power; 585 586 bool enabled; 587 atomic_t num_waiters; 588 atomic_t boosts; 589 590 /* manual wa residency calculations */ 591 struct intel_rps_ei ei; 592 }; 593 594 struct intel_rc6 { 595 bool enabled; 596 u64 prev_hw_residency[4]; 597 u64 cur_residency[4]; 598 }; 599 600 struct intel_llc_pstate { 601 bool enabled; 602 }; 603 604 struct intel_gen6_power_mgmt { 605 struct intel_rps rps; 606 struct intel_rc6 rc6; 607 struct intel_llc_pstate llc_pstate; 608 }; 609 610 /* defined intel_pm.c */ 611 extern spinlock_t mchdev_lock; 612 613 struct intel_ilk_power_mgmt { 614 u8 cur_delay; 615 u8 min_delay; 616 u8 max_delay; 617 u8 fmax; 618 u8 fstart; 619 620 u64 last_count1; 621 unsigned long last_time1; 622 unsigned long chipset_power; 623 u64 last_count2; 624 u64 last_time2; 625 unsigned long gfx_power; 626 u8 corr; 627 628 int c_m; 629 int r_t; 630 }; 631 632 #define MAX_L3_SLICES 2 633 struct intel_l3_parity { 634 u32 *remap_info[MAX_L3_SLICES]; 635 struct work_struct error_work; 636 int which_slice; 637 }; 638 639 struct i915_gem_mm { 640 /** Memory allocator for GTT stolen memory */ 641 struct drm_mm stolen; 642 /** Protects the usage of the GTT stolen memory allocator. This is 643 * always the inner lock when overlapping with struct_mutex. */ 644 struct mutex stolen_lock; 645 646 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ 647 spinlock_t obj_lock; 648 649 /** 650 * List of objects which are purgeable. 651 */ 652 struct list_head purge_list; 653 654 /** 655 * List of objects which have allocated pages and are shrinkable. 656 */ 657 struct list_head shrink_list; 658 659 /** 660 * List of objects which are pending destruction. 661 */ 662 struct llist_head free_list; 663 struct work_struct free_work; 664 /** 665 * Count of objects pending destructions. Used to skip needlessly 666 * waiting on an RCU barrier if no objects are waiting to be freed. 667 */ 668 atomic_t free_count; 669 670 /** 671 * Small stash of WC pages 672 */ 673 struct pagestash wc_stash; 674 675 /** 676 * tmpfs instance used for shmem backed objects 677 */ 678 struct vfsmount *gemfs; 679 680 struct notifier_block oom_notifier; 681 struct notifier_block vmap_notifier; 682 struct shrinker shrinker; 683 684 /** 685 * Workqueue to fault in userptr pages, flushed by the execbuf 686 * when required but otherwise left to userspace to try again 687 * on EAGAIN. 688 */ 689 struct workqueue_struct *userptr_wq; 690 691 /** Bit 6 swizzling required for X tiling */ 692 u32 bit_6_swizzle_x; 693 /** Bit 6 swizzling required for Y tiling */ 694 u32 bit_6_swizzle_y; 695 696 /* shrinker accounting, also useful for userland debugging */ 697 u64 shrink_memory; 698 u32 shrink_count; 699 }; 700 701 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */ 702 703 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */ 704 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */ 705 706 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */ 707 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */ 708 709 #define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */ 710 711 struct ddi_vbt_port_info { 712 /* Non-NULL if port present. */ 713 const struct child_device_config *child; 714 715 int max_tmds_clock; 716 717 /* 718 * This is an index in the HDMI/DVI DDI buffer translation table. 719 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't 720 * populate this field. 721 */ 722 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff 723 u8 hdmi_level_shift; 724 725 u8 supports_dvi:1; 726 u8 supports_hdmi:1; 727 u8 supports_dp:1; 728 u8 supports_edp:1; 729 u8 supports_typec_usb:1; 730 u8 supports_tbt:1; 731 732 u8 alternate_aux_channel; 733 u8 alternate_ddc_pin; 734 735 u8 dp_boost_level; 736 u8 hdmi_boost_level; 737 int dp_max_link_rate; /* 0 for not limited by VBT */ 738 }; 739 740 enum psr_lines_to_wait { 741 PSR_0_LINES_TO_WAIT = 0, 742 PSR_1_LINE_TO_WAIT, 743 PSR_4_LINES_TO_WAIT, 744 PSR_8_LINES_TO_WAIT 745 }; 746 747 struct intel_vbt_data { 748 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 749 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 750 751 /* Feature bits */ 752 unsigned int int_tv_support:1; 753 unsigned int lvds_dither:1; 754 unsigned int int_crt_support:1; 755 unsigned int lvds_use_ssc:1; 756 unsigned int int_lvds_support:1; 757 unsigned int display_clock_mode:1; 758 unsigned int fdi_rx_polarity_inverted:1; 759 unsigned int panel_type:4; 760 int lvds_ssc_freq; 761 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 762 enum drm_panel_orientation orientation; 763 764 enum drrs_support_type drrs_type; 765 766 struct { 767 int rate; 768 int lanes; 769 int preemphasis; 770 int vswing; 771 bool low_vswing; 772 bool initialized; 773 int bpp; 774 struct edp_power_seq pps; 775 } edp; 776 777 struct { 778 bool enable; 779 bool full_link; 780 bool require_aux_wakeup; 781 int idle_frames; 782 enum psr_lines_to_wait lines_to_wait; 783 int tp1_wakeup_time_us; 784 int tp2_tp3_wakeup_time_us; 785 int psr2_tp2_tp3_wakeup_time_us; 786 } psr; 787 788 struct { 789 u16 pwm_freq_hz; 790 bool present; 791 bool active_low_pwm; 792 u8 min_brightness; /* min_brightness/255 of max */ 793 u8 controller; /* brightness controller number */ 794 enum intel_backlight_type type; 795 } backlight; 796 797 /* MIPI DSI */ 798 struct { 799 u16 panel_id; 800 struct mipi_config *config; 801 struct mipi_pps_data *pps; 802 u16 bl_ports; 803 u16 cabc_ports; 804 u8 seq_version; 805 u32 size; 806 u8 *data; 807 const u8 *sequence[MIPI_SEQ_MAX]; 808 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */ 809 enum drm_panel_orientation orientation; 810 } dsi; 811 812 int crt_ddc_pin; 813 814 int child_dev_num; 815 struct child_device_config *child_dev; 816 817 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; 818 struct sdvo_device_mapping sdvo_mappings[2]; 819 }; 820 821 enum intel_ddb_partitioning { 822 INTEL_DDB_PART_1_2, 823 INTEL_DDB_PART_5_6, /* IVB+ */ 824 }; 825 826 struct intel_wm_level { 827 bool enable; 828 u32 pri_val; 829 u32 spr_val; 830 u32 cur_val; 831 u32 fbc_val; 832 }; 833 834 struct ilk_wm_values { 835 u32 wm_pipe[3]; 836 u32 wm_lp[3]; 837 u32 wm_lp_spr[3]; 838 u32 wm_linetime[3]; 839 bool enable_fbc_wm; 840 enum intel_ddb_partitioning partitioning; 841 }; 842 843 struct g4x_pipe_wm { 844 u16 plane[I915_MAX_PLANES]; 845 u16 fbc; 846 }; 847 848 struct g4x_sr_wm { 849 u16 plane; 850 u16 cursor; 851 u16 fbc; 852 }; 853 854 struct vlv_wm_ddl_values { 855 u8 plane[I915_MAX_PLANES]; 856 }; 857 858 struct vlv_wm_values { 859 struct g4x_pipe_wm pipe[3]; 860 struct g4x_sr_wm sr; 861 struct vlv_wm_ddl_values ddl[3]; 862 u8 level; 863 bool cxsr; 864 }; 865 866 struct g4x_wm_values { 867 struct g4x_pipe_wm pipe[2]; 868 struct g4x_sr_wm sr; 869 struct g4x_sr_wm hpll; 870 bool cxsr; 871 bool hpll_en; 872 bool fbc_en; 873 }; 874 875 struct skl_ddb_entry { 876 u16 start, end; /* in number of blocks, 'end' is exclusive */ 877 }; 878 879 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry) 880 { 881 return entry->end - entry->start; 882 } 883 884 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, 885 const struct skl_ddb_entry *e2) 886 { 887 if (e1->start == e2->start && e1->end == e2->end) 888 return true; 889 890 return false; 891 } 892 893 struct skl_ddb_allocation { 894 u8 enabled_slices; /* GEN11 has configurable 2 slices */ 895 }; 896 897 struct skl_ddb_values { 898 unsigned dirty_pipes; 899 struct skl_ddb_allocation ddb; 900 }; 901 902 struct skl_wm_level { 903 u16 min_ddb_alloc; 904 u16 plane_res_b; 905 u8 plane_res_l; 906 bool plane_en; 907 bool ignore_lines; 908 }; 909 910 /* Stores plane specific WM parameters */ 911 struct skl_wm_params { 912 bool x_tiled, y_tiled; 913 bool rc_surface; 914 bool is_planar; 915 u32 width; 916 u8 cpp; 917 u32 plane_pixel_rate; 918 u32 y_min_scanlines; 919 u32 plane_bytes_per_line; 920 uint_fixed_16_16_t plane_blocks_per_line; 921 uint_fixed_16_16_t y_tile_minimum; 922 u32 linetime_us; 923 u32 dbuf_block_size; 924 }; 925 926 enum intel_pipe_crc_source { 927 INTEL_PIPE_CRC_SOURCE_NONE, 928 INTEL_PIPE_CRC_SOURCE_PLANE1, 929 INTEL_PIPE_CRC_SOURCE_PLANE2, 930 INTEL_PIPE_CRC_SOURCE_PLANE3, 931 INTEL_PIPE_CRC_SOURCE_PLANE4, 932 INTEL_PIPE_CRC_SOURCE_PLANE5, 933 INTEL_PIPE_CRC_SOURCE_PLANE6, 934 INTEL_PIPE_CRC_SOURCE_PLANE7, 935 INTEL_PIPE_CRC_SOURCE_PIPE, 936 /* TV/DP on pre-gen5/vlv can't use the pipe source. */ 937 INTEL_PIPE_CRC_SOURCE_TV, 938 INTEL_PIPE_CRC_SOURCE_DP_B, 939 INTEL_PIPE_CRC_SOURCE_DP_C, 940 INTEL_PIPE_CRC_SOURCE_DP_D, 941 INTEL_PIPE_CRC_SOURCE_AUTO, 942 INTEL_PIPE_CRC_SOURCE_MAX, 943 }; 944 945 #define INTEL_PIPE_CRC_ENTRIES_NR 128 946 struct intel_pipe_crc { 947 spinlock_t lock; 948 int skipped; 949 enum intel_pipe_crc_source source; 950 }; 951 952 struct i915_frontbuffer_tracking { 953 spinlock_t lock; 954 955 /* 956 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 957 * scheduled flips. 958 */ 959 unsigned busy_bits; 960 unsigned flip_bits; 961 }; 962 963 struct i915_virtual_gpu { 964 struct mutex lock; /* serialises sending of g2v_notify command pkts */ 965 bool active; 966 u32 caps; 967 }; 968 969 /* used in computing the new watermarks state */ 970 struct intel_wm_config { 971 unsigned int num_pipes_active; 972 bool sprites_enabled; 973 bool sprites_scaled; 974 }; 975 976 struct i915_oa_format { 977 u32 format; 978 int size; 979 }; 980 981 struct i915_oa_reg { 982 i915_reg_t addr; 983 u32 value; 984 }; 985 986 struct i915_oa_config { 987 char uuid[UUID_STRING_LEN + 1]; 988 int id; 989 990 const struct i915_oa_reg *mux_regs; 991 u32 mux_regs_len; 992 const struct i915_oa_reg *b_counter_regs; 993 u32 b_counter_regs_len; 994 const struct i915_oa_reg *flex_regs; 995 u32 flex_regs_len; 996 997 struct attribute_group sysfs_metric; 998 struct attribute *attrs[2]; 999 struct device_attribute sysfs_metric_id; 1000 1001 atomic_t ref_count; 1002 }; 1003 1004 struct i915_perf_stream; 1005 1006 /** 1007 * struct i915_perf_stream_ops - the OPs to support a specific stream type 1008 */ 1009 struct i915_perf_stream_ops { 1010 /** 1011 * @enable: Enables the collection of HW samples, either in response to 1012 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened 1013 * without `I915_PERF_FLAG_DISABLED`. 1014 */ 1015 void (*enable)(struct i915_perf_stream *stream); 1016 1017 /** 1018 * @disable: Disables the collection of HW samples, either in response 1019 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying 1020 * the stream. 1021 */ 1022 void (*disable)(struct i915_perf_stream *stream); 1023 1024 /** 1025 * @poll_wait: Call poll_wait, passing a wait queue that will be woken 1026 * once there is something ready to read() for the stream 1027 */ 1028 void (*poll_wait)(struct i915_perf_stream *stream, 1029 struct file *file, 1030 poll_table *wait); 1031 1032 /** 1033 * @wait_unlocked: For handling a blocking read, wait until there is 1034 * something to ready to read() for the stream. E.g. wait on the same 1035 * wait queue that would be passed to poll_wait(). 1036 */ 1037 int (*wait_unlocked)(struct i915_perf_stream *stream); 1038 1039 /** 1040 * @read: Copy buffered metrics as records to userspace 1041 * **buf**: the userspace, destination buffer 1042 * **count**: the number of bytes to copy, requested by userspace 1043 * **offset**: zero at the start of the read, updated as the read 1044 * proceeds, it represents how many bytes have been copied so far and 1045 * the buffer offset for copying the next record. 1046 * 1047 * Copy as many buffered i915 perf samples and records for this stream 1048 * to userspace as will fit in the given buffer. 1049 * 1050 * Only write complete records; returning -%ENOSPC if there isn't room 1051 * for a complete record. 1052 * 1053 * Return any error condition that results in a short read such as 1054 * -%ENOSPC or -%EFAULT, even though these may be squashed before 1055 * returning to userspace. 1056 */ 1057 int (*read)(struct i915_perf_stream *stream, 1058 char __user *buf, 1059 size_t count, 1060 size_t *offset); 1061 1062 /** 1063 * @destroy: Cleanup any stream specific resources. 1064 * 1065 * The stream will always be disabled before this is called. 1066 */ 1067 void (*destroy)(struct i915_perf_stream *stream); 1068 }; 1069 1070 /** 1071 * struct i915_perf_stream - state for a single open stream FD 1072 */ 1073 struct i915_perf_stream { 1074 /** 1075 * @dev_priv: i915 drm device 1076 */ 1077 struct drm_i915_private *dev_priv; 1078 1079 /** 1080 * @link: Links the stream into ``&drm_i915_private->streams`` 1081 */ 1082 struct list_head link; 1083 1084 /** 1085 * @wakeref: As we keep the device awake while the perf stream is 1086 * active, we track our runtime pm reference for later release. 1087 */ 1088 intel_wakeref_t wakeref; 1089 1090 /** 1091 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*` 1092 * properties given when opening a stream, representing the contents 1093 * of a single sample as read() by userspace. 1094 */ 1095 u32 sample_flags; 1096 1097 /** 1098 * @sample_size: Considering the configured contents of a sample 1099 * combined with the required header size, this is the total size 1100 * of a single sample record. 1101 */ 1102 int sample_size; 1103 1104 /** 1105 * @ctx: %NULL if measuring system-wide across all contexts or a 1106 * specific context that is being monitored. 1107 */ 1108 struct i915_gem_context *ctx; 1109 1110 /** 1111 * @enabled: Whether the stream is currently enabled, considering 1112 * whether the stream was opened in a disabled state and based 1113 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls. 1114 */ 1115 bool enabled; 1116 1117 /** 1118 * @ops: The callbacks providing the implementation of this specific 1119 * type of configured stream. 1120 */ 1121 const struct i915_perf_stream_ops *ops; 1122 1123 /** 1124 * @oa_config: The OA configuration used by the stream. 1125 */ 1126 struct i915_oa_config *oa_config; 1127 1128 /** 1129 * The OA context specific information. 1130 */ 1131 struct intel_context *pinned_ctx; 1132 u32 specific_ctx_id; 1133 u32 specific_ctx_id_mask; 1134 1135 struct hrtimer poll_check_timer; 1136 wait_queue_head_t poll_wq; 1137 bool pollin; 1138 1139 bool periodic; 1140 int period_exponent; 1141 1142 /** 1143 * State of the OA buffer. 1144 */ 1145 struct { 1146 struct i915_vma *vma; 1147 u8 *vaddr; 1148 u32 last_ctx_id; 1149 int format; 1150 int format_size; 1151 int size_exponent; 1152 1153 /** 1154 * Locks reads and writes to all head/tail state 1155 * 1156 * Consider: the head and tail pointer state needs to be read 1157 * consistently from a hrtimer callback (atomic context) and 1158 * read() fop (user context) with tail pointer updates happening 1159 * in atomic context and head updates in user context and the 1160 * (unlikely) possibility of read() errors needing to reset all 1161 * head/tail state. 1162 * 1163 * Note: Contention/performance aren't currently a significant 1164 * concern here considering the relatively low frequency of 1165 * hrtimer callbacks (5ms period) and that reads typically only 1166 * happen in response to a hrtimer event and likely complete 1167 * before the next callback. 1168 * 1169 * Note: This lock is not held *while* reading and copying data 1170 * to userspace so the value of head observed in htrimer 1171 * callbacks won't represent any partial consumption of data. 1172 */ 1173 spinlock_t ptr_lock; 1174 1175 /** 1176 * One 'aging' tail pointer and one 'aged' tail pointer ready to 1177 * used for reading. 1178 * 1179 * Initial values of 0xffffffff are invalid and imply that an 1180 * update is required (and should be ignored by an attempted 1181 * read) 1182 */ 1183 struct { 1184 u32 offset; 1185 } tails[2]; 1186 1187 /** 1188 * Index for the aged tail ready to read() data up to. 1189 */ 1190 unsigned int aged_tail_idx; 1191 1192 /** 1193 * A monotonic timestamp for when the current aging tail pointer 1194 * was read; used to determine when it is old enough to trust. 1195 */ 1196 u64 aging_timestamp; 1197 1198 /** 1199 * Although we can always read back the head pointer register, 1200 * we prefer to avoid trusting the HW state, just to avoid any 1201 * risk that some hardware condition could * somehow bump the 1202 * head pointer unpredictably and cause us to forward the wrong 1203 * OA buffer data to userspace. 1204 */ 1205 u32 head; 1206 } oa_buffer; 1207 }; 1208 1209 /** 1210 * struct i915_oa_ops - Gen specific implementation of an OA unit stream 1211 */ 1212 struct i915_oa_ops { 1213 /** 1214 * @is_valid_b_counter_reg: Validates register's address for 1215 * programming boolean counters for a particular platform. 1216 */ 1217 bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv, 1218 u32 addr); 1219 1220 /** 1221 * @is_valid_mux_reg: Validates register's address for programming mux 1222 * for a particular platform. 1223 */ 1224 bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr); 1225 1226 /** 1227 * @is_valid_flex_reg: Validates register's address for programming 1228 * flex EU filtering for a particular platform. 1229 */ 1230 bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr); 1231 1232 /** 1233 * @enable_metric_set: Selects and applies any MUX configuration to set 1234 * up the Boolean and Custom (B/C) counters that are part of the 1235 * counter reports being sampled. May apply system constraints such as 1236 * disabling EU clock gating as required. 1237 */ 1238 int (*enable_metric_set)(struct i915_perf_stream *stream); 1239 1240 /** 1241 * @disable_metric_set: Remove system constraints associated with using 1242 * the OA unit. 1243 */ 1244 void (*disable_metric_set)(struct i915_perf_stream *stream); 1245 1246 /** 1247 * @oa_enable: Enable periodic sampling 1248 */ 1249 void (*oa_enable)(struct i915_perf_stream *stream); 1250 1251 /** 1252 * @oa_disable: Disable periodic sampling 1253 */ 1254 void (*oa_disable)(struct i915_perf_stream *stream); 1255 1256 /** 1257 * @read: Copy data from the circular OA buffer into a given userspace 1258 * buffer. 1259 */ 1260 int (*read)(struct i915_perf_stream *stream, 1261 char __user *buf, 1262 size_t count, 1263 size_t *offset); 1264 1265 /** 1266 * @oa_hw_tail_read: read the OA tail pointer register 1267 * 1268 * In particular this enables us to share all the fiddly code for 1269 * handling the OA unit tail pointer race that affects multiple 1270 * generations. 1271 */ 1272 u32 (*oa_hw_tail_read)(struct i915_perf_stream *stream); 1273 }; 1274 1275 struct intel_cdclk_state { 1276 unsigned int cdclk, vco, ref, bypass; 1277 u8 voltage_level; 1278 }; 1279 1280 struct drm_i915_private { 1281 struct drm_device drm; 1282 1283 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */ 1284 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ 1285 struct intel_driver_caps caps; 1286 1287 /** 1288 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and 1289 * end of stolen which we can optionally use to create GEM objects 1290 * backed by stolen memory. Note that stolen_usable_size tells us 1291 * exactly how much of this we are actually allowed to use, given that 1292 * some portion of it is in fact reserved for use by hardware functions. 1293 */ 1294 struct resource dsm; 1295 /** 1296 * Reseved portion of Data Stolen Memory 1297 */ 1298 struct resource dsm_reserved; 1299 1300 /* 1301 * Stolen memory is segmented in hardware with different portions 1302 * offlimits to certain functions. 1303 * 1304 * The drm_mm is initialised to the total accessible range, as found 1305 * from the PCI config. On Broadwell+, this is further restricted to 1306 * avoid the first page! The upper end of stolen memory is reserved for 1307 * hardware functions and similarly removed from the accessible range. 1308 */ 1309 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */ 1310 1311 struct intel_uncore uncore; 1312 struct intel_uncore_mmio_debug mmio_debug; 1313 1314 struct i915_virtual_gpu vgpu; 1315 1316 struct intel_gvt *gvt; 1317 1318 struct intel_wopcm wopcm; 1319 1320 struct intel_csr csr; 1321 1322 struct intel_gmbus gmbus[GMBUS_NUM_PINS]; 1323 1324 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 1325 * controller on different i2c buses. */ 1326 struct mutex gmbus_mutex; 1327 1328 /** 1329 * Base address of where the gmbus and gpio blocks are located (either 1330 * on PCH or on SoC for platforms without PCH). 1331 */ 1332 u32 gpio_mmio_base; 1333 1334 /* MMIO base address for MIPI regs */ 1335 u32 mipi_mmio_base; 1336 1337 u32 psr_mmio_base; 1338 1339 u32 pps_mmio_base; 1340 1341 wait_queue_head_t gmbus_wait_queue; 1342 1343 struct pci_dev *bridge_dev; 1344 1345 /* Context used internally to idle the GPU and setup initial state */ 1346 struct i915_gem_context *kernel_context; 1347 1348 struct intel_engine_cs *engine[I915_NUM_ENGINES]; 1349 struct rb_root uabi_engines; 1350 1351 struct resource mch_res; 1352 1353 /* protects the irq masks */ 1354 spinlock_t irq_lock; 1355 1356 bool display_irqs_enabled; 1357 1358 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ 1359 struct pm_qos_request pm_qos; 1360 1361 /* Sideband mailbox protection */ 1362 struct mutex sb_lock; 1363 struct pm_qos_request sb_qos; 1364 1365 /** Cached value of IMR to avoid reads in updating the bitfield */ 1366 union { 1367 u32 irq_mask; 1368 u32 de_irq_mask[I915_MAX_PIPES]; 1369 }; 1370 u32 pm_rps_events; 1371 u32 pipestat_irq_mask[I915_MAX_PIPES]; 1372 1373 struct i915_hotplug hotplug; 1374 struct intel_fbc fbc; 1375 struct i915_drrs drrs; 1376 struct intel_opregion opregion; 1377 struct intel_vbt_data vbt; 1378 1379 bool preserve_bios_swizzle; 1380 1381 /* overlay */ 1382 struct intel_overlay *overlay; 1383 1384 /* backlight registers and fields in struct intel_panel */ 1385 struct mutex backlight_lock; 1386 1387 /* protects panel power sequencer state */ 1388 struct mutex pps_mutex; 1389 1390 unsigned int fsb_freq, mem_freq, is_ddr3; 1391 unsigned int skl_preferred_vco_freq; 1392 unsigned int max_cdclk_freq; 1393 1394 unsigned int max_dotclk_freq; 1395 unsigned int rawclk_freq; 1396 unsigned int hpll_freq; 1397 unsigned int fdi_pll_freq; 1398 unsigned int czclk_freq; 1399 1400 struct { 1401 /* 1402 * The current logical cdclk state. 1403 * See intel_atomic_state.cdclk.logical 1404 * 1405 * For reading holding any crtc lock is sufficient, 1406 * for writing must hold all of them. 1407 */ 1408 struct intel_cdclk_state logical; 1409 /* 1410 * The current actual cdclk state. 1411 * See intel_atomic_state.cdclk.actual 1412 */ 1413 struct intel_cdclk_state actual; 1414 /* The current hardware cdclk state */ 1415 struct intel_cdclk_state hw; 1416 1417 int force_min_cdclk; 1418 } cdclk; 1419 1420 /** 1421 * wq - Driver workqueue for GEM. 1422 * 1423 * NOTE: Work items scheduled here are not allowed to grab any modeset 1424 * locks, for otherwise the flushing done in the pageflip code will 1425 * result in deadlocks. 1426 */ 1427 struct workqueue_struct *wq; 1428 1429 /* ordered wq for modesets */ 1430 struct workqueue_struct *modeset_wq; 1431 1432 /* Display functions */ 1433 struct drm_i915_display_funcs display; 1434 1435 /* PCH chipset type */ 1436 enum intel_pch pch_type; 1437 unsigned short pch_id; 1438 1439 unsigned long quirks; 1440 1441 struct drm_atomic_state *modeset_restore_state; 1442 struct drm_modeset_acquire_ctx reset_ctx; 1443 1444 struct i915_ggtt ggtt; /* VM representing the global address space */ 1445 1446 struct i915_gem_mm mm; 1447 DECLARE_HASHTABLE(mm_structs, 7); 1448 struct mutex mm_lock; 1449 1450 /* Kernel Modesetting */ 1451 1452 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; 1453 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; 1454 1455 #ifdef CONFIG_DEBUG_FS 1456 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; 1457 #endif 1458 1459 /* dpll and cdclk state is protected by connection_mutex */ 1460 int num_shared_dpll; 1461 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 1462 const struct intel_dpll_mgr *dpll_mgr; 1463 1464 /* 1465 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll. 1466 * Must be global rather than per dpll, because on some platforms 1467 * plls share registers. 1468 */ 1469 struct mutex dpll_lock; 1470 1471 unsigned int active_crtcs; 1472 /* minimum acceptable cdclk for each pipe */ 1473 int min_cdclk[I915_MAX_PIPES]; 1474 /* minimum acceptable voltage level for each pipe */ 1475 u8 min_voltage_level[I915_MAX_PIPES]; 1476 1477 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; 1478 1479 struct i915_wa_list gt_wa_list; 1480 1481 struct i915_frontbuffer_tracking fb_tracking; 1482 1483 struct intel_atomic_helper { 1484 struct llist_head free_list; 1485 struct work_struct free_work; 1486 } atomic_helper; 1487 1488 u16 orig_clock; 1489 1490 bool mchbar_need_disable; 1491 1492 struct intel_l3_parity l3_parity; 1493 1494 /* 1495 * edram size in MB. 1496 * Cannot be determined by PCIID. You must always read a register. 1497 */ 1498 u32 edram_size_mb; 1499 1500 /* gen6+ GT PM state */ 1501 struct intel_gen6_power_mgmt gt_pm; 1502 1503 /* ilk-only ips/rps state. Everything in here is protected by the global 1504 * mchdev_lock in intel_pm.c */ 1505 struct intel_ilk_power_mgmt ips; 1506 1507 struct i915_power_domains power_domains; 1508 1509 struct i915_psr psr; 1510 1511 struct i915_gpu_error gpu_error; 1512 1513 struct drm_i915_gem_object *vlv_pctx; 1514 1515 /* list of fbdev register on this device */ 1516 struct intel_fbdev *fbdev; 1517 struct work_struct fbdev_suspend_work; 1518 1519 struct drm_property *broadcast_rgb_property; 1520 struct drm_property *force_audio_property; 1521 1522 /* hda/i915 audio component */ 1523 struct i915_audio_component *audio_component; 1524 bool audio_component_registered; 1525 /** 1526 * av_mutex - mutex for audio/video sync 1527 * 1528 */ 1529 struct mutex av_mutex; 1530 int audio_power_refcount; 1531 1532 struct { 1533 struct mutex mutex; 1534 struct list_head list; 1535 struct llist_head free_list; 1536 struct work_struct free_work; 1537 1538 /* The hw wants to have a stable context identifier for the 1539 * lifetime of the context (for OA, PASID, faults, etc). 1540 * This is limited in execlists to 21 bits. 1541 */ 1542 struct ida hw_ida; 1543 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */ 1544 #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */ 1545 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */ 1546 /* in Gen12 ID 0x7FF is reserved to indicate idle */ 1547 #define GEN12_MAX_CONTEXT_HW_ID (GEN11_MAX_CONTEXT_HW_ID - 1) 1548 struct list_head hw_id_list; 1549 } contexts; 1550 1551 u32 fdi_rx_config; 1552 1553 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ 1554 u32 chv_phy_control; 1555 /* 1556 * Shadows for CHV DPLL_MD regs to keep the state 1557 * checker somewhat working in the presence hardware 1558 * crappiness (can't read out DPLL_MD for pipes B & C). 1559 */ 1560 u32 chv_dpll_md[I915_MAX_PIPES]; 1561 u32 bxt_phy_grc; 1562 1563 u32 suspend_count; 1564 bool power_domains_suspended; 1565 struct i915_suspend_saved_registers regfile; 1566 struct vlv_s0ix_state *vlv_s0ix_state; 1567 1568 enum { 1569 I915_SAGV_UNKNOWN = 0, 1570 I915_SAGV_DISABLED, 1571 I915_SAGV_ENABLED, 1572 I915_SAGV_NOT_CONTROLLED 1573 } sagv_status; 1574 1575 struct { 1576 /* 1577 * Raw watermark latency values: 1578 * in 0.1us units for WM0, 1579 * in 0.5us units for WM1+. 1580 */ 1581 /* primary */ 1582 u16 pri_latency[5]; 1583 /* sprite */ 1584 u16 spr_latency[5]; 1585 /* cursor */ 1586 u16 cur_latency[5]; 1587 /* 1588 * Raw watermark memory latency values 1589 * for SKL for all 8 levels 1590 * in 1us units. 1591 */ 1592 u16 skl_latency[8]; 1593 1594 /* current hardware state */ 1595 union { 1596 struct ilk_wm_values hw; 1597 struct skl_ddb_values skl_hw; 1598 struct vlv_wm_values vlv; 1599 struct g4x_wm_values g4x; 1600 }; 1601 1602 u8 max_level; 1603 1604 /* 1605 * Should be held around atomic WM register writing; also 1606 * protects * intel_crtc->wm.active and 1607 * crtc_state->wm.need_postvbl_update. 1608 */ 1609 struct mutex wm_mutex; 1610 1611 /* 1612 * Set during HW readout of watermarks/DDB. Some platforms 1613 * need to know when we're still using BIOS-provided values 1614 * (which we don't fully trust). 1615 */ 1616 bool distrust_bios_wm; 1617 } wm; 1618 1619 struct dram_info { 1620 bool valid; 1621 bool is_16gb_dimm; 1622 u8 num_channels; 1623 u8 ranks; 1624 u32 bandwidth_kbps; 1625 bool symmetric_memory; 1626 enum intel_dram_type { 1627 INTEL_DRAM_UNKNOWN, 1628 INTEL_DRAM_DDR3, 1629 INTEL_DRAM_DDR4, 1630 INTEL_DRAM_LPDDR3, 1631 INTEL_DRAM_LPDDR4 1632 } type; 1633 } dram_info; 1634 1635 struct intel_bw_info { 1636 unsigned int deratedbw[3]; /* for each QGV point */ 1637 u8 num_qgv_points; 1638 u8 num_planes; 1639 } max_bw[6]; 1640 1641 struct drm_private_obj bw_obj; 1642 1643 struct intel_runtime_pm runtime_pm; 1644 1645 struct { 1646 bool initialized; 1647 1648 struct kobject *metrics_kobj; 1649 struct ctl_table_header *sysctl_header; 1650 1651 /* 1652 * Lock associated with adding/modifying/removing OA configs 1653 * in dev_priv->perf.metrics_idr. 1654 */ 1655 struct mutex metrics_lock; 1656 1657 /* 1658 * List of dynamic configurations, you need to hold 1659 * dev_priv->perf.metrics_lock to access it. 1660 */ 1661 struct idr metrics_idr; 1662 1663 /* 1664 * Lock associated with anything below within this structure 1665 * except exclusive_stream. 1666 */ 1667 struct mutex lock; 1668 struct list_head streams; 1669 1670 /* 1671 * The stream currently using the OA unit. If accessed 1672 * outside a syscall associated to its file 1673 * descriptor, you need to hold 1674 * dev_priv->drm.struct_mutex. 1675 */ 1676 struct i915_perf_stream *exclusive_stream; 1677 1678 /** 1679 * For rate limiting any notifications of spurious 1680 * invalid OA reports 1681 */ 1682 struct ratelimit_state spurious_report_rs; 1683 1684 struct i915_oa_config test_config; 1685 1686 u32 gen7_latched_oastatus1; 1687 u32 ctx_oactxctrl_offset; 1688 u32 ctx_flexeu0_offset; 1689 1690 /** 1691 * The RPT_ID/reason field for Gen8+ includes a bit 1692 * to determine if the CTX ID in the report is valid 1693 * but the specific bit differs between Gen 8 and 9 1694 */ 1695 u32 gen8_valid_ctx_bit; 1696 1697 struct i915_oa_ops ops; 1698 const struct i915_oa_format *oa_formats; 1699 } perf; 1700 1701 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ 1702 struct intel_gt gt; 1703 1704 struct { 1705 struct notifier_block pm_notifier; 1706 1707 /** 1708 * We leave the user IRQ off as much as possible, 1709 * but this means that requests will finish and never 1710 * be retired once the system goes idle. Set a timer to 1711 * fire periodically while the ring is running. When it 1712 * fires, go retire requests. 1713 */ 1714 struct delayed_work retire_work; 1715 1716 /** 1717 * When we detect an idle GPU, we want to turn on 1718 * powersaving features. So once we see that there 1719 * are no more requests outstanding and no more 1720 * arrive within a small period of time, we fire 1721 * off the idle_work. 1722 */ 1723 struct work_struct idle_work; 1724 } gem; 1725 1726 /* For i945gm vblank irq vs. C3 workaround */ 1727 struct { 1728 struct work_struct work; 1729 struct pm_qos_request pm_qos; 1730 u8 c3_disable_latency; 1731 u8 enabled; 1732 } i945gm_vblank; 1733 1734 /* perform PHY state sanity checks? */ 1735 bool chv_phy_assert[2]; 1736 1737 bool ipc_enabled; 1738 1739 /* Used to save the pipe-to-encoder mapping for audio */ 1740 struct intel_encoder *av_enc_map[I915_MAX_PIPES]; 1741 1742 /* necessary resource sharing with HDMI LPE audio driver. */ 1743 struct { 1744 struct platform_device *platdev; 1745 int irq; 1746 } lpe_audio; 1747 1748 struct i915_pmu pmu; 1749 1750 struct i915_hdcp_comp_master *hdcp_master; 1751 bool hdcp_comp_added; 1752 1753 /* Mutex to protect the above hdcp component related values. */ 1754 struct mutex hdcp_comp_mutex; 1755 1756 /* 1757 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 1758 * will be rejected. Instead look for a better place. 1759 */ 1760 }; 1761 1762 struct dram_dimm_info { 1763 u8 size, width, ranks; 1764 }; 1765 1766 struct dram_channel_info { 1767 struct dram_dimm_info dimm_l, dimm_s; 1768 u8 ranks; 1769 bool is_16gb_dimm; 1770 }; 1771 1772 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 1773 { 1774 return container_of(dev, struct drm_i915_private, drm); 1775 } 1776 1777 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) 1778 { 1779 return dev_get_drvdata(kdev); 1780 } 1781 1782 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) 1783 { 1784 return pci_get_drvdata(pdev); 1785 } 1786 1787 /* Simple iterator over all initialised engines */ 1788 #define for_each_engine(engine__, dev_priv__, id__) \ 1789 for ((id__) = 0; \ 1790 (id__) < I915_NUM_ENGINES; \ 1791 (id__)++) \ 1792 for_each_if ((engine__) = (dev_priv__)->engine[(id__)]) 1793 1794 /* Iterator over subset of engines selected by mask */ 1795 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \ 1796 for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->engine_mask; \ 1797 (tmp__) ? \ 1798 ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \ 1799 0;) 1800 1801 #define rb_to_uabi_engine(rb) \ 1802 rb_entry_safe(rb, struct intel_engine_cs, uabi_node) 1803 1804 #define for_each_uabi_engine(engine__, i915__) \ 1805 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\ 1806 (engine__); \ 1807 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 1808 1809 #define I915_GTT_OFFSET_NONE ((u32)-1) 1810 1811 /* 1812 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is 1813 * considered to be the frontbuffer for the given plane interface-wise. This 1814 * doesn't mean that the hw necessarily already scans it out, but that any 1815 * rendering (by the cpu or gpu) will land in the frontbuffer eventually. 1816 * 1817 * We have one bit per pipe and per scanout plane type. 1818 */ 1819 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 1820 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \ 1821 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \ 1822 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \ 1823 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \ 1824 }) 1825 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ 1826 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) 1827 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ 1828 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \ 1829 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) 1830 1831 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info) 1832 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) 1833 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) 1834 1835 #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen) 1836 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id) 1837 1838 #define REVID_FOREVER 0xff 1839 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) 1840 1841 #define INTEL_GEN_MASK(s, e) ( \ 1842 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \ 1843 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \ 1844 GENMASK((e) - 1, (s) - 1)) 1845 1846 /* Returns true if Gen is in inclusive range [Start, End] */ 1847 #define IS_GEN_RANGE(dev_priv, s, e) \ 1848 (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e)))) 1849 1850 #define IS_GEN(dev_priv, n) \ 1851 (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \ 1852 INTEL_INFO(dev_priv)->gen == (n)) 1853 1854 /* 1855 * Return true if revision is in range [since,until] inclusive. 1856 * 1857 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. 1858 */ 1859 #define IS_REVID(p, since, until) \ 1860 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) 1861 1862 static __always_inline unsigned int 1863 __platform_mask_index(const struct intel_runtime_info *info, 1864 enum intel_platform p) 1865 { 1866 const unsigned int pbits = 1867 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 1868 1869 /* Expand the platform_mask array if this fails. */ 1870 BUILD_BUG_ON(INTEL_MAX_PLATFORMS > 1871 pbits * ARRAY_SIZE(info->platform_mask)); 1872 1873 return p / pbits; 1874 } 1875 1876 static __always_inline unsigned int 1877 __platform_mask_bit(const struct intel_runtime_info *info, 1878 enum intel_platform p) 1879 { 1880 const unsigned int pbits = 1881 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 1882 1883 return p % pbits + INTEL_SUBPLATFORM_BITS; 1884 } 1885 1886 static inline u32 1887 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p) 1888 { 1889 const unsigned int pi = __platform_mask_index(info, p); 1890 1891 return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS; 1892 } 1893 1894 static __always_inline bool 1895 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p) 1896 { 1897 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 1898 const unsigned int pi = __platform_mask_index(info, p); 1899 const unsigned int pb = __platform_mask_bit(info, p); 1900 1901 BUILD_BUG_ON(!__builtin_constant_p(p)); 1902 1903 return info->platform_mask[pi] & BIT(pb); 1904 } 1905 1906 static __always_inline bool 1907 IS_SUBPLATFORM(const struct drm_i915_private *i915, 1908 enum intel_platform p, unsigned int s) 1909 { 1910 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 1911 const unsigned int pi = __platform_mask_index(info, p); 1912 const unsigned int pb = __platform_mask_bit(info, p); 1913 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1; 1914 const u32 mask = info->platform_mask[pi]; 1915 1916 BUILD_BUG_ON(!__builtin_constant_p(p)); 1917 BUILD_BUG_ON(!__builtin_constant_p(s)); 1918 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS); 1919 1920 /* Shift and test on the MSB position so sign flag can be used. */ 1921 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); 1922 } 1923 1924 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile) 1925 1926 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) 1927 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) 1928 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) 1929 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) 1930 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) 1931 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM) 1932 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) 1933 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM) 1934 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) 1935 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM) 1936 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) 1937 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) 1938 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) 1939 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) 1940 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) 1941 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE) 1942 #define IS_IRONLAKE_M(dev_priv) \ 1943 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv)) 1944 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) 1945 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ 1946 INTEL_INFO(dev_priv)->gt == 1) 1947 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) 1948 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) 1949 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) 1950 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) 1951 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) 1952 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) 1953 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) 1954 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) 1955 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) 1956 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) 1957 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) 1958 #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) 1959 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) 1960 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ 1961 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) 1962 #define IS_BDW_ULT(dev_priv) \ 1963 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) 1964 #define IS_BDW_ULX(dev_priv) \ 1965 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX) 1966 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ 1967 INTEL_INFO(dev_priv)->gt == 3) 1968 #define IS_HSW_ULT(dev_priv) \ 1969 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) 1970 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ 1971 INTEL_INFO(dev_priv)->gt == 3) 1972 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \ 1973 INTEL_INFO(dev_priv)->gt == 1) 1974 /* ULX machines are also considered ULT. */ 1975 #define IS_HSW_ULX(dev_priv) \ 1976 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) 1977 #define IS_SKL_ULT(dev_priv) \ 1978 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) 1979 #define IS_SKL_ULX(dev_priv) \ 1980 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) 1981 #define IS_KBL_ULT(dev_priv) \ 1982 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) 1983 #define IS_KBL_ULX(dev_priv) \ 1984 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) 1985 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1986 INTEL_INFO(dev_priv)->gt == 2) 1987 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1988 INTEL_INFO(dev_priv)->gt == 3) 1989 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1990 INTEL_INFO(dev_priv)->gt == 4) 1991 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ 1992 INTEL_INFO(dev_priv)->gt == 2) 1993 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ 1994 INTEL_INFO(dev_priv)->gt == 3) 1995 #define IS_CFL_ULT(dev_priv) \ 1996 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) 1997 #define IS_CFL_ULX(dev_priv) \ 1998 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX) 1999 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 2000 INTEL_INFO(dev_priv)->gt == 2) 2001 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 2002 INTEL_INFO(dev_priv)->gt == 3) 2003 #define IS_CNL_WITH_PORT_F(dev_priv) \ 2004 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF) 2005 #define IS_ICL_WITH_PORT_F(dev_priv) \ 2006 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) 2007 2008 #define SKL_REVID_A0 0x0 2009 #define SKL_REVID_B0 0x1 2010 #define SKL_REVID_C0 0x2 2011 #define SKL_REVID_D0 0x3 2012 #define SKL_REVID_E0 0x4 2013 #define SKL_REVID_F0 0x5 2014 #define SKL_REVID_G0 0x6 2015 #define SKL_REVID_H0 0x7 2016 2017 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) 2018 2019 #define BXT_REVID_A0 0x0 2020 #define BXT_REVID_A1 0x1 2021 #define BXT_REVID_B0 0x3 2022 #define BXT_REVID_B_LAST 0x8 2023 #define BXT_REVID_C0 0x9 2024 2025 #define IS_BXT_REVID(dev_priv, since, until) \ 2026 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until)) 2027 2028 #define KBL_REVID_A0 0x0 2029 #define KBL_REVID_B0 0x1 2030 #define KBL_REVID_C0 0x2 2031 #define KBL_REVID_D0 0x3 2032 #define KBL_REVID_E0 0x4 2033 2034 #define IS_KBL_REVID(dev_priv, since, until) \ 2035 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until)) 2036 2037 #define GLK_REVID_A0 0x0 2038 #define GLK_REVID_A1 0x1 2039 2040 #define IS_GLK_REVID(dev_priv, since, until) \ 2041 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until)) 2042 2043 #define CNL_REVID_A0 0x0 2044 #define CNL_REVID_B0 0x1 2045 #define CNL_REVID_C0 0x2 2046 2047 #define IS_CNL_REVID(p, since, until) \ 2048 (IS_CANNONLAKE(p) && IS_REVID(p, since, until)) 2049 2050 #define ICL_REVID_A0 0x0 2051 #define ICL_REVID_A2 0x1 2052 #define ICL_REVID_B0 0x3 2053 #define ICL_REVID_B2 0x4 2054 #define ICL_REVID_C0 0x5 2055 2056 #define IS_ICL_REVID(p, since, until) \ 2057 (IS_ICELAKE(p) && IS_REVID(p, since, until)) 2058 2059 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) 2060 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) 2061 #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) 2062 2063 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id)) 2064 2065 #define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({ \ 2066 unsigned int first__ = (first); \ 2067 unsigned int count__ = (count); \ 2068 (INTEL_INFO(dev_priv)->engine_mask & \ 2069 GENMASK(first__ + count__ - 1, first__)) >> first__; \ 2070 }) 2071 #define VDBOX_MASK(dev_priv) \ 2072 ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS) 2073 #define VEBOX_MASK(dev_priv) \ 2074 ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS) 2075 2076 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) 2077 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) 2078 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb) 2079 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \ 2080 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv)) 2081 2082 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical) 2083 2084 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ 2085 (INTEL_INFO(dev_priv)->has_logical_ring_contexts) 2086 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \ 2087 (INTEL_INFO(dev_priv)->has_logical_ring_elsq) 2088 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \ 2089 (INTEL_INFO(dev_priv)->has_logical_ring_preemption) 2090 2091 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) 2092 2093 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type) 2094 #define HAS_PPGTT(dev_priv) \ 2095 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE) 2096 #define HAS_FULL_PPGTT(dev_priv) \ 2097 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL) 2098 2099 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \ 2100 GEM_BUG_ON((sizes) == 0); \ 2101 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \ 2102 }) 2103 2104 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay) 2105 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ 2106 (INTEL_INFO(dev_priv)->display.overlay_needs_physical) 2107 2108 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 2109 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) 2110 2111 /* WaRsDisableCoarsePowerGating:skl,cnl */ 2112 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ 2113 (IS_CANNONLAKE(dev_priv) || \ 2114 IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv)) 2115 2116 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4) 2117 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \ 2118 IS_GEMINILAKE(dev_priv) || \ 2119 IS_KABYLAKE(dev_priv)) 2120 2121 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 2122 * rows, which changed the alignment requirements and fence programming. 2123 */ 2124 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \ 2125 !(IS_I915G(dev_priv) || \ 2126 IS_I915GM(dev_priv))) 2127 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv) 2128 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug) 2129 2130 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) 2131 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc) 2132 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7) 2133 2134 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) 2135 2136 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) 2137 2138 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) 2139 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg) 2140 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) 2141 #define HAS_TRANSCODER_EDP(dev_priv) (INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_EDP] != 0) 2142 2143 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) 2144 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p) 2145 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ 2146 2147 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps) 2148 2149 #define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr) 2150 2151 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm) 2152 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc) 2153 2154 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc) 2155 2156 #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc) 2157 2158 /* Having GuC is not the same as using GuC */ 2159 #define USES_GUC(dev_priv) intel_uc_uses_guc(&(dev_priv)->gt.uc) 2160 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_uses_guc_submission(&(dev_priv)->gt.uc) 2161 2162 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu) 2163 2164 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs) 2165 2166 2167 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch) 2168 2169 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9) 2170 2171 /* DPF == dynamic parity feature */ 2172 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf) 2173 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ 2174 2 : HAS_L3_DPF(dev_priv)) 2175 2176 #define GT_FREQUENCY_MULTIPLIER 50 2177 #define GEN9_FREQ_SCALER 3 2178 2179 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->num_pipes > 0) 2180 2181 static inline bool intel_vtd_active(void) 2182 { 2183 #ifdef CONFIG_INTEL_IOMMU 2184 if (intel_iommu_gfx_mapped) 2185 return true; 2186 #endif 2187 return false; 2188 } 2189 2190 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) 2191 { 2192 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active(); 2193 } 2194 2195 static inline bool 2196 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv) 2197 { 2198 return IS_BROXTON(dev_priv) && intel_vtd_active(); 2199 } 2200 2201 /* i915_drv.c */ 2202 #ifdef CONFIG_COMPAT 2203 long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); 2204 #else 2205 #define i915_compat_ioctl NULL 2206 #endif 2207 extern const struct dev_pm_ops i915_pm_ops; 2208 2209 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent); 2210 void i915_driver_remove(struct drm_i915_private *i915); 2211 2212 void intel_engine_init_hangcheck(struct intel_engine_cs *engine); 2213 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); 2214 2215 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv) 2216 { 2217 return dev_priv->gvt; 2218 } 2219 2220 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv) 2221 { 2222 return dev_priv->vgpu.active; 2223 } 2224 2225 int i915_getparam_ioctl(struct drm_device *dev, void *data, 2226 struct drm_file *file_priv); 2227 2228 /* i915_gem.c */ 2229 int i915_gem_init_userptr(struct drm_i915_private *dev_priv); 2230 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv); 2231 void i915_gem_sanitize(struct drm_i915_private *i915); 2232 int i915_gem_init_early(struct drm_i915_private *dev_priv); 2233 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv); 2234 int i915_gem_freeze(struct drm_i915_private *dev_priv); 2235 int i915_gem_freeze_late(struct drm_i915_private *dev_priv); 2236 2237 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915) 2238 { 2239 /* 2240 * A single pass should suffice to release all the freed objects (along 2241 * most call paths) , but be a little more paranoid in that freeing 2242 * the objects does take a little amount of time, during which the rcu 2243 * callbacks could have added new objects into the freed list, and 2244 * armed the work again. 2245 */ 2246 while (atomic_read(&i915->mm.free_count)) { 2247 flush_work(&i915->mm.free_work); 2248 rcu_barrier(); 2249 } 2250 } 2251 2252 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915) 2253 { 2254 /* 2255 * Similar to objects above (see i915_gem_drain_freed-objects), in 2256 * general we have workers that are armed by RCU and then rearm 2257 * themselves in their callbacks. To be paranoid, we need to 2258 * drain the workqueue a second time after waiting for the RCU 2259 * grace period so that we catch work queued via RCU from the first 2260 * pass. As neither drain_workqueue() nor flush_workqueue() report 2261 * a result, we make an assumption that we only don't require more 2262 * than 3 passes to catch all _recursive_ RCU delayed work. 2263 * 2264 */ 2265 int pass = 3; 2266 do { 2267 flush_workqueue(i915->wq); 2268 rcu_barrier(); 2269 i915_gem_drain_freed_objects(i915); 2270 } while (--pass); 2271 drain_workqueue(i915->wq); 2272 } 2273 2274 struct i915_vma * __must_check 2275 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, 2276 const struct i915_ggtt_view *view, 2277 u64 size, 2278 u64 alignment, 2279 u64 flags); 2280 2281 int i915_gem_object_unbind(struct drm_i915_gem_object *obj, 2282 unsigned long flags); 2283 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0) 2284 2285 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv); 2286 2287 static inline int __must_check 2288 i915_mutex_lock_interruptible(struct drm_device *dev) 2289 { 2290 return mutex_lock_interruptible(&dev->struct_mutex); 2291 } 2292 2293 int i915_gem_dumb_create(struct drm_file *file_priv, 2294 struct drm_device *dev, 2295 struct drm_mode_create_dumb *args); 2296 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 2297 u32 handle, u64 *offset); 2298 int i915_gem_mmap_gtt_version(void); 2299 2300 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno); 2301 2302 static inline u32 i915_reset_count(struct i915_gpu_error *error) 2303 { 2304 return atomic_read(&error->reset_count); 2305 } 2306 2307 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error, 2308 struct intel_engine_cs *engine) 2309 { 2310 return atomic_read(&error->reset_engine_count[engine->uabi_class]); 2311 } 2312 2313 void i915_gem_init_mmio(struct drm_i915_private *i915); 2314 int __must_check i915_gem_init(struct drm_i915_private *dev_priv); 2315 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv); 2316 void i915_gem_driver_register(struct drm_i915_private *i915); 2317 void i915_gem_driver_unregister(struct drm_i915_private *i915); 2318 void i915_gem_driver_remove(struct drm_i915_private *dev_priv); 2319 void i915_gem_driver_release(struct drm_i915_private *dev_priv); 2320 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv, 2321 unsigned int flags, long timeout); 2322 void i915_gem_suspend(struct drm_i915_private *dev_priv); 2323 void i915_gem_suspend_late(struct drm_i915_private *dev_priv); 2324 void i915_gem_resume(struct drm_i915_private *dev_priv); 2325 vm_fault_t i915_gem_fault(struct vm_fault *vmf); 2326 2327 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file); 2328 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 2329 2330 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 2331 enum i915_cache_level cache_level); 2332 2333 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 2334 struct dma_buf *dma_buf); 2335 2336 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags); 2337 2338 static inline struct i915_gem_context * 2339 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id) 2340 { 2341 return idr_find(&file_priv->context_idr, id); 2342 } 2343 2344 static inline struct i915_gem_context * 2345 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id) 2346 { 2347 struct i915_gem_context *ctx; 2348 2349 rcu_read_lock(); 2350 ctx = __i915_gem_context_lookup_rcu(file_priv, id); 2351 if (ctx && !kref_get_unless_zero(&ctx->ref)) 2352 ctx = NULL; 2353 rcu_read_unlock(); 2354 2355 return ctx; 2356 } 2357 2358 /* i915_gem_evict.c */ 2359 int __must_check i915_gem_evict_something(struct i915_address_space *vm, 2360 u64 min_size, u64 alignment, 2361 unsigned cache_level, 2362 u64 start, u64 end, 2363 unsigned flags); 2364 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm, 2365 struct drm_mm_node *node, 2366 unsigned int flags); 2367 int i915_gem_evict_vm(struct i915_address_space *vm); 2368 2369 /* i915_gem_internal.c */ 2370 struct drm_i915_gem_object * 2371 i915_gem_object_create_internal(struct drm_i915_private *dev_priv, 2372 phys_addr_t size); 2373 2374 /* i915_gem_tiling.c */ 2375 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 2376 { 2377 struct drm_i915_private *dev_priv = to_i915(obj->base.dev); 2378 2379 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 2380 i915_gem_object_is_tiled(obj); 2381 } 2382 2383 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size, 2384 unsigned int tiling, unsigned int stride); 2385 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size, 2386 unsigned int tiling, unsigned int stride); 2387 2388 const char *i915_cache_level_str(struct drm_i915_private *i915, int type); 2389 2390 /* i915_cmd_parser.c */ 2391 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); 2392 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine); 2393 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine); 2394 int intel_engine_cmd_parser(struct intel_engine_cs *engine, 2395 struct drm_i915_gem_object *batch_obj, 2396 struct drm_i915_gem_object *shadow_batch_obj, 2397 u32 batch_start_offset, 2398 u32 batch_len, 2399 bool is_master); 2400 2401 /* intel_device_info.c */ 2402 static inline struct intel_device_info * 2403 mkwrite_device_info(struct drm_i915_private *dev_priv) 2404 { 2405 return (struct intel_device_info *)INTEL_INFO(dev_priv); 2406 } 2407 2408 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 2409 struct drm_file *file); 2410 2411 #define __I915_REG_OP(op__, dev_priv__, ...) \ 2412 intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__) 2413 2414 #define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__)) 2415 #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__)) 2416 2417 #define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__)) 2418 2419 /* These are untraced mmio-accessors that are only valid to be used inside 2420 * critical sections, such as inside IRQ handlers, where forcewake is explicitly 2421 * controlled. 2422 * 2423 * Think twice, and think again, before using these. 2424 * 2425 * As an example, these accessors can possibly be used between: 2426 * 2427 * spin_lock_irq(&dev_priv->uncore.lock); 2428 * intel_uncore_forcewake_get__locked(); 2429 * 2430 * and 2431 * 2432 * intel_uncore_forcewake_put__locked(); 2433 * spin_unlock_irq(&dev_priv->uncore.lock); 2434 * 2435 * 2436 * Note: some registers may not need forcewake held, so 2437 * intel_uncore_forcewake_{get,put} can be omitted, see 2438 * intel_uncore_forcewake_for_reg(). 2439 * 2440 * Certain architectures will die if the same cacheline is concurrently accessed 2441 * by different clients (e.g. on Ivybridge). Access to registers should 2442 * therefore generally be serialised, by either the dev_priv->uncore.lock or 2443 * a more localised lock guarding all access to that bank of registers. 2444 */ 2445 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__)) 2446 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__)) 2447 2448 /* register wait wrappers for display regs */ 2449 #define intel_de_wait_for_register(dev_priv_, reg_, mask_, value_, timeout_) \ 2450 intel_wait_for_register(&(dev_priv_)->uncore, \ 2451 (reg_), (mask_), (value_), (timeout_)) 2452 2453 #define intel_de_wait_for_set(dev_priv_, reg_, mask_, timeout_) ({ \ 2454 u32 mask__ = (mask_); \ 2455 intel_de_wait_for_register((dev_priv_), (reg_), \ 2456 mask__, mask__, (timeout_)); \ 2457 }) 2458 2459 #define intel_de_wait_for_clear(dev_priv_, reg_, mask_, timeout_) \ 2460 intel_de_wait_for_register((dev_priv_), (reg_), (mask_), 0, (timeout_)) 2461 2462 /* i915_mm.c */ 2463 int remap_io_mapping(struct vm_area_struct *vma, 2464 unsigned long addr, unsigned long pfn, unsigned long size, 2465 struct io_mapping *iomap); 2466 2467 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915) 2468 { 2469 if (INTEL_GEN(i915) >= 10) 2470 return CNL_HWS_CSB_WRITE_INDEX; 2471 else 2472 return I915_HWS_CSB_WRITE_INDEX; 2473 } 2474 2475 static inline enum i915_map_type 2476 i915_coherent_map_type(struct drm_i915_private *i915) 2477 { 2478 return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC; 2479 } 2480 2481 #endif 2482