1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #include <linux/aperture.h> 31 #include <linux/acpi.h> 32 #include <linux/device.h> 33 #include <linux/module.h> 34 #include <linux/oom.h> 35 #include <linux/pci.h> 36 #include <linux/pm.h> 37 #include <linux/pm_runtime.h> 38 #include <linux/slab.h> 39 #include <linux/string_helpers.h> 40 #include <linux/vga_switcheroo.h> 41 #include <linux/vt.h> 42 43 #include <drm/drm_atomic_helper.h> 44 #include <drm/drm_client.h> 45 #include <drm/drm_client_event.h> 46 #include <drm/drm_ioctl.h> 47 #include <drm/drm_managed.h> 48 #include <drm/drm_probe_helper.h> 49 #include <drm/intel/display_member.h> 50 #include <drm/intel/display_parent_interface.h> 51 #include <drm/intel/intel_pcode_regs.h> 52 53 #include "display/i9xx_display_sr.h" 54 #include "display/intel_bw.h" 55 #include "display/intel_cdclk.h" 56 #include "display/intel_crtc.h" 57 #include "display/intel_display_device.h" 58 #include "display/intel_display_driver.h" 59 #include "display/intel_display_power.h" 60 #include "display/intel_dmc.h" 61 #include "display/intel_dp.h" 62 #include "display/intel_dpt.h" 63 #include "display/intel_dram.h" 64 #include "display/intel_encoder.h" 65 #include "display/intel_fbdev.h" 66 #include "display/intel_gmbus.h" 67 #include "display/intel_hotplug.h" 68 #include "display/intel_opregion.h" 69 #include "display/intel_overlay.h" 70 #include "display/intel_pch_refclk.h" 71 #include "display/intel_pps.h" 72 #include "display/intel_sbi.h" 73 #include "display/intel_sprite_uapi.h" 74 #include "display/skl_watermark.h" 75 76 #include "gem/i915_gem_context.h" 77 #include "gem/i915_gem_create.h" 78 #include "gem/i915_gem_dmabuf.h" 79 #include "gem/i915_gem_ioctls.h" 80 #include "gem/i915_gem_mman.h" 81 #include "gem/i915_gem_object_frontbuffer.h" 82 #include "gem/i915_gem_pm.h" 83 #include "gt/intel_gt.h" 84 #include "gt/intel_gt_pm.h" 85 #include "gt/intel_gt_print.h" 86 #include "gt/intel_rc6.h" 87 #include "gt/intel_rps.h" 88 89 #include "pxp/intel_pxp.h" 90 #include "pxp/intel_pxp_debugfs.h" 91 #include "pxp/intel_pxp_pm.h" 92 93 #include "i915_bo.h" 94 #include "i915_debugfs.h" 95 #include "i915_display_pc8.h" 96 #include "i915_dpt.h" 97 #include "i915_driver.h" 98 #include "i915_drm_client.h" 99 #include "i915_drv.h" 100 #include "i915_dsb_buffer.h" 101 #include "i915_edram.h" 102 #include "i915_fb_pin.h" 103 #include "i915_file_private.h" 104 #include "i915_getparam.h" 105 #include "i915_gmch.h" 106 #include "i915_hdcp_gsc.h" 107 #include "i915_hwmon.h" 108 #include "i915_initial_plane.h" 109 #include "i915_ioc32.h" 110 #include "i915_ioctl.h" 111 #include "i915_irq.h" 112 #include "i915_memcpy.h" 113 #include "i915_overlay.h" 114 #include "i915_panic.h" 115 #include "i915_perf.h" 116 #include "i915_query.h" 117 #include "i915_reg.h" 118 #include "i915_switcheroo.h" 119 #include "i915_sysfs.h" 120 #include "i915_utils.h" 121 #include "i915_vgpu.h" 122 #include "intel_clock_gating.h" 123 #include "intel_cpu_info.h" 124 #include "intel_gvt.h" 125 #include "intel_memory_region.h" 126 #include "intel_pcode.h" 127 #include "intel_region_ttm.h" 128 #include "vlv_iosf_sb.h" 129 #include "vlv_suspend.h" 130 131 static const struct drm_driver i915_drm_driver; 132 133 static int i915_workqueues_init(struct drm_i915_private *dev_priv) 134 { 135 /* 136 * The i915 workqueue is primarily used for batched retirement of 137 * requests (and thus managing bo) once the task has been completed 138 * by the GPU. i915_retire_requests() is called directly when we 139 * need high-priority retirement, such as waiting for an explicit 140 * bo. 141 * 142 * It is also used for periodic low-priority events, such as 143 * idle-timers and recording error state. 144 * 145 * All tasks on the workqueue are expected to acquire the dev mutex 146 * so there is no point in running more than one instance of the 147 * workqueue at any time. Use an ordered one. 148 */ 149 dev_priv->wq = alloc_ordered_workqueue("i915", 0); 150 if (dev_priv->wq == NULL) 151 goto out_err; 152 153 /* 154 * The unordered i915 workqueue should be used for all work 155 * scheduling that do not require running in order, which used 156 * to be scheduled on the system_percpu_wq before moving to a driver 157 * instance due deprecation of flush_scheduled_work(). 158 */ 159 dev_priv->unordered_wq = alloc_workqueue("i915-unordered", WQ_PERCPU, 160 0); 161 if (dev_priv->unordered_wq == NULL) 162 goto out_free_wq; 163 164 return 0; 165 166 out_free_wq: 167 destroy_workqueue(dev_priv->wq); 168 out_err: 169 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n"); 170 171 return -ENOMEM; 172 } 173 174 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) 175 { 176 destroy_workqueue(dev_priv->unordered_wq); 177 destroy_workqueue(dev_priv->wq); 178 } 179 180 /* 181 * We don't keep the workarounds for pre-production hardware, so we expect our 182 * driver to fail on these machines in one way or another. A little warning on 183 * dmesg may help both the user and the bug triagers. 184 * 185 * Our policy for removing pre-production workarounds is to keep the 186 * current gen workarounds as a guide to the bring-up of the next gen 187 * (workarounds have a habit of persisting!). Anything older than that 188 * should be removed along with the complications they introduce. 189 */ 190 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) 191 { 192 bool pre = false; 193 194 pre |= IS_HASWELL_EARLY_SDV(dev_priv); 195 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6; 196 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA; 197 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 198 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3; 199 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7; 200 pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 201 pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 202 pre |= IS_DG2_G10(dev_priv) && INTEL_REVID(dev_priv) < 0x8; 203 pre |= IS_DG2_G11(dev_priv) && INTEL_REVID(dev_priv) < 0x5; 204 pre |= IS_DG2_G12(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 205 206 if (pre) { 207 drm_err(&dev_priv->drm, "This is a pre-production stepping. " 208 "It may not be fully functional.\n"); 209 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); 210 } 211 } 212 213 static void sanitize_gpu(struct drm_i915_private *i915) 214 { 215 if (!intel_gt_gpu_reset_clobbers_display(to_gt(i915))) { 216 struct intel_gt *gt; 217 unsigned int i; 218 219 for_each_gt(gt, i915, i) 220 intel_gt_reset_all_engines(gt); 221 } 222 } 223 224 /** 225 * i915_driver_early_probe - setup state not requiring device access 226 * @dev_priv: device private 227 * 228 * Initialize everything that is a "SW-only" state, that is state not 229 * requiring accessing the device or exposing the driver via kernel internal 230 * or userspace interfaces. Example steps belonging here: lock initialization, 231 * system memory allocation, setting up device specific attributes and 232 * function hooks not requiring accessing the device. 233 */ 234 static int i915_driver_early_probe(struct drm_i915_private *dev_priv) 235 { 236 struct intel_display *display = dev_priv->display; 237 int ret = 0; 238 239 intel_device_info_runtime_init_early(dev_priv); 240 241 intel_step_init(dev_priv); 242 243 intel_uncore_mmio_debug_init_early(dev_priv); 244 245 spin_lock_init(&dev_priv->gpu_error.lock); 246 247 intel_sbi_init(display); 248 vlv_iosf_sb_init(dev_priv); 249 mutex_init(&dev_priv->sb_lock); 250 251 i915_memcpy_init_early(dev_priv); 252 intel_runtime_pm_init_early(&dev_priv->runtime_pm); 253 254 ret = i915_workqueues_init(dev_priv); 255 if (ret < 0) 256 return ret; 257 258 ret = vlv_suspend_init(dev_priv); 259 if (ret < 0) 260 goto err_workqueues; 261 262 ret = intel_region_ttm_device_init(dev_priv); 263 if (ret) 264 goto err_ttm; 265 266 ret = intel_root_gt_init_early(dev_priv); 267 if (ret < 0) 268 goto err_rootgt; 269 270 i915_gem_init_early(dev_priv); 271 272 intel_irq_init(dev_priv); 273 intel_display_driver_early_probe(display); 274 intel_clock_gating_hooks_init(&dev_priv->drm); 275 276 intel_detect_preproduction_hw(dev_priv); 277 278 return 0; 279 280 err_rootgt: 281 intel_region_ttm_device_fini(dev_priv); 282 err_ttm: 283 vlv_suspend_cleanup(dev_priv); 284 err_workqueues: 285 i915_workqueues_cleanup(dev_priv); 286 return ret; 287 } 288 ALLOW_ERROR_INJECTION(i915_driver_early_probe, ERRNO); 289 290 /** 291 * i915_driver_late_release - cleanup the setup done in 292 * i915_driver_early_probe() 293 * @dev_priv: device private 294 */ 295 static void i915_driver_late_release(struct drm_i915_private *dev_priv) 296 { 297 struct intel_display *display = dev_priv->display; 298 299 intel_irq_fini(dev_priv); 300 intel_display_power_cleanup(display); 301 i915_gem_cleanup_early(dev_priv); 302 intel_gt_driver_late_release_all(dev_priv); 303 intel_region_ttm_device_fini(dev_priv); 304 vlv_suspend_cleanup(dev_priv); 305 i915_workqueues_cleanup(dev_priv); 306 307 mutex_destroy(&dev_priv->sb_lock); 308 vlv_iosf_sb_fini(dev_priv); 309 intel_sbi_fini(display); 310 311 i915_params_free(&dev_priv->params); 312 313 intel_display_device_remove(display); 314 dev_priv->display = NULL; 315 } 316 317 /** 318 * i915_driver_mmio_probe - setup device MMIO 319 * @dev_priv: device private 320 * 321 * Setup minimal device state necessary for MMIO accesses later in the 322 * initialization sequence. The setup here should avoid any other device-wide 323 * side effects or exposing the driver via kernel internal or user space 324 * interfaces. 325 */ 326 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) 327 { 328 struct intel_display *display = dev_priv->display; 329 struct intel_gt *gt; 330 int ret, i; 331 332 ret = i915_gmch_bridge_setup(dev_priv); 333 if (ret < 0) 334 return ret; 335 336 for_each_gt(gt, dev_priv, i) { 337 ret = intel_uncore_init_mmio(gt->uncore); 338 if (ret) 339 return ret; 340 341 ret = drmm_add_action_or_reset(&dev_priv->drm, 342 intel_uncore_fini_mmio, 343 gt->uncore); 344 if (ret) 345 return ret; 346 } 347 348 /* Try to make sure MCHBAR is enabled before poking at it */ 349 i915_gmch_bar_setup(dev_priv); 350 intel_device_info_runtime_init(dev_priv); 351 intel_display_device_info_runtime_init(display); 352 353 for_each_gt(gt, dev_priv, i) { 354 ret = intel_gt_init_mmio(gt); 355 if (ret) 356 goto err_uncore; 357 } 358 359 /* As early as possible, scrub existing GPU state before clobbering */ 360 sanitize_gpu(dev_priv); 361 362 return 0; 363 364 err_uncore: 365 i915_gmch_bar_teardown(dev_priv); 366 367 return ret; 368 } 369 ALLOW_ERROR_INJECTION(i915_driver_mmio_probe, ERRNO); 370 371 /** 372 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe() 373 * @dev_priv: device private 374 */ 375 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv) 376 { 377 i915_gmch_bar_teardown(dev_priv); 378 } 379 380 /** 381 * i915_set_dma_info - set all relevant PCI dma info as configured for the 382 * platform 383 * @i915: valid i915 instance 384 * 385 * Set the dma max segment size, device and coherent masks. The dma mask set 386 * needs to occur before i915_ggtt_probe_hw. 387 * 388 * A couple of platforms have special needs. Address them as well. 389 * 390 */ 391 static int i915_set_dma_info(struct drm_i915_private *i915) 392 { 393 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size; 394 int ret; 395 396 GEM_BUG_ON(!mask_size); 397 398 /* 399 * We don't have a max segment size, so set it to the max so sg's 400 * debugging layer doesn't complain 401 */ 402 dma_set_max_seg_size(i915->drm.dev, UINT_MAX); 403 404 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 405 if (ret) 406 goto mask_err; 407 408 /* overlay on gen2 is broken and can't address above 1G */ 409 if (GRAPHICS_VER(i915) == 2) 410 mask_size = 30; 411 412 /* 413 * 965GM sometimes incorrectly writes to hardware status page (HWS) 414 * using 32bit addressing, overwriting memory if HWS is located 415 * above 4GB. 416 * 417 * The documentation also mentions an issue with undefined 418 * behaviour if any general state is accessed within a page above 4GB, 419 * which also needs to be handled carefully. 420 */ 421 if (IS_I965G(i915) || IS_I965GM(i915)) 422 mask_size = 32; 423 424 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 425 if (ret) 426 goto mask_err; 427 428 return 0; 429 430 mask_err: 431 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret); 432 return ret; 433 } 434 435 /* Wa_14022698537:dg2 */ 436 static void i915_enable_g8(struct drm_i915_private *i915) 437 { 438 if (IS_DG2(i915)) { 439 if (IS_DG2_D(i915) && !intel_match_g8_cpu()) 440 return; 441 442 snb_pcode_write_p(&i915->uncore, PCODE_POWER_SETUP, 443 POWER_SETUP_SUBCOMMAND_G8_ENABLE, 0, 0); 444 } 445 } 446 447 static int i915_pcode_init(struct drm_i915_private *i915) 448 { 449 struct intel_gt *gt; 450 int id, ret; 451 452 for_each_gt(gt, i915, id) { 453 ret = intel_pcode_init(gt->uncore); 454 if (ret) { 455 gt_err(gt, "intel_pcode_init failed %d\n", ret); 456 return ret; 457 } 458 } 459 460 i915_enable_g8(i915); 461 return 0; 462 } 463 464 /** 465 * i915_driver_hw_probe - setup state requiring device access 466 * @dev_priv: device private 467 * 468 * Setup state that requires accessing the device, but doesn't require 469 * exposing the driver via kernel internal or userspace interfaces. 470 */ 471 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) 472 { 473 struct intel_display *display = dev_priv->display; 474 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 475 int ret; 476 477 if (HAS_PPGTT(dev_priv)) { 478 if (intel_vgpu_active(dev_priv) && 479 !intel_vgpu_has_full_ppgtt(dev_priv)) { 480 drm_err(&dev_priv->drm, 481 "incompatible vGPU found, support for isolated ppGTT required\n"); 482 return -ENXIO; 483 } 484 } 485 486 if (HAS_EXECLISTS(dev_priv)) { 487 /* 488 * Older GVT emulation depends upon intercepting CSB mmio, 489 * which we no longer use, preferring to use the HWSP cache 490 * instead. 491 */ 492 if (intel_vgpu_active(dev_priv) && 493 !intel_vgpu_has_hwsp_emulation(dev_priv)) { 494 drm_err(&dev_priv->drm, 495 "old vGPU host found, support for HWSP emulation required\n"); 496 return -ENXIO; 497 } 498 } 499 500 /* needs to be done before ggtt probe */ 501 i915_edram_detect(dev_priv); 502 503 ret = i915_set_dma_info(dev_priv); 504 if (ret) 505 return ret; 506 507 ret = i915_perf_init(dev_priv); 508 if (ret) 509 return ret; 510 511 ret = i915_ggtt_probe_hw(dev_priv); 512 if (ret) 513 goto err_perf; 514 515 ret = aperture_remove_conflicting_pci_devices(pdev, dev_priv->drm.driver->name); 516 if (ret) 517 goto err_ggtt; 518 519 ret = i915_ggtt_init_hw(dev_priv); 520 if (ret) 521 goto err_ggtt; 522 523 /* 524 * Make sure we probe lmem before we probe stolen-lmem. The BAR size 525 * might be different due to bar resizing. 526 */ 527 ret = intel_gt_tiles_init(dev_priv); 528 if (ret) 529 goto err_ggtt; 530 531 ret = intel_memory_regions_hw_probe(dev_priv); 532 if (ret) 533 goto err_ggtt; 534 535 ret = i915_ggtt_enable_hw(dev_priv); 536 if (ret) { 537 drm_err(&dev_priv->drm, "failed to enable GGTT\n"); 538 goto err_mem_regions; 539 } 540 541 pci_set_master(pdev); 542 543 /* On the 945G/GM, the chipset reports the MSI capability on the 544 * integrated graphics even though the support isn't actually there 545 * according to the published specs. It doesn't appear to function 546 * correctly in testing on 945G. 547 * This may be a side effect of MSI having been made available for PEG 548 * and the registers being closely associated. 549 * 550 * According to chipset errata, on the 965GM, MSI interrupts may 551 * be lost or delayed, and was defeatured. MSI interrupts seem to 552 * get lost on g4x as well, and interrupt delivery seems to stay 553 * properly dead afterwards. So we'll just disable them for all 554 * pre-gen5 chipsets. 555 * 556 * dp aux and gmbus irq on gen4 seems to be able to generate legacy 557 * interrupts even when in MSI mode. This results in spurious 558 * interrupt warnings if the legacy irq no. is shared with another 559 * device. The kernel then disables that interrupt source and so 560 * prevents the other device from working properly. 561 */ 562 if (GRAPHICS_VER(dev_priv) >= 5) { 563 if (pci_enable_msi(pdev) < 0) 564 drm_dbg(&dev_priv->drm, "can't enable MSI"); 565 } 566 567 intel_opregion_setup(display); 568 569 ret = i915_pcode_init(dev_priv); 570 if (ret) 571 goto err_opregion; 572 573 /* 574 * Fill the dram structure to get the system dram info. This will be 575 * used for memory latency calculation. 576 */ 577 ret = intel_dram_detect(display); 578 if (ret) 579 goto err_opregion; 580 581 intel_bw_init_hw(display); 582 583 return 0; 584 585 err_opregion: 586 intel_opregion_cleanup(display); 587 if (pdev->msi_enabled) 588 pci_disable_msi(pdev); 589 err_mem_regions: 590 intel_memory_regions_driver_release(dev_priv); 591 err_ggtt: 592 i915_ggtt_driver_release(dev_priv); 593 i915_gem_drain_freed_objects(dev_priv); 594 i915_ggtt_driver_late_release(dev_priv); 595 err_perf: 596 i915_perf_fini(dev_priv); 597 return ret; 598 } 599 ALLOW_ERROR_INJECTION(i915_driver_hw_probe, ERRNO); 600 601 /** 602 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe() 603 * @dev_priv: device private 604 */ 605 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv) 606 { 607 struct intel_display *display = dev_priv->display; 608 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 609 610 i915_perf_fini(dev_priv); 611 612 intel_opregion_cleanup(display); 613 614 if (pdev->msi_enabled) 615 pci_disable_msi(pdev); 616 } 617 618 /** 619 * i915_driver_register - register the driver with the rest of the system 620 * @dev_priv: device private 621 * 622 * Perform any steps necessary to make the driver available via kernel 623 * internal or userspace interfaces. 624 */ 625 static int i915_driver_register(struct drm_i915_private *dev_priv) 626 { 627 struct intel_display *display = dev_priv->display; 628 struct intel_gt *gt; 629 unsigned int i; 630 int ret; 631 632 i915_gem_driver_register(dev_priv); 633 i915_pmu_register(dev_priv); 634 635 intel_vgpu_register(dev_priv); 636 637 /* Reveal our presence to userspace */ 638 ret = drm_dev_register(&dev_priv->drm, 0); 639 if (ret) { 640 i915_probe_error(dev_priv, 641 "Failed to register driver for userspace access!\n"); 642 drm_dev_unregister(&dev_priv->drm); 643 i915_pmu_unregister(dev_priv); 644 i915_gem_driver_unregister(dev_priv); 645 return ret; 646 } 647 648 i915_debugfs_register(dev_priv); 649 i915_setup_sysfs(dev_priv); 650 651 /* Depends on sysfs having been initialized */ 652 i915_perf_register(dev_priv); 653 654 for_each_gt(gt, dev_priv, i) 655 intel_gt_driver_register(gt); 656 657 intel_pxp_debugfs_register(dev_priv->pxp); 658 659 i915_hwmon_register(dev_priv); 660 661 intel_display_driver_register(display); 662 663 intel_display_power_enable(display); 664 intel_runtime_pm_enable(&dev_priv->runtime_pm); 665 666 if (i915_switcheroo_register(dev_priv)) 667 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n"); 668 669 return 0; 670 } 671 672 /** 673 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() 674 * @dev_priv: device private 675 */ 676 static void i915_driver_unregister(struct drm_i915_private *dev_priv) 677 { 678 struct intel_display *display = dev_priv->display; 679 struct intel_gt *gt; 680 unsigned int i; 681 682 i915_switcheroo_unregister(dev_priv); 683 684 intel_runtime_pm_disable(&dev_priv->runtime_pm); 685 intel_display_power_disable(display); 686 687 intel_display_driver_unregister(display); 688 689 intel_pxp_fini(dev_priv); 690 691 for_each_gt(gt, dev_priv, i) 692 intel_gt_driver_unregister(gt); 693 694 i915_hwmon_unregister(dev_priv); 695 696 i915_perf_unregister(dev_priv); 697 i915_pmu_unregister(dev_priv); 698 699 i915_teardown_sysfs(dev_priv); 700 drm_dev_unplug(&dev_priv->drm); 701 702 i915_gem_driver_unregister(dev_priv); 703 } 704 705 void 706 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p) 707 { 708 drm_printf(p, "iommu: %s\n", 709 str_enabled_disabled(i915_vtd_active(i915))); 710 } 711 712 static void i915_welcome_messages(struct drm_i915_private *dev_priv) 713 { 714 if (drm_debug_enabled(DRM_UT_DRIVER)) { 715 struct drm_printer p = drm_dbg_printer(&dev_priv->drm, DRM_UT_DRIVER, 716 "device info:"); 717 struct intel_gt *gt; 718 unsigned int i; 719 720 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n", 721 INTEL_DEVID(dev_priv), 722 INTEL_REVID(dev_priv), 723 intel_platform_name(INTEL_INFO(dev_priv)->platform), 724 intel_subplatform(RUNTIME_INFO(dev_priv), 725 INTEL_INFO(dev_priv)->platform), 726 GRAPHICS_VER(dev_priv)); 727 728 intel_device_info_print(INTEL_INFO(dev_priv), 729 RUNTIME_INFO(dev_priv), &p); 730 i915_print_iommu_status(dev_priv, &p); 731 for_each_gt(gt, dev_priv, i) 732 intel_gt_info_print(>->info, &p); 733 } 734 735 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) 736 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n"); 737 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 738 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n"); 739 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) 740 drm_info(&dev_priv->drm, 741 "DRM_I915_DEBUG_RUNTIME_PM enabled\n"); 742 } 743 744 static void fence_priority_display(struct dma_fence *fence) 745 { 746 if (dma_fence_is_i915(fence)) 747 i915_gem_fence_wait_priority_display(fence); 748 } 749 750 static bool has_auxccs(struct drm_device *drm) 751 { 752 struct drm_i915_private *i915 = to_i915(drm); 753 754 return IS_GRAPHICS_VER(i915, 9, 12) && 755 !HAS_FLAT_CCS(i915); 756 } 757 758 static bool has_fenced_regions(struct drm_device *drm) 759 { 760 return intel_gt_support_legacy_fencing(to_gt(to_i915(drm))); 761 } 762 763 static bool vgpu_active(struct drm_device *drm) 764 { 765 return intel_vgpu_active(to_i915(drm)); 766 } 767 768 static const struct intel_display_parent_interface parent = { 769 .bo = &i915_display_bo_interface, 770 .dpt = &i915_display_dpt_interface, 771 .dsb = &i915_display_dsb_interface, 772 .fb_pin = &i915_display_fb_pin_interface, 773 .frontbuffer = &i915_display_frontbuffer_interface, 774 .hdcp = &i915_display_hdcp_interface, 775 .initial_plane = &i915_display_initial_plane_interface, 776 .irq = &i915_display_irq_interface, 777 .overlay = &i915_display_overlay_interface, 778 .panic = &i915_display_panic_interface, 779 .pc8 = &i915_display_pc8_interface, 780 .pcode = &i915_display_pcode_interface, 781 .rpm = &i915_display_rpm_interface, 782 .rps = &i915_display_rps_interface, 783 .stolen = &i915_display_stolen_interface, 784 .vlv_iosf = &i915_display_vlv_iosf_interface, 785 786 .fence_priority_display = fence_priority_display, 787 .has_auxccs = has_auxccs, 788 .has_fenced_regions = has_fenced_regions, 789 .vgpu_active = vgpu_active, 790 }; 791 792 const struct intel_display_parent_interface *i915_driver_parent_interface(void) 793 { 794 return &parent; 795 } 796 797 /* Ensure drm and display members are placed properly. */ 798 INTEL_DISPLAY_MEMBER_STATIC_ASSERT(struct drm_i915_private, drm, display); 799 800 static struct drm_i915_private * 801 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) 802 { 803 const struct intel_device_info *match_info = 804 (struct intel_device_info *)ent->driver_data; 805 struct drm_i915_private *i915; 806 struct intel_display *display; 807 808 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver, 809 struct drm_i915_private, drm); 810 if (IS_ERR(i915)) 811 return i915; 812 813 pci_set_drvdata(pdev, &i915->drm); 814 815 /* Device parameters start as a copy of module parameters. */ 816 i915_params_copy(&i915->params, &i915_modparams); 817 818 /* Set up device info and initial runtime info. */ 819 intel_device_info_driver_create(i915, pdev->device, match_info); 820 821 display = intel_display_device_probe(pdev, &parent); 822 if (IS_ERR(display)) 823 return ERR_CAST(display); 824 825 i915->display = display; 826 827 return i915; 828 } 829 830 /** 831 * i915_driver_probe - setup chip and create an initial config 832 * @pdev: PCI device 833 * @ent: matching PCI ID entry 834 * 835 * The driver probe routine has to do several things: 836 * - drive output discovery via intel_display_driver_probe() 837 * - initialize the memory manager 838 * - allocate initial config memory 839 * - setup the DRM framebuffer with the allocated memory 840 */ 841 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 842 { 843 struct drm_i915_private *i915; 844 struct intel_display *display; 845 int ret; 846 847 ret = pci_enable_device(pdev); 848 if (ret) { 849 pr_err("Failed to enable graphics device: %pe\n", ERR_PTR(ret)); 850 return ret; 851 } 852 853 i915 = i915_driver_create(pdev, ent); 854 if (IS_ERR(i915)) { 855 pci_disable_device(pdev); 856 return PTR_ERR(i915); 857 } 858 859 display = i915->display; 860 861 ret = i915_driver_early_probe(i915); 862 if (ret < 0) 863 goto out_pci_disable; 864 865 disable_rpm_wakeref_asserts(&i915->runtime_pm); 866 867 intel_vgpu_detect(i915); 868 869 ret = intel_gt_probe_all(i915); 870 if (ret < 0) 871 goto out_runtime_pm_put; 872 873 ret = i915_driver_mmio_probe(i915); 874 if (ret < 0) 875 goto out_runtime_pm_put; 876 877 ret = i915_driver_hw_probe(i915); 878 if (ret < 0) 879 goto out_cleanup_mmio; 880 881 ret = intel_gvt_init(i915); 882 if (ret) 883 goto out_cleanup_hw; 884 885 ret = intel_display_driver_probe_noirq(display); 886 if (ret < 0) 887 goto out_cleanup_gvt; 888 889 ret = intel_irq_install(i915); 890 if (ret) 891 goto out_cleanup_modeset; 892 893 ret = intel_display_driver_probe_nogem(display); 894 if (ret) 895 goto out_cleanup_irq; 896 897 ret = i915_gem_init(i915); 898 if (ret) 899 goto out_cleanup_modeset2; 900 901 ret = intel_pxp_init(i915); 902 if (ret && ret != -ENODEV) 903 drm_dbg(&i915->drm, "pxp init failed with %d\n", ret); 904 905 ret = intel_display_driver_probe(display); 906 if (ret) 907 goto out_cleanup_gem; 908 909 ret = i915_driver_register(i915); 910 if (ret) 911 goto out_cleanup_gem; 912 913 enable_rpm_wakeref_asserts(&i915->runtime_pm); 914 915 i915_welcome_messages(i915); 916 917 i915->do_release = true; 918 919 return 0; 920 921 out_cleanup_gem: 922 intel_pxp_fini(i915); 923 i915_gem_suspend(i915); 924 i915_gem_driver_remove(i915); 925 i915_gem_driver_release(i915); 926 out_cleanup_modeset2: 927 /* FIXME clean up the error path */ 928 intel_display_driver_remove(display); 929 intel_irq_uninstall(i915); 930 intel_display_driver_remove_noirq(display); 931 goto out_cleanup_modeset; 932 out_cleanup_irq: 933 intel_irq_uninstall(i915); 934 out_cleanup_modeset: 935 intel_display_driver_remove_nogem(display); 936 out_cleanup_gvt: 937 intel_gvt_driver_remove(i915); 938 out_cleanup_hw: 939 i915_driver_hw_remove(i915); 940 intel_memory_regions_driver_release(i915); 941 i915_ggtt_driver_release(i915); 942 i915_gem_drain_freed_objects(i915); 943 i915_ggtt_driver_late_release(i915); 944 out_cleanup_mmio: 945 i915_driver_mmio_release(i915); 946 out_runtime_pm_put: 947 enable_rpm_wakeref_asserts(&i915->runtime_pm); 948 i915_driver_late_release(i915); 949 out_pci_disable: 950 pci_disable_device(pdev); 951 i915_probe_error(i915, "Device initialization failed (%d)\n", ret); 952 return ret; 953 } 954 955 void i915_driver_remove(struct drm_i915_private *i915) 956 { 957 struct intel_display *display = i915->display; 958 intel_wakeref_t wakeref; 959 960 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 961 962 i915_driver_unregister(i915); 963 964 /* Flush any external code that still may be under the RCU lock */ 965 synchronize_rcu(); 966 967 i915_gem_suspend(i915); 968 969 intel_gvt_driver_remove(i915); 970 971 intel_display_driver_remove(display); 972 973 intel_irq_uninstall(i915); 974 intel_hpd_cancel_work(display); 975 976 intel_display_driver_remove_noirq(display); 977 978 i915_reset_error_state(i915); 979 i915_gem_driver_remove(i915); 980 981 intel_display_driver_remove_nogem(display); 982 983 i915_driver_hw_remove(i915); 984 985 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 986 } 987 988 static void i915_driver_release(struct drm_device *dev) 989 { 990 struct drm_i915_private *dev_priv = to_i915(dev); 991 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 992 intel_wakeref_t wakeref; 993 994 if (!dev_priv->do_release) 995 return; 996 997 wakeref = intel_runtime_pm_get(rpm); 998 999 i915_gem_driver_release(dev_priv); 1000 1001 intel_memory_regions_driver_release(dev_priv); 1002 i915_ggtt_driver_release(dev_priv); 1003 i915_gem_drain_freed_objects(dev_priv); 1004 i915_ggtt_driver_late_release(dev_priv); 1005 1006 i915_driver_mmio_release(dev_priv); 1007 1008 intel_runtime_pm_put(rpm, wakeref); 1009 1010 intel_runtime_pm_driver_release(rpm); 1011 1012 i915_driver_late_release(dev_priv); 1013 } 1014 1015 static int i915_driver_open(struct drm_device *dev, struct drm_file *file) 1016 { 1017 struct drm_i915_private *i915 = to_i915(dev); 1018 int ret; 1019 1020 ret = i915_gem_open(i915, file); 1021 if (ret) 1022 return ret; 1023 1024 return 0; 1025 } 1026 1027 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) 1028 { 1029 struct drm_i915_file_private *file_priv = file->driver_priv; 1030 1031 i915_gem_context_close(file); 1032 i915_drm_client_put(file_priv->client); 1033 1034 kfree_rcu(file_priv, rcu); 1035 1036 /* Catch up with all the deferred frees from "this" client */ 1037 i915_gem_flush_free_objects(to_i915(dev)); 1038 } 1039 1040 void i915_driver_shutdown(struct drm_i915_private *i915) 1041 { 1042 struct intel_display *display = i915->display; 1043 1044 disable_rpm_wakeref_asserts(&i915->runtime_pm); 1045 intel_runtime_pm_disable(&i915->runtime_pm); 1046 intel_display_power_disable(display); 1047 1048 drm_client_dev_suspend(&i915->drm); 1049 if (intel_display_device_present(display)) { 1050 drm_kms_helper_poll_disable(&i915->drm); 1051 intel_display_driver_disable_user_access(display); 1052 1053 drm_atomic_helper_shutdown(&i915->drm); 1054 } 1055 1056 intel_dp_mst_suspend(display); 1057 1058 intel_irq_suspend(i915); 1059 intel_hpd_cancel_work(display); 1060 1061 if (intel_display_device_present(display)) 1062 intel_display_driver_suspend_access(display); 1063 1064 intel_encoder_suspend_all(display); 1065 intel_encoder_shutdown_all(display); 1066 1067 intel_dmc_suspend(display); 1068 1069 i915_gem_suspend(i915); 1070 1071 /* 1072 * The only requirement is to reboot with display DC states disabled, 1073 * for now leaving all display power wells in the INIT power domain 1074 * enabled. 1075 * 1076 * TODO: 1077 * - unify the pci_driver::shutdown sequence here with the 1078 * pci_driver.driver.pm.poweroff,poweroff_late sequence. 1079 * - unify the driver remove and system/runtime suspend sequences with 1080 * the above unified shutdown/poweroff sequence. 1081 */ 1082 intel_display_power_driver_remove(display); 1083 enable_rpm_wakeref_asserts(&i915->runtime_pm); 1084 1085 intel_runtime_pm_driver_last_release(&i915->runtime_pm); 1086 } 1087 1088 static bool suspend_to_idle(struct drm_i915_private *dev_priv) 1089 { 1090 #if IS_ENABLED(CONFIG_ACPI_SLEEP) 1091 if (acpi_target_system_state() < ACPI_STATE_S3) 1092 return true; 1093 #endif 1094 return false; 1095 } 1096 1097 static void i915_drm_complete(struct drm_device *dev) 1098 { 1099 struct drm_i915_private *i915 = to_i915(dev); 1100 1101 intel_pxp_resume_complete(i915->pxp); 1102 } 1103 1104 static int i915_drm_prepare(struct drm_device *dev) 1105 { 1106 struct drm_i915_private *i915 = to_i915(dev); 1107 1108 intel_pxp_suspend_prepare(i915->pxp); 1109 1110 /* 1111 * NB intel_display_driver_suspend() may issue new requests after we've 1112 * ostensibly marked the GPU as ready-to-sleep here. We need to 1113 * split out that work and pull it forward so that after point, 1114 * the GPU is not woken again. 1115 */ 1116 return i915_gem_backup_suspend(i915); 1117 } 1118 1119 static int i915_drm_suspend(struct drm_device *dev) 1120 { 1121 struct drm_i915_private *dev_priv = to_i915(dev); 1122 struct intel_display *display = dev_priv->display; 1123 pci_power_t opregion_target_state; 1124 1125 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1126 1127 /* We do a lot of poking in a lot of registers, make sure they work 1128 * properly. */ 1129 intel_display_power_disable(display); 1130 drm_client_dev_suspend(dev); 1131 if (intel_display_device_present(display)) { 1132 drm_kms_helper_poll_disable(dev); 1133 intel_display_driver_disable_user_access(display); 1134 } 1135 1136 intel_display_driver_suspend(display); 1137 1138 intel_irq_suspend(dev_priv); 1139 intel_hpd_cancel_work(display); 1140 1141 if (intel_display_device_present(display)) 1142 intel_display_driver_suspend_access(display); 1143 1144 intel_encoder_suspend_all(display); 1145 1146 /* Must be called before GGTT is suspended. */ 1147 intel_dpt_suspend(display); 1148 i915_ggtt_suspend(to_gt(dev_priv)->ggtt); 1149 1150 i9xx_display_sr_save(display); 1151 1152 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; 1153 intel_opregion_suspend(display, opregion_target_state); 1154 1155 dev_priv->suspend_count++; 1156 1157 intel_dmc_suspend(display); 1158 1159 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1160 1161 i915_gem_drain_freed_objects(dev_priv); 1162 1163 return 0; 1164 } 1165 1166 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) 1167 { 1168 struct drm_i915_private *dev_priv = to_i915(dev); 1169 struct intel_display *display = dev_priv->display; 1170 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1171 struct intel_gt *gt; 1172 int ret, i; 1173 bool s2idle = !hibernation && suspend_to_idle(dev_priv); 1174 1175 disable_rpm_wakeref_asserts(rpm); 1176 1177 intel_pxp_suspend(dev_priv->pxp); 1178 1179 i915_gem_suspend_late(dev_priv); 1180 1181 for_each_gt(gt, dev_priv, i) 1182 intel_uncore_suspend(gt->uncore); 1183 1184 intel_display_power_suspend_late(display, s2idle); 1185 1186 ret = vlv_suspend_complete(dev_priv); 1187 if (ret) { 1188 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret); 1189 intel_display_power_resume_early(display); 1190 } 1191 1192 enable_rpm_wakeref_asserts(rpm); 1193 1194 if (!dev_priv->uncore.user_forcewake_count) 1195 intel_runtime_pm_driver_release(rpm); 1196 1197 return ret; 1198 } 1199 1200 static int i915_drm_suspend_noirq(struct drm_device *dev, bool hibernation) 1201 { 1202 struct drm_i915_private *dev_priv = to_i915(dev); 1203 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1204 1205 /* 1206 * During hibernation on some platforms the BIOS may try to access 1207 * the device even though it's already in D3 and hang the machine. So 1208 * leave the device in D0 on those platforms and hope the BIOS will 1209 * power down the device properly. The issue was seen on multiple old 1210 * GENs with different BIOS vendors, so having an explicit blacklist 1211 * is impractical; apply the workaround on everything pre GEN6. The 1212 * platforms where the issue was seen: 1213 * Lenovo Thinkpad X301, X61s, X60, T60, X41 1214 * Fujitsu FSC S7110 1215 * Acer Aspire 1830T 1216 * 1217 * pci_save_state() prevents drivers/pci from 1218 * automagically putting the device into D3. 1219 */ 1220 if (hibernation && GRAPHICS_VER(dev_priv) < 6) 1221 pci_save_state(pdev); 1222 1223 return 0; 1224 } 1225 1226 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915, 1227 pm_message_t state) 1228 { 1229 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 1230 int error; 1231 1232 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND && 1233 state.event != PM_EVENT_FREEZE)) 1234 return -EINVAL; 1235 1236 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1237 return 0; 1238 1239 error = i915_drm_suspend(&i915->drm); 1240 if (error) 1241 return error; 1242 1243 error = i915_drm_suspend_late(&i915->drm, false); 1244 if (error) 1245 return error; 1246 1247 pci_save_state(pdev); 1248 pci_set_power_state(pdev, PCI_D3hot); 1249 1250 return 0; 1251 } 1252 1253 static int i915_drm_resume(struct drm_device *dev) 1254 { 1255 struct drm_i915_private *dev_priv = to_i915(dev); 1256 struct intel_display *display = dev_priv->display; 1257 struct intel_gt *gt; 1258 int ret, i; 1259 1260 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1261 1262 ret = i915_pcode_init(dev_priv); 1263 if (ret) 1264 return ret; 1265 1266 sanitize_gpu(dev_priv); 1267 1268 ret = i915_ggtt_enable_hw(dev_priv); 1269 if (ret) 1270 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n"); 1271 1272 i915_ggtt_resume(to_gt(dev_priv)->ggtt); 1273 1274 for_each_gt(gt, dev_priv, i) 1275 if (GRAPHICS_VER(gt->i915) >= 8) 1276 setup_private_pat(gt); 1277 1278 /* Must be called after GGTT is resumed. */ 1279 intel_dpt_resume(display); 1280 1281 intel_dmc_resume(display); 1282 1283 i9xx_display_sr_restore(display); 1284 1285 intel_gmbus_reset(display); 1286 1287 intel_pps_unlock_regs_wa(display); 1288 1289 intel_init_pch_refclk(display); 1290 1291 /* 1292 * Interrupts have to be enabled before any batches are run. If not the 1293 * GPU will hang. i915_gem_init_hw() will initiate batches to 1294 * update/restore the context. 1295 * 1296 * drm_mode_config_reset() needs AUX interrupts. 1297 * 1298 * Modeset enabling in intel_display_driver_init_hw() also needs working 1299 * interrupts. 1300 */ 1301 intel_irq_resume(dev_priv); 1302 1303 if (intel_display_device_present(display)) 1304 drm_mode_config_reset(dev); 1305 1306 i915_gem_resume(dev_priv); 1307 1308 intel_display_driver_init_hw(display); 1309 1310 intel_clock_gating_init(&dev_priv->drm); 1311 1312 if (intel_display_device_present(display)) 1313 intel_display_driver_resume_access(display); 1314 1315 intel_hpd_init(display); 1316 1317 intel_display_driver_resume(display); 1318 1319 if (intel_display_device_present(display)) { 1320 intel_display_driver_enable_user_access(display); 1321 drm_kms_helper_poll_enable(dev); 1322 } 1323 intel_hpd_poll_disable(display); 1324 1325 intel_opregion_resume(display); 1326 1327 drm_client_dev_resume(dev); 1328 1329 intel_display_power_enable(display); 1330 1331 intel_gvt_resume(dev_priv); 1332 1333 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1334 1335 return 0; 1336 } 1337 1338 static int i915_drm_resume_early(struct drm_device *dev) 1339 { 1340 struct drm_i915_private *dev_priv = to_i915(dev); 1341 struct intel_display *display = dev_priv->display; 1342 struct intel_gt *gt; 1343 int ret, i; 1344 1345 /* 1346 * We have a resume ordering issue with the snd-hda driver also 1347 * requiring our device to be power up. Due to the lack of a 1348 * parent/child relationship we currently solve this with an early 1349 * resume hook. 1350 * 1351 * FIXME: This should be solved with a special hdmi sink device or 1352 * similar so that power domains can be employed. 1353 */ 1354 1355 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1356 1357 ret = vlv_resume_prepare(dev_priv, false); 1358 if (ret) 1359 drm_err(&dev_priv->drm, 1360 "Resume prepare failed: %d, continuing anyway\n", ret); 1361 1362 for_each_gt(gt, dev_priv, i) 1363 intel_gt_resume_early(gt); 1364 1365 intel_display_power_resume_early(display); 1366 1367 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1368 1369 return ret; 1370 } 1371 1372 int i915_driver_resume_switcheroo(struct drm_i915_private *i915) 1373 { 1374 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 1375 int ret; 1376 1377 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1378 return 0; 1379 1380 ret = pci_set_power_state(pdev, PCI_D0); 1381 if (ret) 1382 return ret; 1383 1384 pci_restore_state(pdev); 1385 1386 ret = i915_drm_resume_early(&i915->drm); 1387 if (ret) 1388 return ret; 1389 1390 return i915_drm_resume(&i915->drm); 1391 } 1392 1393 static int i915_pm_prepare(struct device *kdev) 1394 { 1395 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1396 1397 if (!i915) { 1398 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1399 return -ENODEV; 1400 } 1401 1402 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1403 return 0; 1404 1405 return i915_drm_prepare(&i915->drm); 1406 } 1407 1408 static int i915_pm_suspend(struct device *kdev) 1409 { 1410 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1411 1412 if (!i915) { 1413 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1414 return -ENODEV; 1415 } 1416 1417 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1418 return 0; 1419 1420 return i915_drm_suspend(&i915->drm); 1421 } 1422 1423 static int i915_pm_suspend_late(struct device *kdev) 1424 { 1425 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1426 1427 /* 1428 * We have a suspend ordering issue with the snd-hda driver also 1429 * requiring our device to be power up. Due to the lack of a 1430 * parent/child relationship we currently solve this with an late 1431 * suspend hook. 1432 * 1433 * FIXME: This should be solved with a special hdmi sink device or 1434 * similar so that power domains can be employed. 1435 */ 1436 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1437 return 0; 1438 1439 return i915_drm_suspend_late(&i915->drm, false); 1440 } 1441 1442 static int i915_pm_suspend_noirq(struct device *kdev) 1443 { 1444 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1445 1446 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1447 return 0; 1448 1449 return i915_drm_suspend_noirq(&i915->drm, false); 1450 } 1451 1452 static int i915_pm_poweroff_late(struct device *kdev) 1453 { 1454 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1455 1456 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1457 return 0; 1458 1459 return i915_drm_suspend_late(&i915->drm, true); 1460 } 1461 1462 static int i915_pm_poweroff_noirq(struct device *kdev) 1463 { 1464 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1465 1466 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1467 return 0; 1468 1469 return i915_drm_suspend_noirq(&i915->drm, true); 1470 } 1471 1472 static int i915_pm_resume_early(struct device *kdev) 1473 { 1474 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1475 1476 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1477 return 0; 1478 1479 return i915_drm_resume_early(&i915->drm); 1480 } 1481 1482 static int i915_pm_resume(struct device *kdev) 1483 { 1484 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1485 1486 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1487 return 0; 1488 1489 return i915_drm_resume(&i915->drm); 1490 } 1491 1492 static void i915_pm_complete(struct device *kdev) 1493 { 1494 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1495 1496 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1497 return; 1498 1499 i915_drm_complete(&i915->drm); 1500 } 1501 1502 /* freeze: before creating the hibernation_image */ 1503 static int i915_pm_freeze(struct device *kdev) 1504 { 1505 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1506 int ret; 1507 1508 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1509 ret = i915_drm_suspend(&i915->drm); 1510 if (ret) 1511 return ret; 1512 } 1513 1514 ret = i915_gem_freeze(i915); 1515 if (ret) 1516 return ret; 1517 1518 return 0; 1519 } 1520 1521 static int i915_pm_freeze_late(struct device *kdev) 1522 { 1523 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1524 int ret; 1525 1526 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1527 ret = i915_drm_suspend_late(&i915->drm, true); 1528 if (ret) 1529 return ret; 1530 } 1531 1532 ret = i915_gem_freeze_late(i915); 1533 if (ret) 1534 return ret; 1535 1536 return 0; 1537 } 1538 1539 /* thaw: called after creating the hibernation image, but before turning off. */ 1540 static int i915_pm_thaw_early(struct device *kdev) 1541 { 1542 return i915_pm_resume_early(kdev); 1543 } 1544 1545 static int i915_pm_thaw(struct device *kdev) 1546 { 1547 return i915_pm_resume(kdev); 1548 } 1549 1550 /* restore: called after loading the hibernation image. */ 1551 static int i915_pm_restore_early(struct device *kdev) 1552 { 1553 return i915_pm_resume_early(kdev); 1554 } 1555 1556 static int i915_pm_restore(struct device *kdev) 1557 { 1558 return i915_pm_resume(kdev); 1559 } 1560 1561 static int i915_pm_runtime_suspend(struct device *kdev) 1562 { 1563 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1564 struct intel_display *display = dev_priv->display; 1565 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1566 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1567 struct pci_dev *root_pdev; 1568 struct intel_gt *gt; 1569 int ret, i; 1570 1571 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1572 return -ENODEV; 1573 1574 drm_dbg(&dev_priv->drm, "Suspending device\n"); 1575 1576 disable_rpm_wakeref_asserts(rpm); 1577 1578 /* 1579 * We are safe here against re-faults, since the fault handler takes 1580 * an RPM reference. 1581 */ 1582 i915_gem_runtime_suspend(dev_priv); 1583 1584 intel_pxp_runtime_suspend(dev_priv->pxp); 1585 1586 for_each_gt(gt, dev_priv, i) 1587 intel_gt_runtime_suspend(gt); 1588 1589 intel_irq_suspend(dev_priv); 1590 1591 for_each_gt(gt, dev_priv, i) 1592 intel_uncore_suspend(gt->uncore); 1593 1594 intel_display_power_runtime_suspend(display); 1595 1596 ret = vlv_suspend_complete(dev_priv); 1597 if (ret) { 1598 drm_err(&dev_priv->drm, 1599 "Runtime suspend failed, disabling it (%d)\n", ret); 1600 intel_uncore_runtime_resume(&dev_priv->uncore); 1601 1602 intel_irq_resume(dev_priv); 1603 1604 for_each_gt(gt, dev_priv, i) 1605 intel_gt_runtime_resume(gt); 1606 1607 enable_rpm_wakeref_asserts(rpm); 1608 1609 return ret; 1610 } 1611 1612 enable_rpm_wakeref_asserts(rpm); 1613 intel_runtime_pm_driver_release(rpm); 1614 1615 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore)) 1616 drm_err(&dev_priv->drm, 1617 "Unclaimed access detected prior to suspending\n"); 1618 1619 /* 1620 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX 1621 * This should be totally removed when we handle the pci states properly 1622 * on runtime PM. 1623 */ 1624 root_pdev = pcie_find_root_port(pdev); 1625 if (root_pdev) 1626 pci_d3cold_disable(root_pdev); 1627 1628 /* 1629 * FIXME: We really should find a document that references the arguments 1630 * used below! 1631 */ 1632 if (IS_BROADWELL(dev_priv)) { 1633 /* 1634 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop 1635 * being detected, and the call we do at i915_pm_runtime_resume() 1636 * won't be able to restore them. Since PCI_D3hot matches the 1637 * actual specification and appears to be working, use it. 1638 */ 1639 intel_opregion_notify_adapter(display, PCI_D3hot); 1640 } else { 1641 /* 1642 * current versions of firmware which depend on this opregion 1643 * notification have repurposed the D1 definition to mean 1644 * "runtime suspended" vs. what you would normally expect (D3) 1645 * to distinguish it from notifications that might be sent via 1646 * the suspend path. 1647 */ 1648 intel_opregion_notify_adapter(display, PCI_D1); 1649 } 1650 1651 assert_forcewakes_inactive(&dev_priv->uncore); 1652 1653 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) 1654 intel_hpd_poll_enable(display); 1655 1656 drm_dbg(&dev_priv->drm, "Device suspended\n"); 1657 return 0; 1658 } 1659 1660 static int i915_pm_runtime_resume(struct device *kdev) 1661 { 1662 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1663 struct intel_display *display = dev_priv->display; 1664 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1665 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1666 struct pci_dev *root_pdev; 1667 struct intel_gt *gt; 1668 int ret, i; 1669 1670 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1671 return -ENODEV; 1672 1673 drm_dbg(&dev_priv->drm, "Resuming device\n"); 1674 1675 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count)); 1676 disable_rpm_wakeref_asserts(rpm); 1677 1678 intel_opregion_notify_adapter(display, PCI_D0); 1679 1680 root_pdev = pcie_find_root_port(pdev); 1681 if (root_pdev) 1682 pci_d3cold_enable(root_pdev); 1683 1684 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore)) 1685 drm_dbg(&dev_priv->drm, 1686 "Unclaimed access during suspend, bios?\n"); 1687 1688 intel_display_power_runtime_resume(display); 1689 1690 ret = vlv_resume_prepare(dev_priv, true); 1691 1692 for_each_gt(gt, dev_priv, i) 1693 intel_uncore_runtime_resume(gt->uncore); 1694 1695 intel_irq_resume(dev_priv); 1696 1697 /* 1698 * No point of rolling back things in case of an error, as the best 1699 * we can do is to hope that things will still work (and disable RPM). 1700 */ 1701 for_each_gt(gt, dev_priv, i) 1702 intel_gt_runtime_resume(gt); 1703 1704 intel_pxp_runtime_resume(dev_priv->pxp); 1705 1706 /* 1707 * On VLV/CHV display interrupts are part of the display 1708 * power well, so hpd is reinitialized from there. For 1709 * everyone else do it here. 1710 */ 1711 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 1712 intel_hpd_init(display); 1713 intel_hpd_poll_disable(display); 1714 } 1715 1716 skl_watermark_ipc_update(display); 1717 1718 enable_rpm_wakeref_asserts(rpm); 1719 1720 if (ret) 1721 drm_err(&dev_priv->drm, 1722 "Runtime resume failed, disabling it (%d)\n", ret); 1723 else 1724 drm_dbg(&dev_priv->drm, "Device resumed\n"); 1725 1726 return ret; 1727 } 1728 1729 const struct dev_pm_ops i915_pm_ops = { 1730 /* 1731 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, 1732 * PMSG_RESUME] 1733 */ 1734 .prepare = i915_pm_prepare, 1735 .suspend = i915_pm_suspend, 1736 .suspend_late = i915_pm_suspend_late, 1737 .suspend_noirq = i915_pm_suspend_noirq, 1738 .resume_early = i915_pm_resume_early, 1739 .resume = i915_pm_resume, 1740 .complete = i915_pm_complete, 1741 1742 /* 1743 * S4 event handlers 1744 * @freeze* : called (1) before creating the 1745 * hibernation image [PMSG_FREEZE] and 1746 * (2) after rebooting, before restoring 1747 * the image [PMSG_QUIESCE] 1748 * @thaw* : called (1) after creating the hibernation 1749 * image, before writing it [PMSG_THAW] 1750 * and (2) after failing to create or 1751 * restore the image [PMSG_RECOVER] 1752 * @poweroff* : called after writing the hibernation 1753 * image, before rebooting [PMSG_HIBERNATE] 1754 * @restore* : called after rebooting and restoring the 1755 * hibernation image [PMSG_RESTORE] 1756 */ 1757 .freeze = i915_pm_freeze, 1758 .freeze_late = i915_pm_freeze_late, 1759 .thaw_early = i915_pm_thaw_early, 1760 .thaw = i915_pm_thaw, 1761 .poweroff = i915_pm_suspend, 1762 .poweroff_late = i915_pm_poweroff_late, 1763 .poweroff_noirq = i915_pm_poweroff_noirq, 1764 .restore_early = i915_pm_restore_early, 1765 .restore = i915_pm_restore, 1766 1767 /* S0ix (via runtime suspend) event handlers */ 1768 .runtime_suspend = i915_pm_runtime_suspend, 1769 .runtime_resume = i915_pm_runtime_resume, 1770 }; 1771 1772 static const struct file_operations i915_driver_fops = { 1773 .owner = THIS_MODULE, 1774 .open = drm_open, 1775 .release = drm_release_noglobal, 1776 .unlocked_ioctl = drm_ioctl, 1777 .mmap = i915_gem_mmap, 1778 .poll = drm_poll, 1779 .read = drm_read, 1780 .compat_ioctl = i915_ioc32_compat_ioctl, 1781 .llseek = noop_llseek, 1782 #ifdef CONFIG_PROC_FS 1783 .show_fdinfo = drm_show_fdinfo, 1784 #endif 1785 .fop_flags = FOP_UNSIGNED_OFFSET, 1786 }; 1787 1788 static int 1789 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, 1790 struct drm_file *file) 1791 { 1792 return -ENODEV; 1793 } 1794 1795 static const struct drm_ioctl_desc i915_ioctls[] = { 1796 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1797 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), 1798 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), 1799 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), 1800 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), 1801 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), 1802 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW), 1803 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1804 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), 1805 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), 1806 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1807 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), 1808 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1809 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1810 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), 1811 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), 1812 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1813 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1814 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH), 1815 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW), 1816 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1817 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1818 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW), 1819 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), 1820 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), 1821 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW), 1822 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1823 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1824 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), 1825 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW), 1826 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), 1827 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), 1828 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), 1829 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW), 1830 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), 1831 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), 1832 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW), 1833 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW), 1834 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), 1835 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_crtc_get_pipe_from_crtc_id_ioctl, 0), 1836 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), 1837 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER), 1838 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER), 1839 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER), 1840 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER), 1841 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW), 1842 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), 1843 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), 1844 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), 1845 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW), 1846 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), 1847 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), 1848 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), 1849 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), 1850 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW), 1851 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW), 1852 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW), 1853 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW), 1854 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW), 1855 }; 1856 1857 /* 1858 * Interface history: 1859 * 1860 * 1.1: Original. 1861 * 1.2: Add Power Management 1862 * 1.3: Add vblank support 1863 * 1.4: Fix cmdbuffer path, add heap destroy 1864 * 1.5: Add vblank pipe configuration 1865 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 1866 * - Support vertical blank on secondary display pipe 1867 */ 1868 #define DRIVER_MAJOR 1 1869 #define DRIVER_MINOR 6 1870 #define DRIVER_PATCHLEVEL 0 1871 1872 static const struct drm_driver i915_drm_driver = { 1873 .driver_features = 1874 DRIVER_GEM | 1875 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ | 1876 DRIVER_SYNCOBJ_TIMELINE, 1877 .release = i915_driver_release, 1878 .open = i915_driver_open, 1879 .postclose = i915_driver_postclose, 1880 .show_fdinfo = PTR_IF(IS_ENABLED(CONFIG_PROC_FS), i915_drm_client_fdinfo), 1881 1882 .gem_prime_import = i915_gem_prime_import, 1883 1884 .dumb_create = i915_gem_dumb_create, 1885 .dumb_map_offset = i915_gem_dumb_mmap_offset, 1886 1887 INTEL_FBDEV_DRIVER_OPS, 1888 1889 .ioctls = i915_ioctls, 1890 .num_ioctls = ARRAY_SIZE(i915_ioctls), 1891 .fops = &i915_driver_fops, 1892 .name = DRIVER_NAME, 1893 .desc = DRIVER_DESC, 1894 .major = DRIVER_MAJOR, 1895 .minor = DRIVER_MINOR, 1896 .patchlevel = DRIVER_PATCHLEVEL, 1897 }; 1898