1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #include <linux/acpi.h> 31 #include <linux/device.h> 32 #include <linux/module.h> 33 #include <linux/oom.h> 34 #include <linux/pci.h> 35 #include <linux/pm.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/pnp.h> 38 #include <linux/slab.h> 39 #include <linux/vga_switcheroo.h> 40 #include <linux/vt.h> 41 42 #include <drm/drm_aperture.h> 43 #include <drm/drm_atomic_helper.h> 44 #include <drm/drm_ioctl.h> 45 #include <drm/drm_managed.h> 46 #include <drm/drm_probe_helper.h> 47 48 #include "display/intel_acpi.h" 49 #include "display/intel_bw.h" 50 #include "display/intel_cdclk.h" 51 #include "display/intel_display_types.h" 52 #include "display/intel_dmc.h" 53 #include "display/intel_dp.h" 54 #include "display/intel_dpt.h" 55 #include "display/intel_fbdev.h" 56 #include "display/intel_hotplug.h" 57 #include "display/intel_overlay.h" 58 #include "display/intel_pch_refclk.h" 59 #include "display/intel_pipe_crc.h" 60 #include "display/intel_pps.h" 61 #include "display/intel_sprite.h" 62 #include "display/intel_vga.h" 63 64 #include "gem/i915_gem_context.h" 65 #include "gem/i915_gem_ioctls.h" 66 #include "gem/i915_gem_mman.h" 67 #include "gem/i915_gem_pm.h" 68 #include "gt/intel_gt.h" 69 #include "gt/intel_gt_pm.h" 70 #include "gt/intel_rc6.h" 71 72 #include "pxp/intel_pxp_pm.h" 73 74 #include "i915_debugfs.h" 75 #include "i915_driver.h" 76 #include "i915_drv.h" 77 #include "i915_getparam.h" 78 #include "i915_ioc32.h" 79 #include "i915_ioctl.h" 80 #include "i915_irq.h" 81 #include "i915_memcpy.h" 82 #include "i915_perf.h" 83 #include "i915_query.h" 84 #include "i915_suspend.h" 85 #include "i915_switcheroo.h" 86 #include "i915_sysfs.h" 87 #include "i915_vgpu.h" 88 #include "intel_dram.h" 89 #include "intel_gvt.h" 90 #include "intel_memory_region.h" 91 #include "intel_pci_config.h" 92 #include "intel_pcode.h" 93 #include "intel_pm.h" 94 #include "intel_region_ttm.h" 95 #include "vlv_suspend.h" 96 97 static const struct drm_driver i915_drm_driver; 98 99 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv) 100 { 101 int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus); 102 103 dev_priv->bridge_dev = 104 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0)); 105 if (!dev_priv->bridge_dev) { 106 drm_err(&dev_priv->drm, "bridge device not found\n"); 107 return -EIO; 108 } 109 return 0; 110 } 111 112 /* Allocate space for the MCH regs if needed, return nonzero on error */ 113 static int 114 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv) 115 { 116 int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 117 u32 temp_lo, temp_hi = 0; 118 u64 mchbar_addr; 119 int ret; 120 121 if (GRAPHICS_VER(dev_priv) >= 4) 122 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); 123 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); 124 mchbar_addr = ((u64)temp_hi << 32) | temp_lo; 125 126 /* If ACPI doesn't have it, assume we need to allocate it ourselves */ 127 #ifdef CONFIG_PNP 128 if (mchbar_addr && 129 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) 130 return 0; 131 #endif 132 133 /* Get some space for it */ 134 dev_priv->mch_res.name = "i915 MCHBAR"; 135 dev_priv->mch_res.flags = IORESOURCE_MEM; 136 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, 137 &dev_priv->mch_res, 138 MCHBAR_SIZE, MCHBAR_SIZE, 139 PCIBIOS_MIN_MEM, 140 0, pcibios_align_resource, 141 dev_priv->bridge_dev); 142 if (ret) { 143 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret); 144 dev_priv->mch_res.start = 0; 145 return ret; 146 } 147 148 if (GRAPHICS_VER(dev_priv) >= 4) 149 pci_write_config_dword(dev_priv->bridge_dev, reg + 4, 150 upper_32_bits(dev_priv->mch_res.start)); 151 152 pci_write_config_dword(dev_priv->bridge_dev, reg, 153 lower_32_bits(dev_priv->mch_res.start)); 154 return 0; 155 } 156 157 /* Setup MCHBAR if possible, return true if we should disable it again */ 158 static void 159 intel_setup_mchbar(struct drm_i915_private *dev_priv) 160 { 161 int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 162 u32 temp; 163 bool enabled; 164 165 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 166 return; 167 168 dev_priv->mchbar_need_disable = false; 169 170 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 171 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp); 172 enabled = !!(temp & DEVEN_MCHBAR_EN); 173 } else { 174 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); 175 enabled = temp & 1; 176 } 177 178 /* If it's already enabled, don't have to do anything */ 179 if (enabled) 180 return; 181 182 if (intel_alloc_mchbar_resource(dev_priv)) 183 return; 184 185 dev_priv->mchbar_need_disable = true; 186 187 /* Space is allocated or reserved, so enable it. */ 188 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 189 pci_write_config_dword(dev_priv->bridge_dev, DEVEN, 190 temp | DEVEN_MCHBAR_EN); 191 } else { 192 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); 193 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); 194 } 195 } 196 197 static void 198 intel_teardown_mchbar(struct drm_i915_private *dev_priv) 199 { 200 int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 201 202 if (dev_priv->mchbar_need_disable) { 203 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 204 u32 deven_val; 205 206 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, 207 &deven_val); 208 deven_val &= ~DEVEN_MCHBAR_EN; 209 pci_write_config_dword(dev_priv->bridge_dev, DEVEN, 210 deven_val); 211 } else { 212 u32 mchbar_val; 213 214 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, 215 &mchbar_val); 216 mchbar_val &= ~1; 217 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, 218 mchbar_val); 219 } 220 } 221 222 if (dev_priv->mch_res.start) 223 release_resource(&dev_priv->mch_res); 224 } 225 226 static int i915_workqueues_init(struct drm_i915_private *dev_priv) 227 { 228 /* 229 * The i915 workqueue is primarily used for batched retirement of 230 * requests (and thus managing bo) once the task has been completed 231 * by the GPU. i915_retire_requests() is called directly when we 232 * need high-priority retirement, such as waiting for an explicit 233 * bo. 234 * 235 * It is also used for periodic low-priority events, such as 236 * idle-timers and recording error state. 237 * 238 * All tasks on the workqueue are expected to acquire the dev mutex 239 * so there is no point in running more than one instance of the 240 * workqueue at any time. Use an ordered one. 241 */ 242 dev_priv->wq = alloc_ordered_workqueue("i915", 0); 243 if (dev_priv->wq == NULL) 244 goto out_err; 245 246 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); 247 if (dev_priv->hotplug.dp_wq == NULL) 248 goto out_free_wq; 249 250 return 0; 251 252 out_free_wq: 253 destroy_workqueue(dev_priv->wq); 254 out_err: 255 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n"); 256 257 return -ENOMEM; 258 } 259 260 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) 261 { 262 destroy_workqueue(dev_priv->hotplug.dp_wq); 263 destroy_workqueue(dev_priv->wq); 264 } 265 266 /* 267 * We don't keep the workarounds for pre-production hardware, so we expect our 268 * driver to fail on these machines in one way or another. A little warning on 269 * dmesg may help both the user and the bug triagers. 270 * 271 * Our policy for removing pre-production workarounds is to keep the 272 * current gen workarounds as a guide to the bring-up of the next gen 273 * (workarounds have a habit of persisting!). Anything older than that 274 * should be removed along with the complications they introduce. 275 */ 276 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) 277 { 278 bool pre = false; 279 280 pre |= IS_HSW_EARLY_SDV(dev_priv); 281 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6; 282 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA; 283 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 284 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3; 285 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7; 286 287 if (pre) { 288 drm_err(&dev_priv->drm, "This is a pre-production stepping. " 289 "It may not be fully functional.\n"); 290 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); 291 } 292 } 293 294 static void sanitize_gpu(struct drm_i915_private *i915) 295 { 296 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) 297 __intel_gt_reset(to_gt(i915), ALL_ENGINES); 298 } 299 300 /** 301 * i915_driver_early_probe - setup state not requiring device access 302 * @dev_priv: device private 303 * 304 * Initialize everything that is a "SW-only" state, that is state not 305 * requiring accessing the device or exposing the driver via kernel internal 306 * or userspace interfaces. Example steps belonging here: lock initialization, 307 * system memory allocation, setting up device specific attributes and 308 * function hooks not requiring accessing the device. 309 */ 310 static int i915_driver_early_probe(struct drm_i915_private *dev_priv) 311 { 312 int ret = 0; 313 314 if (i915_inject_probe_failure(dev_priv)) 315 return -ENODEV; 316 317 intel_device_info_subplatform_init(dev_priv); 318 intel_step_init(dev_priv); 319 320 intel_gt_init_early(to_gt(dev_priv), dev_priv); 321 intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug); 322 intel_uncore_init_early(&dev_priv->uncore, to_gt(dev_priv)); 323 324 spin_lock_init(&dev_priv->irq_lock); 325 spin_lock_init(&dev_priv->gpu_error.lock); 326 mutex_init(&dev_priv->backlight_lock); 327 328 mutex_init(&dev_priv->sb_lock); 329 cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE); 330 331 mutex_init(&dev_priv->audio.mutex); 332 mutex_init(&dev_priv->wm.wm_mutex); 333 mutex_init(&dev_priv->pps_mutex); 334 mutex_init(&dev_priv->hdcp_comp_mutex); 335 336 i915_memcpy_init_early(dev_priv); 337 intel_runtime_pm_init_early(&dev_priv->runtime_pm); 338 339 ret = i915_workqueues_init(dev_priv); 340 if (ret < 0) 341 return ret; 342 343 ret = vlv_suspend_init(dev_priv); 344 if (ret < 0) 345 goto err_workqueues; 346 347 ret = intel_region_ttm_device_init(dev_priv); 348 if (ret) 349 goto err_ttm; 350 351 intel_wopcm_init_early(&dev_priv->wopcm); 352 353 __intel_gt_init_early(to_gt(dev_priv), dev_priv); 354 355 i915_gem_init_early(dev_priv); 356 357 /* This must be called before any calls to HAS_PCH_* */ 358 intel_detect_pch(dev_priv); 359 360 intel_pm_setup(dev_priv); 361 ret = intel_power_domains_init(dev_priv); 362 if (ret < 0) 363 goto err_gem; 364 intel_irq_init(dev_priv); 365 intel_init_display_hooks(dev_priv); 366 intel_init_clock_gating_hooks(dev_priv); 367 368 intel_detect_preproduction_hw(dev_priv); 369 370 return 0; 371 372 err_gem: 373 i915_gem_cleanup_early(dev_priv); 374 intel_gt_driver_late_release(to_gt(dev_priv)); 375 intel_region_ttm_device_fini(dev_priv); 376 err_ttm: 377 vlv_suspend_cleanup(dev_priv); 378 err_workqueues: 379 i915_workqueues_cleanup(dev_priv); 380 return ret; 381 } 382 383 /** 384 * i915_driver_late_release - cleanup the setup done in 385 * i915_driver_early_probe() 386 * @dev_priv: device private 387 */ 388 static void i915_driver_late_release(struct drm_i915_private *dev_priv) 389 { 390 intel_irq_fini(dev_priv); 391 intel_power_domains_cleanup(dev_priv); 392 i915_gem_cleanup_early(dev_priv); 393 intel_gt_driver_late_release(to_gt(dev_priv)); 394 intel_region_ttm_device_fini(dev_priv); 395 vlv_suspend_cleanup(dev_priv); 396 i915_workqueues_cleanup(dev_priv); 397 398 cpu_latency_qos_remove_request(&dev_priv->sb_qos); 399 mutex_destroy(&dev_priv->sb_lock); 400 401 i915_params_free(&dev_priv->params); 402 } 403 404 /** 405 * i915_driver_mmio_probe - setup device MMIO 406 * @dev_priv: device private 407 * 408 * Setup minimal device state necessary for MMIO accesses later in the 409 * initialization sequence. The setup here should avoid any other device-wide 410 * side effects or exposing the driver via kernel internal or user space 411 * interfaces. 412 */ 413 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) 414 { 415 int ret; 416 417 if (i915_inject_probe_failure(dev_priv)) 418 return -ENODEV; 419 420 ret = i915_get_bridge_dev(dev_priv); 421 if (ret < 0) 422 return ret; 423 424 ret = intel_uncore_setup_mmio(&dev_priv->uncore); 425 if (ret < 0) 426 goto err_bridge; 427 428 ret = intel_uncore_init_mmio(&dev_priv->uncore); 429 if (ret) 430 goto err_mmio; 431 432 /* Try to make sure MCHBAR is enabled before poking at it */ 433 intel_setup_mchbar(dev_priv); 434 intel_device_info_runtime_init(dev_priv); 435 436 ret = intel_gt_init_mmio(to_gt(dev_priv)); 437 if (ret) 438 goto err_uncore; 439 440 /* As early as possible, scrub existing GPU state before clobbering */ 441 sanitize_gpu(dev_priv); 442 443 return 0; 444 445 err_uncore: 446 intel_teardown_mchbar(dev_priv); 447 intel_uncore_fini_mmio(&dev_priv->uncore); 448 err_mmio: 449 intel_uncore_cleanup_mmio(&dev_priv->uncore); 450 err_bridge: 451 pci_dev_put(dev_priv->bridge_dev); 452 453 return ret; 454 } 455 456 /** 457 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe() 458 * @dev_priv: device private 459 */ 460 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv) 461 { 462 intel_teardown_mchbar(dev_priv); 463 intel_uncore_fini_mmio(&dev_priv->uncore); 464 intel_uncore_cleanup_mmio(&dev_priv->uncore); 465 pci_dev_put(dev_priv->bridge_dev); 466 } 467 468 static void intel_sanitize_options(struct drm_i915_private *dev_priv) 469 { 470 intel_gvt_sanitize_options(dev_priv); 471 } 472 473 /** 474 * i915_set_dma_info - set all relevant PCI dma info as configured for the 475 * platform 476 * @i915: valid i915 instance 477 * 478 * Set the dma max segment size, device and coherent masks. The dma mask set 479 * needs to occur before i915_ggtt_probe_hw. 480 * 481 * A couple of platforms have special needs. Address them as well. 482 * 483 */ 484 static int i915_set_dma_info(struct drm_i915_private *i915) 485 { 486 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size; 487 int ret; 488 489 GEM_BUG_ON(!mask_size); 490 491 /* 492 * We don't have a max segment size, so set it to the max so sg's 493 * debugging layer doesn't complain 494 */ 495 dma_set_max_seg_size(i915->drm.dev, UINT_MAX); 496 497 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 498 if (ret) 499 goto mask_err; 500 501 /* overlay on gen2 is broken and can't address above 1G */ 502 if (GRAPHICS_VER(i915) == 2) 503 mask_size = 30; 504 505 /* 506 * 965GM sometimes incorrectly writes to hardware status page (HWS) 507 * using 32bit addressing, overwriting memory if HWS is located 508 * above 4GB. 509 * 510 * The documentation also mentions an issue with undefined 511 * behaviour if any general state is accessed within a page above 4GB, 512 * which also needs to be handled carefully. 513 */ 514 if (IS_I965G(i915) || IS_I965GM(i915)) 515 mask_size = 32; 516 517 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 518 if (ret) 519 goto mask_err; 520 521 return 0; 522 523 mask_err: 524 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret); 525 return ret; 526 } 527 528 /** 529 * i915_driver_hw_probe - setup state requiring device access 530 * @dev_priv: device private 531 * 532 * Setup state that requires accessing the device, but doesn't require 533 * exposing the driver via kernel internal or userspace interfaces. 534 */ 535 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) 536 { 537 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 538 int ret; 539 540 if (i915_inject_probe_failure(dev_priv)) 541 return -ENODEV; 542 543 if (HAS_PPGTT(dev_priv)) { 544 if (intel_vgpu_active(dev_priv) && 545 !intel_vgpu_has_full_ppgtt(dev_priv)) { 546 i915_report_error(dev_priv, 547 "incompatible vGPU found, support for isolated ppGTT required\n"); 548 return -ENXIO; 549 } 550 } 551 552 if (HAS_EXECLISTS(dev_priv)) { 553 /* 554 * Older GVT emulation depends upon intercepting CSB mmio, 555 * which we no longer use, preferring to use the HWSP cache 556 * instead. 557 */ 558 if (intel_vgpu_active(dev_priv) && 559 !intel_vgpu_has_hwsp_emulation(dev_priv)) { 560 i915_report_error(dev_priv, 561 "old vGPU host found, support for HWSP emulation required\n"); 562 return -ENXIO; 563 } 564 } 565 566 intel_sanitize_options(dev_priv); 567 568 /* needs to be done before ggtt probe */ 569 intel_dram_edram_detect(dev_priv); 570 571 ret = i915_set_dma_info(dev_priv); 572 if (ret) 573 return ret; 574 575 i915_perf_init(dev_priv); 576 577 ret = i915_ggtt_probe_hw(dev_priv); 578 if (ret) 579 goto err_perf; 580 581 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver); 582 if (ret) 583 goto err_ggtt; 584 585 ret = i915_ggtt_init_hw(dev_priv); 586 if (ret) 587 goto err_ggtt; 588 589 ret = intel_memory_regions_hw_probe(dev_priv); 590 if (ret) 591 goto err_ggtt; 592 593 intel_gt_init_hw_early(to_gt(dev_priv), &dev_priv->ggtt); 594 595 ret = intel_gt_probe_lmem(to_gt(dev_priv)); 596 if (ret) 597 goto err_mem_regions; 598 599 ret = i915_ggtt_enable_hw(dev_priv); 600 if (ret) { 601 drm_err(&dev_priv->drm, "failed to enable GGTT\n"); 602 goto err_mem_regions; 603 } 604 605 pci_set_master(pdev); 606 607 /* On the 945G/GM, the chipset reports the MSI capability on the 608 * integrated graphics even though the support isn't actually there 609 * according to the published specs. It doesn't appear to function 610 * correctly in testing on 945G. 611 * This may be a side effect of MSI having been made available for PEG 612 * and the registers being closely associated. 613 * 614 * According to chipset errata, on the 965GM, MSI interrupts may 615 * be lost or delayed, and was defeatured. MSI interrupts seem to 616 * get lost on g4x as well, and interrupt delivery seems to stay 617 * properly dead afterwards. So we'll just disable them for all 618 * pre-gen5 chipsets. 619 * 620 * dp aux and gmbus irq on gen4 seems to be able to generate legacy 621 * interrupts even when in MSI mode. This results in spurious 622 * interrupt warnings if the legacy irq no. is shared with another 623 * device. The kernel then disables that interrupt source and so 624 * prevents the other device from working properly. 625 */ 626 if (GRAPHICS_VER(dev_priv) >= 5) { 627 if (pci_enable_msi(pdev) < 0) 628 drm_dbg(&dev_priv->drm, "can't enable MSI"); 629 } 630 631 ret = intel_gvt_init(dev_priv); 632 if (ret) 633 goto err_msi; 634 635 intel_opregion_setup(dev_priv); 636 637 ret = intel_pcode_init(dev_priv); 638 if (ret) 639 goto err_msi; 640 641 /* 642 * Fill the dram structure to get the system dram info. This will be 643 * used for memory latency calculation. 644 */ 645 intel_dram_detect(dev_priv); 646 647 intel_bw_init_hw(dev_priv); 648 649 return 0; 650 651 err_msi: 652 if (pdev->msi_enabled) 653 pci_disable_msi(pdev); 654 err_mem_regions: 655 intel_memory_regions_driver_release(dev_priv); 656 err_ggtt: 657 i915_ggtt_driver_release(dev_priv); 658 i915_gem_drain_freed_objects(dev_priv); 659 i915_ggtt_driver_late_release(dev_priv); 660 err_perf: 661 i915_perf_fini(dev_priv); 662 return ret; 663 } 664 665 /** 666 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe() 667 * @dev_priv: device private 668 */ 669 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv) 670 { 671 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 672 673 i915_perf_fini(dev_priv); 674 675 if (pdev->msi_enabled) 676 pci_disable_msi(pdev); 677 } 678 679 /** 680 * i915_driver_register - register the driver with the rest of the system 681 * @dev_priv: device private 682 * 683 * Perform any steps necessary to make the driver available via kernel 684 * internal or userspace interfaces. 685 */ 686 static void i915_driver_register(struct drm_i915_private *dev_priv) 687 { 688 struct drm_device *dev = &dev_priv->drm; 689 690 i915_gem_driver_register(dev_priv); 691 i915_pmu_register(dev_priv); 692 693 intel_vgpu_register(dev_priv); 694 695 /* Reveal our presence to userspace */ 696 if (drm_dev_register(dev, 0)) { 697 drm_err(&dev_priv->drm, 698 "Failed to register driver for userspace access!\n"); 699 return; 700 } 701 702 i915_debugfs_register(dev_priv); 703 i915_setup_sysfs(dev_priv); 704 705 /* Depends on sysfs having been initialized */ 706 i915_perf_register(dev_priv); 707 708 intel_gt_driver_register(to_gt(dev_priv)); 709 710 intel_display_driver_register(dev_priv); 711 712 intel_power_domains_enable(dev_priv); 713 intel_runtime_pm_enable(&dev_priv->runtime_pm); 714 715 intel_register_dsm_handler(); 716 717 if (i915_switcheroo_register(dev_priv)) 718 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n"); 719 } 720 721 /** 722 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() 723 * @dev_priv: device private 724 */ 725 static void i915_driver_unregister(struct drm_i915_private *dev_priv) 726 { 727 i915_switcheroo_unregister(dev_priv); 728 729 intel_unregister_dsm_handler(); 730 731 intel_runtime_pm_disable(&dev_priv->runtime_pm); 732 intel_power_domains_disable(dev_priv); 733 734 intel_display_driver_unregister(dev_priv); 735 736 intel_gt_driver_unregister(to_gt(dev_priv)); 737 738 i915_perf_unregister(dev_priv); 739 i915_pmu_unregister(dev_priv); 740 741 i915_teardown_sysfs(dev_priv); 742 drm_dev_unplug(&dev_priv->drm); 743 744 i915_gem_driver_unregister(dev_priv); 745 } 746 747 void 748 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p) 749 { 750 drm_printf(p, "iommu: %s\n", enableddisabled(intel_vtd_active(i915))); 751 } 752 753 static void i915_welcome_messages(struct drm_i915_private *dev_priv) 754 { 755 if (drm_debug_enabled(DRM_UT_DRIVER)) { 756 struct drm_printer p = drm_debug_printer("i915 device info:"); 757 758 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n", 759 INTEL_DEVID(dev_priv), 760 INTEL_REVID(dev_priv), 761 intel_platform_name(INTEL_INFO(dev_priv)->platform), 762 intel_subplatform(RUNTIME_INFO(dev_priv), 763 INTEL_INFO(dev_priv)->platform), 764 GRAPHICS_VER(dev_priv)); 765 766 intel_device_info_print_static(INTEL_INFO(dev_priv), &p); 767 intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p); 768 i915_print_iommu_status(dev_priv, &p); 769 intel_gt_info_print(&to_gt(dev_priv)->info, &p); 770 } 771 772 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) 773 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n"); 774 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 775 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n"); 776 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) 777 drm_info(&dev_priv->drm, 778 "DRM_I915_DEBUG_RUNTIME_PM enabled\n"); 779 } 780 781 static struct drm_i915_private * 782 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) 783 { 784 const struct intel_device_info *match_info = 785 (struct intel_device_info *)ent->driver_data; 786 struct intel_device_info *device_info; 787 struct drm_i915_private *i915; 788 789 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver, 790 struct drm_i915_private, drm); 791 if (IS_ERR(i915)) 792 return i915; 793 794 pci_set_drvdata(pdev, i915); 795 796 /* Device parameters start as a copy of module parameters. */ 797 i915_params_copy(&i915->params, &i915_modparams); 798 799 /* Setup the write-once "constant" device info */ 800 device_info = mkwrite_device_info(i915); 801 memcpy(device_info, match_info, sizeof(*device_info)); 802 RUNTIME_INFO(i915)->device_id = pdev->device; 803 804 return i915; 805 } 806 807 /** 808 * i915_driver_probe - setup chip and create an initial config 809 * @pdev: PCI device 810 * @ent: matching PCI ID entry 811 * 812 * The driver probe routine has to do several things: 813 * - drive output discovery via intel_modeset_init() 814 * - initialize the memory manager 815 * - allocate initial config memory 816 * - setup the DRM framebuffer with the allocated memory 817 */ 818 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 819 { 820 const struct intel_device_info *match_info = 821 (struct intel_device_info *)ent->driver_data; 822 struct drm_i915_private *i915; 823 int ret; 824 825 i915 = i915_driver_create(pdev, ent); 826 if (IS_ERR(i915)) 827 return PTR_ERR(i915); 828 829 /* Disable nuclear pageflip by default on pre-ILK */ 830 if (!i915->params.nuclear_pageflip && match_info->graphics.ver < 5) 831 i915->drm.driver_features &= ~DRIVER_ATOMIC; 832 833 /* 834 * Check if we support fake LMEM -- for now we only unleash this for 835 * the live selftests(test-and-exit). 836 */ 837 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 838 if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) { 839 if (GRAPHICS_VER(i915) >= 9 && i915_selftest.live < 0 && 840 i915->params.fake_lmem_start) { 841 mkwrite_device_info(i915)->memory_regions = 842 REGION_SMEM | REGION_LMEM | REGION_STOLEN_SMEM; 843 GEM_BUG_ON(!HAS_LMEM(i915)); 844 } 845 } 846 #endif 847 848 ret = pci_enable_device(pdev); 849 if (ret) 850 goto out_fini; 851 852 ret = i915_driver_early_probe(i915); 853 if (ret < 0) 854 goto out_pci_disable; 855 856 disable_rpm_wakeref_asserts(&i915->runtime_pm); 857 858 intel_vgpu_detect(i915); 859 860 ret = i915_driver_mmio_probe(i915); 861 if (ret < 0) 862 goto out_runtime_pm_put; 863 864 ret = i915_driver_hw_probe(i915); 865 if (ret < 0) 866 goto out_cleanup_mmio; 867 868 ret = intel_modeset_init_noirq(i915); 869 if (ret < 0) 870 goto out_cleanup_hw; 871 872 ret = intel_irq_install(i915); 873 if (ret) 874 goto out_cleanup_modeset; 875 876 ret = intel_modeset_init_nogem(i915); 877 if (ret) 878 goto out_cleanup_irq; 879 880 ret = i915_gem_init(i915); 881 if (ret) 882 goto out_cleanup_modeset2; 883 884 ret = intel_modeset_init(i915); 885 if (ret) 886 goto out_cleanup_gem; 887 888 i915_driver_register(i915); 889 890 enable_rpm_wakeref_asserts(&i915->runtime_pm); 891 892 i915_welcome_messages(i915); 893 894 i915->do_release = true; 895 896 return 0; 897 898 out_cleanup_gem: 899 i915_gem_suspend(i915); 900 i915_gem_driver_remove(i915); 901 i915_gem_driver_release(i915); 902 out_cleanup_modeset2: 903 /* FIXME clean up the error path */ 904 intel_modeset_driver_remove(i915); 905 intel_irq_uninstall(i915); 906 intel_modeset_driver_remove_noirq(i915); 907 goto out_cleanup_modeset; 908 out_cleanup_irq: 909 intel_irq_uninstall(i915); 910 out_cleanup_modeset: 911 intel_modeset_driver_remove_nogem(i915); 912 out_cleanup_hw: 913 i915_driver_hw_remove(i915); 914 intel_memory_regions_driver_release(i915); 915 i915_ggtt_driver_release(i915); 916 i915_gem_drain_freed_objects(i915); 917 i915_ggtt_driver_late_release(i915); 918 out_cleanup_mmio: 919 i915_driver_mmio_release(i915); 920 out_runtime_pm_put: 921 enable_rpm_wakeref_asserts(&i915->runtime_pm); 922 i915_driver_late_release(i915); 923 out_pci_disable: 924 pci_disable_device(pdev); 925 out_fini: 926 i915_probe_error(i915, "Device initialization failed (%d)\n", ret); 927 return ret; 928 } 929 930 void i915_driver_remove(struct drm_i915_private *i915) 931 { 932 disable_rpm_wakeref_asserts(&i915->runtime_pm); 933 934 i915_driver_unregister(i915); 935 936 /* Flush any external code that still may be under the RCU lock */ 937 synchronize_rcu(); 938 939 i915_gem_suspend(i915); 940 941 intel_gvt_driver_remove(i915); 942 943 intel_modeset_driver_remove(i915); 944 945 intel_irq_uninstall(i915); 946 947 intel_modeset_driver_remove_noirq(i915); 948 949 i915_reset_error_state(i915); 950 i915_gem_driver_remove(i915); 951 952 intel_modeset_driver_remove_nogem(i915); 953 954 i915_driver_hw_remove(i915); 955 956 enable_rpm_wakeref_asserts(&i915->runtime_pm); 957 } 958 959 static void i915_driver_release(struct drm_device *dev) 960 { 961 struct drm_i915_private *dev_priv = to_i915(dev); 962 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 963 964 if (!dev_priv->do_release) 965 return; 966 967 disable_rpm_wakeref_asserts(rpm); 968 969 i915_gem_driver_release(dev_priv); 970 971 intel_memory_regions_driver_release(dev_priv); 972 i915_ggtt_driver_release(dev_priv); 973 i915_gem_drain_freed_objects(dev_priv); 974 i915_ggtt_driver_late_release(dev_priv); 975 976 i915_driver_mmio_release(dev_priv); 977 978 enable_rpm_wakeref_asserts(rpm); 979 intel_runtime_pm_driver_release(rpm); 980 981 i915_driver_late_release(dev_priv); 982 } 983 984 static int i915_driver_open(struct drm_device *dev, struct drm_file *file) 985 { 986 struct drm_i915_private *i915 = to_i915(dev); 987 int ret; 988 989 ret = i915_gem_open(i915, file); 990 if (ret) 991 return ret; 992 993 return 0; 994 } 995 996 /** 997 * i915_driver_lastclose - clean up after all DRM clients have exited 998 * @dev: DRM device 999 * 1000 * Take care of cleaning up after all DRM clients have exited. In the 1001 * mode setting case, we want to restore the kernel's initial mode (just 1002 * in case the last client left us in a bad state). 1003 * 1004 * Additionally, in the non-mode setting case, we'll tear down the GTT 1005 * and DMA structures, since the kernel won't be using them, and clea 1006 * up any GEM state. 1007 */ 1008 static void i915_driver_lastclose(struct drm_device *dev) 1009 { 1010 struct drm_i915_private *i915 = to_i915(dev); 1011 1012 intel_fbdev_restore_mode(dev); 1013 1014 if (HAS_DISPLAY(i915)) 1015 vga_switcheroo_process_delayed_switch(); 1016 } 1017 1018 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) 1019 { 1020 struct drm_i915_file_private *file_priv = file->driver_priv; 1021 1022 i915_gem_context_close(file); 1023 1024 kfree_rcu(file_priv, rcu); 1025 1026 /* Catch up with all the deferred frees from "this" client */ 1027 i915_gem_flush_free_objects(to_i915(dev)); 1028 } 1029 1030 static void intel_suspend_encoders(struct drm_i915_private *dev_priv) 1031 { 1032 struct drm_device *dev = &dev_priv->drm; 1033 struct intel_encoder *encoder; 1034 1035 if (!HAS_DISPLAY(dev_priv)) 1036 return; 1037 1038 drm_modeset_lock_all(dev); 1039 for_each_intel_encoder(dev, encoder) 1040 if (encoder->suspend) 1041 encoder->suspend(encoder); 1042 drm_modeset_unlock_all(dev); 1043 } 1044 1045 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv) 1046 { 1047 struct drm_device *dev = &dev_priv->drm; 1048 struct intel_encoder *encoder; 1049 1050 if (!HAS_DISPLAY(dev_priv)) 1051 return; 1052 1053 drm_modeset_lock_all(dev); 1054 for_each_intel_encoder(dev, encoder) 1055 if (encoder->shutdown) 1056 encoder->shutdown(encoder); 1057 drm_modeset_unlock_all(dev); 1058 } 1059 1060 void i915_driver_shutdown(struct drm_i915_private *i915) 1061 { 1062 disable_rpm_wakeref_asserts(&i915->runtime_pm); 1063 intel_runtime_pm_disable(&i915->runtime_pm); 1064 intel_power_domains_disable(i915); 1065 1066 i915_gem_suspend(i915); 1067 1068 if (HAS_DISPLAY(i915)) { 1069 drm_kms_helper_poll_disable(&i915->drm); 1070 1071 drm_atomic_helper_shutdown(&i915->drm); 1072 } 1073 1074 intel_dp_mst_suspend(i915); 1075 1076 intel_runtime_pm_disable_interrupts(i915); 1077 intel_hpd_cancel_work(i915); 1078 1079 intel_suspend_encoders(i915); 1080 intel_shutdown_encoders(i915); 1081 1082 intel_dmc_ucode_suspend(i915); 1083 1084 /* 1085 * The only requirement is to reboot with display DC states disabled, 1086 * for now leaving all display power wells in the INIT power domain 1087 * enabled. 1088 * 1089 * TODO: 1090 * - unify the pci_driver::shutdown sequence here with the 1091 * pci_driver.driver.pm.poweroff,poweroff_late sequence. 1092 * - unify the driver remove and system/runtime suspend sequences with 1093 * the above unified shutdown/poweroff sequence. 1094 */ 1095 intel_power_domains_driver_remove(i915); 1096 enable_rpm_wakeref_asserts(&i915->runtime_pm); 1097 1098 intel_runtime_pm_driver_release(&i915->runtime_pm); 1099 } 1100 1101 static bool suspend_to_idle(struct drm_i915_private *dev_priv) 1102 { 1103 #if IS_ENABLED(CONFIG_ACPI_SLEEP) 1104 if (acpi_target_system_state() < ACPI_STATE_S3) 1105 return true; 1106 #endif 1107 return false; 1108 } 1109 1110 static int i915_drm_prepare(struct drm_device *dev) 1111 { 1112 struct drm_i915_private *i915 = to_i915(dev); 1113 1114 /* 1115 * NB intel_display_suspend() may issue new requests after we've 1116 * ostensibly marked the GPU as ready-to-sleep here. We need to 1117 * split out that work and pull it forward so that after point, 1118 * the GPU is not woken again. 1119 */ 1120 return i915_gem_backup_suspend(i915); 1121 } 1122 1123 static int i915_drm_suspend(struct drm_device *dev) 1124 { 1125 struct drm_i915_private *dev_priv = to_i915(dev); 1126 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1127 pci_power_t opregion_target_state; 1128 1129 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1130 1131 /* We do a lot of poking in a lot of registers, make sure they work 1132 * properly. */ 1133 intel_power_domains_disable(dev_priv); 1134 if (HAS_DISPLAY(dev_priv)) 1135 drm_kms_helper_poll_disable(dev); 1136 1137 pci_save_state(pdev); 1138 1139 intel_display_suspend(dev); 1140 1141 intel_dp_mst_suspend(dev_priv); 1142 1143 intel_runtime_pm_disable_interrupts(dev_priv); 1144 intel_hpd_cancel_work(dev_priv); 1145 1146 intel_suspend_encoders(dev_priv); 1147 1148 intel_suspend_hw(dev_priv); 1149 1150 /* Must be called before GGTT is suspended. */ 1151 intel_dpt_suspend(dev_priv); 1152 i915_ggtt_suspend(&dev_priv->ggtt); 1153 1154 i915_save_display(dev_priv); 1155 1156 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; 1157 intel_opregion_suspend(dev_priv, opregion_target_state); 1158 1159 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); 1160 1161 dev_priv->suspend_count++; 1162 1163 intel_dmc_ucode_suspend(dev_priv); 1164 1165 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1166 1167 return 0; 1168 } 1169 1170 static enum i915_drm_suspend_mode 1171 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate) 1172 { 1173 if (hibernate) 1174 return I915_DRM_SUSPEND_HIBERNATE; 1175 1176 if (suspend_to_idle(dev_priv)) 1177 return I915_DRM_SUSPEND_IDLE; 1178 1179 return I915_DRM_SUSPEND_MEM; 1180 } 1181 1182 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) 1183 { 1184 struct drm_i915_private *dev_priv = to_i915(dev); 1185 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1186 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1187 int ret; 1188 1189 disable_rpm_wakeref_asserts(rpm); 1190 1191 i915_gem_suspend_late(dev_priv); 1192 1193 intel_uncore_suspend(&dev_priv->uncore); 1194 1195 intel_power_domains_suspend(dev_priv, 1196 get_suspend_mode(dev_priv, hibernation)); 1197 1198 intel_display_power_suspend_late(dev_priv); 1199 1200 ret = vlv_suspend_complete(dev_priv); 1201 if (ret) { 1202 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret); 1203 intel_power_domains_resume(dev_priv); 1204 1205 goto out; 1206 } 1207 1208 /* 1209 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX 1210 * This should be totally removed when we handle the pci states properly 1211 * on runtime PM and on s2idle cases. 1212 */ 1213 if (suspend_to_idle(dev_priv)) 1214 pci_d3cold_disable(pdev); 1215 1216 pci_disable_device(pdev); 1217 /* 1218 * During hibernation on some platforms the BIOS may try to access 1219 * the device even though it's already in D3 and hang the machine. So 1220 * leave the device in D0 on those platforms and hope the BIOS will 1221 * power down the device properly. The issue was seen on multiple old 1222 * GENs with different BIOS vendors, so having an explicit blacklist 1223 * is inpractical; apply the workaround on everything pre GEN6. The 1224 * platforms where the issue was seen: 1225 * Lenovo Thinkpad X301, X61s, X60, T60, X41 1226 * Fujitsu FSC S7110 1227 * Acer Aspire 1830T 1228 */ 1229 if (!(hibernation && GRAPHICS_VER(dev_priv) < 6)) 1230 pci_set_power_state(pdev, PCI_D3hot); 1231 1232 out: 1233 enable_rpm_wakeref_asserts(rpm); 1234 if (!dev_priv->uncore.user_forcewake_count) 1235 intel_runtime_pm_driver_release(rpm); 1236 1237 return ret; 1238 } 1239 1240 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915, 1241 pm_message_t state) 1242 { 1243 int error; 1244 1245 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND && 1246 state.event != PM_EVENT_FREEZE)) 1247 return -EINVAL; 1248 1249 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1250 return 0; 1251 1252 error = i915_drm_suspend(&i915->drm); 1253 if (error) 1254 return error; 1255 1256 return i915_drm_suspend_late(&i915->drm, false); 1257 } 1258 1259 static int i915_drm_resume(struct drm_device *dev) 1260 { 1261 struct drm_i915_private *dev_priv = to_i915(dev); 1262 int ret; 1263 1264 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1265 1266 ret = intel_pcode_init(dev_priv); 1267 if (ret) 1268 return ret; 1269 1270 sanitize_gpu(dev_priv); 1271 1272 ret = i915_ggtt_enable_hw(dev_priv); 1273 if (ret) 1274 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n"); 1275 1276 i915_ggtt_resume(&dev_priv->ggtt); 1277 /* Must be called after GGTT is resumed. */ 1278 intel_dpt_resume(dev_priv); 1279 1280 intel_dmc_ucode_resume(dev_priv); 1281 1282 i915_restore_display(dev_priv); 1283 intel_pps_unlock_regs_wa(dev_priv); 1284 1285 intel_init_pch_refclk(dev_priv); 1286 1287 /* 1288 * Interrupts have to be enabled before any batches are run. If not the 1289 * GPU will hang. i915_gem_init_hw() will initiate batches to 1290 * update/restore the context. 1291 * 1292 * drm_mode_config_reset() needs AUX interrupts. 1293 * 1294 * Modeset enabling in intel_modeset_init_hw() also needs working 1295 * interrupts. 1296 */ 1297 intel_runtime_pm_enable_interrupts(dev_priv); 1298 1299 if (HAS_DISPLAY(dev_priv)) 1300 drm_mode_config_reset(dev); 1301 1302 i915_gem_resume(dev_priv); 1303 1304 intel_modeset_init_hw(dev_priv); 1305 intel_init_clock_gating(dev_priv); 1306 intel_hpd_init(dev_priv); 1307 1308 /* MST sideband requires HPD interrupts enabled */ 1309 intel_dp_mst_resume(dev_priv); 1310 intel_display_resume(dev); 1311 1312 intel_hpd_poll_disable(dev_priv); 1313 if (HAS_DISPLAY(dev_priv)) 1314 drm_kms_helper_poll_enable(dev); 1315 1316 intel_opregion_resume(dev_priv); 1317 1318 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); 1319 1320 intel_power_domains_enable(dev_priv); 1321 1322 intel_gvt_resume(dev_priv); 1323 1324 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1325 1326 return 0; 1327 } 1328 1329 static int i915_drm_resume_early(struct drm_device *dev) 1330 { 1331 struct drm_i915_private *dev_priv = to_i915(dev); 1332 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1333 int ret; 1334 1335 /* 1336 * We have a resume ordering issue with the snd-hda driver also 1337 * requiring our device to be power up. Due to the lack of a 1338 * parent/child relationship we currently solve this with an early 1339 * resume hook. 1340 * 1341 * FIXME: This should be solved with a special hdmi sink device or 1342 * similar so that power domains can be employed. 1343 */ 1344 1345 /* 1346 * Note that we need to set the power state explicitly, since we 1347 * powered off the device during freeze and the PCI core won't power 1348 * it back up for us during thaw. Powering off the device during 1349 * freeze is not a hard requirement though, and during the 1350 * suspend/resume phases the PCI core makes sure we get here with the 1351 * device powered on. So in case we change our freeze logic and keep 1352 * the device powered we can also remove the following set power state 1353 * call. 1354 */ 1355 ret = pci_set_power_state(pdev, PCI_D0); 1356 if (ret) { 1357 drm_err(&dev_priv->drm, 1358 "failed to set PCI D0 power state (%d)\n", ret); 1359 return ret; 1360 } 1361 1362 /* 1363 * Note that pci_enable_device() first enables any parent bridge 1364 * device and only then sets the power state for this device. The 1365 * bridge enabling is a nop though, since bridge devices are resumed 1366 * first. The order of enabling power and enabling the device is 1367 * imposed by the PCI core as described above, so here we preserve the 1368 * same order for the freeze/thaw phases. 1369 * 1370 * TODO: eventually we should remove pci_disable_device() / 1371 * pci_enable_enable_device() from suspend/resume. Due to how they 1372 * depend on the device enable refcount we can't anyway depend on them 1373 * disabling/enabling the device. 1374 */ 1375 if (pci_enable_device(pdev)) 1376 return -EIO; 1377 1378 pci_set_master(pdev); 1379 1380 pci_d3cold_enable(pdev); 1381 1382 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1383 1384 ret = vlv_resume_prepare(dev_priv, false); 1385 if (ret) 1386 drm_err(&dev_priv->drm, 1387 "Resume prepare failed: %d, continuing anyway\n", ret); 1388 1389 intel_uncore_resume_early(&dev_priv->uncore); 1390 1391 intel_gt_check_and_clear_faults(to_gt(dev_priv)); 1392 1393 intel_display_power_resume_early(dev_priv); 1394 1395 intel_power_domains_resume(dev_priv); 1396 1397 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1398 1399 return ret; 1400 } 1401 1402 int i915_driver_resume_switcheroo(struct drm_i915_private *i915) 1403 { 1404 int ret; 1405 1406 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1407 return 0; 1408 1409 ret = i915_drm_resume_early(&i915->drm); 1410 if (ret) 1411 return ret; 1412 1413 return i915_drm_resume(&i915->drm); 1414 } 1415 1416 static int i915_pm_prepare(struct device *kdev) 1417 { 1418 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1419 1420 if (!i915) { 1421 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1422 return -ENODEV; 1423 } 1424 1425 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1426 return 0; 1427 1428 return i915_drm_prepare(&i915->drm); 1429 } 1430 1431 static int i915_pm_suspend(struct device *kdev) 1432 { 1433 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1434 1435 if (!i915) { 1436 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1437 return -ENODEV; 1438 } 1439 1440 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1441 return 0; 1442 1443 return i915_drm_suspend(&i915->drm); 1444 } 1445 1446 static int i915_pm_suspend_late(struct device *kdev) 1447 { 1448 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1449 1450 /* 1451 * We have a suspend ordering issue with the snd-hda driver also 1452 * requiring our device to be power up. Due to the lack of a 1453 * parent/child relationship we currently solve this with an late 1454 * suspend hook. 1455 * 1456 * FIXME: This should be solved with a special hdmi sink device or 1457 * similar so that power domains can be employed. 1458 */ 1459 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1460 return 0; 1461 1462 return i915_drm_suspend_late(&i915->drm, false); 1463 } 1464 1465 static int i915_pm_poweroff_late(struct device *kdev) 1466 { 1467 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1468 1469 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1470 return 0; 1471 1472 return i915_drm_suspend_late(&i915->drm, true); 1473 } 1474 1475 static int i915_pm_resume_early(struct device *kdev) 1476 { 1477 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1478 1479 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1480 return 0; 1481 1482 return i915_drm_resume_early(&i915->drm); 1483 } 1484 1485 static int i915_pm_resume(struct device *kdev) 1486 { 1487 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1488 1489 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1490 return 0; 1491 1492 return i915_drm_resume(&i915->drm); 1493 } 1494 1495 /* freeze: before creating the hibernation_image */ 1496 static int i915_pm_freeze(struct device *kdev) 1497 { 1498 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1499 int ret; 1500 1501 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1502 ret = i915_drm_suspend(&i915->drm); 1503 if (ret) 1504 return ret; 1505 } 1506 1507 ret = i915_gem_freeze(i915); 1508 if (ret) 1509 return ret; 1510 1511 return 0; 1512 } 1513 1514 static int i915_pm_freeze_late(struct device *kdev) 1515 { 1516 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1517 int ret; 1518 1519 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1520 ret = i915_drm_suspend_late(&i915->drm, true); 1521 if (ret) 1522 return ret; 1523 } 1524 1525 ret = i915_gem_freeze_late(i915); 1526 if (ret) 1527 return ret; 1528 1529 return 0; 1530 } 1531 1532 /* thaw: called after creating the hibernation image, but before turning off. */ 1533 static int i915_pm_thaw_early(struct device *kdev) 1534 { 1535 return i915_pm_resume_early(kdev); 1536 } 1537 1538 static int i915_pm_thaw(struct device *kdev) 1539 { 1540 return i915_pm_resume(kdev); 1541 } 1542 1543 /* restore: called after loading the hibernation image. */ 1544 static int i915_pm_restore_early(struct device *kdev) 1545 { 1546 return i915_pm_resume_early(kdev); 1547 } 1548 1549 static int i915_pm_restore(struct device *kdev) 1550 { 1551 return i915_pm_resume(kdev); 1552 } 1553 1554 static int intel_runtime_suspend(struct device *kdev) 1555 { 1556 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1557 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1558 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1559 int ret; 1560 1561 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1562 return -ENODEV; 1563 1564 drm_dbg_kms(&dev_priv->drm, "Suspending device\n"); 1565 1566 disable_rpm_wakeref_asserts(rpm); 1567 1568 /* 1569 * We are safe here against re-faults, since the fault handler takes 1570 * an RPM reference. 1571 */ 1572 i915_gem_runtime_suspend(dev_priv); 1573 1574 intel_gt_runtime_suspend(to_gt(dev_priv)); 1575 1576 intel_runtime_pm_disable_interrupts(dev_priv); 1577 1578 intel_uncore_suspend(&dev_priv->uncore); 1579 1580 intel_display_power_suspend(dev_priv); 1581 1582 ret = vlv_suspend_complete(dev_priv); 1583 if (ret) { 1584 drm_err(&dev_priv->drm, 1585 "Runtime suspend failed, disabling it (%d)\n", ret); 1586 intel_uncore_runtime_resume(&dev_priv->uncore); 1587 1588 intel_runtime_pm_enable_interrupts(dev_priv); 1589 1590 intel_gt_runtime_resume(to_gt(dev_priv)); 1591 1592 enable_rpm_wakeref_asserts(rpm); 1593 1594 return ret; 1595 } 1596 1597 enable_rpm_wakeref_asserts(rpm); 1598 intel_runtime_pm_driver_release(rpm); 1599 1600 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore)) 1601 drm_err(&dev_priv->drm, 1602 "Unclaimed access detected prior to suspending\n"); 1603 1604 /* 1605 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX 1606 * This should be totally removed when we handle the pci states properly 1607 * on runtime PM and on s2idle cases. 1608 */ 1609 pci_d3cold_disable(pdev); 1610 rpm->suspended = true; 1611 1612 /* 1613 * FIXME: We really should find a document that references the arguments 1614 * used below! 1615 */ 1616 if (IS_BROADWELL(dev_priv)) { 1617 /* 1618 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop 1619 * being detected, and the call we do at intel_runtime_resume() 1620 * won't be able to restore them. Since PCI_D3hot matches the 1621 * actual specification and appears to be working, use it. 1622 */ 1623 intel_opregion_notify_adapter(dev_priv, PCI_D3hot); 1624 } else { 1625 /* 1626 * current versions of firmware which depend on this opregion 1627 * notification have repurposed the D1 definition to mean 1628 * "runtime suspended" vs. what you would normally expect (D3) 1629 * to distinguish it from notifications that might be sent via 1630 * the suspend path. 1631 */ 1632 intel_opregion_notify_adapter(dev_priv, PCI_D1); 1633 } 1634 1635 assert_forcewakes_inactive(&dev_priv->uncore); 1636 1637 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) 1638 intel_hpd_poll_enable(dev_priv); 1639 1640 drm_dbg_kms(&dev_priv->drm, "Device suspended\n"); 1641 return 0; 1642 } 1643 1644 static int intel_runtime_resume(struct device *kdev) 1645 { 1646 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1647 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1648 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1649 int ret; 1650 1651 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1652 return -ENODEV; 1653 1654 drm_dbg_kms(&dev_priv->drm, "Resuming device\n"); 1655 1656 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count)); 1657 disable_rpm_wakeref_asserts(rpm); 1658 1659 intel_opregion_notify_adapter(dev_priv, PCI_D0); 1660 rpm->suspended = false; 1661 pci_d3cold_enable(pdev); 1662 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore)) 1663 drm_dbg(&dev_priv->drm, 1664 "Unclaimed access during suspend, bios?\n"); 1665 1666 intel_display_power_resume(dev_priv); 1667 1668 ret = vlv_resume_prepare(dev_priv, true); 1669 1670 intel_uncore_runtime_resume(&dev_priv->uncore); 1671 1672 intel_runtime_pm_enable_interrupts(dev_priv); 1673 1674 /* 1675 * No point of rolling back things in case of an error, as the best 1676 * we can do is to hope that things will still work (and disable RPM). 1677 */ 1678 intel_gt_runtime_resume(to_gt(dev_priv)); 1679 1680 /* 1681 * On VLV/CHV display interrupts are part of the display 1682 * power well, so hpd is reinitialized from there. For 1683 * everyone else do it here. 1684 */ 1685 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 1686 intel_hpd_init(dev_priv); 1687 intel_hpd_poll_disable(dev_priv); 1688 } 1689 1690 intel_enable_ipc(dev_priv); 1691 1692 enable_rpm_wakeref_asserts(rpm); 1693 1694 if (ret) 1695 drm_err(&dev_priv->drm, 1696 "Runtime resume failed, disabling it (%d)\n", ret); 1697 else 1698 drm_dbg_kms(&dev_priv->drm, "Device resumed\n"); 1699 1700 return ret; 1701 } 1702 1703 const struct dev_pm_ops i915_pm_ops = { 1704 /* 1705 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, 1706 * PMSG_RESUME] 1707 */ 1708 .prepare = i915_pm_prepare, 1709 .suspend = i915_pm_suspend, 1710 .suspend_late = i915_pm_suspend_late, 1711 .resume_early = i915_pm_resume_early, 1712 .resume = i915_pm_resume, 1713 1714 /* 1715 * S4 event handlers 1716 * @freeze, @freeze_late : called (1) before creating the 1717 * hibernation image [PMSG_FREEZE] and 1718 * (2) after rebooting, before restoring 1719 * the image [PMSG_QUIESCE] 1720 * @thaw, @thaw_early : called (1) after creating the hibernation 1721 * image, before writing it [PMSG_THAW] 1722 * and (2) after failing to create or 1723 * restore the image [PMSG_RECOVER] 1724 * @poweroff, @poweroff_late: called after writing the hibernation 1725 * image, before rebooting [PMSG_HIBERNATE] 1726 * @restore, @restore_early : called after rebooting and restoring the 1727 * hibernation image [PMSG_RESTORE] 1728 */ 1729 .freeze = i915_pm_freeze, 1730 .freeze_late = i915_pm_freeze_late, 1731 .thaw_early = i915_pm_thaw_early, 1732 .thaw = i915_pm_thaw, 1733 .poweroff = i915_pm_suspend, 1734 .poweroff_late = i915_pm_poweroff_late, 1735 .restore_early = i915_pm_restore_early, 1736 .restore = i915_pm_restore, 1737 1738 /* S0ix (via runtime suspend) event handlers */ 1739 .runtime_suspend = intel_runtime_suspend, 1740 .runtime_resume = intel_runtime_resume, 1741 }; 1742 1743 static const struct file_operations i915_driver_fops = { 1744 .owner = THIS_MODULE, 1745 .open = drm_open, 1746 .release = drm_release_noglobal, 1747 .unlocked_ioctl = drm_ioctl, 1748 .mmap = i915_gem_mmap, 1749 .poll = drm_poll, 1750 .read = drm_read, 1751 .compat_ioctl = i915_ioc32_compat_ioctl, 1752 .llseek = noop_llseek, 1753 }; 1754 1755 static int 1756 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, 1757 struct drm_file *file) 1758 { 1759 return -ENODEV; 1760 } 1761 1762 static const struct drm_ioctl_desc i915_ioctls[] = { 1763 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1764 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), 1765 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), 1766 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), 1767 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), 1768 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), 1769 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW), 1770 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1771 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), 1772 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), 1773 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1774 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), 1775 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1776 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1777 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), 1778 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), 1779 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1780 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1781 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH), 1782 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW), 1783 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1784 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1785 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW), 1786 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), 1787 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), 1788 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW), 1789 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1790 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1791 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), 1792 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW), 1793 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), 1794 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), 1795 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), 1796 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW), 1797 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), 1798 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), 1799 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW), 1800 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW), 1801 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), 1802 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0), 1803 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), 1804 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER), 1805 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER), 1806 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER), 1807 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER), 1808 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW), 1809 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), 1810 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), 1811 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), 1812 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW), 1813 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), 1814 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), 1815 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), 1816 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), 1817 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW), 1818 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW), 1819 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW), 1820 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW), 1821 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW), 1822 }; 1823 1824 static const struct drm_driver i915_drm_driver = { 1825 /* Don't use MTRRs here; the Xserver or userspace app should 1826 * deal with them for Intel hardware. 1827 */ 1828 .driver_features = 1829 DRIVER_GEM | 1830 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ | 1831 DRIVER_SYNCOBJ_TIMELINE, 1832 .release = i915_driver_release, 1833 .open = i915_driver_open, 1834 .lastclose = i915_driver_lastclose, 1835 .postclose = i915_driver_postclose, 1836 1837 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1838 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1839 .gem_prime_import = i915_gem_prime_import, 1840 1841 .dumb_create = i915_gem_dumb_create, 1842 .dumb_map_offset = i915_gem_dumb_mmap_offset, 1843 1844 .ioctls = i915_ioctls, 1845 .num_ioctls = ARRAY_SIZE(i915_ioctls), 1846 .fops = &i915_driver_fops, 1847 .name = DRIVER_NAME, 1848 .desc = DRIVER_DESC, 1849 .date = DRIVER_DATE, 1850 .major = DRIVER_MAJOR, 1851 .minor = DRIVER_MINOR, 1852 .patchlevel = DRIVER_PATCHLEVEL, 1853 }; 1854