1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #include <linux/aperture.h> 31 #include <linux/acpi.h> 32 #include <linux/device.h> 33 #include <linux/module.h> 34 #include <linux/oom.h> 35 #include <linux/pci.h> 36 #include <linux/pm.h> 37 #include <linux/pm_runtime.h> 38 #include <linux/slab.h> 39 #include <linux/string_helpers.h> 40 #include <linux/vga_switcheroo.h> 41 #include <linux/vt.h> 42 43 #include <drm/drm_atomic_helper.h> 44 #include <drm/drm_client.h> 45 #include <drm/drm_client_event.h> 46 #include <drm/drm_ioctl.h> 47 #include <drm/drm_managed.h> 48 #include <drm/drm_probe_helper.h> 49 50 #include "display/i9xx_display_sr.h" 51 #include "display/intel_bw.h" 52 #include "display/intel_cdclk.h" 53 #include "display/intel_crtc.h" 54 #include "display/intel_display_driver.h" 55 #include "display/intel_dmc.h" 56 #include "display/intel_dp.h" 57 #include "display/intel_dpt.h" 58 #include "display/intel_encoder.h" 59 #include "display/intel_fbdev.h" 60 #include "display/intel_hotplug.h" 61 #include "display/intel_overlay.h" 62 #include "display/intel_pch_refclk.h" 63 #include "display/intel_pps.h" 64 #include "display/intel_sprite_uapi.h" 65 #include "display/intel_vga.h" 66 #include "display/skl_watermark.h" 67 68 #include "gem/i915_gem_context.h" 69 #include "gem/i915_gem_create.h" 70 #include "gem/i915_gem_dmabuf.h" 71 #include "gem/i915_gem_ioctls.h" 72 #include "gem/i915_gem_mman.h" 73 #include "gem/i915_gem_pm.h" 74 #include "gt/intel_gt.h" 75 #include "gt/intel_gt_pm.h" 76 #include "gt/intel_gt_print.h" 77 #include "gt/intel_rc6.h" 78 79 #include "pxp/intel_pxp.h" 80 #include "pxp/intel_pxp_debugfs.h" 81 #include "pxp/intel_pxp_pm.h" 82 83 #include "soc/intel_dram.h" 84 #include "soc/intel_gmch.h" 85 86 #include "i915_debugfs.h" 87 #include "i915_driver.h" 88 #include "i915_drm_client.h" 89 #include "i915_drv.h" 90 #include "i915_file_private.h" 91 #include "i915_getparam.h" 92 #include "i915_hwmon.h" 93 #include "i915_ioc32.h" 94 #include "i915_ioctl.h" 95 #include "i915_irq.h" 96 #include "i915_memcpy.h" 97 #include "i915_perf.h" 98 #include "i915_query.h" 99 #include "i915_reg.h" 100 #include "i915_switcheroo.h" 101 #include "i915_sysfs.h" 102 #include "i915_utils.h" 103 #include "i915_vgpu.h" 104 #include "intel_clock_gating.h" 105 #include "intel_cpu_info.h" 106 #include "intel_gvt.h" 107 #include "intel_memory_region.h" 108 #include "intel_pci_config.h" 109 #include "intel_pcode.h" 110 #include "intel_region_ttm.h" 111 #include "intel_sbi.h" 112 #include "vlv_sideband.h" 113 #include "vlv_suspend.h" 114 115 static const struct drm_driver i915_drm_driver; 116 117 static int i915_workqueues_init(struct drm_i915_private *dev_priv) 118 { 119 /* 120 * The i915 workqueue is primarily used for batched retirement of 121 * requests (and thus managing bo) once the task has been completed 122 * by the GPU. i915_retire_requests() is called directly when we 123 * need high-priority retirement, such as waiting for an explicit 124 * bo. 125 * 126 * It is also used for periodic low-priority events, such as 127 * idle-timers and recording error state. 128 * 129 * All tasks on the workqueue are expected to acquire the dev mutex 130 * so there is no point in running more than one instance of the 131 * workqueue at any time. Use an ordered one. 132 */ 133 dev_priv->wq = alloc_ordered_workqueue("i915", 0); 134 if (dev_priv->wq == NULL) 135 goto out_err; 136 137 dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); 138 if (dev_priv->display.hotplug.dp_wq == NULL) 139 goto out_free_wq; 140 141 /* 142 * The unordered i915 workqueue should be used for all work 143 * scheduling that do not require running in order, which used 144 * to be scheduled on the system_wq before moving to a driver 145 * instance due deprecation of flush_scheduled_work(). 146 */ 147 dev_priv->unordered_wq = alloc_workqueue("i915-unordered", 0, 0); 148 if (dev_priv->unordered_wq == NULL) 149 goto out_free_dp_wq; 150 151 return 0; 152 153 out_free_dp_wq: 154 destroy_workqueue(dev_priv->display.hotplug.dp_wq); 155 out_free_wq: 156 destroy_workqueue(dev_priv->wq); 157 out_err: 158 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n"); 159 160 return -ENOMEM; 161 } 162 163 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) 164 { 165 destroy_workqueue(dev_priv->unordered_wq); 166 destroy_workqueue(dev_priv->display.hotplug.dp_wq); 167 destroy_workqueue(dev_priv->wq); 168 } 169 170 /* 171 * We don't keep the workarounds for pre-production hardware, so we expect our 172 * driver to fail on these machines in one way or another. A little warning on 173 * dmesg may help both the user and the bug triagers. 174 * 175 * Our policy for removing pre-production workarounds is to keep the 176 * current gen workarounds as a guide to the bring-up of the next gen 177 * (workarounds have a habit of persisting!). Anything older than that 178 * should be removed along with the complications they introduce. 179 */ 180 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) 181 { 182 bool pre = false; 183 184 pre |= IS_HASWELL_EARLY_SDV(dev_priv); 185 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6; 186 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA; 187 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 188 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3; 189 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7; 190 pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 191 pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 192 pre |= IS_DG2_G10(dev_priv) && INTEL_REVID(dev_priv) < 0x8; 193 pre |= IS_DG2_G11(dev_priv) && INTEL_REVID(dev_priv) < 0x5; 194 pre |= IS_DG2_G12(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 195 196 if (pre) { 197 drm_err(&dev_priv->drm, "This is a pre-production stepping. " 198 "It may not be fully functional.\n"); 199 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); 200 } 201 } 202 203 static void sanitize_gpu(struct drm_i915_private *i915) 204 { 205 if (!intel_gt_gpu_reset_clobbers_display(to_gt(i915))) { 206 struct intel_gt *gt; 207 unsigned int i; 208 209 for_each_gt(gt, i915, i) 210 intel_gt_reset_all_engines(gt); 211 } 212 } 213 214 /** 215 * i915_driver_early_probe - setup state not requiring device access 216 * @dev_priv: device private 217 * 218 * Initialize everything that is a "SW-only" state, that is state not 219 * requiring accessing the device or exposing the driver via kernel internal 220 * or userspace interfaces. Example steps belonging here: lock initialization, 221 * system memory allocation, setting up device specific attributes and 222 * function hooks not requiring accessing the device. 223 */ 224 static int i915_driver_early_probe(struct drm_i915_private *dev_priv) 225 { 226 struct intel_display *display = &dev_priv->display; 227 int ret = 0; 228 229 if (i915_inject_probe_failure(dev_priv)) 230 return -ENODEV; 231 232 intel_device_info_runtime_init_early(dev_priv); 233 234 intel_step_init(dev_priv); 235 236 intel_uncore_mmio_debug_init_early(dev_priv); 237 238 spin_lock_init(&dev_priv->irq_lock); 239 spin_lock_init(&dev_priv->gpu_error.lock); 240 241 intel_sbi_init(dev_priv); 242 vlv_iosf_sb_init(dev_priv); 243 mutex_init(&dev_priv->sb_lock); 244 245 i915_memcpy_init_early(dev_priv); 246 intel_runtime_pm_init_early(&dev_priv->runtime_pm); 247 248 ret = i915_workqueues_init(dev_priv); 249 if (ret < 0) 250 return ret; 251 252 ret = vlv_suspend_init(dev_priv); 253 if (ret < 0) 254 goto err_workqueues; 255 256 ret = intel_region_ttm_device_init(dev_priv); 257 if (ret) 258 goto err_ttm; 259 260 ret = intel_root_gt_init_early(dev_priv); 261 if (ret < 0) 262 goto err_rootgt; 263 264 i915_gem_init_early(dev_priv); 265 266 /* This must be called before any calls to HAS_PCH_* */ 267 intel_detect_pch(dev_priv); 268 269 intel_irq_init(dev_priv); 270 intel_display_driver_early_probe(display); 271 intel_clock_gating_hooks_init(dev_priv); 272 273 intel_detect_preproduction_hw(dev_priv); 274 275 return 0; 276 277 err_rootgt: 278 intel_region_ttm_device_fini(dev_priv); 279 err_ttm: 280 vlv_suspend_cleanup(dev_priv); 281 err_workqueues: 282 i915_workqueues_cleanup(dev_priv); 283 return ret; 284 } 285 286 /** 287 * i915_driver_late_release - cleanup the setup done in 288 * i915_driver_early_probe() 289 * @dev_priv: device private 290 */ 291 static void i915_driver_late_release(struct drm_i915_private *dev_priv) 292 { 293 struct intel_display *display = &dev_priv->display; 294 295 intel_irq_fini(dev_priv); 296 intel_power_domains_cleanup(display); 297 i915_gem_cleanup_early(dev_priv); 298 intel_gt_driver_late_release_all(dev_priv); 299 intel_region_ttm_device_fini(dev_priv); 300 vlv_suspend_cleanup(dev_priv); 301 i915_workqueues_cleanup(dev_priv); 302 303 mutex_destroy(&dev_priv->sb_lock); 304 vlv_iosf_sb_fini(dev_priv); 305 intel_sbi_fini(dev_priv); 306 307 i915_params_free(&dev_priv->params); 308 } 309 310 /** 311 * i915_driver_mmio_probe - setup device MMIO 312 * @dev_priv: device private 313 * 314 * Setup minimal device state necessary for MMIO accesses later in the 315 * initialization sequence. The setup here should avoid any other device-wide 316 * side effects or exposing the driver via kernel internal or user space 317 * interfaces. 318 */ 319 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) 320 { 321 struct intel_display *display = &dev_priv->display; 322 struct intel_gt *gt; 323 int ret, i; 324 325 if (i915_inject_probe_failure(dev_priv)) 326 return -ENODEV; 327 328 ret = intel_gmch_bridge_setup(dev_priv); 329 if (ret < 0) 330 return ret; 331 332 for_each_gt(gt, dev_priv, i) { 333 ret = intel_uncore_init_mmio(gt->uncore); 334 if (ret) 335 return ret; 336 337 ret = drmm_add_action_or_reset(&dev_priv->drm, 338 intel_uncore_fini_mmio, 339 gt->uncore); 340 if (ret) 341 return ret; 342 } 343 344 /* Try to make sure MCHBAR is enabled before poking at it */ 345 intel_gmch_bar_setup(dev_priv); 346 intel_device_info_runtime_init(dev_priv); 347 intel_display_device_info_runtime_init(display); 348 349 for_each_gt(gt, dev_priv, i) { 350 ret = intel_gt_init_mmio(gt); 351 if (ret) 352 goto err_uncore; 353 } 354 355 /* As early as possible, scrub existing GPU state before clobbering */ 356 sanitize_gpu(dev_priv); 357 358 return 0; 359 360 err_uncore: 361 intel_gmch_bar_teardown(dev_priv); 362 363 return ret; 364 } 365 366 /** 367 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe() 368 * @dev_priv: device private 369 */ 370 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv) 371 { 372 intel_gmch_bar_teardown(dev_priv); 373 } 374 375 /** 376 * i915_set_dma_info - set all relevant PCI dma info as configured for the 377 * platform 378 * @i915: valid i915 instance 379 * 380 * Set the dma max segment size, device and coherent masks. The dma mask set 381 * needs to occur before i915_ggtt_probe_hw. 382 * 383 * A couple of platforms have special needs. Address them as well. 384 * 385 */ 386 static int i915_set_dma_info(struct drm_i915_private *i915) 387 { 388 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size; 389 int ret; 390 391 GEM_BUG_ON(!mask_size); 392 393 /* 394 * We don't have a max segment size, so set it to the max so sg's 395 * debugging layer doesn't complain 396 */ 397 dma_set_max_seg_size(i915->drm.dev, UINT_MAX); 398 399 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 400 if (ret) 401 goto mask_err; 402 403 /* overlay on gen2 is broken and can't address above 1G */ 404 if (GRAPHICS_VER(i915) == 2) 405 mask_size = 30; 406 407 /* 408 * 965GM sometimes incorrectly writes to hardware status page (HWS) 409 * using 32bit addressing, overwriting memory if HWS is located 410 * above 4GB. 411 * 412 * The documentation also mentions an issue with undefined 413 * behaviour if any general state is accessed within a page above 4GB, 414 * which also needs to be handled carefully. 415 */ 416 if (IS_I965G(i915) || IS_I965GM(i915)) 417 mask_size = 32; 418 419 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 420 if (ret) 421 goto mask_err; 422 423 return 0; 424 425 mask_err: 426 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret); 427 return ret; 428 } 429 430 /* Wa_14022698537:dg2 */ 431 static void i915_enable_g8(struct drm_i915_private *i915) 432 { 433 if (IS_DG2(i915)) { 434 if (IS_DG2_D(i915) && !intel_match_g8_cpu()) 435 return; 436 437 snb_pcode_write_p(&i915->uncore, PCODE_POWER_SETUP, 438 POWER_SETUP_SUBCOMMAND_G8_ENABLE, 0, 0); 439 } 440 } 441 442 static int i915_pcode_init(struct drm_i915_private *i915) 443 { 444 struct intel_gt *gt; 445 int id, ret; 446 447 for_each_gt(gt, i915, id) { 448 ret = intel_pcode_init(gt->uncore); 449 if (ret) { 450 gt_err(gt, "intel_pcode_init failed %d\n", ret); 451 return ret; 452 } 453 } 454 455 i915_enable_g8(i915); 456 return 0; 457 } 458 459 /** 460 * i915_driver_hw_probe - setup state requiring device access 461 * @dev_priv: device private 462 * 463 * Setup state that requires accessing the device, but doesn't require 464 * exposing the driver via kernel internal or userspace interfaces. 465 */ 466 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) 467 { 468 struct intel_display *display = &dev_priv->display; 469 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 470 int ret; 471 472 if (i915_inject_probe_failure(dev_priv)) 473 return -ENODEV; 474 475 if (HAS_PPGTT(dev_priv)) { 476 if (intel_vgpu_active(dev_priv) && 477 !intel_vgpu_has_full_ppgtt(dev_priv)) { 478 drm_err(&dev_priv->drm, 479 "incompatible vGPU found, support for isolated ppGTT required\n"); 480 return -ENXIO; 481 } 482 } 483 484 if (HAS_EXECLISTS(dev_priv)) { 485 /* 486 * Older GVT emulation depends upon intercepting CSB mmio, 487 * which we no longer use, preferring to use the HWSP cache 488 * instead. 489 */ 490 if (intel_vgpu_active(dev_priv) && 491 !intel_vgpu_has_hwsp_emulation(dev_priv)) { 492 drm_err(&dev_priv->drm, 493 "old vGPU host found, support for HWSP emulation required\n"); 494 return -ENXIO; 495 } 496 } 497 498 /* needs to be done before ggtt probe */ 499 intel_dram_edram_detect(dev_priv); 500 501 ret = i915_set_dma_info(dev_priv); 502 if (ret) 503 return ret; 504 505 ret = i915_perf_init(dev_priv); 506 if (ret) 507 return ret; 508 509 ret = i915_ggtt_probe_hw(dev_priv); 510 if (ret) 511 goto err_perf; 512 513 ret = aperture_remove_conflicting_pci_devices(pdev, dev_priv->drm.driver->name); 514 if (ret) 515 goto err_ggtt; 516 517 ret = i915_ggtt_init_hw(dev_priv); 518 if (ret) 519 goto err_ggtt; 520 521 /* 522 * Make sure we probe lmem before we probe stolen-lmem. The BAR size 523 * might be different due to bar resizing. 524 */ 525 ret = intel_gt_tiles_init(dev_priv); 526 if (ret) 527 goto err_ggtt; 528 529 ret = intel_memory_regions_hw_probe(dev_priv); 530 if (ret) 531 goto err_ggtt; 532 533 ret = i915_ggtt_enable_hw(dev_priv); 534 if (ret) { 535 drm_err(&dev_priv->drm, "failed to enable GGTT\n"); 536 goto err_mem_regions; 537 } 538 539 pci_set_master(pdev); 540 541 /* On the 945G/GM, the chipset reports the MSI capability on the 542 * integrated graphics even though the support isn't actually there 543 * according to the published specs. It doesn't appear to function 544 * correctly in testing on 945G. 545 * This may be a side effect of MSI having been made available for PEG 546 * and the registers being closely associated. 547 * 548 * According to chipset errata, on the 965GM, MSI interrupts may 549 * be lost or delayed, and was defeatured. MSI interrupts seem to 550 * get lost on g4x as well, and interrupt delivery seems to stay 551 * properly dead afterwards. So we'll just disable them for all 552 * pre-gen5 chipsets. 553 * 554 * dp aux and gmbus irq on gen4 seems to be able to generate legacy 555 * interrupts even when in MSI mode. This results in spurious 556 * interrupt warnings if the legacy irq no. is shared with another 557 * device. The kernel then disables that interrupt source and so 558 * prevents the other device from working properly. 559 */ 560 if (GRAPHICS_VER(dev_priv) >= 5) { 561 if (pci_enable_msi(pdev) < 0) 562 drm_dbg(&dev_priv->drm, "can't enable MSI"); 563 } 564 565 ret = intel_gvt_init(dev_priv); 566 if (ret) 567 goto err_msi; 568 569 intel_opregion_setup(display); 570 571 ret = i915_pcode_init(dev_priv); 572 if (ret) 573 goto err_opregion; 574 575 /* 576 * Fill the dram structure to get the system dram info. This will be 577 * used for memory latency calculation. 578 */ 579 intel_dram_detect(dev_priv); 580 581 intel_bw_init_hw(display); 582 583 return 0; 584 585 err_opregion: 586 intel_opregion_cleanup(display); 587 err_msi: 588 if (pdev->msi_enabled) 589 pci_disable_msi(pdev); 590 err_mem_regions: 591 intel_memory_regions_driver_release(dev_priv); 592 err_ggtt: 593 i915_ggtt_driver_release(dev_priv); 594 i915_gem_drain_freed_objects(dev_priv); 595 i915_ggtt_driver_late_release(dev_priv); 596 err_perf: 597 i915_perf_fini(dev_priv); 598 return ret; 599 } 600 601 /** 602 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe() 603 * @dev_priv: device private 604 */ 605 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv) 606 { 607 struct intel_display *display = &dev_priv->display; 608 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 609 610 i915_perf_fini(dev_priv); 611 612 intel_opregion_cleanup(display); 613 614 if (pdev->msi_enabled) 615 pci_disable_msi(pdev); 616 } 617 618 /** 619 * i915_driver_register - register the driver with the rest of the system 620 * @dev_priv: device private 621 * 622 * Perform any steps necessary to make the driver available via kernel 623 * internal or userspace interfaces. 624 */ 625 static int i915_driver_register(struct drm_i915_private *dev_priv) 626 { 627 struct intel_display *display = &dev_priv->display; 628 struct intel_gt *gt; 629 unsigned int i; 630 int ret; 631 632 i915_gem_driver_register(dev_priv); 633 i915_pmu_register(dev_priv); 634 635 intel_vgpu_register(dev_priv); 636 637 /* Reveal our presence to userspace */ 638 ret = drm_dev_register(&dev_priv->drm, 0); 639 if (ret) { 640 i915_probe_error(dev_priv, 641 "Failed to register driver for userspace access!\n"); 642 drm_dev_unregister(&dev_priv->drm); 643 i915_pmu_unregister(dev_priv); 644 i915_gem_driver_unregister(dev_priv); 645 return ret; 646 } 647 648 i915_debugfs_register(dev_priv); 649 i915_setup_sysfs(dev_priv); 650 651 /* Depends on sysfs having been initialized */ 652 i915_perf_register(dev_priv); 653 654 for_each_gt(gt, dev_priv, i) 655 intel_gt_driver_register(gt); 656 657 intel_pxp_debugfs_register(dev_priv->pxp); 658 659 i915_hwmon_register(dev_priv); 660 661 intel_display_driver_register(display); 662 663 intel_power_domains_enable(display); 664 intel_runtime_pm_enable(&dev_priv->runtime_pm); 665 666 if (i915_switcheroo_register(dev_priv)) 667 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n"); 668 669 return 0; 670 } 671 672 /** 673 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() 674 * @dev_priv: device private 675 */ 676 static void i915_driver_unregister(struct drm_i915_private *dev_priv) 677 { 678 struct intel_display *display = &dev_priv->display; 679 struct intel_gt *gt; 680 unsigned int i; 681 682 i915_switcheroo_unregister(dev_priv); 683 684 intel_runtime_pm_disable(&dev_priv->runtime_pm); 685 intel_power_domains_disable(display); 686 687 intel_display_driver_unregister(display); 688 689 intel_pxp_fini(dev_priv); 690 691 for_each_gt(gt, dev_priv, i) 692 intel_gt_driver_unregister(gt); 693 694 i915_hwmon_unregister(dev_priv); 695 696 i915_perf_unregister(dev_priv); 697 i915_pmu_unregister(dev_priv); 698 699 i915_teardown_sysfs(dev_priv); 700 drm_dev_unplug(&dev_priv->drm); 701 702 i915_gem_driver_unregister(dev_priv); 703 } 704 705 void 706 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p) 707 { 708 drm_printf(p, "iommu: %s\n", 709 str_enabled_disabled(i915_vtd_active(i915))); 710 } 711 712 static void i915_welcome_messages(struct drm_i915_private *dev_priv) 713 { 714 if (drm_debug_enabled(DRM_UT_DRIVER)) { 715 struct drm_printer p = drm_dbg_printer(&dev_priv->drm, DRM_UT_DRIVER, 716 "device info:"); 717 struct intel_gt *gt; 718 unsigned int i; 719 720 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n", 721 INTEL_DEVID(dev_priv), 722 INTEL_REVID(dev_priv), 723 intel_platform_name(INTEL_INFO(dev_priv)->platform), 724 intel_subplatform(RUNTIME_INFO(dev_priv), 725 INTEL_INFO(dev_priv)->platform), 726 GRAPHICS_VER(dev_priv)); 727 728 intel_device_info_print(INTEL_INFO(dev_priv), 729 RUNTIME_INFO(dev_priv), &p); 730 i915_print_iommu_status(dev_priv, &p); 731 for_each_gt(gt, dev_priv, i) 732 intel_gt_info_print(>->info, &p); 733 } 734 735 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) 736 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n"); 737 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 738 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n"); 739 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) 740 drm_info(&dev_priv->drm, 741 "DRM_I915_DEBUG_RUNTIME_PM enabled\n"); 742 } 743 744 static struct drm_i915_private * 745 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) 746 { 747 const struct intel_device_info *match_info = 748 (struct intel_device_info *)ent->driver_data; 749 struct drm_i915_private *i915; 750 751 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver, 752 struct drm_i915_private, drm); 753 if (IS_ERR(i915)) 754 return i915; 755 756 pci_set_drvdata(pdev, &i915->drm); 757 758 /* Device parameters start as a copy of module parameters. */ 759 i915_params_copy(&i915->params, &i915_modparams); 760 761 /* Set up device info and initial runtime info. */ 762 intel_device_info_driver_create(i915, pdev->device, match_info); 763 764 intel_display_device_probe(pdev); 765 766 return i915; 767 } 768 769 /** 770 * i915_driver_probe - setup chip and create an initial config 771 * @pdev: PCI device 772 * @ent: matching PCI ID entry 773 * 774 * The driver probe routine has to do several things: 775 * - drive output discovery via intel_display_driver_probe() 776 * - initialize the memory manager 777 * - allocate initial config memory 778 * - setup the DRM framebuffer with the allocated memory 779 */ 780 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 781 { 782 struct drm_i915_private *i915; 783 struct intel_display *display; 784 int ret; 785 786 ret = pci_enable_device(pdev); 787 if (ret) { 788 pr_err("Failed to enable graphics device: %pe\n", ERR_PTR(ret)); 789 return ret; 790 } 791 792 i915 = i915_driver_create(pdev, ent); 793 if (IS_ERR(i915)) { 794 pci_disable_device(pdev); 795 return PTR_ERR(i915); 796 } 797 798 display = &i915->display; 799 800 ret = i915_driver_early_probe(i915); 801 if (ret < 0) 802 goto out_pci_disable; 803 804 disable_rpm_wakeref_asserts(&i915->runtime_pm); 805 806 intel_vgpu_detect(i915); 807 808 ret = intel_gt_probe_all(i915); 809 if (ret < 0) 810 goto out_runtime_pm_put; 811 812 ret = i915_driver_mmio_probe(i915); 813 if (ret < 0) 814 goto out_runtime_pm_put; 815 816 ret = i915_driver_hw_probe(i915); 817 if (ret < 0) 818 goto out_cleanup_mmio; 819 820 ret = intel_display_driver_probe_noirq(display); 821 if (ret < 0) 822 goto out_cleanup_hw; 823 824 ret = intel_irq_install(i915); 825 if (ret) 826 goto out_cleanup_modeset; 827 828 ret = intel_display_driver_probe_nogem(display); 829 if (ret) 830 goto out_cleanup_irq; 831 832 ret = i915_gem_init(i915); 833 if (ret) 834 goto out_cleanup_modeset2; 835 836 ret = intel_pxp_init(i915); 837 if (ret && ret != -ENODEV) 838 drm_dbg(&i915->drm, "pxp init failed with %d\n", ret); 839 840 ret = intel_display_driver_probe(display); 841 if (ret) 842 goto out_cleanup_gem; 843 844 ret = i915_driver_register(i915); 845 if (ret) 846 goto out_cleanup_gem; 847 848 enable_rpm_wakeref_asserts(&i915->runtime_pm); 849 850 i915_welcome_messages(i915); 851 852 i915->do_release = true; 853 854 return 0; 855 856 out_cleanup_gem: 857 intel_pxp_fini(i915); 858 i915_gem_suspend(i915); 859 i915_gem_driver_remove(i915); 860 i915_gem_driver_release(i915); 861 out_cleanup_modeset2: 862 /* FIXME clean up the error path */ 863 intel_display_driver_remove(display); 864 intel_irq_uninstall(i915); 865 intel_display_driver_remove_noirq(display); 866 goto out_cleanup_modeset; 867 out_cleanup_irq: 868 intel_irq_uninstall(i915); 869 out_cleanup_modeset: 870 intel_display_driver_remove_nogem(display); 871 out_cleanup_hw: 872 i915_driver_hw_remove(i915); 873 intel_memory_regions_driver_release(i915); 874 i915_ggtt_driver_release(i915); 875 i915_gem_drain_freed_objects(i915); 876 i915_ggtt_driver_late_release(i915); 877 out_cleanup_mmio: 878 i915_driver_mmio_release(i915); 879 out_runtime_pm_put: 880 enable_rpm_wakeref_asserts(&i915->runtime_pm); 881 i915_driver_late_release(i915); 882 out_pci_disable: 883 pci_disable_device(pdev); 884 i915_probe_error(i915, "Device initialization failed (%d)\n", ret); 885 return ret; 886 } 887 888 void i915_driver_remove(struct drm_i915_private *i915) 889 { 890 struct intel_display *display = &i915->display; 891 intel_wakeref_t wakeref; 892 893 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 894 895 i915_driver_unregister(i915); 896 897 /* Flush any external code that still may be under the RCU lock */ 898 synchronize_rcu(); 899 900 i915_gem_suspend(i915); 901 902 intel_gvt_driver_remove(i915); 903 904 intel_display_driver_remove(display); 905 906 intel_irq_uninstall(i915); 907 908 intel_display_driver_remove_noirq(display); 909 910 i915_reset_error_state(i915); 911 i915_gem_driver_remove(i915); 912 913 intel_display_driver_remove_nogem(display); 914 915 i915_driver_hw_remove(i915); 916 917 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 918 } 919 920 static void i915_driver_release(struct drm_device *dev) 921 { 922 struct drm_i915_private *dev_priv = to_i915(dev); 923 struct intel_display *display = &dev_priv->display; 924 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 925 intel_wakeref_t wakeref; 926 927 if (!dev_priv->do_release) 928 return; 929 930 wakeref = intel_runtime_pm_get(rpm); 931 932 i915_gem_driver_release(dev_priv); 933 934 intel_memory_regions_driver_release(dev_priv); 935 i915_ggtt_driver_release(dev_priv); 936 i915_gem_drain_freed_objects(dev_priv); 937 i915_ggtt_driver_late_release(dev_priv); 938 939 i915_driver_mmio_release(dev_priv); 940 941 intel_runtime_pm_put(rpm, wakeref); 942 943 intel_runtime_pm_driver_release(rpm); 944 945 i915_driver_late_release(dev_priv); 946 947 intel_display_device_remove(display); 948 } 949 950 static int i915_driver_open(struct drm_device *dev, struct drm_file *file) 951 { 952 struct drm_i915_private *i915 = to_i915(dev); 953 int ret; 954 955 ret = i915_gem_open(i915, file); 956 if (ret) 957 return ret; 958 959 return 0; 960 } 961 962 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) 963 { 964 struct drm_i915_file_private *file_priv = file->driver_priv; 965 966 i915_gem_context_close(file); 967 i915_drm_client_put(file_priv->client); 968 969 kfree_rcu(file_priv, rcu); 970 971 /* Catch up with all the deferred frees from "this" client */ 972 i915_gem_flush_free_objects(to_i915(dev)); 973 } 974 975 void i915_driver_shutdown(struct drm_i915_private *i915) 976 { 977 struct intel_display *display = &i915->display; 978 979 disable_rpm_wakeref_asserts(&i915->runtime_pm); 980 intel_runtime_pm_disable(&i915->runtime_pm); 981 intel_power_domains_disable(display); 982 983 drm_client_dev_suspend(&i915->drm, false); 984 if (HAS_DISPLAY(i915)) { 985 drm_kms_helper_poll_disable(&i915->drm); 986 intel_display_driver_disable_user_access(display); 987 988 drm_atomic_helper_shutdown(&i915->drm); 989 } 990 991 intel_dp_mst_suspend(display); 992 993 intel_irq_suspend(i915); 994 intel_hpd_cancel_work(display); 995 996 if (HAS_DISPLAY(i915)) 997 intel_display_driver_suspend_access(display); 998 999 intel_encoder_suspend_all(&i915->display); 1000 intel_encoder_shutdown_all(&i915->display); 1001 1002 intel_dmc_suspend(&i915->display); 1003 1004 i915_gem_suspend(i915); 1005 1006 /* 1007 * The only requirement is to reboot with display DC states disabled, 1008 * for now leaving all display power wells in the INIT power domain 1009 * enabled. 1010 * 1011 * TODO: 1012 * - unify the pci_driver::shutdown sequence here with the 1013 * pci_driver.driver.pm.poweroff,poweroff_late sequence. 1014 * - unify the driver remove and system/runtime suspend sequences with 1015 * the above unified shutdown/poweroff sequence. 1016 */ 1017 intel_power_domains_driver_remove(display); 1018 enable_rpm_wakeref_asserts(&i915->runtime_pm); 1019 1020 intel_runtime_pm_driver_last_release(&i915->runtime_pm); 1021 } 1022 1023 static bool suspend_to_idle(struct drm_i915_private *dev_priv) 1024 { 1025 #if IS_ENABLED(CONFIG_ACPI_SLEEP) 1026 if (acpi_target_system_state() < ACPI_STATE_S3) 1027 return true; 1028 #endif 1029 return false; 1030 } 1031 1032 static void i915_drm_complete(struct drm_device *dev) 1033 { 1034 struct drm_i915_private *i915 = to_i915(dev); 1035 1036 intel_pxp_resume_complete(i915->pxp); 1037 } 1038 1039 static int i915_drm_prepare(struct drm_device *dev) 1040 { 1041 struct drm_i915_private *i915 = to_i915(dev); 1042 1043 intel_pxp_suspend_prepare(i915->pxp); 1044 1045 /* 1046 * NB intel_display_driver_suspend() may issue new requests after we've 1047 * ostensibly marked the GPU as ready-to-sleep here. We need to 1048 * split out that work and pull it forward so that after point, 1049 * the GPU is not woken again. 1050 */ 1051 return i915_gem_backup_suspend(i915); 1052 } 1053 1054 static int i915_drm_suspend(struct drm_device *dev) 1055 { 1056 struct drm_i915_private *dev_priv = to_i915(dev); 1057 struct intel_display *display = &dev_priv->display; 1058 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1059 pci_power_t opregion_target_state; 1060 1061 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1062 1063 /* We do a lot of poking in a lot of registers, make sure they work 1064 * properly. */ 1065 intel_power_domains_disable(display); 1066 drm_client_dev_suspend(dev, false); 1067 if (HAS_DISPLAY(dev_priv)) { 1068 drm_kms_helper_poll_disable(dev); 1069 intel_display_driver_disable_user_access(display); 1070 } 1071 1072 pci_save_state(pdev); 1073 1074 intel_display_driver_suspend(display); 1075 1076 intel_irq_suspend(dev_priv); 1077 intel_hpd_cancel_work(display); 1078 1079 if (HAS_DISPLAY(dev_priv)) 1080 intel_display_driver_suspend_access(display); 1081 1082 intel_encoder_suspend_all(&dev_priv->display); 1083 1084 /* Must be called before GGTT is suspended. */ 1085 intel_dpt_suspend(display); 1086 i915_ggtt_suspend(to_gt(dev_priv)->ggtt); 1087 1088 i9xx_display_sr_save(display); 1089 1090 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; 1091 intel_opregion_suspend(display, opregion_target_state); 1092 1093 dev_priv->suspend_count++; 1094 1095 intel_dmc_suspend(display); 1096 1097 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1098 1099 i915_gem_drain_freed_objects(dev_priv); 1100 1101 return 0; 1102 } 1103 1104 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) 1105 { 1106 struct drm_i915_private *dev_priv = to_i915(dev); 1107 struct intel_display *display = &dev_priv->display; 1108 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1109 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1110 struct intel_gt *gt; 1111 int ret, i; 1112 bool s2idle = !hibernation && suspend_to_idle(dev_priv); 1113 1114 disable_rpm_wakeref_asserts(rpm); 1115 1116 intel_pxp_suspend(dev_priv->pxp); 1117 1118 i915_gem_suspend_late(dev_priv); 1119 1120 for_each_gt(gt, dev_priv, i) 1121 intel_uncore_suspend(gt->uncore); 1122 1123 intel_display_power_suspend_late(display, s2idle); 1124 1125 ret = vlv_suspend_complete(dev_priv); 1126 if (ret) { 1127 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret); 1128 intel_display_power_resume_early(display); 1129 1130 goto out; 1131 } 1132 1133 pci_disable_device(pdev); 1134 /* 1135 * During hibernation on some platforms the BIOS may try to access 1136 * the device even though it's already in D3 and hang the machine. So 1137 * leave the device in D0 on those platforms and hope the BIOS will 1138 * power down the device properly. The issue was seen on multiple old 1139 * GENs with different BIOS vendors, so having an explicit blacklist 1140 * is impractical; apply the workaround on everything pre GEN6. The 1141 * platforms where the issue was seen: 1142 * Lenovo Thinkpad X301, X61s, X60, T60, X41 1143 * Fujitsu FSC S7110 1144 * Acer Aspire 1830T 1145 */ 1146 if (!(hibernation && GRAPHICS_VER(dev_priv) < 6)) 1147 pci_set_power_state(pdev, PCI_D3hot); 1148 1149 out: 1150 enable_rpm_wakeref_asserts(rpm); 1151 if (!dev_priv->uncore.user_forcewake_count) 1152 intel_runtime_pm_driver_release(rpm); 1153 1154 return ret; 1155 } 1156 1157 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915, 1158 pm_message_t state) 1159 { 1160 int error; 1161 1162 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND && 1163 state.event != PM_EVENT_FREEZE)) 1164 return -EINVAL; 1165 1166 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1167 return 0; 1168 1169 error = i915_drm_suspend(&i915->drm); 1170 if (error) 1171 return error; 1172 1173 return i915_drm_suspend_late(&i915->drm, false); 1174 } 1175 1176 static int i915_drm_resume(struct drm_device *dev) 1177 { 1178 struct drm_i915_private *dev_priv = to_i915(dev); 1179 struct intel_display *display = &dev_priv->display; 1180 struct intel_gt *gt; 1181 int ret, i; 1182 1183 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1184 1185 ret = i915_pcode_init(dev_priv); 1186 if (ret) 1187 return ret; 1188 1189 sanitize_gpu(dev_priv); 1190 1191 ret = i915_ggtt_enable_hw(dev_priv); 1192 if (ret) 1193 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n"); 1194 1195 i915_ggtt_resume(to_gt(dev_priv)->ggtt); 1196 1197 for_each_gt(gt, dev_priv, i) 1198 if (GRAPHICS_VER(gt->i915) >= 8) 1199 setup_private_pat(gt); 1200 1201 /* Must be called after GGTT is resumed. */ 1202 intel_dpt_resume(display); 1203 1204 intel_dmc_resume(display); 1205 1206 i9xx_display_sr_restore(display); 1207 1208 intel_vga_redisable(display); 1209 1210 intel_gmbus_reset(display); 1211 1212 intel_pps_unlock_regs_wa(display); 1213 1214 intel_init_pch_refclk(display); 1215 1216 /* 1217 * Interrupts have to be enabled before any batches are run. If not the 1218 * GPU will hang. i915_gem_init_hw() will initiate batches to 1219 * update/restore the context. 1220 * 1221 * drm_mode_config_reset() needs AUX interrupts. 1222 * 1223 * Modeset enabling in intel_display_driver_init_hw() also needs working 1224 * interrupts. 1225 */ 1226 intel_irq_resume(dev_priv); 1227 1228 if (HAS_DISPLAY(dev_priv)) 1229 drm_mode_config_reset(dev); 1230 1231 i915_gem_resume(dev_priv); 1232 1233 intel_display_driver_init_hw(display); 1234 1235 intel_clock_gating_init(dev_priv); 1236 1237 if (HAS_DISPLAY(dev_priv)) 1238 intel_display_driver_resume_access(display); 1239 1240 intel_hpd_init(display); 1241 1242 intel_display_driver_resume(display); 1243 1244 if (HAS_DISPLAY(dev_priv)) { 1245 intel_display_driver_enable_user_access(display); 1246 drm_kms_helper_poll_enable(dev); 1247 } 1248 intel_hpd_poll_disable(display); 1249 1250 intel_opregion_resume(display); 1251 1252 drm_client_dev_resume(dev, false); 1253 1254 intel_power_domains_enable(display); 1255 1256 intel_gvt_resume(dev_priv); 1257 1258 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1259 1260 return 0; 1261 } 1262 1263 static int i915_drm_resume_early(struct drm_device *dev) 1264 { 1265 struct drm_i915_private *dev_priv = to_i915(dev); 1266 struct intel_display *display = &dev_priv->display; 1267 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1268 struct intel_gt *gt; 1269 int ret, i; 1270 1271 /* 1272 * We have a resume ordering issue with the snd-hda driver also 1273 * requiring our device to be power up. Due to the lack of a 1274 * parent/child relationship we currently solve this with an early 1275 * resume hook. 1276 * 1277 * FIXME: This should be solved with a special hdmi sink device or 1278 * similar so that power domains can be employed. 1279 */ 1280 1281 /* 1282 * Note that we need to set the power state explicitly, since we 1283 * powered off the device during freeze and the PCI core won't power 1284 * it back up for us during thaw. Powering off the device during 1285 * freeze is not a hard requirement though, and during the 1286 * suspend/resume phases the PCI core makes sure we get here with the 1287 * device powered on. So in case we change our freeze logic and keep 1288 * the device powered we can also remove the following set power state 1289 * call. 1290 */ 1291 ret = pci_set_power_state(pdev, PCI_D0); 1292 if (ret) { 1293 drm_err(&dev_priv->drm, 1294 "failed to set PCI D0 power state (%d)\n", ret); 1295 return ret; 1296 } 1297 1298 /* 1299 * Note that pci_enable_device() first enables any parent bridge 1300 * device and only then sets the power state for this device. The 1301 * bridge enabling is a nop though, since bridge devices are resumed 1302 * first. The order of enabling power and enabling the device is 1303 * imposed by the PCI core as described above, so here we preserve the 1304 * same order for the freeze/thaw phases. 1305 * 1306 * TODO: eventually we should remove pci_disable_device() / 1307 * pci_enable_enable_device() from suspend/resume. Due to how they 1308 * depend on the device enable refcount we can't anyway depend on them 1309 * disabling/enabling the device. 1310 */ 1311 if (pci_enable_device(pdev)) 1312 return -EIO; 1313 1314 pci_set_master(pdev); 1315 1316 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1317 1318 ret = vlv_resume_prepare(dev_priv, false); 1319 if (ret) 1320 drm_err(&dev_priv->drm, 1321 "Resume prepare failed: %d, continuing anyway\n", ret); 1322 1323 for_each_gt(gt, dev_priv, i) 1324 intel_gt_resume_early(gt); 1325 1326 intel_display_power_resume_early(display); 1327 1328 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1329 1330 return ret; 1331 } 1332 1333 int i915_driver_resume_switcheroo(struct drm_i915_private *i915) 1334 { 1335 int ret; 1336 1337 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1338 return 0; 1339 1340 ret = i915_drm_resume_early(&i915->drm); 1341 if (ret) 1342 return ret; 1343 1344 return i915_drm_resume(&i915->drm); 1345 } 1346 1347 static int i915_pm_prepare(struct device *kdev) 1348 { 1349 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1350 1351 if (!i915) { 1352 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1353 return -ENODEV; 1354 } 1355 1356 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1357 return 0; 1358 1359 return i915_drm_prepare(&i915->drm); 1360 } 1361 1362 static int i915_pm_suspend(struct device *kdev) 1363 { 1364 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1365 1366 if (!i915) { 1367 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1368 return -ENODEV; 1369 } 1370 1371 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1372 return 0; 1373 1374 return i915_drm_suspend(&i915->drm); 1375 } 1376 1377 static int i915_pm_suspend_late(struct device *kdev) 1378 { 1379 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1380 1381 /* 1382 * We have a suspend ordering issue with the snd-hda driver also 1383 * requiring our device to be power up. Due to the lack of a 1384 * parent/child relationship we currently solve this with an late 1385 * suspend hook. 1386 * 1387 * FIXME: This should be solved with a special hdmi sink device or 1388 * similar so that power domains can be employed. 1389 */ 1390 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1391 return 0; 1392 1393 return i915_drm_suspend_late(&i915->drm, false); 1394 } 1395 1396 static int i915_pm_poweroff_late(struct device *kdev) 1397 { 1398 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1399 1400 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1401 return 0; 1402 1403 return i915_drm_suspend_late(&i915->drm, true); 1404 } 1405 1406 static int i915_pm_resume_early(struct device *kdev) 1407 { 1408 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1409 1410 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1411 return 0; 1412 1413 return i915_drm_resume_early(&i915->drm); 1414 } 1415 1416 static int i915_pm_resume(struct device *kdev) 1417 { 1418 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1419 1420 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1421 return 0; 1422 1423 return i915_drm_resume(&i915->drm); 1424 } 1425 1426 static void i915_pm_complete(struct device *kdev) 1427 { 1428 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1429 1430 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1431 return; 1432 1433 i915_drm_complete(&i915->drm); 1434 } 1435 1436 /* freeze: before creating the hibernation_image */ 1437 static int i915_pm_freeze(struct device *kdev) 1438 { 1439 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1440 int ret; 1441 1442 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1443 ret = i915_drm_suspend(&i915->drm); 1444 if (ret) 1445 return ret; 1446 } 1447 1448 ret = i915_gem_freeze(i915); 1449 if (ret) 1450 return ret; 1451 1452 return 0; 1453 } 1454 1455 static int i915_pm_freeze_late(struct device *kdev) 1456 { 1457 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1458 int ret; 1459 1460 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1461 ret = i915_drm_suspend_late(&i915->drm, true); 1462 if (ret) 1463 return ret; 1464 } 1465 1466 ret = i915_gem_freeze_late(i915); 1467 if (ret) 1468 return ret; 1469 1470 return 0; 1471 } 1472 1473 /* thaw: called after creating the hibernation image, but before turning off. */ 1474 static int i915_pm_thaw_early(struct device *kdev) 1475 { 1476 return i915_pm_resume_early(kdev); 1477 } 1478 1479 static int i915_pm_thaw(struct device *kdev) 1480 { 1481 return i915_pm_resume(kdev); 1482 } 1483 1484 /* restore: called after loading the hibernation image. */ 1485 static int i915_pm_restore_early(struct device *kdev) 1486 { 1487 return i915_pm_resume_early(kdev); 1488 } 1489 1490 static int i915_pm_restore(struct device *kdev) 1491 { 1492 return i915_pm_resume(kdev); 1493 } 1494 1495 static int intel_runtime_suspend(struct device *kdev) 1496 { 1497 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1498 struct intel_display *display = &dev_priv->display; 1499 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1500 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1501 struct pci_dev *root_pdev; 1502 struct intel_gt *gt; 1503 int ret, i; 1504 1505 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1506 return -ENODEV; 1507 1508 drm_dbg(&dev_priv->drm, "Suspending device\n"); 1509 1510 disable_rpm_wakeref_asserts(rpm); 1511 1512 /* 1513 * We are safe here against re-faults, since the fault handler takes 1514 * an RPM reference. 1515 */ 1516 i915_gem_runtime_suspend(dev_priv); 1517 1518 intel_pxp_runtime_suspend(dev_priv->pxp); 1519 1520 for_each_gt(gt, dev_priv, i) 1521 intel_gt_runtime_suspend(gt); 1522 1523 intel_irq_suspend(dev_priv); 1524 1525 for_each_gt(gt, dev_priv, i) 1526 intel_uncore_suspend(gt->uncore); 1527 1528 intel_display_power_suspend(display); 1529 1530 ret = vlv_suspend_complete(dev_priv); 1531 if (ret) { 1532 drm_err(&dev_priv->drm, 1533 "Runtime suspend failed, disabling it (%d)\n", ret); 1534 intel_uncore_runtime_resume(&dev_priv->uncore); 1535 1536 intel_irq_resume(dev_priv); 1537 1538 for_each_gt(gt, dev_priv, i) 1539 intel_gt_runtime_resume(gt); 1540 1541 enable_rpm_wakeref_asserts(rpm); 1542 1543 return ret; 1544 } 1545 1546 enable_rpm_wakeref_asserts(rpm); 1547 intel_runtime_pm_driver_release(rpm); 1548 1549 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore)) 1550 drm_err(&dev_priv->drm, 1551 "Unclaimed access detected prior to suspending\n"); 1552 1553 /* 1554 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX 1555 * This should be totally removed when we handle the pci states properly 1556 * on runtime PM. 1557 */ 1558 root_pdev = pcie_find_root_port(pdev); 1559 if (root_pdev) 1560 pci_d3cold_disable(root_pdev); 1561 1562 /* 1563 * FIXME: We really should find a document that references the arguments 1564 * used below! 1565 */ 1566 if (IS_BROADWELL(dev_priv)) { 1567 /* 1568 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop 1569 * being detected, and the call we do at intel_runtime_resume() 1570 * won't be able to restore them. Since PCI_D3hot matches the 1571 * actual specification and appears to be working, use it. 1572 */ 1573 intel_opregion_notify_adapter(display, PCI_D3hot); 1574 } else { 1575 /* 1576 * current versions of firmware which depend on this opregion 1577 * notification have repurposed the D1 definition to mean 1578 * "runtime suspended" vs. what you would normally expect (D3) 1579 * to distinguish it from notifications that might be sent via 1580 * the suspend path. 1581 */ 1582 intel_opregion_notify_adapter(display, PCI_D1); 1583 } 1584 1585 assert_forcewakes_inactive(&dev_priv->uncore); 1586 1587 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) 1588 intel_hpd_poll_enable(display); 1589 1590 drm_dbg(&dev_priv->drm, "Device suspended\n"); 1591 return 0; 1592 } 1593 1594 static int intel_runtime_resume(struct device *kdev) 1595 { 1596 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1597 struct intel_display *display = &dev_priv->display; 1598 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1599 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1600 struct pci_dev *root_pdev; 1601 struct intel_gt *gt; 1602 int ret, i; 1603 1604 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1605 return -ENODEV; 1606 1607 drm_dbg(&dev_priv->drm, "Resuming device\n"); 1608 1609 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count)); 1610 disable_rpm_wakeref_asserts(rpm); 1611 1612 intel_opregion_notify_adapter(display, PCI_D0); 1613 1614 root_pdev = pcie_find_root_port(pdev); 1615 if (root_pdev) 1616 pci_d3cold_enable(root_pdev); 1617 1618 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore)) 1619 drm_dbg(&dev_priv->drm, 1620 "Unclaimed access during suspend, bios?\n"); 1621 1622 intel_display_power_resume(display); 1623 1624 ret = vlv_resume_prepare(dev_priv, true); 1625 1626 for_each_gt(gt, dev_priv, i) 1627 intel_uncore_runtime_resume(gt->uncore); 1628 1629 intel_irq_resume(dev_priv); 1630 1631 /* 1632 * No point of rolling back things in case of an error, as the best 1633 * we can do is to hope that things will still work (and disable RPM). 1634 */ 1635 for_each_gt(gt, dev_priv, i) 1636 intel_gt_runtime_resume(gt); 1637 1638 intel_pxp_runtime_resume(dev_priv->pxp); 1639 1640 /* 1641 * On VLV/CHV display interrupts are part of the display 1642 * power well, so hpd is reinitialized from there. For 1643 * everyone else do it here. 1644 */ 1645 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 1646 intel_hpd_init(display); 1647 intel_hpd_poll_disable(display); 1648 } 1649 1650 skl_watermark_ipc_update(display); 1651 1652 enable_rpm_wakeref_asserts(rpm); 1653 1654 if (ret) 1655 drm_err(&dev_priv->drm, 1656 "Runtime resume failed, disabling it (%d)\n", ret); 1657 else 1658 drm_dbg(&dev_priv->drm, "Device resumed\n"); 1659 1660 return ret; 1661 } 1662 1663 const struct dev_pm_ops i915_pm_ops = { 1664 /* 1665 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, 1666 * PMSG_RESUME] 1667 */ 1668 .prepare = i915_pm_prepare, 1669 .suspend = i915_pm_suspend, 1670 .suspend_late = i915_pm_suspend_late, 1671 .resume_early = i915_pm_resume_early, 1672 .resume = i915_pm_resume, 1673 .complete = i915_pm_complete, 1674 1675 /* 1676 * S4 event handlers 1677 * @freeze, @freeze_late : called (1) before creating the 1678 * hibernation image [PMSG_FREEZE] and 1679 * (2) after rebooting, before restoring 1680 * the image [PMSG_QUIESCE] 1681 * @thaw, @thaw_early : called (1) after creating the hibernation 1682 * image, before writing it [PMSG_THAW] 1683 * and (2) after failing to create or 1684 * restore the image [PMSG_RECOVER] 1685 * @poweroff, @poweroff_late: called after writing the hibernation 1686 * image, before rebooting [PMSG_HIBERNATE] 1687 * @restore, @restore_early : called after rebooting and restoring the 1688 * hibernation image [PMSG_RESTORE] 1689 */ 1690 .freeze = i915_pm_freeze, 1691 .freeze_late = i915_pm_freeze_late, 1692 .thaw_early = i915_pm_thaw_early, 1693 .thaw = i915_pm_thaw, 1694 .poweroff = i915_pm_suspend, 1695 .poweroff_late = i915_pm_poweroff_late, 1696 .restore_early = i915_pm_restore_early, 1697 .restore = i915_pm_restore, 1698 1699 /* S0ix (via runtime suspend) event handlers */ 1700 .runtime_suspend = intel_runtime_suspend, 1701 .runtime_resume = intel_runtime_resume, 1702 }; 1703 1704 static const struct file_operations i915_driver_fops = { 1705 .owner = THIS_MODULE, 1706 .open = drm_open, 1707 .release = drm_release_noglobal, 1708 .unlocked_ioctl = drm_ioctl, 1709 .mmap = i915_gem_mmap, 1710 .poll = drm_poll, 1711 .read = drm_read, 1712 .compat_ioctl = i915_ioc32_compat_ioctl, 1713 .llseek = noop_llseek, 1714 #ifdef CONFIG_PROC_FS 1715 .show_fdinfo = drm_show_fdinfo, 1716 #endif 1717 .fop_flags = FOP_UNSIGNED_OFFSET, 1718 }; 1719 1720 static int 1721 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, 1722 struct drm_file *file) 1723 { 1724 return -ENODEV; 1725 } 1726 1727 static const struct drm_ioctl_desc i915_ioctls[] = { 1728 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1729 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), 1730 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), 1731 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), 1732 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), 1733 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), 1734 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW), 1735 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1736 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), 1737 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), 1738 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1739 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), 1740 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1741 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1742 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), 1743 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), 1744 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1745 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1746 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH), 1747 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW), 1748 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1749 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1750 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW), 1751 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), 1752 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), 1753 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW), 1754 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1755 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1756 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), 1757 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW), 1758 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), 1759 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), 1760 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), 1761 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW), 1762 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), 1763 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), 1764 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW), 1765 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW), 1766 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), 1767 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_crtc_get_pipe_from_crtc_id_ioctl, 0), 1768 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), 1769 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER), 1770 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER), 1771 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER), 1772 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER), 1773 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW), 1774 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), 1775 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), 1776 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), 1777 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW), 1778 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), 1779 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), 1780 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), 1781 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), 1782 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW), 1783 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW), 1784 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW), 1785 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW), 1786 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW), 1787 }; 1788 1789 /* 1790 * Interface history: 1791 * 1792 * 1.1: Original. 1793 * 1.2: Add Power Management 1794 * 1.3: Add vblank support 1795 * 1.4: Fix cmdbuffer path, add heap destroy 1796 * 1.5: Add vblank pipe configuration 1797 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 1798 * - Support vertical blank on secondary display pipe 1799 */ 1800 #define DRIVER_MAJOR 1 1801 #define DRIVER_MINOR 6 1802 #define DRIVER_PATCHLEVEL 0 1803 1804 static const struct drm_driver i915_drm_driver = { 1805 /* Don't use MTRRs here; the Xserver or userspace app should 1806 * deal with them for Intel hardware. 1807 */ 1808 .driver_features = 1809 DRIVER_GEM | 1810 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ | 1811 DRIVER_SYNCOBJ_TIMELINE, 1812 .release = i915_driver_release, 1813 .open = i915_driver_open, 1814 .postclose = i915_driver_postclose, 1815 .show_fdinfo = PTR_IF(IS_ENABLED(CONFIG_PROC_FS), i915_drm_client_fdinfo), 1816 1817 .gem_prime_import = i915_gem_prime_import, 1818 1819 .dumb_create = i915_gem_dumb_create, 1820 .dumb_map_offset = i915_gem_dumb_mmap_offset, 1821 1822 INTEL_FBDEV_DRIVER_OPS, 1823 1824 .ioctls = i915_ioctls, 1825 .num_ioctls = ARRAY_SIZE(i915_ioctls), 1826 .fops = &i915_driver_fops, 1827 .name = DRIVER_NAME, 1828 .desc = DRIVER_DESC, 1829 .major = DRIVER_MAJOR, 1830 .minor = DRIVER_MINOR, 1831 .patchlevel = DRIVER_PATCHLEVEL, 1832 }; 1833