xref: /linux/drivers/gpu/drm/i915/i915_driver.c (revision 88872790923e2d80edf29a00b4e440f1473fa8f5)
1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2  */
3 /*
4  *
5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6  * All Rights Reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the
10  * "Software"), to deal in the Software without restriction, including
11  * without limitation the rights to use, copy, modify, merge, publish,
12  * distribute, sub license, and/or sell copies of the Software, and to
13  * permit persons to whom the Software is furnished to do so, subject to
14  * the following conditions:
15  *
16  * The above copyright notice and this permission notice (including the
17  * next paragraph) shall be included in all copies or substantial portions
18  * of the Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27  *
28  */
29 
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/module.h>
33 #include <linux/oom.h>
34 #include <linux/pci.h>
35 #include <linux/pm.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/slab.h>
38 #include <linux/string_helpers.h>
39 #include <linux/vga_switcheroo.h>
40 #include <linux/vt.h>
41 
42 #include <drm/drm_aperture.h>
43 #include <drm/drm_atomic_helper.h>
44 #include <drm/drm_ioctl.h>
45 #include <drm/drm_managed.h>
46 #include <drm/drm_probe_helper.h>
47 
48 #include "display/intel_acpi.h"
49 #include "display/intel_bw.h"
50 #include "display/intel_cdclk.h"
51 #include "display/intel_display_driver.h"
52 #include "display/intel_display_types.h"
53 #include "display/intel_dmc.h"
54 #include "display/intel_dp.h"
55 #include "display/intel_dpt.h"
56 #include "display/intel_fbdev.h"
57 #include "display/intel_hotplug.h"
58 #include "display/intel_overlay.h"
59 #include "display/intel_pch_refclk.h"
60 #include "display/intel_pipe_crc.h"
61 #include "display/intel_pps.h"
62 #include "display/intel_sprite.h"
63 #include "display/intel_vga.h"
64 #include "display/skl_watermark.h"
65 
66 #include "gem/i915_gem_context.h"
67 #include "gem/i915_gem_create.h"
68 #include "gem/i915_gem_dmabuf.h"
69 #include "gem/i915_gem_ioctls.h"
70 #include "gem/i915_gem_mman.h"
71 #include "gem/i915_gem_pm.h"
72 #include "gt/intel_gt.h"
73 #include "gt/intel_gt_pm.h"
74 #include "gt/intel_rc6.h"
75 
76 #include "pxp/intel_pxp.h"
77 #include "pxp/intel_pxp_debugfs.h"
78 #include "pxp/intel_pxp_pm.h"
79 
80 #include "soc/intel_dram.h"
81 #include "soc/intel_gmch.h"
82 
83 #include "i915_debugfs.h"
84 #include "i915_driver.h"
85 #include "i915_drm_client.h"
86 #include "i915_drv.h"
87 #include "i915_file_private.h"
88 #include "i915_getparam.h"
89 #include "i915_hwmon.h"
90 #include "i915_ioc32.h"
91 #include "i915_ioctl.h"
92 #include "i915_irq.h"
93 #include "i915_memcpy.h"
94 #include "i915_perf.h"
95 #include "i915_query.h"
96 #include "i915_suspend.h"
97 #include "i915_switcheroo.h"
98 #include "i915_sysfs.h"
99 #include "i915_utils.h"
100 #include "i915_vgpu.h"
101 #include "intel_clock_gating.h"
102 #include "intel_gvt.h"
103 #include "intel_memory_region.h"
104 #include "intel_pci_config.h"
105 #include "intel_pcode.h"
106 #include "intel_region_ttm.h"
107 #include "vlv_suspend.h"
108 
109 static const struct drm_driver i915_drm_driver;
110 
111 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
112 {
113 	/*
114 	 * The i915 workqueue is primarily used for batched retirement of
115 	 * requests (and thus managing bo) once the task has been completed
116 	 * by the GPU. i915_retire_requests() is called directly when we
117 	 * need high-priority retirement, such as waiting for an explicit
118 	 * bo.
119 	 *
120 	 * It is also used for periodic low-priority events, such as
121 	 * idle-timers and recording error state.
122 	 *
123 	 * All tasks on the workqueue are expected to acquire the dev mutex
124 	 * so there is no point in running more than one instance of the
125 	 * workqueue at any time.  Use an ordered one.
126 	 */
127 	dev_priv->wq = alloc_ordered_workqueue("i915", 0);
128 	if (dev_priv->wq == NULL)
129 		goto out_err;
130 
131 	dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
132 	if (dev_priv->display.hotplug.dp_wq == NULL)
133 		goto out_free_wq;
134 
135 	/*
136 	 * The unordered i915 workqueue should be used for all work
137 	 * scheduling that do not require running in order, which used
138 	 * to be scheduled on the system_wq before moving to a driver
139 	 * instance due deprecation of flush_scheduled_work().
140 	 */
141 	dev_priv->unordered_wq = alloc_workqueue("i915-unordered", 0, 0);
142 	if (dev_priv->unordered_wq == NULL)
143 		goto out_free_dp_wq;
144 
145 	return 0;
146 
147 out_free_dp_wq:
148 	destroy_workqueue(dev_priv->display.hotplug.dp_wq);
149 out_free_wq:
150 	destroy_workqueue(dev_priv->wq);
151 out_err:
152 	drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
153 
154 	return -ENOMEM;
155 }
156 
157 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
158 {
159 	destroy_workqueue(dev_priv->unordered_wq);
160 	destroy_workqueue(dev_priv->display.hotplug.dp_wq);
161 	destroy_workqueue(dev_priv->wq);
162 }
163 
164 /*
165  * We don't keep the workarounds for pre-production hardware, so we expect our
166  * driver to fail on these machines in one way or another. A little warning on
167  * dmesg may help both the user and the bug triagers.
168  *
169  * Our policy for removing pre-production workarounds is to keep the
170  * current gen workarounds as a guide to the bring-up of the next gen
171  * (workarounds have a habit of persisting!). Anything older than that
172  * should be removed along with the complications they introduce.
173  */
174 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
175 {
176 	bool pre = false;
177 
178 	pre |= IS_HASWELL_EARLY_SDV(dev_priv);
179 	pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
180 	pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
181 	pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
182 	pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
183 	pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
184 	pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
185 	pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
186 	pre |= IS_DG2_G10(dev_priv) && INTEL_REVID(dev_priv) < 0x8;
187 	pre |= IS_DG2_G11(dev_priv) && INTEL_REVID(dev_priv) < 0x5;
188 	pre |= IS_DG2_G12(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
189 
190 	if (pre) {
191 		drm_err(&dev_priv->drm, "This is a pre-production stepping. "
192 			  "It may not be fully functional.\n");
193 		add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
194 	}
195 }
196 
197 static void sanitize_gpu(struct drm_i915_private *i915)
198 {
199 	if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) {
200 		struct intel_gt *gt;
201 		unsigned int i;
202 
203 		for_each_gt(gt, i915, i)
204 			__intel_gt_reset(gt, ALL_ENGINES);
205 	}
206 }
207 
208 /**
209  * i915_driver_early_probe - setup state not requiring device access
210  * @dev_priv: device private
211  *
212  * Initialize everything that is a "SW-only" state, that is state not
213  * requiring accessing the device or exposing the driver via kernel internal
214  * or userspace interfaces. Example steps belonging here: lock initialization,
215  * system memory allocation, setting up device specific attributes and
216  * function hooks not requiring accessing the device.
217  */
218 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
219 {
220 	int ret = 0;
221 
222 	if (i915_inject_probe_failure(dev_priv))
223 		return -ENODEV;
224 
225 	intel_device_info_runtime_init_early(dev_priv);
226 
227 	intel_step_init(dev_priv);
228 
229 	intel_uncore_mmio_debug_init_early(dev_priv);
230 
231 	spin_lock_init(&dev_priv->irq_lock);
232 	spin_lock_init(&dev_priv->gpu_error.lock);
233 	mutex_init(&dev_priv->display.backlight.lock);
234 
235 	mutex_init(&dev_priv->sb_lock);
236 	cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
237 
238 	mutex_init(&dev_priv->display.audio.mutex);
239 	mutex_init(&dev_priv->display.wm.wm_mutex);
240 	mutex_init(&dev_priv->display.pps.mutex);
241 	mutex_init(&dev_priv->display.hdcp.hdcp_mutex);
242 
243 	i915_memcpy_init_early(dev_priv);
244 	intel_runtime_pm_init_early(&dev_priv->runtime_pm);
245 
246 	ret = i915_workqueues_init(dev_priv);
247 	if (ret < 0)
248 		return ret;
249 
250 	ret = vlv_suspend_init(dev_priv);
251 	if (ret < 0)
252 		goto err_workqueues;
253 
254 	ret = intel_region_ttm_device_init(dev_priv);
255 	if (ret)
256 		goto err_ttm;
257 
258 	ret = intel_root_gt_init_early(dev_priv);
259 	if (ret < 0)
260 		goto err_rootgt;
261 
262 	i915_gem_init_early(dev_priv);
263 
264 	/* This must be called before any calls to HAS_PCH_* */
265 	intel_detect_pch(dev_priv);
266 
267 	intel_irq_init(dev_priv);
268 	intel_display_driver_early_probe(dev_priv);
269 	intel_clock_gating_hooks_init(dev_priv);
270 
271 	intel_detect_preproduction_hw(dev_priv);
272 
273 	return 0;
274 
275 err_rootgt:
276 	intel_region_ttm_device_fini(dev_priv);
277 err_ttm:
278 	vlv_suspend_cleanup(dev_priv);
279 err_workqueues:
280 	i915_workqueues_cleanup(dev_priv);
281 	return ret;
282 }
283 
284 /**
285  * i915_driver_late_release - cleanup the setup done in
286  *			       i915_driver_early_probe()
287  * @dev_priv: device private
288  */
289 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
290 {
291 	intel_irq_fini(dev_priv);
292 	intel_power_domains_cleanup(dev_priv);
293 	i915_gem_cleanup_early(dev_priv);
294 	intel_gt_driver_late_release_all(dev_priv);
295 	intel_region_ttm_device_fini(dev_priv);
296 	vlv_suspend_cleanup(dev_priv);
297 	i915_workqueues_cleanup(dev_priv);
298 
299 	cpu_latency_qos_remove_request(&dev_priv->sb_qos);
300 	mutex_destroy(&dev_priv->sb_lock);
301 
302 	i915_params_free(&dev_priv->params);
303 }
304 
305 /**
306  * i915_driver_mmio_probe - setup device MMIO
307  * @dev_priv: device private
308  *
309  * Setup minimal device state necessary for MMIO accesses later in the
310  * initialization sequence. The setup here should avoid any other device-wide
311  * side effects or exposing the driver via kernel internal or user space
312  * interfaces.
313  */
314 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
315 {
316 	struct intel_gt *gt;
317 	int ret, i;
318 
319 	if (i915_inject_probe_failure(dev_priv))
320 		return -ENODEV;
321 
322 	ret = intel_gmch_bridge_setup(dev_priv);
323 	if (ret < 0)
324 		return ret;
325 
326 	for_each_gt(gt, dev_priv, i) {
327 		ret = intel_uncore_init_mmio(gt->uncore);
328 		if (ret)
329 			return ret;
330 
331 		ret = drmm_add_action_or_reset(&dev_priv->drm,
332 					       intel_uncore_fini_mmio,
333 					       gt->uncore);
334 		if (ret)
335 			return ret;
336 	}
337 
338 	/* Try to make sure MCHBAR is enabled before poking at it */
339 	intel_gmch_bar_setup(dev_priv);
340 	intel_device_info_runtime_init(dev_priv);
341 
342 	for_each_gt(gt, dev_priv, i) {
343 		ret = intel_gt_init_mmio(gt);
344 		if (ret)
345 			goto err_uncore;
346 	}
347 
348 	/* As early as possible, scrub existing GPU state before clobbering */
349 	sanitize_gpu(dev_priv);
350 
351 	return 0;
352 
353 err_uncore:
354 	intel_gmch_bar_teardown(dev_priv);
355 
356 	return ret;
357 }
358 
359 /**
360  * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
361  * @dev_priv: device private
362  */
363 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
364 {
365 	intel_gmch_bar_teardown(dev_priv);
366 }
367 
368 /**
369  * i915_set_dma_info - set all relevant PCI dma info as configured for the
370  * platform
371  * @i915: valid i915 instance
372  *
373  * Set the dma max segment size, device and coherent masks.  The dma mask set
374  * needs to occur before i915_ggtt_probe_hw.
375  *
376  * A couple of platforms have special needs.  Address them as well.
377  *
378  */
379 static int i915_set_dma_info(struct drm_i915_private *i915)
380 {
381 	unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
382 	int ret;
383 
384 	GEM_BUG_ON(!mask_size);
385 
386 	/*
387 	 * We don't have a max segment size, so set it to the max so sg's
388 	 * debugging layer doesn't complain
389 	 */
390 	dma_set_max_seg_size(i915->drm.dev, UINT_MAX);
391 
392 	ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
393 	if (ret)
394 		goto mask_err;
395 
396 	/* overlay on gen2 is broken and can't address above 1G */
397 	if (GRAPHICS_VER(i915) == 2)
398 		mask_size = 30;
399 
400 	/*
401 	 * 965GM sometimes incorrectly writes to hardware status page (HWS)
402 	 * using 32bit addressing, overwriting memory if HWS is located
403 	 * above 4GB.
404 	 *
405 	 * The documentation also mentions an issue with undefined
406 	 * behaviour if any general state is accessed within a page above 4GB,
407 	 * which also needs to be handled carefully.
408 	 */
409 	if (IS_I965G(i915) || IS_I965GM(i915))
410 		mask_size = 32;
411 
412 	ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
413 	if (ret)
414 		goto mask_err;
415 
416 	return 0;
417 
418 mask_err:
419 	drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
420 	return ret;
421 }
422 
423 static int i915_pcode_init(struct drm_i915_private *i915)
424 {
425 	struct intel_gt *gt;
426 	int id, ret;
427 
428 	for_each_gt(gt, i915, id) {
429 		ret = intel_pcode_init(gt->uncore);
430 		if (ret) {
431 			drm_err(&gt->i915->drm, "gt%d: intel_pcode_init failed %d\n", id, ret);
432 			return ret;
433 		}
434 	}
435 
436 	return 0;
437 }
438 
439 /**
440  * i915_driver_hw_probe - setup state requiring device access
441  * @dev_priv: device private
442  *
443  * Setup state that requires accessing the device, but doesn't require
444  * exposing the driver via kernel internal or userspace interfaces.
445  */
446 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
447 {
448 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
449 	int ret;
450 
451 	if (i915_inject_probe_failure(dev_priv))
452 		return -ENODEV;
453 
454 	if (HAS_PPGTT(dev_priv)) {
455 		if (intel_vgpu_active(dev_priv) &&
456 		    !intel_vgpu_has_full_ppgtt(dev_priv)) {
457 			i915_report_error(dev_priv,
458 					  "incompatible vGPU found, support for isolated ppGTT required\n");
459 			return -ENXIO;
460 		}
461 	}
462 
463 	if (HAS_EXECLISTS(dev_priv)) {
464 		/*
465 		 * Older GVT emulation depends upon intercepting CSB mmio,
466 		 * which we no longer use, preferring to use the HWSP cache
467 		 * instead.
468 		 */
469 		if (intel_vgpu_active(dev_priv) &&
470 		    !intel_vgpu_has_hwsp_emulation(dev_priv)) {
471 			i915_report_error(dev_priv,
472 					  "old vGPU host found, support for HWSP emulation required\n");
473 			return -ENXIO;
474 		}
475 	}
476 
477 	/* needs to be done before ggtt probe */
478 	intel_dram_edram_detect(dev_priv);
479 
480 	ret = i915_set_dma_info(dev_priv);
481 	if (ret)
482 		return ret;
483 
484 	ret = i915_perf_init(dev_priv);
485 	if (ret)
486 		return ret;
487 
488 	ret = i915_ggtt_probe_hw(dev_priv);
489 	if (ret)
490 		goto err_perf;
491 
492 	ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver);
493 	if (ret)
494 		goto err_ggtt;
495 
496 	ret = i915_ggtt_init_hw(dev_priv);
497 	if (ret)
498 		goto err_ggtt;
499 
500 	/*
501 	 * Make sure we probe lmem before we probe stolen-lmem. The BAR size
502 	 * might be different due to bar resizing.
503 	 */
504 	ret = intel_gt_tiles_init(dev_priv);
505 	if (ret)
506 		goto err_ggtt;
507 
508 	ret = intel_memory_regions_hw_probe(dev_priv);
509 	if (ret)
510 		goto err_ggtt;
511 
512 	ret = i915_ggtt_enable_hw(dev_priv);
513 	if (ret) {
514 		drm_err(&dev_priv->drm, "failed to enable GGTT\n");
515 		goto err_mem_regions;
516 	}
517 
518 	pci_set_master(pdev);
519 
520 	/* On the 945G/GM, the chipset reports the MSI capability on the
521 	 * integrated graphics even though the support isn't actually there
522 	 * according to the published specs.  It doesn't appear to function
523 	 * correctly in testing on 945G.
524 	 * This may be a side effect of MSI having been made available for PEG
525 	 * and the registers being closely associated.
526 	 *
527 	 * According to chipset errata, on the 965GM, MSI interrupts may
528 	 * be lost or delayed, and was defeatured. MSI interrupts seem to
529 	 * get lost on g4x as well, and interrupt delivery seems to stay
530 	 * properly dead afterwards. So we'll just disable them for all
531 	 * pre-gen5 chipsets.
532 	 *
533 	 * dp aux and gmbus irq on gen4 seems to be able to generate legacy
534 	 * interrupts even when in MSI mode. This results in spurious
535 	 * interrupt warnings if the legacy irq no. is shared with another
536 	 * device. The kernel then disables that interrupt source and so
537 	 * prevents the other device from working properly.
538 	 */
539 	if (GRAPHICS_VER(dev_priv) >= 5) {
540 		if (pci_enable_msi(pdev) < 0)
541 			drm_dbg(&dev_priv->drm, "can't enable MSI");
542 	}
543 
544 	ret = intel_gvt_init(dev_priv);
545 	if (ret)
546 		goto err_msi;
547 
548 	intel_opregion_setup(dev_priv);
549 
550 	ret = i915_pcode_init(dev_priv);
551 	if (ret)
552 		goto err_opregion;
553 
554 	/*
555 	 * Fill the dram structure to get the system dram info. This will be
556 	 * used for memory latency calculation.
557 	 */
558 	intel_dram_detect(dev_priv);
559 
560 	intel_bw_init_hw(dev_priv);
561 
562 	return 0;
563 
564 err_opregion:
565 	intel_opregion_cleanup(dev_priv);
566 err_msi:
567 	if (pdev->msi_enabled)
568 		pci_disable_msi(pdev);
569 err_mem_regions:
570 	intel_memory_regions_driver_release(dev_priv);
571 err_ggtt:
572 	i915_ggtt_driver_release(dev_priv);
573 	i915_gem_drain_freed_objects(dev_priv);
574 	i915_ggtt_driver_late_release(dev_priv);
575 err_perf:
576 	i915_perf_fini(dev_priv);
577 	return ret;
578 }
579 
580 /**
581  * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
582  * @dev_priv: device private
583  */
584 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
585 {
586 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
587 
588 	i915_perf_fini(dev_priv);
589 
590 	intel_opregion_cleanup(dev_priv);
591 
592 	if (pdev->msi_enabled)
593 		pci_disable_msi(pdev);
594 }
595 
596 /**
597  * i915_driver_register - register the driver with the rest of the system
598  * @dev_priv: device private
599  *
600  * Perform any steps necessary to make the driver available via kernel
601  * internal or userspace interfaces.
602  */
603 static void i915_driver_register(struct drm_i915_private *dev_priv)
604 {
605 	struct intel_gt *gt;
606 	unsigned int i;
607 
608 	i915_gem_driver_register(dev_priv);
609 	i915_pmu_register(dev_priv);
610 
611 	intel_vgpu_register(dev_priv);
612 
613 	/* Reveal our presence to userspace */
614 	if (drm_dev_register(&dev_priv->drm, 0)) {
615 		drm_err(&dev_priv->drm,
616 			"Failed to register driver for userspace access!\n");
617 		return;
618 	}
619 
620 	i915_debugfs_register(dev_priv);
621 	i915_setup_sysfs(dev_priv);
622 
623 	/* Depends on sysfs having been initialized */
624 	i915_perf_register(dev_priv);
625 
626 	for_each_gt(gt, dev_priv, i)
627 		intel_gt_driver_register(gt);
628 
629 	intel_pxp_debugfs_register(dev_priv->pxp);
630 
631 	i915_hwmon_register(dev_priv);
632 
633 	intel_display_driver_register(dev_priv);
634 
635 	intel_power_domains_enable(dev_priv);
636 	intel_runtime_pm_enable(&dev_priv->runtime_pm);
637 
638 	intel_register_dsm_handler();
639 
640 	if (i915_switcheroo_register(dev_priv))
641 		drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
642 }
643 
644 /**
645  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
646  * @dev_priv: device private
647  */
648 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
649 {
650 	struct intel_gt *gt;
651 	unsigned int i;
652 
653 	i915_switcheroo_unregister(dev_priv);
654 
655 	intel_unregister_dsm_handler();
656 
657 	intel_runtime_pm_disable(&dev_priv->runtime_pm);
658 	intel_power_domains_disable(dev_priv);
659 
660 	intel_display_driver_unregister(dev_priv);
661 
662 	intel_pxp_fini(dev_priv);
663 
664 	for_each_gt(gt, dev_priv, i)
665 		intel_gt_driver_unregister(gt);
666 
667 	i915_hwmon_unregister(dev_priv);
668 
669 	i915_perf_unregister(dev_priv);
670 	i915_pmu_unregister(dev_priv);
671 
672 	i915_teardown_sysfs(dev_priv);
673 	drm_dev_unplug(&dev_priv->drm);
674 
675 	i915_gem_driver_unregister(dev_priv);
676 }
677 
678 void
679 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p)
680 {
681 	drm_printf(p, "iommu: %s\n",
682 		   str_enabled_disabled(i915_vtd_active(i915)));
683 }
684 
685 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
686 {
687 	if (drm_debug_enabled(DRM_UT_DRIVER)) {
688 		struct drm_printer p = drm_debug_printer("i915 device info:");
689 		struct intel_gt *gt;
690 		unsigned int i;
691 
692 		drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
693 			   INTEL_DEVID(dev_priv),
694 			   INTEL_REVID(dev_priv),
695 			   intel_platform_name(INTEL_INFO(dev_priv)->platform),
696 			   intel_subplatform(RUNTIME_INFO(dev_priv),
697 					     INTEL_INFO(dev_priv)->platform),
698 			   GRAPHICS_VER(dev_priv));
699 
700 		intel_device_info_print(INTEL_INFO(dev_priv),
701 					RUNTIME_INFO(dev_priv), &p);
702 		i915_print_iommu_status(dev_priv, &p);
703 		for_each_gt(gt, dev_priv, i)
704 			intel_gt_info_print(&gt->info, &p);
705 	}
706 
707 	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
708 		drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
709 	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
710 		drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
711 	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
712 		drm_info(&dev_priv->drm,
713 			 "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
714 }
715 
716 static struct drm_i915_private *
717 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
718 {
719 	const struct intel_device_info *match_info =
720 		(struct intel_device_info *)ent->driver_data;
721 	struct drm_i915_private *i915;
722 
723 	i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver,
724 				  struct drm_i915_private, drm);
725 	if (IS_ERR(i915))
726 		return i915;
727 
728 	pci_set_drvdata(pdev, i915);
729 
730 	/* Device parameters start as a copy of module parameters. */
731 	i915_params_copy(&i915->params, &i915_modparams);
732 
733 	/* Set up device info and initial runtime info. */
734 	intel_device_info_driver_create(i915, pdev->device, match_info);
735 
736 	intel_display_device_probe(i915);
737 
738 	return i915;
739 }
740 
741 /**
742  * i915_driver_probe - setup chip and create an initial config
743  * @pdev: PCI device
744  * @ent: matching PCI ID entry
745  *
746  * The driver probe routine has to do several things:
747  *   - drive output discovery via intel_display_driver_probe()
748  *   - initialize the memory manager
749  *   - allocate initial config memory
750  *   - setup the DRM framebuffer with the allocated memory
751  */
752 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
753 {
754 	struct drm_i915_private *i915;
755 	int ret;
756 
757 	ret = pci_enable_device(pdev);
758 	if (ret) {
759 		pr_err("Failed to enable graphics device: %pe\n", ERR_PTR(ret));
760 		return ret;
761 	}
762 
763 	i915 = i915_driver_create(pdev, ent);
764 	if (IS_ERR(i915)) {
765 		pci_disable_device(pdev);
766 		return PTR_ERR(i915);
767 	}
768 
769 	ret = i915_driver_early_probe(i915);
770 	if (ret < 0)
771 		goto out_pci_disable;
772 
773 	disable_rpm_wakeref_asserts(&i915->runtime_pm);
774 
775 	intel_vgpu_detect(i915);
776 
777 	ret = intel_gt_probe_all(i915);
778 	if (ret < 0)
779 		goto out_runtime_pm_put;
780 
781 	ret = i915_driver_mmio_probe(i915);
782 	if (ret < 0)
783 		goto out_tiles_cleanup;
784 
785 	ret = i915_driver_hw_probe(i915);
786 	if (ret < 0)
787 		goto out_cleanup_mmio;
788 
789 	ret = intel_display_driver_probe_noirq(i915);
790 	if (ret < 0)
791 		goto out_cleanup_hw;
792 
793 	ret = intel_irq_install(i915);
794 	if (ret)
795 		goto out_cleanup_modeset;
796 
797 	ret = intel_display_driver_probe_nogem(i915);
798 	if (ret)
799 		goto out_cleanup_irq;
800 
801 	ret = i915_gem_init(i915);
802 	if (ret)
803 		goto out_cleanup_modeset2;
804 
805 	intel_pxp_init(i915);
806 
807 	ret = intel_display_driver_probe(i915);
808 	if (ret)
809 		goto out_cleanup_gem;
810 
811 	i915_driver_register(i915);
812 
813 	enable_rpm_wakeref_asserts(&i915->runtime_pm);
814 
815 	i915_welcome_messages(i915);
816 
817 	i915->do_release = true;
818 
819 	return 0;
820 
821 out_cleanup_gem:
822 	i915_gem_suspend(i915);
823 	i915_gem_driver_remove(i915);
824 	i915_gem_driver_release(i915);
825 out_cleanup_modeset2:
826 	/* FIXME clean up the error path */
827 	intel_display_driver_remove(i915);
828 	intel_irq_uninstall(i915);
829 	intel_display_driver_remove_noirq(i915);
830 	goto out_cleanup_modeset;
831 out_cleanup_irq:
832 	intel_irq_uninstall(i915);
833 out_cleanup_modeset:
834 	intel_display_driver_remove_nogem(i915);
835 out_cleanup_hw:
836 	i915_driver_hw_remove(i915);
837 	intel_memory_regions_driver_release(i915);
838 	i915_ggtt_driver_release(i915);
839 	i915_gem_drain_freed_objects(i915);
840 	i915_ggtt_driver_late_release(i915);
841 out_cleanup_mmio:
842 	i915_driver_mmio_release(i915);
843 out_tiles_cleanup:
844 	intel_gt_release_all(i915);
845 out_runtime_pm_put:
846 	enable_rpm_wakeref_asserts(&i915->runtime_pm);
847 	i915_driver_late_release(i915);
848 out_pci_disable:
849 	pci_disable_device(pdev);
850 	i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
851 	return ret;
852 }
853 
854 void i915_driver_remove(struct drm_i915_private *i915)
855 {
856 	intel_wakeref_t wakeref;
857 
858 	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
859 
860 	i915_driver_unregister(i915);
861 
862 	/* Flush any external code that still may be under the RCU lock */
863 	synchronize_rcu();
864 
865 	i915_gem_suspend(i915);
866 
867 	intel_gvt_driver_remove(i915);
868 
869 	intel_display_driver_remove(i915);
870 
871 	intel_irq_uninstall(i915);
872 
873 	intel_display_driver_remove_noirq(i915);
874 
875 	i915_reset_error_state(i915);
876 	i915_gem_driver_remove(i915);
877 
878 	intel_display_driver_remove_nogem(i915);
879 
880 	i915_driver_hw_remove(i915);
881 
882 	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
883 }
884 
885 static void i915_driver_release(struct drm_device *dev)
886 {
887 	struct drm_i915_private *dev_priv = to_i915(dev);
888 	struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
889 	intel_wakeref_t wakeref;
890 
891 	if (!dev_priv->do_release)
892 		return;
893 
894 	wakeref = intel_runtime_pm_get(rpm);
895 
896 	i915_gem_driver_release(dev_priv);
897 
898 	intel_memory_regions_driver_release(dev_priv);
899 	i915_ggtt_driver_release(dev_priv);
900 	i915_gem_drain_freed_objects(dev_priv);
901 	i915_ggtt_driver_late_release(dev_priv);
902 
903 	i915_driver_mmio_release(dev_priv);
904 
905 	intel_runtime_pm_put(rpm, wakeref);
906 
907 	intel_runtime_pm_driver_release(rpm);
908 
909 	i915_driver_late_release(dev_priv);
910 }
911 
912 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
913 {
914 	struct drm_i915_private *i915 = to_i915(dev);
915 	int ret;
916 
917 	ret = i915_gem_open(i915, file);
918 	if (ret)
919 		return ret;
920 
921 	return 0;
922 }
923 
924 /**
925  * i915_driver_lastclose - clean up after all DRM clients have exited
926  * @dev: DRM device
927  *
928  * Take care of cleaning up after all DRM clients have exited.  In the
929  * mode setting case, we want to restore the kernel's initial mode (just
930  * in case the last client left us in a bad state).
931  *
932  * Additionally, in the non-mode setting case, we'll tear down the GTT
933  * and DMA structures, since the kernel won't be using them, and clea
934  * up any GEM state.
935  */
936 static void i915_driver_lastclose(struct drm_device *dev)
937 {
938 	struct drm_i915_private *i915 = to_i915(dev);
939 
940 	intel_fbdev_restore_mode(i915);
941 
942 	vga_switcheroo_process_delayed_switch();
943 }
944 
945 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
946 {
947 	struct drm_i915_file_private *file_priv = file->driver_priv;
948 
949 	i915_gem_context_close(file);
950 	i915_drm_client_put(file_priv->client);
951 
952 	kfree_rcu(file_priv, rcu);
953 
954 	/* Catch up with all the deferred frees from "this" client */
955 	i915_gem_flush_free_objects(to_i915(dev));
956 }
957 
958 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
959 {
960 	struct intel_encoder *encoder;
961 
962 	if (!HAS_DISPLAY(dev_priv))
963 		return;
964 
965 	/*
966 	 * TODO: check and remove holding the modeset locks if none of
967 	 * the encoders depends on this.
968 	 */
969 	drm_modeset_lock_all(&dev_priv->drm);
970 	for_each_intel_encoder(&dev_priv->drm, encoder)
971 		if (encoder->suspend)
972 			encoder->suspend(encoder);
973 	drm_modeset_unlock_all(&dev_priv->drm);
974 
975 	for_each_intel_encoder(&dev_priv->drm, encoder)
976 		if (encoder->suspend_complete)
977 			encoder->suspend_complete(encoder);
978 }
979 
980 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv)
981 {
982 	struct intel_encoder *encoder;
983 
984 	if (!HAS_DISPLAY(dev_priv))
985 		return;
986 
987 	/*
988 	 * TODO: check and remove holding the modeset locks if none of
989 	 * the encoders depends on this.
990 	 */
991 	drm_modeset_lock_all(&dev_priv->drm);
992 	for_each_intel_encoder(&dev_priv->drm, encoder)
993 		if (encoder->shutdown)
994 			encoder->shutdown(encoder);
995 	drm_modeset_unlock_all(&dev_priv->drm);
996 
997 	for_each_intel_encoder(&dev_priv->drm, encoder)
998 		if (encoder->shutdown_complete)
999 			encoder->shutdown_complete(encoder);
1000 }
1001 
1002 void i915_driver_shutdown(struct drm_i915_private *i915)
1003 {
1004 	disable_rpm_wakeref_asserts(&i915->runtime_pm);
1005 	intel_runtime_pm_disable(&i915->runtime_pm);
1006 	intel_power_domains_disable(i915);
1007 
1008 	if (HAS_DISPLAY(i915)) {
1009 		drm_kms_helper_poll_disable(&i915->drm);
1010 
1011 		drm_atomic_helper_shutdown(&i915->drm);
1012 	}
1013 
1014 	intel_dp_mst_suspend(i915);
1015 
1016 	intel_runtime_pm_disable_interrupts(i915);
1017 	intel_hpd_cancel_work(i915);
1018 
1019 	intel_suspend_encoders(i915);
1020 	intel_shutdown_encoders(i915);
1021 
1022 	intel_dmc_suspend(i915);
1023 
1024 	i915_gem_suspend(i915);
1025 
1026 	/*
1027 	 * The only requirement is to reboot with display DC states disabled,
1028 	 * for now leaving all display power wells in the INIT power domain
1029 	 * enabled.
1030 	 *
1031 	 * TODO:
1032 	 * - unify the pci_driver::shutdown sequence here with the
1033 	 *   pci_driver.driver.pm.poweroff,poweroff_late sequence.
1034 	 * - unify the driver remove and system/runtime suspend sequences with
1035 	 *   the above unified shutdown/poweroff sequence.
1036 	 */
1037 	intel_power_domains_driver_remove(i915);
1038 	enable_rpm_wakeref_asserts(&i915->runtime_pm);
1039 
1040 	intel_runtime_pm_driver_release(&i915->runtime_pm);
1041 }
1042 
1043 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1044 {
1045 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1046 	if (acpi_target_system_state() < ACPI_STATE_S3)
1047 		return true;
1048 #endif
1049 	return false;
1050 }
1051 
1052 static void i915_drm_complete(struct drm_device *dev)
1053 {
1054 	struct drm_i915_private *i915 = to_i915(dev);
1055 
1056 	intel_pxp_resume_complete(i915->pxp);
1057 }
1058 
1059 static int i915_drm_prepare(struct drm_device *dev)
1060 {
1061 	struct drm_i915_private *i915 = to_i915(dev);
1062 
1063 	intel_pxp_suspend_prepare(i915->pxp);
1064 
1065 	/*
1066 	 * NB intel_display_driver_suspend() may issue new requests after we've
1067 	 * ostensibly marked the GPU as ready-to-sleep here. We need to
1068 	 * split out that work and pull it forward so that after point,
1069 	 * the GPU is not woken again.
1070 	 */
1071 	return i915_gem_backup_suspend(i915);
1072 }
1073 
1074 static int i915_drm_suspend(struct drm_device *dev)
1075 {
1076 	struct drm_i915_private *dev_priv = to_i915(dev);
1077 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1078 	pci_power_t opregion_target_state;
1079 
1080 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1081 
1082 	/* We do a lot of poking in a lot of registers, make sure they work
1083 	 * properly. */
1084 	intel_power_domains_disable(dev_priv);
1085 	if (HAS_DISPLAY(dev_priv))
1086 		drm_kms_helper_poll_disable(dev);
1087 
1088 	pci_save_state(pdev);
1089 
1090 	intel_display_driver_suspend(dev_priv);
1091 
1092 	intel_dp_mst_suspend(dev_priv);
1093 
1094 	intel_runtime_pm_disable_interrupts(dev_priv);
1095 	intel_hpd_cancel_work(dev_priv);
1096 
1097 	intel_suspend_encoders(dev_priv);
1098 
1099 	/* Must be called before GGTT is suspended. */
1100 	intel_dpt_suspend(dev_priv);
1101 	i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
1102 
1103 	i915_save_display(dev_priv);
1104 
1105 	opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1106 	intel_opregion_suspend(dev_priv, opregion_target_state);
1107 
1108 	intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1109 
1110 	dev_priv->suspend_count++;
1111 
1112 	intel_dmc_suspend(dev_priv);
1113 
1114 	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1115 
1116 	i915_gem_drain_freed_objects(dev_priv);
1117 
1118 	return 0;
1119 }
1120 
1121 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1122 {
1123 	struct drm_i915_private *dev_priv = to_i915(dev);
1124 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1125 	struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1126 	struct intel_gt *gt;
1127 	int ret, i;
1128 	bool s2idle = !hibernation && suspend_to_idle(dev_priv);
1129 
1130 	disable_rpm_wakeref_asserts(rpm);
1131 
1132 	intel_pxp_suspend(dev_priv->pxp);
1133 
1134 	i915_gem_suspend_late(dev_priv);
1135 
1136 	for_each_gt(gt, dev_priv, i)
1137 		intel_uncore_suspend(gt->uncore);
1138 
1139 	intel_power_domains_suspend(dev_priv, s2idle);
1140 
1141 	intel_display_power_suspend_late(dev_priv);
1142 
1143 	ret = vlv_suspend_complete(dev_priv);
1144 	if (ret) {
1145 		drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1146 		intel_power_domains_resume(dev_priv);
1147 
1148 		goto out;
1149 	}
1150 
1151 	pci_disable_device(pdev);
1152 	/*
1153 	 * During hibernation on some platforms the BIOS may try to access
1154 	 * the device even though it's already in D3 and hang the machine. So
1155 	 * leave the device in D0 on those platforms and hope the BIOS will
1156 	 * power down the device properly. The issue was seen on multiple old
1157 	 * GENs with different BIOS vendors, so having an explicit blacklist
1158 	 * is inpractical; apply the workaround on everything pre GEN6. The
1159 	 * platforms where the issue was seen:
1160 	 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1161 	 * Fujitsu FSC S7110
1162 	 * Acer Aspire 1830T
1163 	 */
1164 	if (!(hibernation && GRAPHICS_VER(dev_priv) < 6))
1165 		pci_set_power_state(pdev, PCI_D3hot);
1166 
1167 out:
1168 	enable_rpm_wakeref_asserts(rpm);
1169 	if (!dev_priv->uncore.user_forcewake_count)
1170 		intel_runtime_pm_driver_release(rpm);
1171 
1172 	return ret;
1173 }
1174 
1175 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915,
1176 				   pm_message_t state)
1177 {
1178 	int error;
1179 
1180 	if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1181 			     state.event != PM_EVENT_FREEZE))
1182 		return -EINVAL;
1183 
1184 	if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1185 		return 0;
1186 
1187 	error = i915_drm_suspend(&i915->drm);
1188 	if (error)
1189 		return error;
1190 
1191 	return i915_drm_suspend_late(&i915->drm, false);
1192 }
1193 
1194 static int i915_drm_resume(struct drm_device *dev)
1195 {
1196 	struct drm_i915_private *dev_priv = to_i915(dev);
1197 	struct intel_gt *gt;
1198 	int ret, i;
1199 
1200 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1201 
1202 	ret = i915_pcode_init(dev_priv);
1203 	if (ret)
1204 		return ret;
1205 
1206 	sanitize_gpu(dev_priv);
1207 
1208 	ret = i915_ggtt_enable_hw(dev_priv);
1209 	if (ret)
1210 		drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1211 
1212 	i915_ggtt_resume(to_gt(dev_priv)->ggtt);
1213 
1214 	for_each_gt(gt, dev_priv, i)
1215 		if (GRAPHICS_VER(gt->i915) >= 8)
1216 			setup_private_pat(gt);
1217 
1218 	/* Must be called after GGTT is resumed. */
1219 	intel_dpt_resume(dev_priv);
1220 
1221 	intel_dmc_resume(dev_priv);
1222 
1223 	i915_restore_display(dev_priv);
1224 	intel_pps_unlock_regs_wa(dev_priv);
1225 
1226 	intel_init_pch_refclk(dev_priv);
1227 
1228 	/*
1229 	 * Interrupts have to be enabled before any batches are run. If not the
1230 	 * GPU will hang. i915_gem_init_hw() will initiate batches to
1231 	 * update/restore the context.
1232 	 *
1233 	 * drm_mode_config_reset() needs AUX interrupts.
1234 	 *
1235 	 * Modeset enabling in intel_display_driver_init_hw() also needs working
1236 	 * interrupts.
1237 	 */
1238 	intel_runtime_pm_enable_interrupts(dev_priv);
1239 
1240 	if (HAS_DISPLAY(dev_priv))
1241 		drm_mode_config_reset(dev);
1242 
1243 	i915_gem_resume(dev_priv);
1244 
1245 	intel_display_driver_init_hw(dev_priv);
1246 
1247 	intel_clock_gating_init(dev_priv);
1248 	intel_hpd_init(dev_priv);
1249 
1250 	/* MST sideband requires HPD interrupts enabled */
1251 	intel_dp_mst_resume(dev_priv);
1252 	intel_display_driver_resume(dev_priv);
1253 
1254 	intel_hpd_poll_disable(dev_priv);
1255 	if (HAS_DISPLAY(dev_priv))
1256 		drm_kms_helper_poll_enable(dev);
1257 
1258 	intel_opregion_resume(dev_priv);
1259 
1260 	intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1261 
1262 	intel_power_domains_enable(dev_priv);
1263 
1264 	intel_gvt_resume(dev_priv);
1265 
1266 	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1267 
1268 	return 0;
1269 }
1270 
1271 static int i915_drm_resume_early(struct drm_device *dev)
1272 {
1273 	struct drm_i915_private *dev_priv = to_i915(dev);
1274 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1275 	struct intel_gt *gt;
1276 	int ret, i;
1277 
1278 	/*
1279 	 * We have a resume ordering issue with the snd-hda driver also
1280 	 * requiring our device to be power up. Due to the lack of a
1281 	 * parent/child relationship we currently solve this with an early
1282 	 * resume hook.
1283 	 *
1284 	 * FIXME: This should be solved with a special hdmi sink device or
1285 	 * similar so that power domains can be employed.
1286 	 */
1287 
1288 	/*
1289 	 * Note that we need to set the power state explicitly, since we
1290 	 * powered off the device during freeze and the PCI core won't power
1291 	 * it back up for us during thaw. Powering off the device during
1292 	 * freeze is not a hard requirement though, and during the
1293 	 * suspend/resume phases the PCI core makes sure we get here with the
1294 	 * device powered on. So in case we change our freeze logic and keep
1295 	 * the device powered we can also remove the following set power state
1296 	 * call.
1297 	 */
1298 	ret = pci_set_power_state(pdev, PCI_D0);
1299 	if (ret) {
1300 		drm_err(&dev_priv->drm,
1301 			"failed to set PCI D0 power state (%d)\n", ret);
1302 		return ret;
1303 	}
1304 
1305 	/*
1306 	 * Note that pci_enable_device() first enables any parent bridge
1307 	 * device and only then sets the power state for this device. The
1308 	 * bridge enabling is a nop though, since bridge devices are resumed
1309 	 * first. The order of enabling power and enabling the device is
1310 	 * imposed by the PCI core as described above, so here we preserve the
1311 	 * same order for the freeze/thaw phases.
1312 	 *
1313 	 * TODO: eventually we should remove pci_disable_device() /
1314 	 * pci_enable_enable_device() from suspend/resume. Due to how they
1315 	 * depend on the device enable refcount we can't anyway depend on them
1316 	 * disabling/enabling the device.
1317 	 */
1318 	if (pci_enable_device(pdev))
1319 		return -EIO;
1320 
1321 	pci_set_master(pdev);
1322 
1323 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1324 
1325 	ret = vlv_resume_prepare(dev_priv, false);
1326 	if (ret)
1327 		drm_err(&dev_priv->drm,
1328 			"Resume prepare failed: %d, continuing anyway\n", ret);
1329 
1330 	for_each_gt(gt, dev_priv, i) {
1331 		intel_uncore_resume_early(gt->uncore);
1332 		intel_gt_check_and_clear_faults(gt);
1333 	}
1334 
1335 	intel_display_power_resume_early(dev_priv);
1336 
1337 	intel_power_domains_resume(dev_priv);
1338 
1339 	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1340 
1341 	return ret;
1342 }
1343 
1344 int i915_driver_resume_switcheroo(struct drm_i915_private *i915)
1345 {
1346 	int ret;
1347 
1348 	if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1349 		return 0;
1350 
1351 	ret = i915_drm_resume_early(&i915->drm);
1352 	if (ret)
1353 		return ret;
1354 
1355 	return i915_drm_resume(&i915->drm);
1356 }
1357 
1358 static int i915_pm_prepare(struct device *kdev)
1359 {
1360 	struct drm_i915_private *i915 = kdev_to_i915(kdev);
1361 
1362 	if (!i915) {
1363 		dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1364 		return -ENODEV;
1365 	}
1366 
1367 	if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1368 		return 0;
1369 
1370 	return i915_drm_prepare(&i915->drm);
1371 }
1372 
1373 static int i915_pm_suspend(struct device *kdev)
1374 {
1375 	struct drm_i915_private *i915 = kdev_to_i915(kdev);
1376 
1377 	if (!i915) {
1378 		dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1379 		return -ENODEV;
1380 	}
1381 
1382 	if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1383 		return 0;
1384 
1385 	return i915_drm_suspend(&i915->drm);
1386 }
1387 
1388 static int i915_pm_suspend_late(struct device *kdev)
1389 {
1390 	struct drm_i915_private *i915 = kdev_to_i915(kdev);
1391 
1392 	/*
1393 	 * We have a suspend ordering issue with the snd-hda driver also
1394 	 * requiring our device to be power up. Due to the lack of a
1395 	 * parent/child relationship we currently solve this with an late
1396 	 * suspend hook.
1397 	 *
1398 	 * FIXME: This should be solved with a special hdmi sink device or
1399 	 * similar so that power domains can be employed.
1400 	 */
1401 	if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1402 		return 0;
1403 
1404 	return i915_drm_suspend_late(&i915->drm, false);
1405 }
1406 
1407 static int i915_pm_poweroff_late(struct device *kdev)
1408 {
1409 	struct drm_i915_private *i915 = kdev_to_i915(kdev);
1410 
1411 	if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1412 		return 0;
1413 
1414 	return i915_drm_suspend_late(&i915->drm, true);
1415 }
1416 
1417 static int i915_pm_resume_early(struct device *kdev)
1418 {
1419 	struct drm_i915_private *i915 = kdev_to_i915(kdev);
1420 
1421 	if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1422 		return 0;
1423 
1424 	return i915_drm_resume_early(&i915->drm);
1425 }
1426 
1427 static int i915_pm_resume(struct device *kdev)
1428 {
1429 	struct drm_i915_private *i915 = kdev_to_i915(kdev);
1430 
1431 	if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1432 		return 0;
1433 
1434 	return i915_drm_resume(&i915->drm);
1435 }
1436 
1437 static void i915_pm_complete(struct device *kdev)
1438 {
1439 	struct drm_i915_private *i915 = kdev_to_i915(kdev);
1440 
1441 	if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1442 		return;
1443 
1444 	i915_drm_complete(&i915->drm);
1445 }
1446 
1447 /* freeze: before creating the hibernation_image */
1448 static int i915_pm_freeze(struct device *kdev)
1449 {
1450 	struct drm_i915_private *i915 = kdev_to_i915(kdev);
1451 	int ret;
1452 
1453 	if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1454 		ret = i915_drm_suspend(&i915->drm);
1455 		if (ret)
1456 			return ret;
1457 	}
1458 
1459 	ret = i915_gem_freeze(i915);
1460 	if (ret)
1461 		return ret;
1462 
1463 	return 0;
1464 }
1465 
1466 static int i915_pm_freeze_late(struct device *kdev)
1467 {
1468 	struct drm_i915_private *i915 = kdev_to_i915(kdev);
1469 	int ret;
1470 
1471 	if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1472 		ret = i915_drm_suspend_late(&i915->drm, true);
1473 		if (ret)
1474 			return ret;
1475 	}
1476 
1477 	ret = i915_gem_freeze_late(i915);
1478 	if (ret)
1479 		return ret;
1480 
1481 	return 0;
1482 }
1483 
1484 /* thaw: called after creating the hibernation image, but before turning off. */
1485 static int i915_pm_thaw_early(struct device *kdev)
1486 {
1487 	return i915_pm_resume_early(kdev);
1488 }
1489 
1490 static int i915_pm_thaw(struct device *kdev)
1491 {
1492 	return i915_pm_resume(kdev);
1493 }
1494 
1495 /* restore: called after loading the hibernation image. */
1496 static int i915_pm_restore_early(struct device *kdev)
1497 {
1498 	return i915_pm_resume_early(kdev);
1499 }
1500 
1501 static int i915_pm_restore(struct device *kdev)
1502 {
1503 	return i915_pm_resume(kdev);
1504 }
1505 
1506 static int intel_runtime_suspend(struct device *kdev)
1507 {
1508 	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1509 	struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1510 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1511 	struct pci_dev *root_pdev;
1512 	struct intel_gt *gt;
1513 	int ret, i;
1514 
1515 	if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1516 		return -ENODEV;
1517 
1518 	drm_dbg(&dev_priv->drm, "Suspending device\n");
1519 
1520 	disable_rpm_wakeref_asserts(rpm);
1521 
1522 	/*
1523 	 * We are safe here against re-faults, since the fault handler takes
1524 	 * an RPM reference.
1525 	 */
1526 	i915_gem_runtime_suspend(dev_priv);
1527 
1528 	intel_pxp_runtime_suspend(dev_priv->pxp);
1529 
1530 	for_each_gt(gt, dev_priv, i)
1531 		intel_gt_runtime_suspend(gt);
1532 
1533 	intel_runtime_pm_disable_interrupts(dev_priv);
1534 
1535 	for_each_gt(gt, dev_priv, i)
1536 		intel_uncore_suspend(gt->uncore);
1537 
1538 	intel_display_power_suspend(dev_priv);
1539 
1540 	ret = vlv_suspend_complete(dev_priv);
1541 	if (ret) {
1542 		drm_err(&dev_priv->drm,
1543 			"Runtime suspend failed, disabling it (%d)\n", ret);
1544 		intel_uncore_runtime_resume(&dev_priv->uncore);
1545 
1546 		intel_runtime_pm_enable_interrupts(dev_priv);
1547 
1548 		for_each_gt(gt, dev_priv, i)
1549 			intel_gt_runtime_resume(gt);
1550 
1551 		enable_rpm_wakeref_asserts(rpm);
1552 
1553 		return ret;
1554 	}
1555 
1556 	enable_rpm_wakeref_asserts(rpm);
1557 	intel_runtime_pm_driver_release(rpm);
1558 
1559 	if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1560 		drm_err(&dev_priv->drm,
1561 			"Unclaimed access detected prior to suspending\n");
1562 
1563 	/*
1564 	 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
1565 	 * This should be totally removed when we handle the pci states properly
1566 	 * on runtime PM.
1567 	 */
1568 	root_pdev = pcie_find_root_port(pdev);
1569 	if (root_pdev)
1570 		pci_d3cold_disable(root_pdev);
1571 
1572 	/*
1573 	 * FIXME: We really should find a document that references the arguments
1574 	 * used below!
1575 	 */
1576 	if (IS_BROADWELL(dev_priv)) {
1577 		/*
1578 		 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1579 		 * being detected, and the call we do at intel_runtime_resume()
1580 		 * won't be able to restore them. Since PCI_D3hot matches the
1581 		 * actual specification and appears to be working, use it.
1582 		 */
1583 		intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1584 	} else {
1585 		/*
1586 		 * current versions of firmware which depend on this opregion
1587 		 * notification have repurposed the D1 definition to mean
1588 		 * "runtime suspended" vs. what you would normally expect (D3)
1589 		 * to distinguish it from notifications that might be sent via
1590 		 * the suspend path.
1591 		 */
1592 		intel_opregion_notify_adapter(dev_priv, PCI_D1);
1593 	}
1594 
1595 	assert_forcewakes_inactive(&dev_priv->uncore);
1596 
1597 	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1598 		intel_hpd_poll_enable(dev_priv);
1599 
1600 	drm_dbg(&dev_priv->drm, "Device suspended\n");
1601 	return 0;
1602 }
1603 
1604 static int intel_runtime_resume(struct device *kdev)
1605 {
1606 	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1607 	struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1608 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1609 	struct pci_dev *root_pdev;
1610 	struct intel_gt *gt;
1611 	int ret, i;
1612 
1613 	if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1614 		return -ENODEV;
1615 
1616 	drm_dbg(&dev_priv->drm, "Resuming device\n");
1617 
1618 	drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1619 	disable_rpm_wakeref_asserts(rpm);
1620 
1621 	intel_opregion_notify_adapter(dev_priv, PCI_D0);
1622 
1623 	root_pdev = pcie_find_root_port(pdev);
1624 	if (root_pdev)
1625 		pci_d3cold_enable(root_pdev);
1626 
1627 	if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1628 		drm_dbg(&dev_priv->drm,
1629 			"Unclaimed access during suspend, bios?\n");
1630 
1631 	intel_display_power_resume(dev_priv);
1632 
1633 	ret = vlv_resume_prepare(dev_priv, true);
1634 
1635 	for_each_gt(gt, dev_priv, i)
1636 		intel_uncore_runtime_resume(gt->uncore);
1637 
1638 	intel_runtime_pm_enable_interrupts(dev_priv);
1639 
1640 	/*
1641 	 * No point of rolling back things in case of an error, as the best
1642 	 * we can do is to hope that things will still work (and disable RPM).
1643 	 */
1644 	for_each_gt(gt, dev_priv, i)
1645 		intel_gt_runtime_resume(gt);
1646 
1647 	intel_pxp_runtime_resume(dev_priv->pxp);
1648 
1649 	/*
1650 	 * On VLV/CHV display interrupts are part of the display
1651 	 * power well, so hpd is reinitialized from there. For
1652 	 * everyone else do it here.
1653 	 */
1654 	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1655 		intel_hpd_init(dev_priv);
1656 		intel_hpd_poll_disable(dev_priv);
1657 	}
1658 
1659 	skl_watermark_ipc_update(dev_priv);
1660 
1661 	enable_rpm_wakeref_asserts(rpm);
1662 
1663 	if (ret)
1664 		drm_err(&dev_priv->drm,
1665 			"Runtime resume failed, disabling it (%d)\n", ret);
1666 	else
1667 		drm_dbg(&dev_priv->drm, "Device resumed\n");
1668 
1669 	return ret;
1670 }
1671 
1672 const struct dev_pm_ops i915_pm_ops = {
1673 	/*
1674 	 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1675 	 * PMSG_RESUME]
1676 	 */
1677 	.prepare = i915_pm_prepare,
1678 	.suspend = i915_pm_suspend,
1679 	.suspend_late = i915_pm_suspend_late,
1680 	.resume_early = i915_pm_resume_early,
1681 	.resume = i915_pm_resume,
1682 	.complete = i915_pm_complete,
1683 
1684 	/*
1685 	 * S4 event handlers
1686 	 * @freeze, @freeze_late    : called (1) before creating the
1687 	 *                            hibernation image [PMSG_FREEZE] and
1688 	 *                            (2) after rebooting, before restoring
1689 	 *                            the image [PMSG_QUIESCE]
1690 	 * @thaw, @thaw_early       : called (1) after creating the hibernation
1691 	 *                            image, before writing it [PMSG_THAW]
1692 	 *                            and (2) after failing to create or
1693 	 *                            restore the image [PMSG_RECOVER]
1694 	 * @poweroff, @poweroff_late: called after writing the hibernation
1695 	 *                            image, before rebooting [PMSG_HIBERNATE]
1696 	 * @restore, @restore_early : called after rebooting and restoring the
1697 	 *                            hibernation image [PMSG_RESTORE]
1698 	 */
1699 	.freeze = i915_pm_freeze,
1700 	.freeze_late = i915_pm_freeze_late,
1701 	.thaw_early = i915_pm_thaw_early,
1702 	.thaw = i915_pm_thaw,
1703 	.poweroff = i915_pm_suspend,
1704 	.poweroff_late = i915_pm_poweroff_late,
1705 	.restore_early = i915_pm_restore_early,
1706 	.restore = i915_pm_restore,
1707 
1708 	/* S0ix (via runtime suspend) event handlers */
1709 	.runtime_suspend = intel_runtime_suspend,
1710 	.runtime_resume = intel_runtime_resume,
1711 };
1712 
1713 static const struct file_operations i915_driver_fops = {
1714 	.owner = THIS_MODULE,
1715 	.open = drm_open,
1716 	.release = drm_release_noglobal,
1717 	.unlocked_ioctl = drm_ioctl,
1718 	.mmap = i915_gem_mmap,
1719 	.poll = drm_poll,
1720 	.read = drm_read,
1721 	.compat_ioctl = i915_ioc32_compat_ioctl,
1722 	.llseek = noop_llseek,
1723 #ifdef CONFIG_PROC_FS
1724 	.show_fdinfo = drm_show_fdinfo,
1725 #endif
1726 };
1727 
1728 static int
1729 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1730 			  struct drm_file *file)
1731 {
1732 	return -ENODEV;
1733 }
1734 
1735 static const struct drm_ioctl_desc i915_ioctls[] = {
1736 	DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1737 	DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1738 	DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1739 	DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1740 	DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1741 	DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1742 	DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1743 	DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1744 	DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1745 	DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1746 	DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1747 	DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1748 	DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1749 	DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1750 	DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1751 	DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1752 	DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1753 	DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1754 	DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH),
1755 	DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1756 	DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1757 	DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1758 	DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1759 	DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1760 	DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1761 	DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1762 	DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1763 	DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1764 	DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1765 	DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW),
1766 	DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1767 	DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1768 	DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1769 	DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1770 	DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1771 	DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1772 	DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1773 	DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1774 	DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1775 	DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
1776 	DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1777 	DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1778 	DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1779 	DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1780 	DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1781 	DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1782 	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1783 	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1784 	DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1785 	DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1786 	DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1787 	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1788 	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1789 	DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1790 	DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1791 	DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1792 	DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1793 	DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1794 	DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1795 };
1796 
1797 /*
1798  * Interface history:
1799  *
1800  * 1.1: Original.
1801  * 1.2: Add Power Management
1802  * 1.3: Add vblank support
1803  * 1.4: Fix cmdbuffer path, add heap destroy
1804  * 1.5: Add vblank pipe configuration
1805  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
1806  *      - Support vertical blank on secondary display pipe
1807  */
1808 #define DRIVER_MAJOR		1
1809 #define DRIVER_MINOR		6
1810 #define DRIVER_PATCHLEVEL	0
1811 
1812 static const struct drm_driver i915_drm_driver = {
1813 	/* Don't use MTRRs here; the Xserver or userspace app should
1814 	 * deal with them for Intel hardware.
1815 	 */
1816 	.driver_features =
1817 	    DRIVER_GEM |
1818 	    DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1819 	    DRIVER_SYNCOBJ_TIMELINE,
1820 	.release = i915_driver_release,
1821 	.open = i915_driver_open,
1822 	.lastclose = i915_driver_lastclose,
1823 	.postclose = i915_driver_postclose,
1824 	.show_fdinfo = PTR_IF(IS_ENABLED(CONFIG_PROC_FS), i915_drm_client_fdinfo),
1825 
1826 	.gem_prime_import = i915_gem_prime_import,
1827 
1828 	.dumb_create = i915_gem_dumb_create,
1829 	.dumb_map_offset = i915_gem_dumb_mmap_offset,
1830 
1831 	.ioctls = i915_ioctls,
1832 	.num_ioctls = ARRAY_SIZE(i915_ioctls),
1833 	.fops = &i915_driver_fops,
1834 	.name = DRIVER_NAME,
1835 	.desc = DRIVER_DESC,
1836 	.date = DRIVER_DATE,
1837 	.major = DRIVER_MAJOR,
1838 	.minor = DRIVER_MINOR,
1839 	.patchlevel = DRIVER_PATCHLEVEL,
1840 };
1841