1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #include <linux/aperture.h> 31 #include <linux/acpi.h> 32 #include <linux/device.h> 33 #include <linux/module.h> 34 #include <linux/oom.h> 35 #include <linux/pci.h> 36 #include <linux/pm.h> 37 #include <linux/pm_runtime.h> 38 #include <linux/slab.h> 39 #include <linux/string_helpers.h> 40 #include <linux/vga_switcheroo.h> 41 #include <linux/vt.h> 42 43 #include <drm/drm_atomic_helper.h> 44 #include <drm/drm_client.h> 45 #include <drm/drm_client_event.h> 46 #include <drm/drm_ioctl.h> 47 #include <drm/drm_managed.h> 48 #include <drm/drm_probe_helper.h> 49 #include <drm/intel/display_member.h> 50 #include <drm/intel/display_parent_interface.h> 51 #include <drm/intel/intel_pcode_regs.h> 52 53 #include "display/i9xx_display_sr.h" 54 #include "display/intel_bw.h" 55 #include "display/intel_cdclk.h" 56 #include "display/intel_crtc.h" 57 #include "display/intel_display_device.h" 58 #include "display/intel_display_driver.h" 59 #include "display/intel_display_power.h" 60 #include "display/intel_dmc.h" 61 #include "display/intel_dp.h" 62 #include "display/intel_dpt.h" 63 #include "display/intel_dram.h" 64 #include "display/intel_encoder.h" 65 #include "display/intel_fbdev.h" 66 #include "display/intel_gmbus.h" 67 #include "display/intel_hotplug.h" 68 #include "display/intel_opregion.h" 69 #include "display/intel_overlay.h" 70 #include "display/intel_pch_refclk.h" 71 #include "display/intel_pps.h" 72 #include "display/intel_sbi.h" 73 #include "display/intel_sprite_uapi.h" 74 #include "display/skl_watermark.h" 75 76 #include "gem/i915_gem_context.h" 77 #include "gem/i915_gem_create.h" 78 #include "gem/i915_gem_dmabuf.h" 79 #include "gem/i915_gem_ioctls.h" 80 #include "gem/i915_gem_mman.h" 81 #include "gem/i915_gem_object_frontbuffer.h" 82 #include "gem/i915_gem_pm.h" 83 #include "gt/intel_gt.h" 84 #include "gt/intel_gt_pm.h" 85 #include "gt/intel_gt_print.h" 86 #include "gt/intel_rc6.h" 87 #include "gt/intel_rps.h" 88 89 #include "pxp/intel_pxp.h" 90 #include "pxp/intel_pxp_debugfs.h" 91 #include "pxp/intel_pxp_pm.h" 92 93 #include "i915_bo.h" 94 #include "i915_debugfs.h" 95 #include "i915_display_pc8.h" 96 #include "i915_dpt.h" 97 #include "i915_driver.h" 98 #include "i915_drm_client.h" 99 #include "i915_drv.h" 100 #include "i915_dsb_buffer.h" 101 #include "i915_edram.h" 102 #include "i915_file_private.h" 103 #include "i915_getparam.h" 104 #include "i915_gmch.h" 105 #include "i915_hdcp_gsc.h" 106 #include "i915_hwmon.h" 107 #include "i915_initial_plane.h" 108 #include "i915_ioc32.h" 109 #include "i915_ioctl.h" 110 #include "i915_irq.h" 111 #include "i915_memcpy.h" 112 #include "i915_overlay.h" 113 #include "i915_panic.h" 114 #include "i915_perf.h" 115 #include "i915_query.h" 116 #include "i915_reg.h" 117 #include "i915_switcheroo.h" 118 #include "i915_sysfs.h" 119 #include "i915_utils.h" 120 #include "i915_vgpu.h" 121 #include "intel_clock_gating.h" 122 #include "intel_cpu_info.h" 123 #include "intel_gvt.h" 124 #include "intel_memory_region.h" 125 #include "intel_pci_config.h" 126 #include "intel_pcode.h" 127 #include "intel_region_ttm.h" 128 #include "vlv_iosf_sb.h" 129 #include "vlv_suspend.h" 130 131 static const struct drm_driver i915_drm_driver; 132 133 static int i915_workqueues_init(struct drm_i915_private *dev_priv) 134 { 135 /* 136 * The i915 workqueue is primarily used for batched retirement of 137 * requests (and thus managing bo) once the task has been completed 138 * by the GPU. i915_retire_requests() is called directly when we 139 * need high-priority retirement, such as waiting for an explicit 140 * bo. 141 * 142 * It is also used for periodic low-priority events, such as 143 * idle-timers and recording error state. 144 * 145 * All tasks on the workqueue are expected to acquire the dev mutex 146 * so there is no point in running more than one instance of the 147 * workqueue at any time. Use an ordered one. 148 */ 149 dev_priv->wq = alloc_ordered_workqueue("i915", 0); 150 if (dev_priv->wq == NULL) 151 goto out_err; 152 153 /* 154 * The unordered i915 workqueue should be used for all work 155 * scheduling that do not require running in order, which used 156 * to be scheduled on the system_percpu_wq before moving to a driver 157 * instance due deprecation of flush_scheduled_work(). 158 */ 159 dev_priv->unordered_wq = alloc_workqueue("i915-unordered", WQ_PERCPU, 160 0); 161 if (dev_priv->unordered_wq == NULL) 162 goto out_free_wq; 163 164 return 0; 165 166 out_free_wq: 167 destroy_workqueue(dev_priv->wq); 168 out_err: 169 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n"); 170 171 return -ENOMEM; 172 } 173 174 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) 175 { 176 destroy_workqueue(dev_priv->unordered_wq); 177 destroy_workqueue(dev_priv->wq); 178 } 179 180 /* 181 * We don't keep the workarounds for pre-production hardware, so we expect our 182 * driver to fail on these machines in one way or another. A little warning on 183 * dmesg may help both the user and the bug triagers. 184 * 185 * Our policy for removing pre-production workarounds is to keep the 186 * current gen workarounds as a guide to the bring-up of the next gen 187 * (workarounds have a habit of persisting!). Anything older than that 188 * should be removed along with the complications they introduce. 189 */ 190 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) 191 { 192 bool pre = false; 193 194 pre |= IS_HASWELL_EARLY_SDV(dev_priv); 195 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6; 196 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA; 197 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 198 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3; 199 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7; 200 pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 201 pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 202 pre |= IS_DG2_G10(dev_priv) && INTEL_REVID(dev_priv) < 0x8; 203 pre |= IS_DG2_G11(dev_priv) && INTEL_REVID(dev_priv) < 0x5; 204 pre |= IS_DG2_G12(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 205 206 if (pre) { 207 drm_err(&dev_priv->drm, "This is a pre-production stepping. " 208 "It may not be fully functional.\n"); 209 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); 210 } 211 } 212 213 static void sanitize_gpu(struct drm_i915_private *i915) 214 { 215 if (!intel_gt_gpu_reset_clobbers_display(to_gt(i915))) { 216 struct intel_gt *gt; 217 unsigned int i; 218 219 for_each_gt(gt, i915, i) 220 intel_gt_reset_all_engines(gt); 221 } 222 } 223 224 /** 225 * i915_driver_early_probe - setup state not requiring device access 226 * @dev_priv: device private 227 * 228 * Initialize everything that is a "SW-only" state, that is state not 229 * requiring accessing the device or exposing the driver via kernel internal 230 * or userspace interfaces. Example steps belonging here: lock initialization, 231 * system memory allocation, setting up device specific attributes and 232 * function hooks not requiring accessing the device. 233 */ 234 static int i915_driver_early_probe(struct drm_i915_private *dev_priv) 235 { 236 struct intel_display *display = dev_priv->display; 237 int ret = 0; 238 239 intel_device_info_runtime_init_early(dev_priv); 240 241 intel_step_init(dev_priv); 242 243 intel_uncore_mmio_debug_init_early(dev_priv); 244 245 spin_lock_init(&dev_priv->gpu_error.lock); 246 247 intel_sbi_init(display); 248 vlv_iosf_sb_init(dev_priv); 249 mutex_init(&dev_priv->sb_lock); 250 251 i915_memcpy_init_early(dev_priv); 252 intel_runtime_pm_init_early(&dev_priv->runtime_pm); 253 254 ret = i915_workqueues_init(dev_priv); 255 if (ret < 0) 256 return ret; 257 258 ret = vlv_suspend_init(dev_priv); 259 if (ret < 0) 260 goto err_workqueues; 261 262 ret = intel_region_ttm_device_init(dev_priv); 263 if (ret) 264 goto err_ttm; 265 266 ret = intel_root_gt_init_early(dev_priv); 267 if (ret < 0) 268 goto err_rootgt; 269 270 i915_gem_init_early(dev_priv); 271 272 intel_irq_init(dev_priv); 273 intel_display_driver_early_probe(display); 274 intel_clock_gating_hooks_init(&dev_priv->drm); 275 276 intel_detect_preproduction_hw(dev_priv); 277 278 return 0; 279 280 err_rootgt: 281 intel_region_ttm_device_fini(dev_priv); 282 err_ttm: 283 vlv_suspend_cleanup(dev_priv); 284 err_workqueues: 285 i915_workqueues_cleanup(dev_priv); 286 return ret; 287 } 288 ALLOW_ERROR_INJECTION(i915_driver_early_probe, ERRNO); 289 290 /** 291 * i915_driver_late_release - cleanup the setup done in 292 * i915_driver_early_probe() 293 * @dev_priv: device private 294 */ 295 static void i915_driver_late_release(struct drm_i915_private *dev_priv) 296 { 297 struct intel_display *display = dev_priv->display; 298 299 intel_irq_fini(dev_priv); 300 intel_power_domains_cleanup(display); 301 i915_gem_cleanup_early(dev_priv); 302 intel_gt_driver_late_release_all(dev_priv); 303 intel_region_ttm_device_fini(dev_priv); 304 vlv_suspend_cleanup(dev_priv); 305 i915_workqueues_cleanup(dev_priv); 306 307 mutex_destroy(&dev_priv->sb_lock); 308 vlv_iosf_sb_fini(dev_priv); 309 intel_sbi_fini(display); 310 311 i915_params_free(&dev_priv->params); 312 313 intel_display_device_remove(display); 314 } 315 316 /** 317 * i915_driver_mmio_probe - setup device MMIO 318 * @dev_priv: device private 319 * 320 * Setup minimal device state necessary for MMIO accesses later in the 321 * initialization sequence. The setup here should avoid any other device-wide 322 * side effects or exposing the driver via kernel internal or user space 323 * interfaces. 324 */ 325 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) 326 { 327 struct intel_display *display = dev_priv->display; 328 struct intel_gt *gt; 329 int ret, i; 330 331 ret = i915_gmch_bridge_setup(dev_priv); 332 if (ret < 0) 333 return ret; 334 335 for_each_gt(gt, dev_priv, i) { 336 ret = intel_uncore_init_mmio(gt->uncore); 337 if (ret) 338 return ret; 339 340 ret = drmm_add_action_or_reset(&dev_priv->drm, 341 intel_uncore_fini_mmio, 342 gt->uncore); 343 if (ret) 344 return ret; 345 } 346 347 /* Try to make sure MCHBAR is enabled before poking at it */ 348 i915_gmch_bar_setup(dev_priv); 349 intel_device_info_runtime_init(dev_priv); 350 intel_display_device_info_runtime_init(display); 351 352 for_each_gt(gt, dev_priv, i) { 353 ret = intel_gt_init_mmio(gt); 354 if (ret) 355 goto err_uncore; 356 } 357 358 /* As early as possible, scrub existing GPU state before clobbering */ 359 sanitize_gpu(dev_priv); 360 361 return 0; 362 363 err_uncore: 364 i915_gmch_bar_teardown(dev_priv); 365 366 return ret; 367 } 368 ALLOW_ERROR_INJECTION(i915_driver_mmio_probe, ERRNO); 369 370 /** 371 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe() 372 * @dev_priv: device private 373 */ 374 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv) 375 { 376 i915_gmch_bar_teardown(dev_priv); 377 } 378 379 /** 380 * i915_set_dma_info - set all relevant PCI dma info as configured for the 381 * platform 382 * @i915: valid i915 instance 383 * 384 * Set the dma max segment size, device and coherent masks. The dma mask set 385 * needs to occur before i915_ggtt_probe_hw. 386 * 387 * A couple of platforms have special needs. Address them as well. 388 * 389 */ 390 static int i915_set_dma_info(struct drm_i915_private *i915) 391 { 392 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size; 393 int ret; 394 395 GEM_BUG_ON(!mask_size); 396 397 /* 398 * We don't have a max segment size, so set it to the max so sg's 399 * debugging layer doesn't complain 400 */ 401 dma_set_max_seg_size(i915->drm.dev, UINT_MAX); 402 403 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 404 if (ret) 405 goto mask_err; 406 407 /* overlay on gen2 is broken and can't address above 1G */ 408 if (GRAPHICS_VER(i915) == 2) 409 mask_size = 30; 410 411 /* 412 * 965GM sometimes incorrectly writes to hardware status page (HWS) 413 * using 32bit addressing, overwriting memory if HWS is located 414 * above 4GB. 415 * 416 * The documentation also mentions an issue with undefined 417 * behaviour if any general state is accessed within a page above 4GB, 418 * which also needs to be handled carefully. 419 */ 420 if (IS_I965G(i915) || IS_I965GM(i915)) 421 mask_size = 32; 422 423 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 424 if (ret) 425 goto mask_err; 426 427 return 0; 428 429 mask_err: 430 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret); 431 return ret; 432 } 433 434 /* Wa_14022698537:dg2 */ 435 static void i915_enable_g8(struct drm_i915_private *i915) 436 { 437 if (IS_DG2(i915)) { 438 if (IS_DG2_D(i915) && !intel_match_g8_cpu()) 439 return; 440 441 snb_pcode_write_p(&i915->uncore, PCODE_POWER_SETUP, 442 POWER_SETUP_SUBCOMMAND_G8_ENABLE, 0, 0); 443 } 444 } 445 446 static int i915_pcode_init(struct drm_i915_private *i915) 447 { 448 struct intel_gt *gt; 449 int id, ret; 450 451 for_each_gt(gt, i915, id) { 452 ret = intel_pcode_init(gt->uncore); 453 if (ret) { 454 gt_err(gt, "intel_pcode_init failed %d\n", ret); 455 return ret; 456 } 457 } 458 459 i915_enable_g8(i915); 460 return 0; 461 } 462 463 /** 464 * i915_driver_hw_probe - setup state requiring device access 465 * @dev_priv: device private 466 * 467 * Setup state that requires accessing the device, but doesn't require 468 * exposing the driver via kernel internal or userspace interfaces. 469 */ 470 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) 471 { 472 struct intel_display *display = dev_priv->display; 473 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 474 int ret; 475 476 if (HAS_PPGTT(dev_priv)) { 477 if (intel_vgpu_active(dev_priv) && 478 !intel_vgpu_has_full_ppgtt(dev_priv)) { 479 drm_err(&dev_priv->drm, 480 "incompatible vGPU found, support for isolated ppGTT required\n"); 481 return -ENXIO; 482 } 483 } 484 485 if (HAS_EXECLISTS(dev_priv)) { 486 /* 487 * Older GVT emulation depends upon intercepting CSB mmio, 488 * which we no longer use, preferring to use the HWSP cache 489 * instead. 490 */ 491 if (intel_vgpu_active(dev_priv) && 492 !intel_vgpu_has_hwsp_emulation(dev_priv)) { 493 drm_err(&dev_priv->drm, 494 "old vGPU host found, support for HWSP emulation required\n"); 495 return -ENXIO; 496 } 497 } 498 499 /* needs to be done before ggtt probe */ 500 i915_edram_detect(dev_priv); 501 502 ret = i915_set_dma_info(dev_priv); 503 if (ret) 504 return ret; 505 506 ret = i915_perf_init(dev_priv); 507 if (ret) 508 return ret; 509 510 ret = i915_ggtt_probe_hw(dev_priv); 511 if (ret) 512 goto err_perf; 513 514 ret = aperture_remove_conflicting_pci_devices(pdev, dev_priv->drm.driver->name); 515 if (ret) 516 goto err_ggtt; 517 518 ret = i915_ggtt_init_hw(dev_priv); 519 if (ret) 520 goto err_ggtt; 521 522 /* 523 * Make sure we probe lmem before we probe stolen-lmem. The BAR size 524 * might be different due to bar resizing. 525 */ 526 ret = intel_gt_tiles_init(dev_priv); 527 if (ret) 528 goto err_ggtt; 529 530 ret = intel_memory_regions_hw_probe(dev_priv); 531 if (ret) 532 goto err_ggtt; 533 534 ret = i915_ggtt_enable_hw(dev_priv); 535 if (ret) { 536 drm_err(&dev_priv->drm, "failed to enable GGTT\n"); 537 goto err_mem_regions; 538 } 539 540 pci_set_master(pdev); 541 542 /* On the 945G/GM, the chipset reports the MSI capability on the 543 * integrated graphics even though the support isn't actually there 544 * according to the published specs. It doesn't appear to function 545 * correctly in testing on 945G. 546 * This may be a side effect of MSI having been made available for PEG 547 * and the registers being closely associated. 548 * 549 * According to chipset errata, on the 965GM, MSI interrupts may 550 * be lost or delayed, and was defeatured. MSI interrupts seem to 551 * get lost on g4x as well, and interrupt delivery seems to stay 552 * properly dead afterwards. So we'll just disable them for all 553 * pre-gen5 chipsets. 554 * 555 * dp aux and gmbus irq on gen4 seems to be able to generate legacy 556 * interrupts even when in MSI mode. This results in spurious 557 * interrupt warnings if the legacy irq no. is shared with another 558 * device. The kernel then disables that interrupt source and so 559 * prevents the other device from working properly. 560 */ 561 if (GRAPHICS_VER(dev_priv) >= 5) { 562 if (pci_enable_msi(pdev) < 0) 563 drm_dbg(&dev_priv->drm, "can't enable MSI"); 564 } 565 566 intel_opregion_setup(display); 567 568 ret = i915_pcode_init(dev_priv); 569 if (ret) 570 goto err_opregion; 571 572 /* 573 * Fill the dram structure to get the system dram info. This will be 574 * used for memory latency calculation. 575 */ 576 ret = intel_dram_detect(display); 577 if (ret) 578 goto err_opregion; 579 580 intel_bw_init_hw(display); 581 582 return 0; 583 584 err_opregion: 585 intel_opregion_cleanup(display); 586 if (pdev->msi_enabled) 587 pci_disable_msi(pdev); 588 err_mem_regions: 589 intel_memory_regions_driver_release(dev_priv); 590 err_ggtt: 591 i915_ggtt_driver_release(dev_priv); 592 i915_gem_drain_freed_objects(dev_priv); 593 i915_ggtt_driver_late_release(dev_priv); 594 err_perf: 595 i915_perf_fini(dev_priv); 596 return ret; 597 } 598 ALLOW_ERROR_INJECTION(i915_driver_hw_probe, ERRNO); 599 600 /** 601 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe() 602 * @dev_priv: device private 603 */ 604 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv) 605 { 606 struct intel_display *display = dev_priv->display; 607 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 608 609 i915_perf_fini(dev_priv); 610 611 intel_opregion_cleanup(display); 612 613 if (pdev->msi_enabled) 614 pci_disable_msi(pdev); 615 } 616 617 /** 618 * i915_driver_register - register the driver with the rest of the system 619 * @dev_priv: device private 620 * 621 * Perform any steps necessary to make the driver available via kernel 622 * internal or userspace interfaces. 623 */ 624 static int i915_driver_register(struct drm_i915_private *dev_priv) 625 { 626 struct intel_display *display = dev_priv->display; 627 struct intel_gt *gt; 628 unsigned int i; 629 int ret; 630 631 i915_gem_driver_register(dev_priv); 632 i915_pmu_register(dev_priv); 633 634 intel_vgpu_register(dev_priv); 635 636 /* Reveal our presence to userspace */ 637 ret = drm_dev_register(&dev_priv->drm, 0); 638 if (ret) { 639 i915_probe_error(dev_priv, 640 "Failed to register driver for userspace access!\n"); 641 drm_dev_unregister(&dev_priv->drm); 642 i915_pmu_unregister(dev_priv); 643 i915_gem_driver_unregister(dev_priv); 644 return ret; 645 } 646 647 i915_debugfs_register(dev_priv); 648 i915_setup_sysfs(dev_priv); 649 650 /* Depends on sysfs having been initialized */ 651 i915_perf_register(dev_priv); 652 653 for_each_gt(gt, dev_priv, i) 654 intel_gt_driver_register(gt); 655 656 intel_pxp_debugfs_register(dev_priv->pxp); 657 658 i915_hwmon_register(dev_priv); 659 660 intel_display_driver_register(display); 661 662 intel_power_domains_enable(display); 663 intel_runtime_pm_enable(&dev_priv->runtime_pm); 664 665 if (i915_switcheroo_register(dev_priv)) 666 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n"); 667 668 return 0; 669 } 670 671 /** 672 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() 673 * @dev_priv: device private 674 */ 675 static void i915_driver_unregister(struct drm_i915_private *dev_priv) 676 { 677 struct intel_display *display = dev_priv->display; 678 struct intel_gt *gt; 679 unsigned int i; 680 681 i915_switcheroo_unregister(dev_priv); 682 683 intel_runtime_pm_disable(&dev_priv->runtime_pm); 684 intel_power_domains_disable(display); 685 686 intel_display_driver_unregister(display); 687 688 intel_pxp_fini(dev_priv); 689 690 for_each_gt(gt, dev_priv, i) 691 intel_gt_driver_unregister(gt); 692 693 i915_hwmon_unregister(dev_priv); 694 695 i915_perf_unregister(dev_priv); 696 i915_pmu_unregister(dev_priv); 697 698 i915_teardown_sysfs(dev_priv); 699 drm_dev_unplug(&dev_priv->drm); 700 701 i915_gem_driver_unregister(dev_priv); 702 } 703 704 void 705 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p) 706 { 707 drm_printf(p, "iommu: %s\n", 708 str_enabled_disabled(i915_vtd_active(i915))); 709 } 710 711 static void i915_welcome_messages(struct drm_i915_private *dev_priv) 712 { 713 if (drm_debug_enabled(DRM_UT_DRIVER)) { 714 struct drm_printer p = drm_dbg_printer(&dev_priv->drm, DRM_UT_DRIVER, 715 "device info:"); 716 struct intel_gt *gt; 717 unsigned int i; 718 719 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n", 720 INTEL_DEVID(dev_priv), 721 INTEL_REVID(dev_priv), 722 intel_platform_name(INTEL_INFO(dev_priv)->platform), 723 intel_subplatform(RUNTIME_INFO(dev_priv), 724 INTEL_INFO(dev_priv)->platform), 725 GRAPHICS_VER(dev_priv)); 726 727 intel_device_info_print(INTEL_INFO(dev_priv), 728 RUNTIME_INFO(dev_priv), &p); 729 i915_print_iommu_status(dev_priv, &p); 730 for_each_gt(gt, dev_priv, i) 731 intel_gt_info_print(>->info, &p); 732 } 733 734 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) 735 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n"); 736 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 737 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n"); 738 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) 739 drm_info(&dev_priv->drm, 740 "DRM_I915_DEBUG_RUNTIME_PM enabled\n"); 741 } 742 743 static void fence_priority_display(struct dma_fence *fence) 744 { 745 if (dma_fence_is_i915(fence)) 746 i915_gem_fence_wait_priority_display(fence); 747 } 748 749 static bool has_auxccs(struct drm_device *drm) 750 { 751 struct drm_i915_private *i915 = to_i915(drm); 752 753 return IS_GRAPHICS_VER(i915, 9, 12) && 754 !HAS_FLAT_CCS(i915); 755 } 756 757 static bool has_fenced_regions(struct drm_device *drm) 758 { 759 return intel_gt_support_legacy_fencing(to_gt(to_i915(drm))); 760 } 761 762 static bool vgpu_active(struct drm_device *drm) 763 { 764 return intel_vgpu_active(to_i915(drm)); 765 } 766 767 static const struct intel_display_parent_interface parent = { 768 .bo = &i915_display_bo_interface, 769 .dpt = &i915_display_dpt_interface, 770 .dsb = &i915_display_dsb_interface, 771 .frontbuffer = &i915_display_frontbuffer_interface, 772 .hdcp = &i915_display_hdcp_interface, 773 .initial_plane = &i915_display_initial_plane_interface, 774 .irq = &i915_display_irq_interface, 775 .overlay = &i915_display_overlay_interface, 776 .panic = &i915_display_panic_interface, 777 .pc8 = &i915_display_pc8_interface, 778 .pcode = &i915_display_pcode_interface, 779 .rpm = &i915_display_rpm_interface, 780 .rps = &i915_display_rps_interface, 781 .stolen = &i915_display_stolen_interface, 782 .vma = &i915_display_vma_interface, 783 784 .fence_priority_display = fence_priority_display, 785 .has_auxccs = has_auxccs, 786 .has_fenced_regions = has_fenced_regions, 787 .vgpu_active = vgpu_active, 788 }; 789 790 const struct intel_display_parent_interface *i915_driver_parent_interface(void) 791 { 792 return &parent; 793 } 794 795 /* Ensure drm and display members are placed properly. */ 796 INTEL_DISPLAY_MEMBER_STATIC_ASSERT(struct drm_i915_private, drm, display); 797 798 static struct drm_i915_private * 799 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) 800 { 801 const struct intel_device_info *match_info = 802 (struct intel_device_info *)ent->driver_data; 803 struct drm_i915_private *i915; 804 struct intel_display *display; 805 806 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver, 807 struct drm_i915_private, drm); 808 if (IS_ERR(i915)) 809 return i915; 810 811 pci_set_drvdata(pdev, &i915->drm); 812 813 /* Device parameters start as a copy of module parameters. */ 814 i915_params_copy(&i915->params, &i915_modparams); 815 816 /* Set up device info and initial runtime info. */ 817 intel_device_info_driver_create(i915, pdev->device, match_info); 818 819 display = intel_display_device_probe(pdev, &parent); 820 if (IS_ERR(display)) 821 return ERR_CAST(display); 822 823 i915->display = display; 824 825 return i915; 826 } 827 828 /** 829 * i915_driver_probe - setup chip and create an initial config 830 * @pdev: PCI device 831 * @ent: matching PCI ID entry 832 * 833 * The driver probe routine has to do several things: 834 * - drive output discovery via intel_display_driver_probe() 835 * - initialize the memory manager 836 * - allocate initial config memory 837 * - setup the DRM framebuffer with the allocated memory 838 */ 839 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 840 { 841 struct drm_i915_private *i915; 842 struct intel_display *display; 843 int ret; 844 845 ret = pci_enable_device(pdev); 846 if (ret) { 847 pr_err("Failed to enable graphics device: %pe\n", ERR_PTR(ret)); 848 return ret; 849 } 850 851 i915 = i915_driver_create(pdev, ent); 852 if (IS_ERR(i915)) { 853 pci_disable_device(pdev); 854 return PTR_ERR(i915); 855 } 856 857 display = i915->display; 858 859 ret = i915_driver_early_probe(i915); 860 if (ret < 0) 861 goto out_pci_disable; 862 863 disable_rpm_wakeref_asserts(&i915->runtime_pm); 864 865 intel_vgpu_detect(i915); 866 867 ret = intel_gt_probe_all(i915); 868 if (ret < 0) 869 goto out_runtime_pm_put; 870 871 ret = i915_driver_mmio_probe(i915); 872 if (ret < 0) 873 goto out_runtime_pm_put; 874 875 ret = i915_driver_hw_probe(i915); 876 if (ret < 0) 877 goto out_cleanup_mmio; 878 879 ret = intel_gvt_init(i915); 880 if (ret) 881 goto out_cleanup_hw; 882 883 ret = intel_display_driver_probe_noirq(display); 884 if (ret < 0) 885 goto out_cleanup_gvt; 886 887 ret = intel_irq_install(i915); 888 if (ret) 889 goto out_cleanup_modeset; 890 891 ret = intel_display_driver_probe_nogem(display); 892 if (ret) 893 goto out_cleanup_irq; 894 895 ret = i915_gem_init(i915); 896 if (ret) 897 goto out_cleanup_modeset2; 898 899 ret = intel_pxp_init(i915); 900 if (ret && ret != -ENODEV) 901 drm_dbg(&i915->drm, "pxp init failed with %d\n", ret); 902 903 ret = intel_display_driver_probe(display); 904 if (ret) 905 goto out_cleanup_gem; 906 907 ret = i915_driver_register(i915); 908 if (ret) 909 goto out_cleanup_gem; 910 911 enable_rpm_wakeref_asserts(&i915->runtime_pm); 912 913 i915_welcome_messages(i915); 914 915 i915->do_release = true; 916 917 return 0; 918 919 out_cleanup_gem: 920 intel_pxp_fini(i915); 921 i915_gem_suspend(i915); 922 i915_gem_driver_remove(i915); 923 i915_gem_driver_release(i915); 924 out_cleanup_modeset2: 925 /* FIXME clean up the error path */ 926 intel_display_driver_remove(display); 927 intel_irq_uninstall(i915); 928 intel_display_driver_remove_noirq(display); 929 goto out_cleanup_modeset; 930 out_cleanup_irq: 931 intel_irq_uninstall(i915); 932 out_cleanup_modeset: 933 intel_display_driver_remove_nogem(display); 934 out_cleanup_gvt: 935 intel_gvt_driver_remove(i915); 936 out_cleanup_hw: 937 i915_driver_hw_remove(i915); 938 intel_memory_regions_driver_release(i915); 939 i915_ggtt_driver_release(i915); 940 i915_gem_drain_freed_objects(i915); 941 i915_ggtt_driver_late_release(i915); 942 out_cleanup_mmio: 943 i915_driver_mmio_release(i915); 944 out_runtime_pm_put: 945 enable_rpm_wakeref_asserts(&i915->runtime_pm); 946 i915_driver_late_release(i915); 947 out_pci_disable: 948 pci_disable_device(pdev); 949 i915_probe_error(i915, "Device initialization failed (%d)\n", ret); 950 return ret; 951 } 952 953 void i915_driver_remove(struct drm_i915_private *i915) 954 { 955 struct intel_display *display = i915->display; 956 intel_wakeref_t wakeref; 957 958 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 959 960 i915_driver_unregister(i915); 961 962 /* Flush any external code that still may be under the RCU lock */ 963 synchronize_rcu(); 964 965 i915_gem_suspend(i915); 966 967 intel_gvt_driver_remove(i915); 968 969 intel_display_driver_remove(display); 970 971 intel_irq_uninstall(i915); 972 973 intel_display_driver_remove_noirq(display); 974 975 i915_reset_error_state(i915); 976 i915_gem_driver_remove(i915); 977 978 intel_display_driver_remove_nogem(display); 979 980 i915_driver_hw_remove(i915); 981 982 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 983 } 984 985 static void i915_driver_release(struct drm_device *dev) 986 { 987 struct drm_i915_private *dev_priv = to_i915(dev); 988 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 989 intel_wakeref_t wakeref; 990 991 if (!dev_priv->do_release) 992 return; 993 994 wakeref = intel_runtime_pm_get(rpm); 995 996 i915_gem_driver_release(dev_priv); 997 998 intel_memory_regions_driver_release(dev_priv); 999 i915_ggtt_driver_release(dev_priv); 1000 i915_gem_drain_freed_objects(dev_priv); 1001 i915_ggtt_driver_late_release(dev_priv); 1002 1003 i915_driver_mmio_release(dev_priv); 1004 1005 intel_runtime_pm_put(rpm, wakeref); 1006 1007 intel_runtime_pm_driver_release(rpm); 1008 1009 i915_driver_late_release(dev_priv); 1010 } 1011 1012 static int i915_driver_open(struct drm_device *dev, struct drm_file *file) 1013 { 1014 struct drm_i915_private *i915 = to_i915(dev); 1015 int ret; 1016 1017 ret = i915_gem_open(i915, file); 1018 if (ret) 1019 return ret; 1020 1021 return 0; 1022 } 1023 1024 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) 1025 { 1026 struct drm_i915_file_private *file_priv = file->driver_priv; 1027 1028 i915_gem_context_close(file); 1029 i915_drm_client_put(file_priv->client); 1030 1031 kfree_rcu(file_priv, rcu); 1032 1033 /* Catch up with all the deferred frees from "this" client */ 1034 i915_gem_flush_free_objects(to_i915(dev)); 1035 } 1036 1037 void i915_driver_shutdown(struct drm_i915_private *i915) 1038 { 1039 struct intel_display *display = i915->display; 1040 1041 disable_rpm_wakeref_asserts(&i915->runtime_pm); 1042 intel_runtime_pm_disable(&i915->runtime_pm); 1043 intel_power_domains_disable(display); 1044 1045 drm_client_dev_suspend(&i915->drm); 1046 if (intel_display_device_present(display)) { 1047 drm_kms_helper_poll_disable(&i915->drm); 1048 intel_display_driver_disable_user_access(display); 1049 1050 drm_atomic_helper_shutdown(&i915->drm); 1051 } 1052 1053 intel_dp_mst_suspend(display); 1054 1055 intel_irq_suspend(i915); 1056 intel_hpd_cancel_work(display); 1057 1058 if (intel_display_device_present(display)) 1059 intel_display_driver_suspend_access(display); 1060 1061 intel_encoder_suspend_all(display); 1062 intel_encoder_shutdown_all(display); 1063 1064 intel_dmc_suspend(display); 1065 1066 i915_gem_suspend(i915); 1067 1068 /* 1069 * The only requirement is to reboot with display DC states disabled, 1070 * for now leaving all display power wells in the INIT power domain 1071 * enabled. 1072 * 1073 * TODO: 1074 * - unify the pci_driver::shutdown sequence here with the 1075 * pci_driver.driver.pm.poweroff,poweroff_late sequence. 1076 * - unify the driver remove and system/runtime suspend sequences with 1077 * the above unified shutdown/poweroff sequence. 1078 */ 1079 intel_power_domains_driver_remove(display); 1080 enable_rpm_wakeref_asserts(&i915->runtime_pm); 1081 1082 intel_runtime_pm_driver_last_release(&i915->runtime_pm); 1083 } 1084 1085 static bool suspend_to_idle(struct drm_i915_private *dev_priv) 1086 { 1087 #if IS_ENABLED(CONFIG_ACPI_SLEEP) 1088 if (acpi_target_system_state() < ACPI_STATE_S3) 1089 return true; 1090 #endif 1091 return false; 1092 } 1093 1094 static void i915_drm_complete(struct drm_device *dev) 1095 { 1096 struct drm_i915_private *i915 = to_i915(dev); 1097 1098 intel_pxp_resume_complete(i915->pxp); 1099 } 1100 1101 static int i915_drm_prepare(struct drm_device *dev) 1102 { 1103 struct drm_i915_private *i915 = to_i915(dev); 1104 1105 intel_pxp_suspend_prepare(i915->pxp); 1106 1107 /* 1108 * NB intel_display_driver_suspend() may issue new requests after we've 1109 * ostensibly marked the GPU as ready-to-sleep here. We need to 1110 * split out that work and pull it forward so that after point, 1111 * the GPU is not woken again. 1112 */ 1113 return i915_gem_backup_suspend(i915); 1114 } 1115 1116 static int i915_drm_suspend(struct drm_device *dev) 1117 { 1118 struct drm_i915_private *dev_priv = to_i915(dev); 1119 struct intel_display *display = dev_priv->display; 1120 pci_power_t opregion_target_state; 1121 1122 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1123 1124 /* We do a lot of poking in a lot of registers, make sure they work 1125 * properly. */ 1126 intel_power_domains_disable(display); 1127 drm_client_dev_suspend(dev); 1128 if (intel_display_device_present(display)) { 1129 drm_kms_helper_poll_disable(dev); 1130 intel_display_driver_disable_user_access(display); 1131 } 1132 1133 intel_display_driver_suspend(display); 1134 1135 intel_irq_suspend(dev_priv); 1136 intel_hpd_cancel_work(display); 1137 1138 if (intel_display_device_present(display)) 1139 intel_display_driver_suspend_access(display); 1140 1141 intel_encoder_suspend_all(display); 1142 1143 /* Must be called before GGTT is suspended. */ 1144 intel_dpt_suspend(display); 1145 i915_ggtt_suspend(to_gt(dev_priv)->ggtt); 1146 1147 i9xx_display_sr_save(display); 1148 1149 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; 1150 intel_opregion_suspend(display, opregion_target_state); 1151 1152 dev_priv->suspend_count++; 1153 1154 intel_dmc_suspend(display); 1155 1156 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1157 1158 i915_gem_drain_freed_objects(dev_priv); 1159 1160 return 0; 1161 } 1162 1163 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) 1164 { 1165 struct drm_i915_private *dev_priv = to_i915(dev); 1166 struct intel_display *display = dev_priv->display; 1167 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1168 struct intel_gt *gt; 1169 int ret, i; 1170 bool s2idle = !hibernation && suspend_to_idle(dev_priv); 1171 1172 disable_rpm_wakeref_asserts(rpm); 1173 1174 intel_pxp_suspend(dev_priv->pxp); 1175 1176 i915_gem_suspend_late(dev_priv); 1177 1178 for_each_gt(gt, dev_priv, i) 1179 intel_uncore_suspend(gt->uncore); 1180 1181 intel_display_power_suspend_late(display, s2idle); 1182 1183 ret = vlv_suspend_complete(dev_priv); 1184 if (ret) { 1185 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret); 1186 intel_display_power_resume_early(display); 1187 } 1188 1189 enable_rpm_wakeref_asserts(rpm); 1190 1191 if (!dev_priv->uncore.user_forcewake_count) 1192 intel_runtime_pm_driver_release(rpm); 1193 1194 return ret; 1195 } 1196 1197 static int i915_drm_suspend_noirq(struct drm_device *dev, bool hibernation) 1198 { 1199 struct drm_i915_private *dev_priv = to_i915(dev); 1200 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1201 1202 /* 1203 * During hibernation on some platforms the BIOS may try to access 1204 * the device even though it's already in D3 and hang the machine. So 1205 * leave the device in D0 on those platforms and hope the BIOS will 1206 * power down the device properly. The issue was seen on multiple old 1207 * GENs with different BIOS vendors, so having an explicit blacklist 1208 * is impractical; apply the workaround on everything pre GEN6. The 1209 * platforms where the issue was seen: 1210 * Lenovo Thinkpad X301, X61s, X60, T60, X41 1211 * Fujitsu FSC S7110 1212 * Acer Aspire 1830T 1213 * 1214 * pci_save_state() prevents drivers/pci from 1215 * automagically putting the device into D3. 1216 */ 1217 if (hibernation && GRAPHICS_VER(dev_priv) < 6) 1218 pci_save_state(pdev); 1219 1220 return 0; 1221 } 1222 1223 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915, 1224 pm_message_t state) 1225 { 1226 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 1227 int error; 1228 1229 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND && 1230 state.event != PM_EVENT_FREEZE)) 1231 return -EINVAL; 1232 1233 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1234 return 0; 1235 1236 error = i915_drm_suspend(&i915->drm); 1237 if (error) 1238 return error; 1239 1240 error = i915_drm_suspend_late(&i915->drm, false); 1241 if (error) 1242 return error; 1243 1244 pci_save_state(pdev); 1245 pci_set_power_state(pdev, PCI_D3hot); 1246 1247 return 0; 1248 } 1249 1250 static int i915_drm_resume(struct drm_device *dev) 1251 { 1252 struct drm_i915_private *dev_priv = to_i915(dev); 1253 struct intel_display *display = dev_priv->display; 1254 struct intel_gt *gt; 1255 int ret, i; 1256 1257 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1258 1259 ret = i915_pcode_init(dev_priv); 1260 if (ret) 1261 return ret; 1262 1263 sanitize_gpu(dev_priv); 1264 1265 ret = i915_ggtt_enable_hw(dev_priv); 1266 if (ret) 1267 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n"); 1268 1269 i915_ggtt_resume(to_gt(dev_priv)->ggtt); 1270 1271 for_each_gt(gt, dev_priv, i) 1272 if (GRAPHICS_VER(gt->i915) >= 8) 1273 setup_private_pat(gt); 1274 1275 /* Must be called after GGTT is resumed. */ 1276 intel_dpt_resume(display); 1277 1278 intel_dmc_resume(display); 1279 1280 i9xx_display_sr_restore(display); 1281 1282 intel_gmbus_reset(display); 1283 1284 intel_pps_unlock_regs_wa(display); 1285 1286 intel_init_pch_refclk(display); 1287 1288 /* 1289 * Interrupts have to be enabled before any batches are run. If not the 1290 * GPU will hang. i915_gem_init_hw() will initiate batches to 1291 * update/restore the context. 1292 * 1293 * drm_mode_config_reset() needs AUX interrupts. 1294 * 1295 * Modeset enabling in intel_display_driver_init_hw() also needs working 1296 * interrupts. 1297 */ 1298 intel_irq_resume(dev_priv); 1299 1300 if (intel_display_device_present(display)) 1301 drm_mode_config_reset(dev); 1302 1303 i915_gem_resume(dev_priv); 1304 1305 intel_display_driver_init_hw(display); 1306 1307 intel_clock_gating_init(&dev_priv->drm); 1308 1309 if (intel_display_device_present(display)) 1310 intel_display_driver_resume_access(display); 1311 1312 intel_hpd_init(display); 1313 1314 intel_display_driver_resume(display); 1315 1316 if (intel_display_device_present(display)) { 1317 intel_display_driver_enable_user_access(display); 1318 drm_kms_helper_poll_enable(dev); 1319 } 1320 intel_hpd_poll_disable(display); 1321 1322 intel_opregion_resume(display); 1323 1324 drm_client_dev_resume(dev); 1325 1326 intel_power_domains_enable(display); 1327 1328 intel_gvt_resume(dev_priv); 1329 1330 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1331 1332 return 0; 1333 } 1334 1335 static int i915_drm_resume_early(struct drm_device *dev) 1336 { 1337 struct drm_i915_private *dev_priv = to_i915(dev); 1338 struct intel_display *display = dev_priv->display; 1339 struct intel_gt *gt; 1340 int ret, i; 1341 1342 /* 1343 * We have a resume ordering issue with the snd-hda driver also 1344 * requiring our device to be power up. Due to the lack of a 1345 * parent/child relationship we currently solve this with an early 1346 * resume hook. 1347 * 1348 * FIXME: This should be solved with a special hdmi sink device or 1349 * similar so that power domains can be employed. 1350 */ 1351 1352 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1353 1354 ret = vlv_resume_prepare(dev_priv, false); 1355 if (ret) 1356 drm_err(&dev_priv->drm, 1357 "Resume prepare failed: %d, continuing anyway\n", ret); 1358 1359 for_each_gt(gt, dev_priv, i) 1360 intel_gt_resume_early(gt); 1361 1362 intel_display_power_resume_early(display); 1363 1364 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1365 1366 return ret; 1367 } 1368 1369 int i915_driver_resume_switcheroo(struct drm_i915_private *i915) 1370 { 1371 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 1372 int ret; 1373 1374 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1375 return 0; 1376 1377 ret = pci_set_power_state(pdev, PCI_D0); 1378 if (ret) 1379 return ret; 1380 1381 pci_restore_state(pdev); 1382 1383 ret = i915_drm_resume_early(&i915->drm); 1384 if (ret) 1385 return ret; 1386 1387 return i915_drm_resume(&i915->drm); 1388 } 1389 1390 static int i915_pm_prepare(struct device *kdev) 1391 { 1392 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1393 1394 if (!i915) { 1395 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1396 return -ENODEV; 1397 } 1398 1399 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1400 return 0; 1401 1402 return i915_drm_prepare(&i915->drm); 1403 } 1404 1405 static int i915_pm_suspend(struct device *kdev) 1406 { 1407 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1408 1409 if (!i915) { 1410 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1411 return -ENODEV; 1412 } 1413 1414 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1415 return 0; 1416 1417 return i915_drm_suspend(&i915->drm); 1418 } 1419 1420 static int i915_pm_suspend_late(struct device *kdev) 1421 { 1422 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1423 1424 /* 1425 * We have a suspend ordering issue with the snd-hda driver also 1426 * requiring our device to be power up. Due to the lack of a 1427 * parent/child relationship we currently solve this with an late 1428 * suspend hook. 1429 * 1430 * FIXME: This should be solved with a special hdmi sink device or 1431 * similar so that power domains can be employed. 1432 */ 1433 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1434 return 0; 1435 1436 return i915_drm_suspend_late(&i915->drm, false); 1437 } 1438 1439 static int i915_pm_suspend_noirq(struct device *kdev) 1440 { 1441 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1442 1443 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1444 return 0; 1445 1446 return i915_drm_suspend_noirq(&i915->drm, false); 1447 } 1448 1449 static int i915_pm_poweroff_late(struct device *kdev) 1450 { 1451 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1452 1453 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1454 return 0; 1455 1456 return i915_drm_suspend_late(&i915->drm, true); 1457 } 1458 1459 static int i915_pm_poweroff_noirq(struct device *kdev) 1460 { 1461 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1462 1463 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1464 return 0; 1465 1466 return i915_drm_suspend_noirq(&i915->drm, true); 1467 } 1468 1469 static int i915_pm_resume_early(struct device *kdev) 1470 { 1471 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1472 1473 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1474 return 0; 1475 1476 return i915_drm_resume_early(&i915->drm); 1477 } 1478 1479 static int i915_pm_resume(struct device *kdev) 1480 { 1481 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1482 1483 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1484 return 0; 1485 1486 return i915_drm_resume(&i915->drm); 1487 } 1488 1489 static void i915_pm_complete(struct device *kdev) 1490 { 1491 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1492 1493 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1494 return; 1495 1496 i915_drm_complete(&i915->drm); 1497 } 1498 1499 /* freeze: before creating the hibernation_image */ 1500 static int i915_pm_freeze(struct device *kdev) 1501 { 1502 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1503 int ret; 1504 1505 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1506 ret = i915_drm_suspend(&i915->drm); 1507 if (ret) 1508 return ret; 1509 } 1510 1511 ret = i915_gem_freeze(i915); 1512 if (ret) 1513 return ret; 1514 1515 return 0; 1516 } 1517 1518 static int i915_pm_freeze_late(struct device *kdev) 1519 { 1520 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1521 int ret; 1522 1523 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1524 ret = i915_drm_suspend_late(&i915->drm, true); 1525 if (ret) 1526 return ret; 1527 } 1528 1529 ret = i915_gem_freeze_late(i915); 1530 if (ret) 1531 return ret; 1532 1533 return 0; 1534 } 1535 1536 /* thaw: called after creating the hibernation image, but before turning off. */ 1537 static int i915_pm_thaw_early(struct device *kdev) 1538 { 1539 return i915_pm_resume_early(kdev); 1540 } 1541 1542 static int i915_pm_thaw(struct device *kdev) 1543 { 1544 return i915_pm_resume(kdev); 1545 } 1546 1547 /* restore: called after loading the hibernation image. */ 1548 static int i915_pm_restore_early(struct device *kdev) 1549 { 1550 return i915_pm_resume_early(kdev); 1551 } 1552 1553 static int i915_pm_restore(struct device *kdev) 1554 { 1555 return i915_pm_resume(kdev); 1556 } 1557 1558 static int intel_runtime_suspend(struct device *kdev) 1559 { 1560 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1561 struct intel_display *display = dev_priv->display; 1562 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1563 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1564 struct pci_dev *root_pdev; 1565 struct intel_gt *gt; 1566 int ret, i; 1567 1568 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1569 return -ENODEV; 1570 1571 drm_dbg(&dev_priv->drm, "Suspending device\n"); 1572 1573 disable_rpm_wakeref_asserts(rpm); 1574 1575 /* 1576 * We are safe here against re-faults, since the fault handler takes 1577 * an RPM reference. 1578 */ 1579 i915_gem_runtime_suspend(dev_priv); 1580 1581 intel_pxp_runtime_suspend(dev_priv->pxp); 1582 1583 for_each_gt(gt, dev_priv, i) 1584 intel_gt_runtime_suspend(gt); 1585 1586 intel_irq_suspend(dev_priv); 1587 1588 for_each_gt(gt, dev_priv, i) 1589 intel_uncore_suspend(gt->uncore); 1590 1591 intel_display_power_suspend(display); 1592 1593 ret = vlv_suspend_complete(dev_priv); 1594 if (ret) { 1595 drm_err(&dev_priv->drm, 1596 "Runtime suspend failed, disabling it (%d)\n", ret); 1597 intel_uncore_runtime_resume(&dev_priv->uncore); 1598 1599 intel_irq_resume(dev_priv); 1600 1601 for_each_gt(gt, dev_priv, i) 1602 intel_gt_runtime_resume(gt); 1603 1604 enable_rpm_wakeref_asserts(rpm); 1605 1606 return ret; 1607 } 1608 1609 enable_rpm_wakeref_asserts(rpm); 1610 intel_runtime_pm_driver_release(rpm); 1611 1612 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore)) 1613 drm_err(&dev_priv->drm, 1614 "Unclaimed access detected prior to suspending\n"); 1615 1616 /* 1617 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX 1618 * This should be totally removed when we handle the pci states properly 1619 * on runtime PM. 1620 */ 1621 root_pdev = pcie_find_root_port(pdev); 1622 if (root_pdev) 1623 pci_d3cold_disable(root_pdev); 1624 1625 /* 1626 * FIXME: We really should find a document that references the arguments 1627 * used below! 1628 */ 1629 if (IS_BROADWELL(dev_priv)) { 1630 /* 1631 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop 1632 * being detected, and the call we do at intel_runtime_resume() 1633 * won't be able to restore them. Since PCI_D3hot matches the 1634 * actual specification and appears to be working, use it. 1635 */ 1636 intel_opregion_notify_adapter(display, PCI_D3hot); 1637 } else { 1638 /* 1639 * current versions of firmware which depend on this opregion 1640 * notification have repurposed the D1 definition to mean 1641 * "runtime suspended" vs. what you would normally expect (D3) 1642 * to distinguish it from notifications that might be sent via 1643 * the suspend path. 1644 */ 1645 intel_opregion_notify_adapter(display, PCI_D1); 1646 } 1647 1648 assert_forcewakes_inactive(&dev_priv->uncore); 1649 1650 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) 1651 intel_hpd_poll_enable(display); 1652 1653 drm_dbg(&dev_priv->drm, "Device suspended\n"); 1654 return 0; 1655 } 1656 1657 static int intel_runtime_resume(struct device *kdev) 1658 { 1659 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1660 struct intel_display *display = dev_priv->display; 1661 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1662 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1663 struct pci_dev *root_pdev; 1664 struct intel_gt *gt; 1665 int ret, i; 1666 1667 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1668 return -ENODEV; 1669 1670 drm_dbg(&dev_priv->drm, "Resuming device\n"); 1671 1672 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count)); 1673 disable_rpm_wakeref_asserts(rpm); 1674 1675 intel_opregion_notify_adapter(display, PCI_D0); 1676 1677 root_pdev = pcie_find_root_port(pdev); 1678 if (root_pdev) 1679 pci_d3cold_enable(root_pdev); 1680 1681 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore)) 1682 drm_dbg(&dev_priv->drm, 1683 "Unclaimed access during suspend, bios?\n"); 1684 1685 intel_display_power_resume(display); 1686 1687 ret = vlv_resume_prepare(dev_priv, true); 1688 1689 for_each_gt(gt, dev_priv, i) 1690 intel_uncore_runtime_resume(gt->uncore); 1691 1692 intel_irq_resume(dev_priv); 1693 1694 /* 1695 * No point of rolling back things in case of an error, as the best 1696 * we can do is to hope that things will still work (and disable RPM). 1697 */ 1698 for_each_gt(gt, dev_priv, i) 1699 intel_gt_runtime_resume(gt); 1700 1701 intel_pxp_runtime_resume(dev_priv->pxp); 1702 1703 /* 1704 * On VLV/CHV display interrupts are part of the display 1705 * power well, so hpd is reinitialized from there. For 1706 * everyone else do it here. 1707 */ 1708 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 1709 intel_hpd_init(display); 1710 intel_hpd_poll_disable(display); 1711 } 1712 1713 skl_watermark_ipc_update(display); 1714 1715 enable_rpm_wakeref_asserts(rpm); 1716 1717 if (ret) 1718 drm_err(&dev_priv->drm, 1719 "Runtime resume failed, disabling it (%d)\n", ret); 1720 else 1721 drm_dbg(&dev_priv->drm, "Device resumed\n"); 1722 1723 return ret; 1724 } 1725 1726 const struct dev_pm_ops i915_pm_ops = { 1727 /* 1728 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, 1729 * PMSG_RESUME] 1730 */ 1731 .prepare = i915_pm_prepare, 1732 .suspend = i915_pm_suspend, 1733 .suspend_late = i915_pm_suspend_late, 1734 .suspend_noirq = i915_pm_suspend_noirq, 1735 .resume_early = i915_pm_resume_early, 1736 .resume = i915_pm_resume, 1737 .complete = i915_pm_complete, 1738 1739 /* 1740 * S4 event handlers 1741 * @freeze* : called (1) before creating the 1742 * hibernation image [PMSG_FREEZE] and 1743 * (2) after rebooting, before restoring 1744 * the image [PMSG_QUIESCE] 1745 * @thaw* : called (1) after creating the hibernation 1746 * image, before writing it [PMSG_THAW] 1747 * and (2) after failing to create or 1748 * restore the image [PMSG_RECOVER] 1749 * @poweroff* : called after writing the hibernation 1750 * image, before rebooting [PMSG_HIBERNATE] 1751 * @restore* : called after rebooting and restoring the 1752 * hibernation image [PMSG_RESTORE] 1753 */ 1754 .freeze = i915_pm_freeze, 1755 .freeze_late = i915_pm_freeze_late, 1756 .thaw_early = i915_pm_thaw_early, 1757 .thaw = i915_pm_thaw, 1758 .poweroff = i915_pm_suspend, 1759 .poweroff_late = i915_pm_poweroff_late, 1760 .poweroff_noirq = i915_pm_poweroff_noirq, 1761 .restore_early = i915_pm_restore_early, 1762 .restore = i915_pm_restore, 1763 1764 /* S0ix (via runtime suspend) event handlers */ 1765 .runtime_suspend = intel_runtime_suspend, 1766 .runtime_resume = intel_runtime_resume, 1767 }; 1768 1769 static const struct file_operations i915_driver_fops = { 1770 .owner = THIS_MODULE, 1771 .open = drm_open, 1772 .release = drm_release_noglobal, 1773 .unlocked_ioctl = drm_ioctl, 1774 .mmap = i915_gem_mmap, 1775 .poll = drm_poll, 1776 .read = drm_read, 1777 .compat_ioctl = i915_ioc32_compat_ioctl, 1778 .llseek = noop_llseek, 1779 #ifdef CONFIG_PROC_FS 1780 .show_fdinfo = drm_show_fdinfo, 1781 #endif 1782 .fop_flags = FOP_UNSIGNED_OFFSET, 1783 }; 1784 1785 static int 1786 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, 1787 struct drm_file *file) 1788 { 1789 return -ENODEV; 1790 } 1791 1792 static const struct drm_ioctl_desc i915_ioctls[] = { 1793 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1794 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), 1795 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), 1796 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), 1797 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), 1798 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), 1799 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW), 1800 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1801 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), 1802 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), 1803 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1804 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), 1805 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1806 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1807 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), 1808 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), 1809 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1810 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1811 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH), 1812 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW), 1813 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1814 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1815 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW), 1816 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), 1817 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), 1818 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW), 1819 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1820 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1821 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), 1822 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW), 1823 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), 1824 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), 1825 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), 1826 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW), 1827 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), 1828 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), 1829 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW), 1830 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW), 1831 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), 1832 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_crtc_get_pipe_from_crtc_id_ioctl, 0), 1833 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), 1834 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER), 1835 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER), 1836 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER), 1837 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER), 1838 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW), 1839 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), 1840 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), 1841 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), 1842 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW), 1843 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), 1844 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), 1845 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), 1846 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), 1847 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW), 1848 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW), 1849 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW), 1850 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW), 1851 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW), 1852 }; 1853 1854 /* 1855 * Interface history: 1856 * 1857 * 1.1: Original. 1858 * 1.2: Add Power Management 1859 * 1.3: Add vblank support 1860 * 1.4: Fix cmdbuffer path, add heap destroy 1861 * 1.5: Add vblank pipe configuration 1862 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 1863 * - Support vertical blank on secondary display pipe 1864 */ 1865 #define DRIVER_MAJOR 1 1866 #define DRIVER_MINOR 6 1867 #define DRIVER_PATCHLEVEL 0 1868 1869 static const struct drm_driver i915_drm_driver = { 1870 /* Don't use MTRRs here; the Xserver or userspace app should 1871 * deal with them for Intel hardware. 1872 */ 1873 .driver_features = 1874 DRIVER_GEM | 1875 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ | 1876 DRIVER_SYNCOBJ_TIMELINE, 1877 .release = i915_driver_release, 1878 .open = i915_driver_open, 1879 .postclose = i915_driver_postclose, 1880 .show_fdinfo = PTR_IF(IS_ENABLED(CONFIG_PROC_FS), i915_drm_client_fdinfo), 1881 1882 .gem_prime_import = i915_gem_prime_import, 1883 1884 .dumb_create = i915_gem_dumb_create, 1885 .dumb_map_offset = i915_gem_dumb_mmap_offset, 1886 1887 INTEL_FBDEV_DRIVER_OPS, 1888 1889 .ioctls = i915_ioctls, 1890 .num_ioctls = ARRAY_SIZE(i915_ioctls), 1891 .fops = &i915_driver_fops, 1892 .name = DRIVER_NAME, 1893 .desc = DRIVER_DESC, 1894 .major = DRIVER_MAJOR, 1895 .minor = DRIVER_MINOR, 1896 .patchlevel = DRIVER_PATCHLEVEL, 1897 }; 1898