1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #include <linux/acpi.h> 31 #include <linux/device.h> 32 #include <linux/module.h> 33 #include <linux/oom.h> 34 #include <linux/pci.h> 35 #include <linux/pm.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/slab.h> 38 #include <linux/string_helpers.h> 39 #include <linux/vga_switcheroo.h> 40 #include <linux/vt.h> 41 42 #include <drm/drm_aperture.h> 43 #include <drm/drm_atomic_helper.h> 44 #include <drm/drm_ioctl.h> 45 #include <drm/drm_managed.h> 46 #include <drm/drm_probe_helper.h> 47 48 #include "display/intel_acpi.h" 49 #include "display/intel_bw.h" 50 #include "display/intel_cdclk.h" 51 #include "display/intel_display_driver.h" 52 #include "display/intel_display_types.h" 53 #include "display/intel_dmc.h" 54 #include "display/intel_dp.h" 55 #include "display/intel_dpt.h" 56 #include "display/intel_encoder.h" 57 #include "display/intel_fbdev.h" 58 #include "display/intel_hotplug.h" 59 #include "display/intel_overlay.h" 60 #include "display/intel_pch_refclk.h" 61 #include "display/intel_pipe_crc.h" 62 #include "display/intel_pps.h" 63 #include "display/intel_sprite.h" 64 #include "display/intel_vga.h" 65 #include "display/skl_watermark.h" 66 67 #include "gem/i915_gem_context.h" 68 #include "gem/i915_gem_create.h" 69 #include "gem/i915_gem_dmabuf.h" 70 #include "gem/i915_gem_ioctls.h" 71 #include "gem/i915_gem_mman.h" 72 #include "gem/i915_gem_pm.h" 73 #include "gt/intel_gt.h" 74 #include "gt/intel_gt_pm.h" 75 #include "gt/intel_gt_print.h" 76 #include "gt/intel_rc6.h" 77 78 #include "pxp/intel_pxp.h" 79 #include "pxp/intel_pxp_debugfs.h" 80 #include "pxp/intel_pxp_pm.h" 81 82 #include "soc/intel_dram.h" 83 #include "soc/intel_gmch.h" 84 85 #include "i915_debugfs.h" 86 #include "i915_driver.h" 87 #include "i915_drm_client.h" 88 #include "i915_drv.h" 89 #include "i915_file_private.h" 90 #include "i915_getparam.h" 91 #include "i915_hwmon.h" 92 #include "i915_ioc32.h" 93 #include "i915_ioctl.h" 94 #include "i915_irq.h" 95 #include "i915_memcpy.h" 96 #include "i915_perf.h" 97 #include "i915_query.h" 98 #include "i915_suspend.h" 99 #include "i915_switcheroo.h" 100 #include "i915_sysfs.h" 101 #include "i915_utils.h" 102 #include "i915_vgpu.h" 103 #include "intel_clock_gating.h" 104 #include "intel_gvt.h" 105 #include "intel_memory_region.h" 106 #include "intel_pci_config.h" 107 #include "intel_pcode.h" 108 #include "intel_region_ttm.h" 109 #include "vlv_suspend.h" 110 111 static const struct drm_driver i915_drm_driver; 112 113 static int i915_workqueues_init(struct drm_i915_private *dev_priv) 114 { 115 /* 116 * The i915 workqueue is primarily used for batched retirement of 117 * requests (and thus managing bo) once the task has been completed 118 * by the GPU. i915_retire_requests() is called directly when we 119 * need high-priority retirement, such as waiting for an explicit 120 * bo. 121 * 122 * It is also used for periodic low-priority events, such as 123 * idle-timers and recording error state. 124 * 125 * All tasks on the workqueue are expected to acquire the dev mutex 126 * so there is no point in running more than one instance of the 127 * workqueue at any time. Use an ordered one. 128 */ 129 dev_priv->wq = alloc_ordered_workqueue("i915", 0); 130 if (dev_priv->wq == NULL) 131 goto out_err; 132 133 dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); 134 if (dev_priv->display.hotplug.dp_wq == NULL) 135 goto out_free_wq; 136 137 /* 138 * The unordered i915 workqueue should be used for all work 139 * scheduling that do not require running in order, which used 140 * to be scheduled on the system_wq before moving to a driver 141 * instance due deprecation of flush_scheduled_work(). 142 */ 143 dev_priv->unordered_wq = alloc_workqueue("i915-unordered", 0, 0); 144 if (dev_priv->unordered_wq == NULL) 145 goto out_free_dp_wq; 146 147 return 0; 148 149 out_free_dp_wq: 150 destroy_workqueue(dev_priv->display.hotplug.dp_wq); 151 out_free_wq: 152 destroy_workqueue(dev_priv->wq); 153 out_err: 154 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n"); 155 156 return -ENOMEM; 157 } 158 159 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) 160 { 161 destroy_workqueue(dev_priv->unordered_wq); 162 destroy_workqueue(dev_priv->display.hotplug.dp_wq); 163 destroy_workqueue(dev_priv->wq); 164 } 165 166 /* 167 * We don't keep the workarounds for pre-production hardware, so we expect our 168 * driver to fail on these machines in one way or another. A little warning on 169 * dmesg may help both the user and the bug triagers. 170 * 171 * Our policy for removing pre-production workarounds is to keep the 172 * current gen workarounds as a guide to the bring-up of the next gen 173 * (workarounds have a habit of persisting!). Anything older than that 174 * should be removed along with the complications they introduce. 175 */ 176 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) 177 { 178 bool pre = false; 179 180 pre |= IS_HASWELL_EARLY_SDV(dev_priv); 181 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6; 182 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA; 183 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 184 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3; 185 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7; 186 pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 187 pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 188 pre |= IS_DG2_G10(dev_priv) && INTEL_REVID(dev_priv) < 0x8; 189 pre |= IS_DG2_G11(dev_priv) && INTEL_REVID(dev_priv) < 0x5; 190 pre |= IS_DG2_G12(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 191 192 if (pre) { 193 drm_err(&dev_priv->drm, "This is a pre-production stepping. " 194 "It may not be fully functional.\n"); 195 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); 196 } 197 } 198 199 static void sanitize_gpu(struct drm_i915_private *i915) 200 { 201 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) { 202 struct intel_gt *gt; 203 unsigned int i; 204 205 for_each_gt(gt, i915, i) 206 intel_gt_reset_all_engines(gt); 207 } 208 } 209 210 /** 211 * i915_driver_early_probe - setup state not requiring device access 212 * @dev_priv: device private 213 * 214 * Initialize everything that is a "SW-only" state, that is state not 215 * requiring accessing the device or exposing the driver via kernel internal 216 * or userspace interfaces. Example steps belonging here: lock initialization, 217 * system memory allocation, setting up device specific attributes and 218 * function hooks not requiring accessing the device. 219 */ 220 static int i915_driver_early_probe(struct drm_i915_private *dev_priv) 221 { 222 int ret = 0; 223 224 if (i915_inject_probe_failure(dev_priv)) 225 return -ENODEV; 226 227 intel_device_info_runtime_init_early(dev_priv); 228 229 intel_step_init(dev_priv); 230 231 intel_uncore_mmio_debug_init_early(dev_priv); 232 233 spin_lock_init(&dev_priv->irq_lock); 234 spin_lock_init(&dev_priv->gpu_error.lock); 235 236 mutex_init(&dev_priv->sb_lock); 237 cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE); 238 239 i915_memcpy_init_early(dev_priv); 240 intel_runtime_pm_init_early(&dev_priv->runtime_pm); 241 242 ret = i915_workqueues_init(dev_priv); 243 if (ret < 0) 244 return ret; 245 246 ret = vlv_suspend_init(dev_priv); 247 if (ret < 0) 248 goto err_workqueues; 249 250 ret = intel_region_ttm_device_init(dev_priv); 251 if (ret) 252 goto err_ttm; 253 254 ret = intel_root_gt_init_early(dev_priv); 255 if (ret < 0) 256 goto err_rootgt; 257 258 i915_gem_init_early(dev_priv); 259 260 /* This must be called before any calls to HAS_PCH_* */ 261 intel_detect_pch(dev_priv); 262 263 intel_irq_init(dev_priv); 264 intel_display_driver_early_probe(dev_priv); 265 intel_clock_gating_hooks_init(dev_priv); 266 267 intel_detect_preproduction_hw(dev_priv); 268 269 return 0; 270 271 err_rootgt: 272 intel_region_ttm_device_fini(dev_priv); 273 err_ttm: 274 vlv_suspend_cleanup(dev_priv); 275 err_workqueues: 276 i915_workqueues_cleanup(dev_priv); 277 return ret; 278 } 279 280 /** 281 * i915_driver_late_release - cleanup the setup done in 282 * i915_driver_early_probe() 283 * @dev_priv: device private 284 */ 285 static void i915_driver_late_release(struct drm_i915_private *dev_priv) 286 { 287 intel_irq_fini(dev_priv); 288 intel_power_domains_cleanup(dev_priv); 289 i915_gem_cleanup_early(dev_priv); 290 intel_gt_driver_late_release_all(dev_priv); 291 intel_region_ttm_device_fini(dev_priv); 292 vlv_suspend_cleanup(dev_priv); 293 i915_workqueues_cleanup(dev_priv); 294 295 cpu_latency_qos_remove_request(&dev_priv->sb_qos); 296 mutex_destroy(&dev_priv->sb_lock); 297 298 i915_params_free(&dev_priv->params); 299 } 300 301 /** 302 * i915_driver_mmio_probe - setup device MMIO 303 * @dev_priv: device private 304 * 305 * Setup minimal device state necessary for MMIO accesses later in the 306 * initialization sequence. The setup here should avoid any other device-wide 307 * side effects or exposing the driver via kernel internal or user space 308 * interfaces. 309 */ 310 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) 311 { 312 struct intel_gt *gt; 313 int ret, i; 314 315 if (i915_inject_probe_failure(dev_priv)) 316 return -ENODEV; 317 318 ret = intel_gmch_bridge_setup(dev_priv); 319 if (ret < 0) 320 return ret; 321 322 for_each_gt(gt, dev_priv, i) { 323 ret = intel_uncore_init_mmio(gt->uncore); 324 if (ret) 325 return ret; 326 327 ret = drmm_add_action_or_reset(&dev_priv->drm, 328 intel_uncore_fini_mmio, 329 gt->uncore); 330 if (ret) 331 return ret; 332 } 333 334 /* Try to make sure MCHBAR is enabled before poking at it */ 335 intel_gmch_bar_setup(dev_priv); 336 intel_device_info_runtime_init(dev_priv); 337 intel_display_device_info_runtime_init(dev_priv); 338 339 for_each_gt(gt, dev_priv, i) { 340 ret = intel_gt_init_mmio(gt); 341 if (ret) 342 goto err_uncore; 343 } 344 345 /* As early as possible, scrub existing GPU state before clobbering */ 346 sanitize_gpu(dev_priv); 347 348 return 0; 349 350 err_uncore: 351 intel_gmch_bar_teardown(dev_priv); 352 353 return ret; 354 } 355 356 /** 357 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe() 358 * @dev_priv: device private 359 */ 360 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv) 361 { 362 intel_gmch_bar_teardown(dev_priv); 363 } 364 365 /** 366 * i915_set_dma_info - set all relevant PCI dma info as configured for the 367 * platform 368 * @i915: valid i915 instance 369 * 370 * Set the dma max segment size, device and coherent masks. The dma mask set 371 * needs to occur before i915_ggtt_probe_hw. 372 * 373 * A couple of platforms have special needs. Address them as well. 374 * 375 */ 376 static int i915_set_dma_info(struct drm_i915_private *i915) 377 { 378 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size; 379 int ret; 380 381 GEM_BUG_ON(!mask_size); 382 383 /* 384 * We don't have a max segment size, so set it to the max so sg's 385 * debugging layer doesn't complain 386 */ 387 dma_set_max_seg_size(i915->drm.dev, UINT_MAX); 388 389 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 390 if (ret) 391 goto mask_err; 392 393 /* overlay on gen2 is broken and can't address above 1G */ 394 if (GRAPHICS_VER(i915) == 2) 395 mask_size = 30; 396 397 /* 398 * 965GM sometimes incorrectly writes to hardware status page (HWS) 399 * using 32bit addressing, overwriting memory if HWS is located 400 * above 4GB. 401 * 402 * The documentation also mentions an issue with undefined 403 * behaviour if any general state is accessed within a page above 4GB, 404 * which also needs to be handled carefully. 405 */ 406 if (IS_I965G(i915) || IS_I965GM(i915)) 407 mask_size = 32; 408 409 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 410 if (ret) 411 goto mask_err; 412 413 return 0; 414 415 mask_err: 416 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret); 417 return ret; 418 } 419 420 static int i915_pcode_init(struct drm_i915_private *i915) 421 { 422 struct intel_gt *gt; 423 int id, ret; 424 425 for_each_gt(gt, i915, id) { 426 ret = intel_pcode_init(gt->uncore); 427 if (ret) { 428 gt_err(gt, "intel_pcode_init failed %d\n", ret); 429 return ret; 430 } 431 } 432 433 return 0; 434 } 435 436 /** 437 * i915_driver_hw_probe - setup state requiring device access 438 * @dev_priv: device private 439 * 440 * Setup state that requires accessing the device, but doesn't require 441 * exposing the driver via kernel internal or userspace interfaces. 442 */ 443 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) 444 { 445 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 446 int ret; 447 448 if (i915_inject_probe_failure(dev_priv)) 449 return -ENODEV; 450 451 if (HAS_PPGTT(dev_priv)) { 452 if (intel_vgpu_active(dev_priv) && 453 !intel_vgpu_has_full_ppgtt(dev_priv)) { 454 i915_report_error(dev_priv, 455 "incompatible vGPU found, support for isolated ppGTT required\n"); 456 return -ENXIO; 457 } 458 } 459 460 if (HAS_EXECLISTS(dev_priv)) { 461 /* 462 * Older GVT emulation depends upon intercepting CSB mmio, 463 * which we no longer use, preferring to use the HWSP cache 464 * instead. 465 */ 466 if (intel_vgpu_active(dev_priv) && 467 !intel_vgpu_has_hwsp_emulation(dev_priv)) { 468 i915_report_error(dev_priv, 469 "old vGPU host found, support for HWSP emulation required\n"); 470 return -ENXIO; 471 } 472 } 473 474 /* needs to be done before ggtt probe */ 475 intel_dram_edram_detect(dev_priv); 476 477 ret = i915_set_dma_info(dev_priv); 478 if (ret) 479 return ret; 480 481 ret = i915_perf_init(dev_priv); 482 if (ret) 483 return ret; 484 485 ret = i915_ggtt_probe_hw(dev_priv); 486 if (ret) 487 goto err_perf; 488 489 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver); 490 if (ret) 491 goto err_ggtt; 492 493 ret = i915_ggtt_init_hw(dev_priv); 494 if (ret) 495 goto err_ggtt; 496 497 /* 498 * Make sure we probe lmem before we probe stolen-lmem. The BAR size 499 * might be different due to bar resizing. 500 */ 501 ret = intel_gt_tiles_init(dev_priv); 502 if (ret) 503 goto err_ggtt; 504 505 ret = intel_memory_regions_hw_probe(dev_priv); 506 if (ret) 507 goto err_ggtt; 508 509 ret = i915_ggtt_enable_hw(dev_priv); 510 if (ret) { 511 drm_err(&dev_priv->drm, "failed to enable GGTT\n"); 512 goto err_mem_regions; 513 } 514 515 pci_set_master(pdev); 516 517 /* On the 945G/GM, the chipset reports the MSI capability on the 518 * integrated graphics even though the support isn't actually there 519 * according to the published specs. It doesn't appear to function 520 * correctly in testing on 945G. 521 * This may be a side effect of MSI having been made available for PEG 522 * and the registers being closely associated. 523 * 524 * According to chipset errata, on the 965GM, MSI interrupts may 525 * be lost or delayed, and was defeatured. MSI interrupts seem to 526 * get lost on g4x as well, and interrupt delivery seems to stay 527 * properly dead afterwards. So we'll just disable them for all 528 * pre-gen5 chipsets. 529 * 530 * dp aux and gmbus irq on gen4 seems to be able to generate legacy 531 * interrupts even when in MSI mode. This results in spurious 532 * interrupt warnings if the legacy irq no. is shared with another 533 * device. The kernel then disables that interrupt source and so 534 * prevents the other device from working properly. 535 */ 536 if (GRAPHICS_VER(dev_priv) >= 5) { 537 if (pci_enable_msi(pdev) < 0) 538 drm_dbg(&dev_priv->drm, "can't enable MSI"); 539 } 540 541 ret = intel_gvt_init(dev_priv); 542 if (ret) 543 goto err_msi; 544 545 intel_opregion_setup(dev_priv); 546 547 ret = i915_pcode_init(dev_priv); 548 if (ret) 549 goto err_opregion; 550 551 /* 552 * Fill the dram structure to get the system dram info. This will be 553 * used for memory latency calculation. 554 */ 555 intel_dram_detect(dev_priv); 556 557 intel_bw_init_hw(dev_priv); 558 559 return 0; 560 561 err_opregion: 562 intel_opregion_cleanup(dev_priv); 563 err_msi: 564 if (pdev->msi_enabled) 565 pci_disable_msi(pdev); 566 err_mem_regions: 567 intel_memory_regions_driver_release(dev_priv); 568 err_ggtt: 569 i915_ggtt_driver_release(dev_priv); 570 i915_gem_drain_freed_objects(dev_priv); 571 i915_ggtt_driver_late_release(dev_priv); 572 err_perf: 573 i915_perf_fini(dev_priv); 574 return ret; 575 } 576 577 /** 578 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe() 579 * @dev_priv: device private 580 */ 581 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv) 582 { 583 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 584 585 i915_perf_fini(dev_priv); 586 587 intel_opregion_cleanup(dev_priv); 588 589 if (pdev->msi_enabled) 590 pci_disable_msi(pdev); 591 } 592 593 /** 594 * i915_driver_register - register the driver with the rest of the system 595 * @dev_priv: device private 596 * 597 * Perform any steps necessary to make the driver available via kernel 598 * internal or userspace interfaces. 599 */ 600 static void i915_driver_register(struct drm_i915_private *dev_priv) 601 { 602 struct intel_gt *gt; 603 unsigned int i; 604 605 i915_gem_driver_register(dev_priv); 606 i915_pmu_register(dev_priv); 607 608 intel_vgpu_register(dev_priv); 609 610 /* Reveal our presence to userspace */ 611 if (drm_dev_register(&dev_priv->drm, 0)) { 612 drm_err(&dev_priv->drm, 613 "Failed to register driver for userspace access!\n"); 614 return; 615 } 616 617 i915_debugfs_register(dev_priv); 618 i915_setup_sysfs(dev_priv); 619 620 /* Depends on sysfs having been initialized */ 621 i915_perf_register(dev_priv); 622 623 for_each_gt(gt, dev_priv, i) 624 intel_gt_driver_register(gt); 625 626 intel_pxp_debugfs_register(dev_priv->pxp); 627 628 i915_hwmon_register(dev_priv); 629 630 intel_display_driver_register(dev_priv); 631 632 intel_power_domains_enable(dev_priv); 633 intel_runtime_pm_enable(&dev_priv->runtime_pm); 634 635 intel_register_dsm_handler(); 636 637 if (i915_switcheroo_register(dev_priv)) 638 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n"); 639 } 640 641 /** 642 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() 643 * @dev_priv: device private 644 */ 645 static void i915_driver_unregister(struct drm_i915_private *dev_priv) 646 { 647 struct intel_gt *gt; 648 unsigned int i; 649 650 i915_switcheroo_unregister(dev_priv); 651 652 intel_unregister_dsm_handler(); 653 654 intel_runtime_pm_disable(&dev_priv->runtime_pm); 655 intel_power_domains_disable(dev_priv); 656 657 intel_display_driver_unregister(dev_priv); 658 659 intel_pxp_fini(dev_priv); 660 661 for_each_gt(gt, dev_priv, i) 662 intel_gt_driver_unregister(gt); 663 664 i915_hwmon_unregister(dev_priv); 665 666 i915_perf_unregister(dev_priv); 667 i915_pmu_unregister(dev_priv); 668 669 i915_teardown_sysfs(dev_priv); 670 drm_dev_unplug(&dev_priv->drm); 671 672 i915_gem_driver_unregister(dev_priv); 673 } 674 675 void 676 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p) 677 { 678 drm_printf(p, "iommu: %s\n", 679 str_enabled_disabled(i915_vtd_active(i915))); 680 } 681 682 static void i915_welcome_messages(struct drm_i915_private *dev_priv) 683 { 684 if (drm_debug_enabled(DRM_UT_DRIVER)) { 685 struct drm_printer p = drm_dbg_printer(&dev_priv->drm, DRM_UT_DRIVER, 686 "device info:"); 687 struct intel_gt *gt; 688 unsigned int i; 689 690 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n", 691 INTEL_DEVID(dev_priv), 692 INTEL_REVID(dev_priv), 693 intel_platform_name(INTEL_INFO(dev_priv)->platform), 694 intel_subplatform(RUNTIME_INFO(dev_priv), 695 INTEL_INFO(dev_priv)->platform), 696 GRAPHICS_VER(dev_priv)); 697 698 intel_device_info_print(INTEL_INFO(dev_priv), 699 RUNTIME_INFO(dev_priv), &p); 700 i915_print_iommu_status(dev_priv, &p); 701 for_each_gt(gt, dev_priv, i) 702 intel_gt_info_print(>->info, &p); 703 } 704 705 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) 706 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n"); 707 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 708 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n"); 709 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) 710 drm_info(&dev_priv->drm, 711 "DRM_I915_DEBUG_RUNTIME_PM enabled\n"); 712 } 713 714 static struct drm_i915_private * 715 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) 716 { 717 const struct intel_device_info *match_info = 718 (struct intel_device_info *)ent->driver_data; 719 struct drm_i915_private *i915; 720 721 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver, 722 struct drm_i915_private, drm); 723 if (IS_ERR(i915)) 724 return i915; 725 726 pci_set_drvdata(pdev, i915); 727 728 /* Device parameters start as a copy of module parameters. */ 729 i915_params_copy(&i915->params, &i915_modparams); 730 731 /* Set up device info and initial runtime info. */ 732 intel_device_info_driver_create(i915, pdev->device, match_info); 733 734 intel_display_device_probe(i915); 735 736 return i915; 737 } 738 739 /** 740 * i915_driver_probe - setup chip and create an initial config 741 * @pdev: PCI device 742 * @ent: matching PCI ID entry 743 * 744 * The driver probe routine has to do several things: 745 * - drive output discovery via intel_display_driver_probe() 746 * - initialize the memory manager 747 * - allocate initial config memory 748 * - setup the DRM framebuffer with the allocated memory 749 */ 750 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 751 { 752 struct drm_i915_private *i915; 753 int ret; 754 755 ret = pci_enable_device(pdev); 756 if (ret) { 757 pr_err("Failed to enable graphics device: %pe\n", ERR_PTR(ret)); 758 return ret; 759 } 760 761 i915 = i915_driver_create(pdev, ent); 762 if (IS_ERR(i915)) { 763 pci_disable_device(pdev); 764 return PTR_ERR(i915); 765 } 766 767 ret = i915_driver_early_probe(i915); 768 if (ret < 0) 769 goto out_pci_disable; 770 771 disable_rpm_wakeref_asserts(&i915->runtime_pm); 772 773 intel_vgpu_detect(i915); 774 775 ret = intel_gt_probe_all(i915); 776 if (ret < 0) 777 goto out_runtime_pm_put; 778 779 ret = i915_driver_mmio_probe(i915); 780 if (ret < 0) 781 goto out_runtime_pm_put; 782 783 ret = i915_driver_hw_probe(i915); 784 if (ret < 0) 785 goto out_cleanup_mmio; 786 787 ret = intel_display_driver_probe_noirq(i915); 788 if (ret < 0) 789 goto out_cleanup_hw; 790 791 ret = intel_irq_install(i915); 792 if (ret) 793 goto out_cleanup_modeset; 794 795 ret = intel_display_driver_probe_nogem(i915); 796 if (ret) 797 goto out_cleanup_irq; 798 799 ret = i915_gem_init(i915); 800 if (ret) 801 goto out_cleanup_modeset2; 802 803 ret = intel_pxp_init(i915); 804 if (ret && ret != -ENODEV) 805 drm_dbg(&i915->drm, "pxp init failed with %d\n", ret); 806 807 ret = intel_display_driver_probe(i915); 808 if (ret) 809 goto out_cleanup_gem; 810 811 i915_driver_register(i915); 812 813 enable_rpm_wakeref_asserts(&i915->runtime_pm); 814 815 i915_welcome_messages(i915); 816 817 i915->do_release = true; 818 819 return 0; 820 821 out_cleanup_gem: 822 i915_gem_suspend(i915); 823 i915_gem_driver_remove(i915); 824 i915_gem_driver_release(i915); 825 out_cleanup_modeset2: 826 /* FIXME clean up the error path */ 827 intel_display_driver_remove(i915); 828 intel_irq_uninstall(i915); 829 intel_display_driver_remove_noirq(i915); 830 goto out_cleanup_modeset; 831 out_cleanup_irq: 832 intel_irq_uninstall(i915); 833 out_cleanup_modeset: 834 intel_display_driver_remove_nogem(i915); 835 out_cleanup_hw: 836 i915_driver_hw_remove(i915); 837 intel_memory_regions_driver_release(i915); 838 i915_ggtt_driver_release(i915); 839 i915_gem_drain_freed_objects(i915); 840 i915_ggtt_driver_late_release(i915); 841 out_cleanup_mmio: 842 i915_driver_mmio_release(i915); 843 out_runtime_pm_put: 844 enable_rpm_wakeref_asserts(&i915->runtime_pm); 845 i915_driver_late_release(i915); 846 out_pci_disable: 847 pci_disable_device(pdev); 848 i915_probe_error(i915, "Device initialization failed (%d)\n", ret); 849 return ret; 850 } 851 852 void i915_driver_remove(struct drm_i915_private *i915) 853 { 854 intel_wakeref_t wakeref; 855 856 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 857 858 i915_driver_unregister(i915); 859 860 /* Flush any external code that still may be under the RCU lock */ 861 synchronize_rcu(); 862 863 i915_gem_suspend(i915); 864 865 intel_gvt_driver_remove(i915); 866 867 intel_display_driver_remove(i915); 868 869 intel_irq_uninstall(i915); 870 871 intel_display_driver_remove_noirq(i915); 872 873 i915_reset_error_state(i915); 874 i915_gem_driver_remove(i915); 875 876 intel_display_driver_remove_nogem(i915); 877 878 i915_driver_hw_remove(i915); 879 880 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 881 } 882 883 static void i915_driver_release(struct drm_device *dev) 884 { 885 struct drm_i915_private *dev_priv = to_i915(dev); 886 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 887 intel_wakeref_t wakeref; 888 889 if (!dev_priv->do_release) 890 return; 891 892 wakeref = intel_runtime_pm_get(rpm); 893 894 i915_gem_driver_release(dev_priv); 895 896 intel_memory_regions_driver_release(dev_priv); 897 i915_ggtt_driver_release(dev_priv); 898 i915_gem_drain_freed_objects(dev_priv); 899 i915_ggtt_driver_late_release(dev_priv); 900 901 i915_driver_mmio_release(dev_priv); 902 903 intel_runtime_pm_put(rpm, wakeref); 904 905 intel_runtime_pm_driver_release(rpm); 906 907 i915_driver_late_release(dev_priv); 908 909 intel_display_device_remove(dev_priv); 910 } 911 912 static int i915_driver_open(struct drm_device *dev, struct drm_file *file) 913 { 914 struct drm_i915_private *i915 = to_i915(dev); 915 int ret; 916 917 ret = i915_gem_open(i915, file); 918 if (ret) 919 return ret; 920 921 return 0; 922 } 923 924 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) 925 { 926 struct drm_i915_file_private *file_priv = file->driver_priv; 927 928 i915_gem_context_close(file); 929 i915_drm_client_put(file_priv->client); 930 931 kfree_rcu(file_priv, rcu); 932 933 /* Catch up with all the deferred frees from "this" client */ 934 i915_gem_flush_free_objects(to_i915(dev)); 935 } 936 937 void i915_driver_shutdown(struct drm_i915_private *i915) 938 { 939 disable_rpm_wakeref_asserts(&i915->runtime_pm); 940 intel_runtime_pm_disable(&i915->runtime_pm); 941 intel_power_domains_disable(i915); 942 943 intel_fbdev_set_suspend(&i915->drm, FBINFO_STATE_SUSPENDED, true); 944 if (HAS_DISPLAY(i915)) { 945 drm_kms_helper_poll_disable(&i915->drm); 946 intel_display_driver_disable_user_access(i915); 947 948 drm_atomic_helper_shutdown(&i915->drm); 949 } 950 951 intel_dp_mst_suspend(i915); 952 953 intel_runtime_pm_disable_interrupts(i915); 954 intel_hpd_cancel_work(i915); 955 956 if (HAS_DISPLAY(i915)) 957 intel_display_driver_suspend_access(i915); 958 959 intel_encoder_suspend_all(&i915->display); 960 intel_encoder_shutdown_all(&i915->display); 961 962 intel_dmc_suspend(i915); 963 964 i915_gem_suspend(i915); 965 966 /* 967 * The only requirement is to reboot with display DC states disabled, 968 * for now leaving all display power wells in the INIT power domain 969 * enabled. 970 * 971 * TODO: 972 * - unify the pci_driver::shutdown sequence here with the 973 * pci_driver.driver.pm.poweroff,poweroff_late sequence. 974 * - unify the driver remove and system/runtime suspend sequences with 975 * the above unified shutdown/poweroff sequence. 976 */ 977 intel_power_domains_driver_remove(i915); 978 enable_rpm_wakeref_asserts(&i915->runtime_pm); 979 980 intel_runtime_pm_driver_last_release(&i915->runtime_pm); 981 } 982 983 static bool suspend_to_idle(struct drm_i915_private *dev_priv) 984 { 985 #if IS_ENABLED(CONFIG_ACPI_SLEEP) 986 if (acpi_target_system_state() < ACPI_STATE_S3) 987 return true; 988 #endif 989 return false; 990 } 991 992 static void i915_drm_complete(struct drm_device *dev) 993 { 994 struct drm_i915_private *i915 = to_i915(dev); 995 996 intel_pxp_resume_complete(i915->pxp); 997 } 998 999 static int i915_drm_prepare(struct drm_device *dev) 1000 { 1001 struct drm_i915_private *i915 = to_i915(dev); 1002 1003 intel_pxp_suspend_prepare(i915->pxp); 1004 1005 /* 1006 * NB intel_display_driver_suspend() may issue new requests after we've 1007 * ostensibly marked the GPU as ready-to-sleep here. We need to 1008 * split out that work and pull it forward so that after point, 1009 * the GPU is not woken again. 1010 */ 1011 return i915_gem_backup_suspend(i915); 1012 } 1013 1014 static int i915_drm_suspend(struct drm_device *dev) 1015 { 1016 struct drm_i915_private *dev_priv = to_i915(dev); 1017 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1018 pci_power_t opregion_target_state; 1019 1020 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1021 1022 /* We do a lot of poking in a lot of registers, make sure they work 1023 * properly. */ 1024 intel_power_domains_disable(dev_priv); 1025 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); 1026 if (HAS_DISPLAY(dev_priv)) { 1027 drm_kms_helper_poll_disable(dev); 1028 intel_display_driver_disable_user_access(dev_priv); 1029 } 1030 1031 pci_save_state(pdev); 1032 1033 intel_display_driver_suspend(dev_priv); 1034 1035 intel_dp_mst_suspend(dev_priv); 1036 1037 intel_runtime_pm_disable_interrupts(dev_priv); 1038 intel_hpd_cancel_work(dev_priv); 1039 1040 if (HAS_DISPLAY(dev_priv)) 1041 intel_display_driver_suspend_access(dev_priv); 1042 1043 intel_encoder_suspend_all(&dev_priv->display); 1044 1045 /* Must be called before GGTT is suspended. */ 1046 intel_dpt_suspend(dev_priv); 1047 i915_ggtt_suspend(to_gt(dev_priv)->ggtt); 1048 1049 i915_save_display(dev_priv); 1050 1051 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; 1052 intel_opregion_suspend(dev_priv, opregion_target_state); 1053 1054 dev_priv->suspend_count++; 1055 1056 intel_dmc_suspend(dev_priv); 1057 1058 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1059 1060 i915_gem_drain_freed_objects(dev_priv); 1061 1062 return 0; 1063 } 1064 1065 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) 1066 { 1067 struct drm_i915_private *dev_priv = to_i915(dev); 1068 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1069 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1070 struct intel_gt *gt; 1071 int ret, i; 1072 bool s2idle = !hibernation && suspend_to_idle(dev_priv); 1073 1074 disable_rpm_wakeref_asserts(rpm); 1075 1076 intel_pxp_suspend(dev_priv->pxp); 1077 1078 i915_gem_suspend_late(dev_priv); 1079 1080 for_each_gt(gt, dev_priv, i) 1081 intel_uncore_suspend(gt->uncore); 1082 1083 intel_power_domains_suspend(dev_priv, s2idle); 1084 1085 intel_display_power_suspend_late(dev_priv); 1086 1087 ret = vlv_suspend_complete(dev_priv); 1088 if (ret) { 1089 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret); 1090 intel_power_domains_resume(dev_priv); 1091 1092 goto out; 1093 } 1094 1095 pci_disable_device(pdev); 1096 /* 1097 * During hibernation on some platforms the BIOS may try to access 1098 * the device even though it's already in D3 and hang the machine. So 1099 * leave the device in D0 on those platforms and hope the BIOS will 1100 * power down the device properly. The issue was seen on multiple old 1101 * GENs with different BIOS vendors, so having an explicit blacklist 1102 * is inpractical; apply the workaround on everything pre GEN6. The 1103 * platforms where the issue was seen: 1104 * Lenovo Thinkpad X301, X61s, X60, T60, X41 1105 * Fujitsu FSC S7110 1106 * Acer Aspire 1830T 1107 */ 1108 if (!(hibernation && GRAPHICS_VER(dev_priv) < 6)) 1109 pci_set_power_state(pdev, PCI_D3hot); 1110 1111 out: 1112 enable_rpm_wakeref_asserts(rpm); 1113 if (!dev_priv->uncore.user_forcewake_count) 1114 intel_runtime_pm_driver_release(rpm); 1115 1116 return ret; 1117 } 1118 1119 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915, 1120 pm_message_t state) 1121 { 1122 int error; 1123 1124 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND && 1125 state.event != PM_EVENT_FREEZE)) 1126 return -EINVAL; 1127 1128 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1129 return 0; 1130 1131 error = i915_drm_suspend(&i915->drm); 1132 if (error) 1133 return error; 1134 1135 return i915_drm_suspend_late(&i915->drm, false); 1136 } 1137 1138 static int i915_drm_resume(struct drm_device *dev) 1139 { 1140 struct drm_i915_private *dev_priv = to_i915(dev); 1141 struct intel_gt *gt; 1142 int ret, i; 1143 1144 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1145 1146 ret = i915_pcode_init(dev_priv); 1147 if (ret) 1148 return ret; 1149 1150 sanitize_gpu(dev_priv); 1151 1152 ret = i915_ggtt_enable_hw(dev_priv); 1153 if (ret) 1154 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n"); 1155 1156 i915_ggtt_resume(to_gt(dev_priv)->ggtt); 1157 1158 for_each_gt(gt, dev_priv, i) 1159 if (GRAPHICS_VER(gt->i915) >= 8) 1160 setup_private_pat(gt); 1161 1162 /* Must be called after GGTT is resumed. */ 1163 intel_dpt_resume(dev_priv); 1164 1165 intel_dmc_resume(dev_priv); 1166 1167 i915_restore_display(dev_priv); 1168 intel_pps_unlock_regs_wa(dev_priv); 1169 1170 intel_init_pch_refclk(dev_priv); 1171 1172 /* 1173 * Interrupts have to be enabled before any batches are run. If not the 1174 * GPU will hang. i915_gem_init_hw() will initiate batches to 1175 * update/restore the context. 1176 * 1177 * drm_mode_config_reset() needs AUX interrupts. 1178 * 1179 * Modeset enabling in intel_display_driver_init_hw() also needs working 1180 * interrupts. 1181 */ 1182 intel_runtime_pm_enable_interrupts(dev_priv); 1183 1184 if (HAS_DISPLAY(dev_priv)) 1185 drm_mode_config_reset(dev); 1186 1187 i915_gem_resume(dev_priv); 1188 1189 intel_display_driver_init_hw(dev_priv); 1190 1191 intel_clock_gating_init(dev_priv); 1192 1193 if (HAS_DISPLAY(dev_priv)) 1194 intel_display_driver_resume_access(dev_priv); 1195 1196 intel_hpd_init(dev_priv); 1197 1198 /* MST sideband requires HPD interrupts enabled */ 1199 intel_dp_mst_resume(dev_priv); 1200 intel_display_driver_resume(dev_priv); 1201 1202 if (HAS_DISPLAY(dev_priv)) { 1203 intel_display_driver_enable_user_access(dev_priv); 1204 drm_kms_helper_poll_enable(dev); 1205 } 1206 intel_hpd_poll_disable(dev_priv); 1207 1208 intel_opregion_resume(dev_priv); 1209 1210 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); 1211 1212 intel_power_domains_enable(dev_priv); 1213 1214 intel_gvt_resume(dev_priv); 1215 1216 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1217 1218 return 0; 1219 } 1220 1221 static int i915_drm_resume_early(struct drm_device *dev) 1222 { 1223 struct drm_i915_private *dev_priv = to_i915(dev); 1224 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1225 struct intel_gt *gt; 1226 int ret, i; 1227 1228 /* 1229 * We have a resume ordering issue with the snd-hda driver also 1230 * requiring our device to be power up. Due to the lack of a 1231 * parent/child relationship we currently solve this with an early 1232 * resume hook. 1233 * 1234 * FIXME: This should be solved with a special hdmi sink device or 1235 * similar so that power domains can be employed. 1236 */ 1237 1238 /* 1239 * Note that we need to set the power state explicitly, since we 1240 * powered off the device during freeze and the PCI core won't power 1241 * it back up for us during thaw. Powering off the device during 1242 * freeze is not a hard requirement though, and during the 1243 * suspend/resume phases the PCI core makes sure we get here with the 1244 * device powered on. So in case we change our freeze logic and keep 1245 * the device powered we can also remove the following set power state 1246 * call. 1247 */ 1248 ret = pci_set_power_state(pdev, PCI_D0); 1249 if (ret) { 1250 drm_err(&dev_priv->drm, 1251 "failed to set PCI D0 power state (%d)\n", ret); 1252 return ret; 1253 } 1254 1255 /* 1256 * Note that pci_enable_device() first enables any parent bridge 1257 * device and only then sets the power state for this device. The 1258 * bridge enabling is a nop though, since bridge devices are resumed 1259 * first. The order of enabling power and enabling the device is 1260 * imposed by the PCI core as described above, so here we preserve the 1261 * same order for the freeze/thaw phases. 1262 * 1263 * TODO: eventually we should remove pci_disable_device() / 1264 * pci_enable_enable_device() from suspend/resume. Due to how they 1265 * depend on the device enable refcount we can't anyway depend on them 1266 * disabling/enabling the device. 1267 */ 1268 if (pci_enable_device(pdev)) 1269 return -EIO; 1270 1271 pci_set_master(pdev); 1272 1273 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1274 1275 ret = vlv_resume_prepare(dev_priv, false); 1276 if (ret) 1277 drm_err(&dev_priv->drm, 1278 "Resume prepare failed: %d, continuing anyway\n", ret); 1279 1280 for_each_gt(gt, dev_priv, i) 1281 intel_gt_resume_early(gt); 1282 1283 intel_display_power_resume_early(dev_priv); 1284 1285 intel_power_domains_resume(dev_priv); 1286 1287 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1288 1289 return ret; 1290 } 1291 1292 int i915_driver_resume_switcheroo(struct drm_i915_private *i915) 1293 { 1294 int ret; 1295 1296 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1297 return 0; 1298 1299 ret = i915_drm_resume_early(&i915->drm); 1300 if (ret) 1301 return ret; 1302 1303 return i915_drm_resume(&i915->drm); 1304 } 1305 1306 static int i915_pm_prepare(struct device *kdev) 1307 { 1308 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1309 1310 if (!i915) { 1311 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1312 return -ENODEV; 1313 } 1314 1315 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1316 return 0; 1317 1318 return i915_drm_prepare(&i915->drm); 1319 } 1320 1321 static int i915_pm_suspend(struct device *kdev) 1322 { 1323 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1324 1325 if (!i915) { 1326 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1327 return -ENODEV; 1328 } 1329 1330 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1331 return 0; 1332 1333 return i915_drm_suspend(&i915->drm); 1334 } 1335 1336 static int i915_pm_suspend_late(struct device *kdev) 1337 { 1338 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1339 1340 /* 1341 * We have a suspend ordering issue with the snd-hda driver also 1342 * requiring our device to be power up. Due to the lack of a 1343 * parent/child relationship we currently solve this with an late 1344 * suspend hook. 1345 * 1346 * FIXME: This should be solved with a special hdmi sink device or 1347 * similar so that power domains can be employed. 1348 */ 1349 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1350 return 0; 1351 1352 return i915_drm_suspend_late(&i915->drm, false); 1353 } 1354 1355 static int i915_pm_poweroff_late(struct device *kdev) 1356 { 1357 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1358 1359 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1360 return 0; 1361 1362 return i915_drm_suspend_late(&i915->drm, true); 1363 } 1364 1365 static int i915_pm_resume_early(struct device *kdev) 1366 { 1367 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1368 1369 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1370 return 0; 1371 1372 return i915_drm_resume_early(&i915->drm); 1373 } 1374 1375 static int i915_pm_resume(struct device *kdev) 1376 { 1377 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1378 1379 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1380 return 0; 1381 1382 return i915_drm_resume(&i915->drm); 1383 } 1384 1385 static void i915_pm_complete(struct device *kdev) 1386 { 1387 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1388 1389 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1390 return; 1391 1392 i915_drm_complete(&i915->drm); 1393 } 1394 1395 /* freeze: before creating the hibernation_image */ 1396 static int i915_pm_freeze(struct device *kdev) 1397 { 1398 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1399 int ret; 1400 1401 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1402 ret = i915_drm_suspend(&i915->drm); 1403 if (ret) 1404 return ret; 1405 } 1406 1407 ret = i915_gem_freeze(i915); 1408 if (ret) 1409 return ret; 1410 1411 return 0; 1412 } 1413 1414 static int i915_pm_freeze_late(struct device *kdev) 1415 { 1416 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1417 int ret; 1418 1419 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1420 ret = i915_drm_suspend_late(&i915->drm, true); 1421 if (ret) 1422 return ret; 1423 } 1424 1425 ret = i915_gem_freeze_late(i915); 1426 if (ret) 1427 return ret; 1428 1429 return 0; 1430 } 1431 1432 /* thaw: called after creating the hibernation image, but before turning off. */ 1433 static int i915_pm_thaw_early(struct device *kdev) 1434 { 1435 return i915_pm_resume_early(kdev); 1436 } 1437 1438 static int i915_pm_thaw(struct device *kdev) 1439 { 1440 return i915_pm_resume(kdev); 1441 } 1442 1443 /* restore: called after loading the hibernation image. */ 1444 static int i915_pm_restore_early(struct device *kdev) 1445 { 1446 return i915_pm_resume_early(kdev); 1447 } 1448 1449 static int i915_pm_restore(struct device *kdev) 1450 { 1451 return i915_pm_resume(kdev); 1452 } 1453 1454 static int intel_runtime_suspend(struct device *kdev) 1455 { 1456 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1457 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1458 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1459 struct pci_dev *root_pdev; 1460 struct intel_gt *gt; 1461 int ret, i; 1462 1463 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1464 return -ENODEV; 1465 1466 drm_dbg(&dev_priv->drm, "Suspending device\n"); 1467 1468 disable_rpm_wakeref_asserts(rpm); 1469 1470 /* 1471 * We are safe here against re-faults, since the fault handler takes 1472 * an RPM reference. 1473 */ 1474 i915_gem_runtime_suspend(dev_priv); 1475 1476 intel_pxp_runtime_suspend(dev_priv->pxp); 1477 1478 for_each_gt(gt, dev_priv, i) 1479 intel_gt_runtime_suspend(gt); 1480 1481 intel_runtime_pm_disable_interrupts(dev_priv); 1482 1483 for_each_gt(gt, dev_priv, i) 1484 intel_uncore_suspend(gt->uncore); 1485 1486 intel_display_power_suspend(dev_priv); 1487 1488 ret = vlv_suspend_complete(dev_priv); 1489 if (ret) { 1490 drm_err(&dev_priv->drm, 1491 "Runtime suspend failed, disabling it (%d)\n", ret); 1492 intel_uncore_runtime_resume(&dev_priv->uncore); 1493 1494 intel_runtime_pm_enable_interrupts(dev_priv); 1495 1496 for_each_gt(gt, dev_priv, i) 1497 intel_gt_runtime_resume(gt); 1498 1499 enable_rpm_wakeref_asserts(rpm); 1500 1501 return ret; 1502 } 1503 1504 enable_rpm_wakeref_asserts(rpm); 1505 intel_runtime_pm_driver_release(rpm); 1506 1507 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore)) 1508 drm_err(&dev_priv->drm, 1509 "Unclaimed access detected prior to suspending\n"); 1510 1511 /* 1512 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX 1513 * This should be totally removed when we handle the pci states properly 1514 * on runtime PM. 1515 */ 1516 root_pdev = pcie_find_root_port(pdev); 1517 if (root_pdev) 1518 pci_d3cold_disable(root_pdev); 1519 1520 /* 1521 * FIXME: We really should find a document that references the arguments 1522 * used below! 1523 */ 1524 if (IS_BROADWELL(dev_priv)) { 1525 /* 1526 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop 1527 * being detected, and the call we do at intel_runtime_resume() 1528 * won't be able to restore them. Since PCI_D3hot matches the 1529 * actual specification and appears to be working, use it. 1530 */ 1531 intel_opregion_notify_adapter(dev_priv, PCI_D3hot); 1532 } else { 1533 /* 1534 * current versions of firmware which depend on this opregion 1535 * notification have repurposed the D1 definition to mean 1536 * "runtime suspended" vs. what you would normally expect (D3) 1537 * to distinguish it from notifications that might be sent via 1538 * the suspend path. 1539 */ 1540 intel_opregion_notify_adapter(dev_priv, PCI_D1); 1541 } 1542 1543 assert_forcewakes_inactive(&dev_priv->uncore); 1544 1545 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) 1546 intel_hpd_poll_enable(dev_priv); 1547 1548 drm_dbg(&dev_priv->drm, "Device suspended\n"); 1549 return 0; 1550 } 1551 1552 static int intel_runtime_resume(struct device *kdev) 1553 { 1554 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1555 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1556 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1557 struct pci_dev *root_pdev; 1558 struct intel_gt *gt; 1559 int ret, i; 1560 1561 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1562 return -ENODEV; 1563 1564 drm_dbg(&dev_priv->drm, "Resuming device\n"); 1565 1566 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count)); 1567 disable_rpm_wakeref_asserts(rpm); 1568 1569 intel_opregion_notify_adapter(dev_priv, PCI_D0); 1570 1571 root_pdev = pcie_find_root_port(pdev); 1572 if (root_pdev) 1573 pci_d3cold_enable(root_pdev); 1574 1575 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore)) 1576 drm_dbg(&dev_priv->drm, 1577 "Unclaimed access during suspend, bios?\n"); 1578 1579 intel_display_power_resume(dev_priv); 1580 1581 ret = vlv_resume_prepare(dev_priv, true); 1582 1583 for_each_gt(gt, dev_priv, i) 1584 intel_uncore_runtime_resume(gt->uncore); 1585 1586 intel_runtime_pm_enable_interrupts(dev_priv); 1587 1588 /* 1589 * No point of rolling back things in case of an error, as the best 1590 * we can do is to hope that things will still work (and disable RPM). 1591 */ 1592 for_each_gt(gt, dev_priv, i) 1593 intel_gt_runtime_resume(gt); 1594 1595 intel_pxp_runtime_resume(dev_priv->pxp); 1596 1597 /* 1598 * On VLV/CHV display interrupts are part of the display 1599 * power well, so hpd is reinitialized from there. For 1600 * everyone else do it here. 1601 */ 1602 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 1603 intel_hpd_init(dev_priv); 1604 intel_hpd_poll_disable(dev_priv); 1605 } 1606 1607 skl_watermark_ipc_update(dev_priv); 1608 1609 enable_rpm_wakeref_asserts(rpm); 1610 1611 if (ret) 1612 drm_err(&dev_priv->drm, 1613 "Runtime resume failed, disabling it (%d)\n", ret); 1614 else 1615 drm_dbg(&dev_priv->drm, "Device resumed\n"); 1616 1617 return ret; 1618 } 1619 1620 const struct dev_pm_ops i915_pm_ops = { 1621 /* 1622 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, 1623 * PMSG_RESUME] 1624 */ 1625 .prepare = i915_pm_prepare, 1626 .suspend = i915_pm_suspend, 1627 .suspend_late = i915_pm_suspend_late, 1628 .resume_early = i915_pm_resume_early, 1629 .resume = i915_pm_resume, 1630 .complete = i915_pm_complete, 1631 1632 /* 1633 * S4 event handlers 1634 * @freeze, @freeze_late : called (1) before creating the 1635 * hibernation image [PMSG_FREEZE] and 1636 * (2) after rebooting, before restoring 1637 * the image [PMSG_QUIESCE] 1638 * @thaw, @thaw_early : called (1) after creating the hibernation 1639 * image, before writing it [PMSG_THAW] 1640 * and (2) after failing to create or 1641 * restore the image [PMSG_RECOVER] 1642 * @poweroff, @poweroff_late: called after writing the hibernation 1643 * image, before rebooting [PMSG_HIBERNATE] 1644 * @restore, @restore_early : called after rebooting and restoring the 1645 * hibernation image [PMSG_RESTORE] 1646 */ 1647 .freeze = i915_pm_freeze, 1648 .freeze_late = i915_pm_freeze_late, 1649 .thaw_early = i915_pm_thaw_early, 1650 .thaw = i915_pm_thaw, 1651 .poweroff = i915_pm_suspend, 1652 .poweroff_late = i915_pm_poweroff_late, 1653 .restore_early = i915_pm_restore_early, 1654 .restore = i915_pm_restore, 1655 1656 /* S0ix (via runtime suspend) event handlers */ 1657 .runtime_suspend = intel_runtime_suspend, 1658 .runtime_resume = intel_runtime_resume, 1659 }; 1660 1661 static const struct file_operations i915_driver_fops = { 1662 .owner = THIS_MODULE, 1663 .open = drm_open, 1664 .release = drm_release_noglobal, 1665 .unlocked_ioctl = drm_ioctl, 1666 .mmap = i915_gem_mmap, 1667 .poll = drm_poll, 1668 .read = drm_read, 1669 .compat_ioctl = i915_ioc32_compat_ioctl, 1670 .llseek = noop_llseek, 1671 #ifdef CONFIG_PROC_FS 1672 .show_fdinfo = drm_show_fdinfo, 1673 #endif 1674 }; 1675 1676 static int 1677 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, 1678 struct drm_file *file) 1679 { 1680 return -ENODEV; 1681 } 1682 1683 static const struct drm_ioctl_desc i915_ioctls[] = { 1684 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1685 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), 1686 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), 1687 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), 1688 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), 1689 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), 1690 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW), 1691 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1692 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), 1693 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), 1694 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1695 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), 1696 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1697 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1698 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), 1699 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), 1700 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1701 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1702 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH), 1703 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW), 1704 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1705 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1706 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW), 1707 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), 1708 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), 1709 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW), 1710 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1711 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1712 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), 1713 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW), 1714 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), 1715 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), 1716 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), 1717 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW), 1718 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), 1719 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), 1720 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW), 1721 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW), 1722 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), 1723 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0), 1724 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), 1725 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER), 1726 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER), 1727 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER), 1728 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER), 1729 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW), 1730 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), 1731 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), 1732 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), 1733 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW), 1734 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), 1735 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), 1736 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), 1737 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), 1738 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW), 1739 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW), 1740 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW), 1741 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW), 1742 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW), 1743 }; 1744 1745 /* 1746 * Interface history: 1747 * 1748 * 1.1: Original. 1749 * 1.2: Add Power Management 1750 * 1.3: Add vblank support 1751 * 1.4: Fix cmdbuffer path, add heap destroy 1752 * 1.5: Add vblank pipe configuration 1753 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 1754 * - Support vertical blank on secondary display pipe 1755 */ 1756 #define DRIVER_MAJOR 1 1757 #define DRIVER_MINOR 6 1758 #define DRIVER_PATCHLEVEL 0 1759 1760 static const struct drm_driver i915_drm_driver = { 1761 /* Don't use MTRRs here; the Xserver or userspace app should 1762 * deal with them for Intel hardware. 1763 */ 1764 .driver_features = 1765 DRIVER_GEM | 1766 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ | 1767 DRIVER_SYNCOBJ_TIMELINE, 1768 .release = i915_driver_release, 1769 .open = i915_driver_open, 1770 .postclose = i915_driver_postclose, 1771 .show_fdinfo = PTR_IF(IS_ENABLED(CONFIG_PROC_FS), i915_drm_client_fdinfo), 1772 1773 .gem_prime_import = i915_gem_prime_import, 1774 1775 .dumb_create = i915_gem_dumb_create, 1776 .dumb_map_offset = i915_gem_dumb_mmap_offset, 1777 1778 .ioctls = i915_ioctls, 1779 .num_ioctls = ARRAY_SIZE(i915_ioctls), 1780 .fops = &i915_driver_fops, 1781 .name = DRIVER_NAME, 1782 .desc = DRIVER_DESC, 1783 .date = DRIVER_DATE, 1784 .major = DRIVER_MAJOR, 1785 .minor = DRIVER_MINOR, 1786 .patchlevel = DRIVER_PATCHLEVEL, 1787 }; 1788