1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #include <linux/aperture.h> 31 #include <linux/acpi.h> 32 #include <linux/device.h> 33 #include <linux/module.h> 34 #include <linux/oom.h> 35 #include <linux/pci.h> 36 #include <linux/pm.h> 37 #include <linux/pm_runtime.h> 38 #include <linux/slab.h> 39 #include <linux/string_helpers.h> 40 #include <linux/vga_switcheroo.h> 41 #include <linux/vt.h> 42 43 #include <drm/drm_atomic_helper.h> 44 #include <drm/drm_client.h> 45 #include <drm/drm_client_event.h> 46 #include <drm/drm_ioctl.h> 47 #include <drm/drm_managed.h> 48 #include <drm/drm_probe_helper.h> 49 #include <drm/intel/display_member.h> 50 #include <drm/intel/display_parent_interface.h> 51 #include <drm/intel/intel_pcode_regs.h> 52 53 #include "display/i9xx_display_sr.h" 54 #include "display/intel_cdclk.h" 55 #include "display/intel_crtc.h" 56 #include "display/intel_display_device.h" 57 #include "display/intel_display_driver.h" 58 #include "display/intel_display_power.h" 59 #include "display/intel_dmc.h" 60 #include "display/intel_dp.h" 61 #include "display/intel_dpt.h" 62 #include "display/intel_fbdev.h" 63 #include "display/intel_gmbus.h" 64 #include "display/intel_hotplug.h" 65 #include "display/intel_opregion.h" 66 #include "display/intel_overlay.h" 67 #include "display/intel_pch_refclk.h" 68 #include "display/intel_pps.h" 69 #include "display/intel_sbi.h" 70 #include "display/intel_sprite_uapi.h" 71 #include "display/skl_watermark.h" 72 73 #include "gem/i915_gem_context.h" 74 #include "gem/i915_gem_create.h" 75 #include "gem/i915_gem_dmabuf.h" 76 #include "gem/i915_gem_ioctls.h" 77 #include "gem/i915_gem_mman.h" 78 #include "gem/i915_gem_object_frontbuffer.h" 79 #include "gem/i915_gem_panic.h" 80 #include "gem/i915_gem_pm.h" 81 #include "gt/intel_gt.h" 82 #include "gt/intel_gt_pm.h" 83 #include "gt/intel_gt_print.h" 84 #include "gt/intel_rc6.h" 85 #include "gt/intel_rps.h" 86 87 #include "pxp/intel_pxp.h" 88 #include "pxp/intel_pxp_debugfs.h" 89 #include "pxp/intel_pxp_pm.h" 90 91 #include "i915_bo.h" 92 #include "i915_debugfs.h" 93 #include "i915_display_pc8.h" 94 #include "i915_dpt.h" 95 #include "i915_driver.h" 96 #include "i915_drm_client.h" 97 #include "i915_drv.h" 98 #include "i915_dsb_buffer.h" 99 #include "i915_edram.h" 100 #include "i915_fb_pin.h" 101 #include "i915_file_private.h" 102 #include "i915_getparam.h" 103 #include "i915_gmch.h" 104 #include "i915_hdcp_gsc.h" 105 #include "i915_hwmon.h" 106 #include "i915_initial_plane.h" 107 #include "i915_ioc32.h" 108 #include "i915_ioctl.h" 109 #include "i915_irq.h" 110 #include "i915_memcpy.h" 111 #include "i915_overlay.h" 112 #include "i915_perf.h" 113 #include "i915_query.h" 114 #include "i915_reg.h" 115 #include "i915_switcheroo.h" 116 #include "i915_sysfs.h" 117 #include "i915_utils.h" 118 #include "i915_vgpu.h" 119 #include "intel_clock_gating.h" 120 #include "intel_cpu_info.h" 121 #include "intel_gvt.h" 122 #include "intel_memory_region.h" 123 #include "intel_pcode.h" 124 #include "intel_region_ttm.h" 125 #include "vlv_iosf_sb.h" 126 #include "vlv_suspend.h" 127 128 static const struct drm_driver i915_drm_driver; 129 130 static int i915_workqueues_init(struct drm_i915_private *dev_priv) 131 { 132 /* 133 * The i915 workqueue is primarily used for batched retirement of 134 * requests (and thus managing bo) once the task has been completed 135 * by the GPU. i915_retire_requests() is called directly when we 136 * need high-priority retirement, such as waiting for an explicit 137 * bo. 138 * 139 * It is also used for periodic low-priority events, such as 140 * idle-timers and recording error state. 141 * 142 * All tasks on the workqueue are expected to acquire the dev mutex 143 * so there is no point in running more than one instance of the 144 * workqueue at any time. Use an ordered one. 145 */ 146 dev_priv->wq = alloc_ordered_workqueue("i915", 0); 147 if (dev_priv->wq == NULL) 148 goto out_err; 149 150 /* 151 * The unordered i915 workqueue should be used for all work 152 * scheduling that do not require running in order, which used 153 * to be scheduled on the system_percpu_wq before moving to a driver 154 * instance due deprecation of flush_scheduled_work(). 155 */ 156 dev_priv->unordered_wq = alloc_workqueue("i915-unordered", WQ_PERCPU, 157 0); 158 if (dev_priv->unordered_wq == NULL) 159 goto out_free_wq; 160 161 return 0; 162 163 out_free_wq: 164 destroy_workqueue(dev_priv->wq); 165 out_err: 166 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n"); 167 168 return -ENOMEM; 169 } 170 171 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) 172 { 173 destroy_workqueue(dev_priv->unordered_wq); 174 destroy_workqueue(dev_priv->wq); 175 } 176 177 /* 178 * We don't keep the workarounds for pre-production hardware, so we expect our 179 * driver to fail on these machines in one way or another. A little warning on 180 * dmesg may help both the user and the bug triagers. 181 * 182 * Our policy for removing pre-production workarounds is to keep the 183 * current gen workarounds as a guide to the bring-up of the next gen 184 * (workarounds have a habit of persisting!). Anything older than that 185 * should be removed along with the complications they introduce. 186 */ 187 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) 188 { 189 bool pre = false; 190 191 pre |= IS_HASWELL_EARLY_SDV(dev_priv); 192 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6; 193 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA; 194 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 195 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3; 196 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7; 197 pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 198 pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 199 pre |= IS_DG2_G10(dev_priv) && INTEL_REVID(dev_priv) < 0x8; 200 pre |= IS_DG2_G11(dev_priv) && INTEL_REVID(dev_priv) < 0x5; 201 pre |= IS_DG2_G12(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 202 203 if (pre) { 204 drm_err(&dev_priv->drm, "This is a pre-production stepping. " 205 "It may not be fully functional.\n"); 206 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); 207 } 208 } 209 210 static void sanitize_gpu(struct drm_i915_private *i915) 211 { 212 if (!intel_gt_gpu_reset_clobbers_display(to_gt(i915))) { 213 struct intel_gt *gt; 214 unsigned int i; 215 216 for_each_gt(gt, i915, i) 217 intel_gt_reset_all_engines(gt); 218 } 219 } 220 221 /** 222 * i915_driver_early_probe - setup state not requiring device access 223 * @dev_priv: device private 224 * 225 * Initialize everything that is a "SW-only" state, that is state not 226 * requiring accessing the device or exposing the driver via kernel internal 227 * or userspace interfaces. Example steps belonging here: lock initialization, 228 * system memory allocation, setting up device specific attributes and 229 * function hooks not requiring accessing the device. 230 */ 231 static int i915_driver_early_probe(struct drm_i915_private *dev_priv) 232 { 233 struct intel_display *display = dev_priv->display; 234 int ret = 0; 235 236 intel_device_info_runtime_init_early(dev_priv); 237 238 intel_step_init(dev_priv); 239 240 intel_uncore_mmio_debug_init_early(dev_priv); 241 242 spin_lock_init(&dev_priv->gpu_error.lock); 243 244 intel_sbi_init(display); 245 vlv_iosf_sb_init(dev_priv); 246 mutex_init(&dev_priv->sb_lock); 247 248 i915_memcpy_init_early(dev_priv); 249 intel_runtime_pm_init_early(&dev_priv->runtime_pm); 250 251 ret = i915_workqueues_init(dev_priv); 252 if (ret < 0) 253 return ret; 254 255 ret = vlv_suspend_init(dev_priv); 256 if (ret < 0) 257 goto err_workqueues; 258 259 ret = intel_region_ttm_device_init(dev_priv); 260 if (ret) 261 goto err_ttm; 262 263 ret = intel_root_gt_init_early(dev_priv); 264 if (ret < 0) 265 goto err_rootgt; 266 267 i915_gem_init_early(dev_priv); 268 269 intel_irq_init(dev_priv); 270 intel_display_driver_early_probe(display); 271 intel_clock_gating_hooks_init(&dev_priv->drm); 272 273 intel_detect_preproduction_hw(dev_priv); 274 275 return 0; 276 277 err_rootgt: 278 intel_region_ttm_device_fini(dev_priv); 279 err_ttm: 280 vlv_suspend_cleanup(dev_priv); 281 err_workqueues: 282 i915_workqueues_cleanup(dev_priv); 283 return ret; 284 } 285 ALLOW_ERROR_INJECTION(i915_driver_early_probe, ERRNO); 286 287 /** 288 * i915_driver_late_release - cleanup the setup done in 289 * i915_driver_early_probe() 290 * @dev_priv: device private 291 */ 292 static void i915_driver_late_release(struct drm_i915_private *dev_priv) 293 { 294 struct intel_display *display = dev_priv->display; 295 296 intel_irq_fini(dev_priv); 297 intel_display_power_cleanup(display); 298 i915_gem_cleanup_early(dev_priv); 299 intel_gt_driver_late_release_all(dev_priv); 300 intel_region_ttm_device_fini(dev_priv); 301 vlv_suspend_cleanup(dev_priv); 302 i915_workqueues_cleanup(dev_priv); 303 304 mutex_destroy(&dev_priv->sb_lock); 305 vlv_iosf_sb_fini(dev_priv); 306 intel_sbi_fini(display); 307 308 i915_params_free(&dev_priv->params); 309 310 intel_display_device_remove(display); 311 dev_priv->display = NULL; 312 } 313 314 /** 315 * i915_driver_mmio_probe - setup device MMIO 316 * @dev_priv: device private 317 * 318 * Setup minimal device state necessary for MMIO accesses later in the 319 * initialization sequence. The setup here should avoid any other device-wide 320 * side effects or exposing the driver via kernel internal or user space 321 * interfaces. 322 */ 323 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) 324 { 325 struct intel_display *display = dev_priv->display; 326 struct intel_gt *gt; 327 int ret, i; 328 329 ret = i915_gmch_bridge_setup(dev_priv); 330 if (ret < 0) 331 return ret; 332 333 for_each_gt(gt, dev_priv, i) { 334 ret = intel_uncore_init_mmio(gt->uncore); 335 if (ret) 336 return ret; 337 338 ret = drmm_add_action_or_reset(&dev_priv->drm, 339 intel_uncore_fini_mmio, 340 gt->uncore); 341 if (ret) 342 return ret; 343 } 344 345 /* Try to make sure MCHBAR is enabled before poking at it */ 346 i915_gmch_bar_setup(dev_priv); 347 intel_device_info_runtime_init(dev_priv); 348 intel_display_device_info_runtime_init(display); 349 350 for_each_gt(gt, dev_priv, i) { 351 ret = intel_gt_init_mmio(gt); 352 if (ret) 353 goto err_uncore; 354 } 355 356 /* As early as possible, scrub existing GPU state before clobbering */ 357 sanitize_gpu(dev_priv); 358 359 return 0; 360 361 err_uncore: 362 i915_gmch_bar_teardown(dev_priv); 363 364 return ret; 365 } 366 ALLOW_ERROR_INJECTION(i915_driver_mmio_probe, ERRNO); 367 368 /** 369 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe() 370 * @dev_priv: device private 371 */ 372 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv) 373 { 374 i915_gmch_bar_teardown(dev_priv); 375 } 376 377 /** 378 * i915_set_dma_info - set all relevant PCI dma info as configured for the 379 * platform 380 * @i915: valid i915 instance 381 * 382 * Set the dma max segment size, device and coherent masks. The dma mask set 383 * needs to occur before i915_ggtt_probe_hw. 384 * 385 * A couple of platforms have special needs. Address them as well. 386 * 387 */ 388 static int i915_set_dma_info(struct drm_i915_private *i915) 389 { 390 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size; 391 int ret; 392 393 GEM_BUG_ON(!mask_size); 394 395 /* 396 * We don't have a max segment size, so set it to the max so sg's 397 * debugging layer doesn't complain 398 */ 399 dma_set_max_seg_size(i915->drm.dev, UINT_MAX); 400 401 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 402 if (ret) 403 goto mask_err; 404 405 /* overlay on gen2 is broken and can't address above 1G */ 406 if (GRAPHICS_VER(i915) == 2) 407 mask_size = 30; 408 409 /* 410 * 965GM sometimes incorrectly writes to hardware status page (HWS) 411 * using 32bit addressing, overwriting memory if HWS is located 412 * above 4GB. 413 * 414 * The documentation also mentions an issue with undefined 415 * behaviour if any general state is accessed within a page above 4GB, 416 * which also needs to be handled carefully. 417 */ 418 if (IS_I965G(i915) || IS_I965GM(i915)) 419 mask_size = 32; 420 421 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 422 if (ret) 423 goto mask_err; 424 425 return 0; 426 427 mask_err: 428 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret); 429 return ret; 430 } 431 432 /* Wa_14022698537:dg2 */ 433 static void i915_enable_g8(struct drm_i915_private *i915) 434 { 435 if (IS_DG2(i915)) { 436 if (IS_DG2_D(i915) && !intel_match_g8_cpu()) 437 return; 438 439 snb_pcode_write_p(&i915->uncore, PCODE_POWER_SETUP, 440 POWER_SETUP_SUBCOMMAND_G8_ENABLE, 0, 0); 441 } 442 } 443 444 static int i915_pcode_init(struct drm_i915_private *i915) 445 { 446 struct intel_gt *gt; 447 int id, ret; 448 449 for_each_gt(gt, i915, id) { 450 ret = intel_pcode_init(gt->uncore); 451 if (ret) { 452 gt_err(gt, "intel_pcode_init failed %d\n", ret); 453 return ret; 454 } 455 } 456 457 i915_enable_g8(i915); 458 return 0; 459 } 460 461 /** 462 * i915_driver_hw_probe - setup state requiring device access 463 * @dev_priv: device private 464 * 465 * Setup state that requires accessing the device, but doesn't require 466 * exposing the driver via kernel internal or userspace interfaces. 467 */ 468 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) 469 { 470 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 471 int ret; 472 473 if (HAS_PPGTT(dev_priv)) { 474 if (intel_vgpu_active(dev_priv) && 475 !intel_vgpu_has_full_ppgtt(dev_priv)) { 476 drm_err(&dev_priv->drm, 477 "incompatible vGPU found, support for isolated ppGTT required\n"); 478 return -ENXIO; 479 } 480 } 481 482 if (HAS_EXECLISTS(dev_priv)) { 483 /* 484 * Older GVT emulation depends upon intercepting CSB mmio, 485 * which we no longer use, preferring to use the HWSP cache 486 * instead. 487 */ 488 if (intel_vgpu_active(dev_priv) && 489 !intel_vgpu_has_hwsp_emulation(dev_priv)) { 490 drm_err(&dev_priv->drm, 491 "old vGPU host found, support for HWSP emulation required\n"); 492 return -ENXIO; 493 } 494 } 495 496 /* needs to be done before ggtt probe */ 497 i915_edram_detect(dev_priv); 498 499 ret = i915_set_dma_info(dev_priv); 500 if (ret) 501 return ret; 502 503 ret = i915_perf_init(dev_priv); 504 if (ret) 505 return ret; 506 507 ret = i915_ggtt_probe_hw(dev_priv); 508 if (ret) 509 goto err_perf; 510 511 ret = aperture_remove_conflicting_pci_devices(pdev, dev_priv->drm.driver->name); 512 if (ret) 513 goto err_ggtt; 514 515 ret = i915_ggtt_init_hw(dev_priv); 516 if (ret) 517 goto err_ggtt; 518 519 /* 520 * Make sure we probe lmem before we probe stolen-lmem. The BAR size 521 * might be different due to bar resizing. 522 */ 523 ret = intel_gt_tiles_init(dev_priv); 524 if (ret) 525 goto err_ggtt; 526 527 ret = intel_memory_regions_hw_probe(dev_priv); 528 if (ret) 529 goto err_ggtt; 530 531 ret = i915_ggtt_enable_hw(dev_priv); 532 if (ret) { 533 drm_err(&dev_priv->drm, "failed to enable GGTT\n"); 534 goto err_mem_regions; 535 } 536 537 pci_set_master(pdev); 538 539 /* On the 945G/GM, the chipset reports the MSI capability on the 540 * integrated graphics even though the support isn't actually there 541 * according to the published specs. It doesn't appear to function 542 * correctly in testing on 945G. 543 * This may be a side effect of MSI having been made available for PEG 544 * and the registers being closely associated. 545 * 546 * According to chipset errata, on the 965GM, MSI interrupts may 547 * be lost or delayed, and was defeatured. MSI interrupts seem to 548 * get lost on g4x as well, and interrupt delivery seems to stay 549 * properly dead afterwards. So we'll just disable them for all 550 * pre-gen5 chipsets. 551 * 552 * dp aux and gmbus irq on gen4 seems to be able to generate legacy 553 * interrupts even when in MSI mode. This results in spurious 554 * interrupt warnings if the legacy irq no. is shared with another 555 * device. The kernel then disables that interrupt source and so 556 * prevents the other device from working properly. 557 */ 558 if (GRAPHICS_VER(dev_priv) >= 5) { 559 if (pci_enable_msi(pdev) < 0) 560 drm_dbg(&dev_priv->drm, "can't enable MSI"); 561 } 562 563 ret = i915_pcode_init(dev_priv); 564 if (ret) 565 goto err_msi; 566 567 return 0; 568 569 err_msi: 570 pci_disable_msi(pdev); 571 err_mem_regions: 572 intel_memory_regions_driver_release(dev_priv); 573 err_ggtt: 574 i915_ggtt_driver_release(dev_priv); 575 i915_gem_drain_freed_objects(dev_priv); 576 i915_ggtt_driver_late_release(dev_priv); 577 err_perf: 578 i915_perf_fini(dev_priv); 579 return ret; 580 } 581 ALLOW_ERROR_INJECTION(i915_driver_hw_probe, ERRNO); 582 583 /** 584 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe() 585 * @dev_priv: device private 586 */ 587 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv) 588 { 589 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 590 591 i915_perf_fini(dev_priv); 592 593 pci_disable_msi(pdev); 594 } 595 596 /** 597 * i915_driver_register - register the driver with the rest of the system 598 * @dev_priv: device private 599 * 600 * Perform any steps necessary to make the driver available via kernel 601 * internal or userspace interfaces. 602 */ 603 static int i915_driver_register(struct drm_i915_private *dev_priv) 604 { 605 struct intel_display *display = dev_priv->display; 606 struct intel_gt *gt; 607 unsigned int i; 608 int ret; 609 610 i915_gem_driver_register(dev_priv); 611 i915_pmu_register(dev_priv); 612 613 intel_vgpu_register(dev_priv); 614 615 /* Reveal our presence to userspace */ 616 ret = drm_dev_register(&dev_priv->drm, 0); 617 if (ret) { 618 i915_probe_error(dev_priv, 619 "Failed to register driver for userspace access!\n"); 620 drm_dev_unregister(&dev_priv->drm); 621 i915_pmu_unregister(dev_priv); 622 i915_gem_driver_unregister(dev_priv); 623 return ret; 624 } 625 626 i915_debugfs_register(dev_priv); 627 i915_setup_sysfs(dev_priv); 628 629 /* Depends on sysfs having been initialized */ 630 i915_perf_register(dev_priv); 631 632 for_each_gt(gt, dev_priv, i) 633 intel_gt_driver_register(gt); 634 635 intel_pxp_debugfs_register(dev_priv->pxp); 636 637 i915_hwmon_register(dev_priv); 638 639 intel_display_driver_register(display); 640 641 intel_display_driver_runtime_pm_enable(display); 642 intel_runtime_pm_enable(&dev_priv->runtime_pm); 643 644 if (i915_switcheroo_register(dev_priv)) 645 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n"); 646 647 return 0; 648 } 649 650 /** 651 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() 652 * @dev_priv: device private 653 */ 654 static void i915_driver_unregister(struct drm_i915_private *dev_priv) 655 { 656 struct intel_display *display = dev_priv->display; 657 struct intel_gt *gt; 658 unsigned int i; 659 660 i915_switcheroo_unregister(dev_priv); 661 662 intel_runtime_pm_disable(&dev_priv->runtime_pm); 663 intel_display_driver_runtime_pm_disable(display); 664 665 intel_display_driver_unregister(display); 666 667 intel_pxp_fini(dev_priv); 668 669 for_each_gt(gt, dev_priv, i) 670 intel_gt_driver_unregister(gt); 671 672 i915_hwmon_unregister(dev_priv); 673 674 i915_perf_unregister(dev_priv); 675 i915_pmu_unregister(dev_priv); 676 677 i915_teardown_sysfs(dev_priv); 678 drm_dev_unplug(&dev_priv->drm); 679 680 i915_gem_driver_unregister(dev_priv); 681 } 682 683 void 684 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p) 685 { 686 drm_printf(p, "iommu: %s\n", 687 str_enabled_disabled(i915_vtd_active(i915))); 688 } 689 690 static void i915_welcome_messages(struct drm_i915_private *dev_priv) 691 { 692 if (drm_debug_enabled(DRM_UT_DRIVER)) { 693 struct drm_printer p = drm_dbg_printer(&dev_priv->drm, DRM_UT_DRIVER, 694 "device info:"); 695 struct intel_gt *gt; 696 unsigned int i; 697 698 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n", 699 INTEL_DEVID(dev_priv), 700 INTEL_REVID(dev_priv), 701 intel_platform_name(INTEL_INFO(dev_priv)->platform), 702 intel_subplatform(RUNTIME_INFO(dev_priv), 703 INTEL_INFO(dev_priv)->platform), 704 GRAPHICS_VER(dev_priv)); 705 706 intel_device_info_print(INTEL_INFO(dev_priv), 707 RUNTIME_INFO(dev_priv), &p); 708 i915_print_iommu_status(dev_priv, &p); 709 for_each_gt(gt, dev_priv, i) 710 intel_gt_info_print(>->info, &p); 711 } 712 713 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) 714 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n"); 715 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 716 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n"); 717 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) 718 drm_info(&dev_priv->drm, 719 "DRM_I915_DEBUG_RUNTIME_PM enabled\n"); 720 } 721 722 static void fence_priority_display(struct dma_fence *fence) 723 { 724 if (dma_fence_is_i915(fence)) 725 i915_gem_fence_wait_priority_display(fence); 726 } 727 728 static bool has_auxccs(struct drm_device *drm) 729 { 730 struct drm_i915_private *i915 = to_i915(drm); 731 732 return IS_GRAPHICS_VER(i915, 9, 12) && 733 !HAS_FLAT_CCS(i915); 734 } 735 736 static bool has_fenced_regions(struct drm_device *drm) 737 { 738 return intel_gt_support_legacy_fencing(to_gt(to_i915(drm))); 739 } 740 741 static bool vgpu_active(struct drm_device *drm) 742 { 743 return intel_vgpu_active(to_i915(drm)); 744 } 745 746 static const struct intel_display_parent_interface parent = { 747 .bo = &i915_display_bo_interface, 748 .dpt = &i915_display_dpt_interface, 749 .dsb = &i915_display_dsb_interface, 750 .fb_pin = &i915_display_fb_pin_interface, 751 .frontbuffer = &i915_display_frontbuffer_interface, 752 .hdcp = &i915_display_hdcp_interface, 753 .initial_plane = &i915_display_initial_plane_interface, 754 .irq = &i915_display_irq_interface, 755 .overlay = &i915_display_overlay_interface, 756 .panic = &i915_display_panic_interface, 757 .pc8 = &i915_display_pc8_interface, 758 .pcode = &i915_display_pcode_interface, 759 .rpm = &i915_display_rpm_interface, 760 .rps = &i915_display_rps_interface, 761 .stolen = &i915_display_stolen_interface, 762 .vlv_iosf = &i915_display_vlv_iosf_interface, 763 764 .fence_priority_display = fence_priority_display, 765 .has_auxccs = has_auxccs, 766 .has_fenced_regions = has_fenced_regions, 767 .vgpu_active = vgpu_active, 768 }; 769 770 const struct intel_display_parent_interface *i915_driver_parent_interface(void) 771 { 772 return &parent; 773 } 774 775 /* Ensure drm and display members are placed properly. */ 776 INTEL_DISPLAY_MEMBER_STATIC_ASSERT(struct drm_i915_private, drm, display); 777 778 static struct drm_i915_private * 779 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) 780 { 781 const struct intel_device_info *match_info = 782 (struct intel_device_info *)ent->driver_data; 783 struct drm_i915_private *i915; 784 785 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver, 786 struct drm_i915_private, drm); 787 if (IS_ERR(i915)) 788 return i915; 789 790 pci_set_drvdata(pdev, &i915->drm); 791 792 /* Device parameters start as a copy of module parameters. */ 793 i915_params_copy(&i915->params, &i915_modparams); 794 795 /* Set up device info and initial runtime info. */ 796 intel_device_info_driver_create(i915, pdev->device, match_info); 797 798 return i915; 799 } 800 801 /** 802 * i915_driver_probe - setup chip and create an initial config 803 * @pdev: PCI device 804 * @ent: matching PCI ID entry 805 * 806 * The driver probe routine has to do several things: 807 * - drive output discovery via intel_display_driver_probe() 808 * - initialize the memory manager 809 * - allocate initial config memory 810 * - setup the DRM framebuffer with the allocated memory 811 */ 812 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 813 { 814 struct drm_i915_private *i915; 815 struct intel_display *display; 816 int ret; 817 818 ret = pci_enable_device(pdev); 819 if (ret) { 820 pr_err("Failed to enable graphics device: %pe\n", ERR_PTR(ret)); 821 return ret; 822 } 823 824 i915 = i915_driver_create(pdev, ent); 825 if (IS_ERR(i915)) { 826 pci_disable_device(pdev); 827 return PTR_ERR(i915); 828 } 829 830 display = intel_display_device_probe(pdev, &parent); 831 if (IS_ERR(display)) { 832 ret = PTR_ERR(display); 833 goto out_pci_disable; 834 } 835 836 i915->display = display; 837 838 ret = i915_driver_early_probe(i915); 839 if (ret < 0) 840 goto out_pci_disable; 841 842 disable_rpm_wakeref_asserts(&i915->runtime_pm); 843 844 intel_vgpu_detect(i915); 845 846 ret = intel_gt_probe_all(i915); 847 if (ret < 0) 848 goto out_runtime_pm_put; 849 850 ret = i915_driver_mmio_probe(i915); 851 if (ret < 0) 852 goto out_runtime_pm_put; 853 854 ret = i915_driver_hw_probe(i915); 855 if (ret < 0) 856 goto out_cleanup_mmio; 857 858 ret = intel_gvt_init(i915); 859 if (ret) 860 goto out_cleanup_hw; 861 862 ret = intel_display_driver_probe_noirq(display); 863 if (ret < 0) 864 goto out_cleanup_gvt; 865 866 ret = intel_irq_install(i915); 867 if (ret) 868 goto out_cleanup_modeset; 869 870 ret = intel_display_driver_probe_nogem(display); 871 if (ret) 872 goto out_cleanup_irq; 873 874 ret = i915_gem_init(i915); 875 if (ret) 876 goto out_cleanup_modeset2; 877 878 ret = intel_pxp_init(i915); 879 if (ret && ret != -ENODEV) 880 drm_dbg(&i915->drm, "pxp init failed with %d\n", ret); 881 882 ret = intel_display_driver_probe(display); 883 if (ret) 884 goto out_cleanup_gem; 885 886 ret = i915_driver_register(i915); 887 if (ret) 888 goto out_cleanup_gem; 889 890 enable_rpm_wakeref_asserts(&i915->runtime_pm); 891 892 i915_welcome_messages(i915); 893 894 i915->do_release = true; 895 896 return 0; 897 898 out_cleanup_gem: 899 intel_pxp_fini(i915); 900 i915_gem_suspend(i915); 901 i915_gem_driver_remove(i915); 902 i915_gem_driver_release(i915); 903 out_cleanup_modeset2: 904 /* FIXME clean up the error path */ 905 intel_display_driver_remove(display); 906 intel_irq_uninstall(i915); 907 intel_display_driver_remove_noirq(display); 908 goto out_cleanup_modeset; 909 out_cleanup_irq: 910 intel_irq_uninstall(i915); 911 out_cleanup_modeset: 912 intel_display_driver_remove_nogem(display); 913 out_cleanup_gvt: 914 intel_gvt_driver_remove(i915); 915 out_cleanup_hw: 916 i915_driver_hw_remove(i915); 917 intel_memory_regions_driver_release(i915); 918 i915_ggtt_driver_release(i915); 919 i915_gem_drain_freed_objects(i915); 920 i915_ggtt_driver_late_release(i915); 921 out_cleanup_mmio: 922 i915_driver_mmio_release(i915); 923 out_runtime_pm_put: 924 enable_rpm_wakeref_asserts(&i915->runtime_pm); 925 i915_driver_late_release(i915); 926 out_pci_disable: 927 pci_disable_device(pdev); 928 i915_probe_error(i915, "Device initialization failed (%d)\n", ret); 929 return ret; 930 } 931 932 void i915_driver_remove(struct drm_i915_private *i915) 933 { 934 struct intel_display *display = i915->display; 935 intel_wakeref_t wakeref; 936 937 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 938 939 i915_driver_unregister(i915); 940 941 /* Flush any external code that still may be under the RCU lock */ 942 synchronize_rcu(); 943 944 i915_gem_suspend(i915); 945 946 intel_gvt_driver_remove(i915); 947 948 intel_display_driver_remove(display); 949 950 intel_irq_uninstall(i915); 951 952 intel_display_driver_remove_noirq(display); 953 954 i915_reset_error_state(i915); 955 i915_gem_driver_remove(i915); 956 957 intel_display_driver_remove_nogem(display); 958 959 i915_driver_hw_remove(i915); 960 961 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 962 } 963 964 static void i915_driver_release(struct drm_device *dev) 965 { 966 struct drm_i915_private *dev_priv = to_i915(dev); 967 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 968 intel_wakeref_t wakeref; 969 970 if (!dev_priv->do_release) 971 return; 972 973 wakeref = intel_runtime_pm_get(rpm); 974 975 i915_gem_driver_release(dev_priv); 976 977 intel_memory_regions_driver_release(dev_priv); 978 i915_ggtt_driver_release(dev_priv); 979 i915_gem_drain_freed_objects(dev_priv); 980 i915_ggtt_driver_late_release(dev_priv); 981 982 i915_driver_mmio_release(dev_priv); 983 984 intel_runtime_pm_put(rpm, wakeref); 985 986 intel_runtime_pm_driver_release(rpm); 987 988 i915_driver_late_release(dev_priv); 989 } 990 991 static int i915_driver_open(struct drm_device *dev, struct drm_file *file) 992 { 993 struct drm_i915_private *i915 = to_i915(dev); 994 int ret; 995 996 ret = i915_gem_open(i915, file); 997 if (ret) 998 return ret; 999 1000 return 0; 1001 } 1002 1003 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) 1004 { 1005 struct drm_i915_file_private *file_priv = file->driver_priv; 1006 1007 i915_gem_context_close(file); 1008 i915_drm_client_put(file_priv->client); 1009 1010 kfree_rcu(file_priv, rcu); 1011 1012 /* Catch up with all the deferred frees from "this" client */ 1013 i915_gem_flush_free_objects(to_i915(dev)); 1014 } 1015 1016 void i915_driver_shutdown(struct drm_i915_private *i915) 1017 { 1018 struct intel_display *display = i915->display; 1019 1020 disable_rpm_wakeref_asserts(&i915->runtime_pm); 1021 intel_runtime_pm_disable(&i915->runtime_pm); 1022 1023 intel_display_driver_shutdown(display); 1024 1025 intel_irq_suspend(i915); 1026 1027 intel_dmc_suspend(display); 1028 1029 i915_gem_suspend(i915); 1030 1031 /* 1032 * TODO: 1033 * - unify the pci_driver::shutdown sequence here with the 1034 * pci_driver.driver.pm.poweroff,poweroff_late sequence. 1035 * - unify the driver remove and system/runtime suspend sequences with 1036 * the above unified shutdown/poweroff sequence. 1037 */ 1038 1039 intel_display_driver_shutdown_late(display); 1040 enable_rpm_wakeref_asserts(&i915->runtime_pm); 1041 1042 intel_runtime_pm_driver_last_release(&i915->runtime_pm); 1043 } 1044 1045 static bool suspend_to_idle(struct drm_i915_private *dev_priv) 1046 { 1047 #if IS_ENABLED(CONFIG_ACPI_SLEEP) 1048 if (acpi_target_system_state() < ACPI_STATE_S3) 1049 return true; 1050 #endif 1051 return false; 1052 } 1053 1054 static void i915_drm_complete(struct drm_device *dev) 1055 { 1056 struct drm_i915_private *i915 = to_i915(dev); 1057 1058 intel_pxp_resume_complete(i915->pxp); 1059 } 1060 1061 static int i915_drm_prepare(struct drm_device *dev) 1062 { 1063 struct drm_i915_private *i915 = to_i915(dev); 1064 1065 intel_pxp_suspend_prepare(i915->pxp); 1066 1067 /* 1068 * NB intel_display_driver_pm_suspend() may issue new requests after 1069 * we've ostensibly marked the GPU as ready-to-sleep here. We need to 1070 * split out that work and pull it forward so that after point, the GPU 1071 * is not woken again. 1072 */ 1073 return i915_gem_backup_suspend(i915); 1074 } 1075 1076 static int i915_drm_suspend(struct drm_device *dev) 1077 { 1078 struct drm_i915_private *dev_priv = to_i915(dev); 1079 struct intel_display *display = dev_priv->display; 1080 pci_power_t opregion_target_state; 1081 1082 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1083 1084 intel_display_driver_pm_suspend(display); 1085 1086 intel_irq_suspend(dev_priv); 1087 1088 /* Must be called before GGTT is suspended. */ 1089 intel_dpt_suspend(display); 1090 i915_ggtt_suspend(to_gt(dev_priv)->ggtt); 1091 1092 i9xx_display_sr_save(display); 1093 1094 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; 1095 intel_opregion_suspend(display, opregion_target_state); 1096 1097 dev_priv->suspend_count++; 1098 1099 intel_dmc_suspend(display); 1100 1101 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1102 1103 i915_gem_drain_freed_objects(dev_priv); 1104 1105 return 0; 1106 } 1107 1108 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) 1109 { 1110 struct drm_i915_private *dev_priv = to_i915(dev); 1111 struct intel_display *display = dev_priv->display; 1112 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1113 struct intel_gt *gt; 1114 int ret, i; 1115 bool s2idle = !hibernation && suspend_to_idle(dev_priv); 1116 1117 disable_rpm_wakeref_asserts(rpm); 1118 1119 intel_pxp_suspend(dev_priv->pxp); 1120 1121 i915_gem_suspend_late(dev_priv); 1122 1123 for_each_gt(gt, dev_priv, i) 1124 intel_uncore_suspend(gt->uncore); 1125 1126 intel_display_driver_pm_suspend_late(display, s2idle); 1127 1128 ret = vlv_suspend_complete(dev_priv); 1129 if (ret) { 1130 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret); 1131 intel_display_driver_pm_resume_early(display); 1132 } 1133 1134 enable_rpm_wakeref_asserts(rpm); 1135 1136 if (!dev_priv->uncore.user_forcewake_count) 1137 intel_runtime_pm_driver_release(rpm); 1138 1139 return ret; 1140 } 1141 1142 static int i915_drm_suspend_noirq(struct drm_device *dev, bool hibernation) 1143 { 1144 struct drm_i915_private *dev_priv = to_i915(dev); 1145 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1146 1147 /* 1148 * During hibernation on some platforms the BIOS may try to access 1149 * the device even though it's already in D3 and hang the machine. So 1150 * leave the device in D0 on those platforms and hope the BIOS will 1151 * power down the device properly. The issue was seen on multiple old 1152 * GENs with different BIOS vendors, so having an explicit blacklist 1153 * is impractical; apply the workaround on everything pre GEN6. The 1154 * platforms where the issue was seen: 1155 * Lenovo Thinkpad X301, X61s, X60, T60, X41 1156 * Fujitsu FSC S7110 1157 * Acer Aspire 1830T 1158 * 1159 * pci_save_state() prevents drivers/pci from 1160 * automagically putting the device into D3. 1161 */ 1162 if (hibernation && GRAPHICS_VER(dev_priv) < 6) 1163 pci_save_state(pdev); 1164 1165 return 0; 1166 } 1167 1168 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915, 1169 pm_message_t state) 1170 { 1171 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 1172 int error; 1173 1174 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND && 1175 state.event != PM_EVENT_FREEZE)) 1176 return -EINVAL; 1177 1178 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1179 return 0; 1180 1181 error = i915_drm_suspend(&i915->drm); 1182 if (error) 1183 return error; 1184 1185 error = i915_drm_suspend_late(&i915->drm, false); 1186 if (error) 1187 return error; 1188 1189 pci_save_state(pdev); 1190 pci_set_power_state(pdev, PCI_D3hot); 1191 1192 return 0; 1193 } 1194 1195 static int i915_drm_resume(struct drm_device *dev) 1196 { 1197 struct drm_i915_private *dev_priv = to_i915(dev); 1198 struct intel_display *display = dev_priv->display; 1199 struct intel_gt *gt; 1200 int ret, i; 1201 1202 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1203 1204 ret = i915_pcode_init(dev_priv); 1205 if (ret) 1206 return ret; 1207 1208 sanitize_gpu(dev_priv); 1209 1210 ret = i915_ggtt_enable_hw(dev_priv); 1211 if (ret) 1212 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n"); 1213 1214 i915_ggtt_resume(to_gt(dev_priv)->ggtt); 1215 1216 for_each_gt(gt, dev_priv, i) 1217 if (GRAPHICS_VER(gt->i915) >= 8) 1218 setup_private_pat(gt); 1219 1220 /* Must be called after GGTT is resumed. */ 1221 intel_dpt_resume(display); 1222 1223 intel_dmc_resume(display); 1224 1225 i9xx_display_sr_restore(display); 1226 1227 intel_gmbus_reset(display); 1228 1229 intel_pps_unlock_regs_wa(display); 1230 1231 intel_init_pch_refclk(display); 1232 1233 /* 1234 * Interrupts have to be enabled before any batches are run. If not the 1235 * GPU will hang. i915_gem_init_hw() will initiate batches to 1236 * update/restore the context. 1237 * 1238 * drm_mode_config_reset() needs AUX interrupts. 1239 * 1240 * Modeset enabling in intel_display_driver_init_hw() also needs working 1241 * interrupts. 1242 */ 1243 intel_irq_resume(dev_priv); 1244 1245 if (intel_display_device_present(display)) 1246 drm_mode_config_reset(dev); 1247 1248 i915_gem_resume(dev_priv); 1249 1250 intel_display_driver_init_hw(display); 1251 1252 intel_clock_gating_init(&dev_priv->drm); 1253 1254 intel_display_driver_pm_resume(display); 1255 1256 intel_gvt_resume(dev_priv); 1257 1258 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1259 1260 return 0; 1261 } 1262 1263 static int i915_drm_resume_early(struct drm_device *dev) 1264 { 1265 struct drm_i915_private *dev_priv = to_i915(dev); 1266 struct intel_display *display = dev_priv->display; 1267 struct intel_gt *gt; 1268 int ret, i; 1269 1270 /* 1271 * We have a resume ordering issue with the snd-hda driver also 1272 * requiring our device to be power up. Due to the lack of a 1273 * parent/child relationship we currently solve this with an early 1274 * resume hook. 1275 * 1276 * FIXME: This should be solved with a special hdmi sink device or 1277 * similar so that power domains can be employed. 1278 */ 1279 1280 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1281 1282 ret = vlv_resume_prepare(dev_priv, false); 1283 if (ret) 1284 drm_err(&dev_priv->drm, 1285 "Resume prepare failed: %d, continuing anyway\n", ret); 1286 1287 for_each_gt(gt, dev_priv, i) 1288 intel_gt_resume_early(gt); 1289 1290 intel_display_driver_pm_resume_early(display); 1291 1292 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1293 1294 return ret; 1295 } 1296 1297 int i915_driver_resume_switcheroo(struct drm_i915_private *i915) 1298 { 1299 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 1300 int ret; 1301 1302 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1303 return 0; 1304 1305 ret = pci_set_power_state(pdev, PCI_D0); 1306 if (ret) 1307 return ret; 1308 1309 pci_restore_state(pdev); 1310 1311 ret = i915_drm_resume_early(&i915->drm); 1312 if (ret) 1313 return ret; 1314 1315 return i915_drm_resume(&i915->drm); 1316 } 1317 1318 static int i915_pm_prepare(struct device *kdev) 1319 { 1320 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1321 1322 if (!i915) { 1323 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1324 return -ENODEV; 1325 } 1326 1327 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1328 return 0; 1329 1330 return i915_drm_prepare(&i915->drm); 1331 } 1332 1333 static int i915_pm_suspend(struct device *kdev) 1334 { 1335 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1336 1337 if (!i915) { 1338 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1339 return -ENODEV; 1340 } 1341 1342 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1343 return 0; 1344 1345 return i915_drm_suspend(&i915->drm); 1346 } 1347 1348 static int i915_pm_suspend_late(struct device *kdev) 1349 { 1350 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1351 1352 /* 1353 * We have a suspend ordering issue with the snd-hda driver also 1354 * requiring our device to be power up. Due to the lack of a 1355 * parent/child relationship we currently solve this with an late 1356 * suspend hook. 1357 * 1358 * FIXME: This should be solved with a special hdmi sink device or 1359 * similar so that power domains can be employed. 1360 */ 1361 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1362 return 0; 1363 1364 return i915_drm_suspend_late(&i915->drm, false); 1365 } 1366 1367 static int i915_pm_suspend_noirq(struct device *kdev) 1368 { 1369 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1370 1371 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1372 return 0; 1373 1374 return i915_drm_suspend_noirq(&i915->drm, false); 1375 } 1376 1377 static int i915_pm_poweroff_late(struct device *kdev) 1378 { 1379 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1380 1381 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1382 return 0; 1383 1384 return i915_drm_suspend_late(&i915->drm, true); 1385 } 1386 1387 static int i915_pm_poweroff_noirq(struct device *kdev) 1388 { 1389 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1390 1391 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1392 return 0; 1393 1394 return i915_drm_suspend_noirq(&i915->drm, true); 1395 } 1396 1397 static int i915_pm_resume_early(struct device *kdev) 1398 { 1399 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1400 1401 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1402 return 0; 1403 1404 return i915_drm_resume_early(&i915->drm); 1405 } 1406 1407 static int i915_pm_resume(struct device *kdev) 1408 { 1409 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1410 1411 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1412 return 0; 1413 1414 return i915_drm_resume(&i915->drm); 1415 } 1416 1417 static void i915_pm_complete(struct device *kdev) 1418 { 1419 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1420 1421 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1422 return; 1423 1424 i915_drm_complete(&i915->drm); 1425 } 1426 1427 /* freeze: before creating the hibernation_image */ 1428 static int i915_pm_freeze(struct device *kdev) 1429 { 1430 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1431 int ret; 1432 1433 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1434 ret = i915_drm_suspend(&i915->drm); 1435 if (ret) 1436 return ret; 1437 } 1438 1439 ret = i915_gem_freeze(i915); 1440 if (ret) 1441 return ret; 1442 1443 return 0; 1444 } 1445 1446 static int i915_pm_freeze_late(struct device *kdev) 1447 { 1448 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1449 int ret; 1450 1451 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1452 ret = i915_drm_suspend_late(&i915->drm, true); 1453 if (ret) 1454 return ret; 1455 } 1456 1457 ret = i915_gem_freeze_late(i915); 1458 if (ret) 1459 return ret; 1460 1461 return 0; 1462 } 1463 1464 /* thaw: called after creating the hibernation image, but before turning off. */ 1465 static int i915_pm_thaw_early(struct device *kdev) 1466 { 1467 return i915_pm_resume_early(kdev); 1468 } 1469 1470 static int i915_pm_thaw(struct device *kdev) 1471 { 1472 return i915_pm_resume(kdev); 1473 } 1474 1475 /* restore: called after loading the hibernation image. */ 1476 static int i915_pm_restore_early(struct device *kdev) 1477 { 1478 return i915_pm_resume_early(kdev); 1479 } 1480 1481 static int i915_pm_restore(struct device *kdev) 1482 { 1483 return i915_pm_resume(kdev); 1484 } 1485 1486 static int i915_pm_runtime_suspend(struct device *kdev) 1487 { 1488 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1489 struct intel_display *display = dev_priv->display; 1490 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1491 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1492 struct pci_dev *root_pdev; 1493 struct intel_gt *gt; 1494 int ret, i; 1495 1496 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1497 return -ENODEV; 1498 1499 drm_dbg(&dev_priv->drm, "Suspending device\n"); 1500 1501 disable_rpm_wakeref_asserts(rpm); 1502 1503 /* 1504 * We are safe here against re-faults, since the fault handler takes 1505 * an RPM reference. 1506 */ 1507 i915_gem_runtime_suspend(dev_priv); 1508 1509 intel_pxp_runtime_suspend(dev_priv->pxp); 1510 1511 for_each_gt(gt, dev_priv, i) 1512 intel_gt_runtime_suspend(gt); 1513 1514 intel_display_driver_pm_runtime_suspend(display); 1515 1516 intel_irq_suspend(dev_priv); 1517 1518 for_each_gt(gt, dev_priv, i) 1519 intel_uncore_suspend(gt->uncore); 1520 1521 intel_display_driver_pm_runtime_suspend_late(display); 1522 1523 ret = vlv_suspend_complete(dev_priv); 1524 if (ret) { 1525 drm_err(&dev_priv->drm, 1526 "Runtime suspend failed, disabling it (%d)\n", ret); 1527 1528 intel_display_driver_pm_runtime_resume_early(display); 1529 1530 for_each_gt(gt, dev_priv, i) 1531 intel_uncore_runtime_resume(gt->uncore); 1532 1533 intel_irq_resume(dev_priv); 1534 1535 for_each_gt(gt, dev_priv, i) 1536 intel_gt_runtime_resume(gt); 1537 1538 intel_display_driver_pm_runtime_resume(display); 1539 1540 enable_rpm_wakeref_asserts(rpm); 1541 1542 return ret; 1543 } 1544 1545 enable_rpm_wakeref_asserts(rpm); 1546 intel_runtime_pm_driver_release(rpm); 1547 1548 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore)) 1549 drm_err(&dev_priv->drm, 1550 "Unclaimed access detected prior to suspending\n"); 1551 1552 /* 1553 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX 1554 * This should be totally removed when we handle the pci states properly 1555 * on runtime PM. 1556 */ 1557 root_pdev = pcie_find_root_port(pdev); 1558 if (root_pdev) 1559 pci_d3cold_disable(root_pdev); 1560 1561 assert_forcewakes_inactive(&dev_priv->uncore); 1562 1563 drm_dbg(&dev_priv->drm, "Device suspended\n"); 1564 return 0; 1565 } 1566 1567 static int i915_pm_runtime_resume(struct device *kdev) 1568 { 1569 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1570 struct intel_display *display = dev_priv->display; 1571 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1572 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1573 struct pci_dev *root_pdev; 1574 struct intel_gt *gt; 1575 int ret, i; 1576 1577 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1578 return -ENODEV; 1579 1580 drm_dbg(&dev_priv->drm, "Resuming device\n"); 1581 1582 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count)); 1583 disable_rpm_wakeref_asserts(rpm); 1584 1585 root_pdev = pcie_find_root_port(pdev); 1586 if (root_pdev) 1587 pci_d3cold_enable(root_pdev); 1588 1589 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore)) 1590 drm_dbg(&dev_priv->drm, 1591 "Unclaimed access during suspend, bios?\n"); 1592 1593 intel_display_driver_pm_runtime_resume_early(display); 1594 1595 ret = vlv_resume_prepare(dev_priv, true); 1596 1597 for_each_gt(gt, dev_priv, i) 1598 intel_uncore_runtime_resume(gt->uncore); 1599 1600 intel_irq_resume(dev_priv); 1601 1602 /* 1603 * No point of rolling back things in case of an error, as the best 1604 * we can do is to hope that things will still work (and disable RPM). 1605 */ 1606 for_each_gt(gt, dev_priv, i) 1607 intel_gt_runtime_resume(gt); 1608 1609 intel_pxp_runtime_resume(dev_priv->pxp); 1610 1611 intel_display_driver_pm_runtime_resume(display); 1612 1613 enable_rpm_wakeref_asserts(rpm); 1614 1615 if (ret) 1616 drm_err(&dev_priv->drm, 1617 "Runtime resume failed, disabling it (%d)\n", ret); 1618 else 1619 drm_dbg(&dev_priv->drm, "Device resumed\n"); 1620 1621 return ret; 1622 } 1623 1624 const struct dev_pm_ops i915_pm_ops = { 1625 /* 1626 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, 1627 * PMSG_RESUME] 1628 */ 1629 .prepare = i915_pm_prepare, 1630 .suspend = i915_pm_suspend, 1631 .suspend_late = i915_pm_suspend_late, 1632 .suspend_noirq = i915_pm_suspend_noirq, 1633 .resume_early = i915_pm_resume_early, 1634 .resume = i915_pm_resume, 1635 .complete = i915_pm_complete, 1636 1637 /* 1638 * S4 event handlers 1639 * @freeze* : called (1) before creating the 1640 * hibernation image [PMSG_FREEZE] and 1641 * (2) after rebooting, before restoring 1642 * the image [PMSG_QUIESCE] 1643 * @thaw* : called (1) after creating the hibernation 1644 * image, before writing it [PMSG_THAW] 1645 * and (2) after failing to create or 1646 * restore the image [PMSG_RECOVER] 1647 * @poweroff* : called after writing the hibernation 1648 * image, before rebooting [PMSG_HIBERNATE] 1649 * @restore* : called after rebooting and restoring the 1650 * hibernation image [PMSG_RESTORE] 1651 */ 1652 .freeze = i915_pm_freeze, 1653 .freeze_late = i915_pm_freeze_late, 1654 .thaw_early = i915_pm_thaw_early, 1655 .thaw = i915_pm_thaw, 1656 .poweroff = i915_pm_suspend, 1657 .poweroff_late = i915_pm_poweroff_late, 1658 .poweroff_noirq = i915_pm_poweroff_noirq, 1659 .restore_early = i915_pm_restore_early, 1660 .restore = i915_pm_restore, 1661 1662 /* S0ix (via runtime suspend) event handlers */ 1663 .runtime_suspend = i915_pm_runtime_suspend, 1664 .runtime_resume = i915_pm_runtime_resume, 1665 }; 1666 1667 static const struct file_operations i915_driver_fops = { 1668 .owner = THIS_MODULE, 1669 .open = drm_open, 1670 .release = drm_release_noglobal, 1671 .unlocked_ioctl = drm_ioctl, 1672 .mmap = i915_gem_mmap, 1673 .poll = drm_poll, 1674 .read = drm_read, 1675 .compat_ioctl = i915_ioc32_compat_ioctl, 1676 .llseek = noop_llseek, 1677 #ifdef CONFIG_PROC_FS 1678 .show_fdinfo = drm_show_fdinfo, 1679 #endif 1680 .fop_flags = FOP_UNSIGNED_OFFSET, 1681 }; 1682 1683 static int 1684 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, 1685 struct drm_file *file) 1686 { 1687 return -ENODEV; 1688 } 1689 1690 static const struct drm_ioctl_desc i915_ioctls[] = { 1691 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1692 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), 1693 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), 1694 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), 1695 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), 1696 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), 1697 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW), 1698 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1699 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), 1700 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), 1701 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1702 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), 1703 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1704 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1705 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), 1706 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), 1707 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1708 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1709 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH), 1710 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW), 1711 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1712 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1713 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW), 1714 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), 1715 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), 1716 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW), 1717 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1718 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1719 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), 1720 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW), 1721 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), 1722 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), 1723 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), 1724 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW), 1725 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), 1726 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), 1727 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW), 1728 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW), 1729 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), 1730 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_crtc_get_pipe_from_crtc_id_ioctl, 0), 1731 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), 1732 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER), 1733 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER), 1734 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER), 1735 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER), 1736 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW), 1737 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), 1738 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), 1739 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), 1740 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW), 1741 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), 1742 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), 1743 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), 1744 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), 1745 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW), 1746 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW), 1747 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW), 1748 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW), 1749 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW), 1750 }; 1751 1752 /* 1753 * Interface history: 1754 * 1755 * 1.1: Original. 1756 * 1.2: Add Power Management 1757 * 1.3: Add vblank support 1758 * 1.4: Fix cmdbuffer path, add heap destroy 1759 * 1.5: Add vblank pipe configuration 1760 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 1761 * - Support vertical blank on secondary display pipe 1762 */ 1763 #define DRIVER_MAJOR 1 1764 #define DRIVER_MINOR 6 1765 #define DRIVER_PATCHLEVEL 0 1766 1767 static const struct drm_driver i915_drm_driver = { 1768 .driver_features = 1769 DRIVER_GEM | 1770 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ | 1771 DRIVER_SYNCOBJ_TIMELINE, 1772 .release = i915_driver_release, 1773 .open = i915_driver_open, 1774 .postclose = i915_driver_postclose, 1775 .show_fdinfo = PTR_IF(IS_ENABLED(CONFIG_PROC_FS), i915_drm_client_fdinfo), 1776 1777 .gem_prime_import = i915_gem_prime_import, 1778 1779 .dumb_create = i915_gem_dumb_create, 1780 .dumb_map_offset = i915_gem_dumb_mmap_offset, 1781 1782 INTEL_FBDEV_DRIVER_OPS, 1783 1784 .ioctls = i915_ioctls, 1785 .num_ioctls = ARRAY_SIZE(i915_ioctls), 1786 .fops = &i915_driver_fops, 1787 .name = DRIVER_NAME, 1788 .desc = DRIVER_DESC, 1789 .major = DRIVER_MAJOR, 1790 .minor = DRIVER_MINOR, 1791 .patchlevel = DRIVER_PATCHLEVEL, 1792 }; 1793