1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #include <linux/aperture.h> 31 #include <linux/acpi.h> 32 #include <linux/device.h> 33 #include <linux/module.h> 34 #include <linux/oom.h> 35 #include <linux/pci.h> 36 #include <linux/pm.h> 37 #include <linux/pm_runtime.h> 38 #include <linux/slab.h> 39 #include <linux/string_helpers.h> 40 #include <linux/vga_switcheroo.h> 41 #include <linux/vt.h> 42 43 #include <drm/drm_atomic_helper.h> 44 #include <drm/drm_client.h> 45 #include <drm/drm_client_event.h> 46 #include <drm/drm_ioctl.h> 47 #include <drm/drm_managed.h> 48 #include <drm/drm_probe_helper.h> 49 #include <drm/intel/display_member.h> 50 #include <drm/intel/display_parent_interface.h> 51 52 #include "display/i9xx_display_sr.h" 53 #include "display/intel_bw.h" 54 #include "display/intel_cdclk.h" 55 #include "display/intel_crtc.h" 56 #include "display/intel_display_device.h" 57 #include "display/intel_display_driver.h" 58 #include "display/intel_display_power.h" 59 #include "display/intel_dmc.h" 60 #include "display/intel_dp.h" 61 #include "display/intel_dpt.h" 62 #include "display/intel_dram.h" 63 #include "display/intel_encoder.h" 64 #include "display/intel_fbdev.h" 65 #include "display/intel_gmbus.h" 66 #include "display/intel_hotplug.h" 67 #include "display/intel_opregion.h" 68 #include "display/intel_overlay.h" 69 #include "display/intel_pch_refclk.h" 70 #include "display/intel_pps.h" 71 #include "display/intel_sbi.h" 72 #include "display/intel_sprite_uapi.h" 73 #include "display/skl_watermark.h" 74 75 #include "gem/i915_gem_context.h" 76 #include "gem/i915_gem_create.h" 77 #include "gem/i915_gem_dmabuf.h" 78 #include "gem/i915_gem_ioctls.h" 79 #include "gem/i915_gem_mman.h" 80 #include "gem/i915_gem_pm.h" 81 #include "gt/intel_gt.h" 82 #include "gt/intel_gt_pm.h" 83 #include "gt/intel_gt_print.h" 84 #include "gt/intel_rc6.h" 85 #include "gt/intel_rps.h" 86 87 #include "pxp/intel_pxp.h" 88 #include "pxp/intel_pxp_debugfs.h" 89 #include "pxp/intel_pxp_pm.h" 90 91 #include "i915_debugfs.h" 92 #include "i915_display_pc8.h" 93 #include "i915_driver.h" 94 #include "i915_drm_client.h" 95 #include "i915_drv.h" 96 #include "i915_edram.h" 97 #include "i915_file_private.h" 98 #include "i915_getparam.h" 99 #include "i915_gmch.h" 100 #include "i915_hdcp_gsc.h" 101 #include "i915_hwmon.h" 102 #include "i915_initial_plane.h" 103 #include "i915_ioc32.h" 104 #include "i915_ioctl.h" 105 #include "i915_irq.h" 106 #include "i915_memcpy.h" 107 #include "i915_panic.h" 108 #include "i915_perf.h" 109 #include "i915_query.h" 110 #include "i915_reg.h" 111 #include "i915_switcheroo.h" 112 #include "i915_sysfs.h" 113 #include "i915_utils.h" 114 #include "i915_vgpu.h" 115 #include "intel_clock_gating.h" 116 #include "intel_cpu_info.h" 117 #include "intel_gvt.h" 118 #include "intel_memory_region.h" 119 #include "intel_pci_config.h" 120 #include "intel_pcode.h" 121 #include "intel_region_ttm.h" 122 #include "vlv_iosf_sb.h" 123 #include "vlv_suspend.h" 124 125 static const struct drm_driver i915_drm_driver; 126 127 static int i915_workqueues_init(struct drm_i915_private *dev_priv) 128 { 129 /* 130 * The i915 workqueue is primarily used for batched retirement of 131 * requests (and thus managing bo) once the task has been completed 132 * by the GPU. i915_retire_requests() is called directly when we 133 * need high-priority retirement, such as waiting for an explicit 134 * bo. 135 * 136 * It is also used for periodic low-priority events, such as 137 * idle-timers and recording error state. 138 * 139 * All tasks on the workqueue are expected to acquire the dev mutex 140 * so there is no point in running more than one instance of the 141 * workqueue at any time. Use an ordered one. 142 */ 143 dev_priv->wq = alloc_ordered_workqueue("i915", 0); 144 if (dev_priv->wq == NULL) 145 goto out_err; 146 147 /* 148 * The unordered i915 workqueue should be used for all work 149 * scheduling that do not require running in order, which used 150 * to be scheduled on the system_wq before moving to a driver 151 * instance due deprecation of flush_scheduled_work(). 152 */ 153 dev_priv->unordered_wq = alloc_workqueue("i915-unordered", 0, 0); 154 if (dev_priv->unordered_wq == NULL) 155 goto out_free_wq; 156 157 return 0; 158 159 out_free_wq: 160 destroy_workqueue(dev_priv->wq); 161 out_err: 162 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n"); 163 164 return -ENOMEM; 165 } 166 167 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) 168 { 169 destroy_workqueue(dev_priv->unordered_wq); 170 destroy_workqueue(dev_priv->wq); 171 } 172 173 /* 174 * We don't keep the workarounds for pre-production hardware, so we expect our 175 * driver to fail on these machines in one way or another. A little warning on 176 * dmesg may help both the user and the bug triagers. 177 * 178 * Our policy for removing pre-production workarounds is to keep the 179 * current gen workarounds as a guide to the bring-up of the next gen 180 * (workarounds have a habit of persisting!). Anything older than that 181 * should be removed along with the complications they introduce. 182 */ 183 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) 184 { 185 bool pre = false; 186 187 pre |= IS_HASWELL_EARLY_SDV(dev_priv); 188 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6; 189 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA; 190 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 191 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3; 192 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7; 193 pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 194 pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 195 pre |= IS_DG2_G10(dev_priv) && INTEL_REVID(dev_priv) < 0x8; 196 pre |= IS_DG2_G11(dev_priv) && INTEL_REVID(dev_priv) < 0x5; 197 pre |= IS_DG2_G12(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 198 199 if (pre) { 200 drm_err(&dev_priv->drm, "This is a pre-production stepping. " 201 "It may not be fully functional.\n"); 202 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); 203 } 204 } 205 206 static void sanitize_gpu(struct drm_i915_private *i915) 207 { 208 if (!intel_gt_gpu_reset_clobbers_display(to_gt(i915))) { 209 struct intel_gt *gt; 210 unsigned int i; 211 212 for_each_gt(gt, i915, i) 213 intel_gt_reset_all_engines(gt); 214 } 215 } 216 217 /** 218 * i915_driver_early_probe - setup state not requiring device access 219 * @dev_priv: device private 220 * 221 * Initialize everything that is a "SW-only" state, that is state not 222 * requiring accessing the device or exposing the driver via kernel internal 223 * or userspace interfaces. Example steps belonging here: lock initialization, 224 * system memory allocation, setting up device specific attributes and 225 * function hooks not requiring accessing the device. 226 */ 227 static int i915_driver_early_probe(struct drm_i915_private *dev_priv) 228 { 229 struct intel_display *display = dev_priv->display; 230 int ret = 0; 231 232 intel_device_info_runtime_init_early(dev_priv); 233 234 intel_step_init(dev_priv); 235 236 intel_uncore_mmio_debug_init_early(dev_priv); 237 238 spin_lock_init(&dev_priv->gpu_error.lock); 239 240 intel_sbi_init(display); 241 vlv_iosf_sb_init(dev_priv); 242 mutex_init(&dev_priv->sb_lock); 243 244 i915_memcpy_init_early(dev_priv); 245 intel_runtime_pm_init_early(&dev_priv->runtime_pm); 246 247 ret = i915_workqueues_init(dev_priv); 248 if (ret < 0) 249 return ret; 250 251 ret = vlv_suspend_init(dev_priv); 252 if (ret < 0) 253 goto err_workqueues; 254 255 ret = intel_region_ttm_device_init(dev_priv); 256 if (ret) 257 goto err_ttm; 258 259 ret = intel_root_gt_init_early(dev_priv); 260 if (ret < 0) 261 goto err_rootgt; 262 263 i915_gem_init_early(dev_priv); 264 265 intel_irq_init(dev_priv); 266 intel_display_driver_early_probe(display); 267 intel_clock_gating_hooks_init(&dev_priv->drm); 268 269 intel_detect_preproduction_hw(dev_priv); 270 271 return 0; 272 273 err_rootgt: 274 intel_region_ttm_device_fini(dev_priv); 275 err_ttm: 276 vlv_suspend_cleanup(dev_priv); 277 err_workqueues: 278 i915_workqueues_cleanup(dev_priv); 279 return ret; 280 } 281 ALLOW_ERROR_INJECTION(i915_driver_early_probe, ERRNO); 282 283 /** 284 * i915_driver_late_release - cleanup the setup done in 285 * i915_driver_early_probe() 286 * @dev_priv: device private 287 */ 288 static void i915_driver_late_release(struct drm_i915_private *dev_priv) 289 { 290 struct intel_display *display = dev_priv->display; 291 292 intel_irq_fini(dev_priv); 293 intel_power_domains_cleanup(display); 294 i915_gem_cleanup_early(dev_priv); 295 intel_gt_driver_late_release_all(dev_priv); 296 intel_region_ttm_device_fini(dev_priv); 297 vlv_suspend_cleanup(dev_priv); 298 i915_workqueues_cleanup(dev_priv); 299 300 mutex_destroy(&dev_priv->sb_lock); 301 vlv_iosf_sb_fini(dev_priv); 302 intel_sbi_fini(display); 303 304 i915_params_free(&dev_priv->params); 305 306 intel_display_device_remove(display); 307 } 308 309 /** 310 * i915_driver_mmio_probe - setup device MMIO 311 * @dev_priv: device private 312 * 313 * Setup minimal device state necessary for MMIO accesses later in the 314 * initialization sequence. The setup here should avoid any other device-wide 315 * side effects or exposing the driver via kernel internal or user space 316 * interfaces. 317 */ 318 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) 319 { 320 struct intel_display *display = dev_priv->display; 321 struct intel_gt *gt; 322 int ret, i; 323 324 ret = i915_gmch_bridge_setup(dev_priv); 325 if (ret < 0) 326 return ret; 327 328 for_each_gt(gt, dev_priv, i) { 329 ret = intel_uncore_init_mmio(gt->uncore); 330 if (ret) 331 return ret; 332 333 ret = drmm_add_action_or_reset(&dev_priv->drm, 334 intel_uncore_fini_mmio, 335 gt->uncore); 336 if (ret) 337 return ret; 338 } 339 340 /* Try to make sure MCHBAR is enabled before poking at it */ 341 i915_gmch_bar_setup(dev_priv); 342 intel_device_info_runtime_init(dev_priv); 343 intel_display_device_info_runtime_init(display); 344 345 for_each_gt(gt, dev_priv, i) { 346 ret = intel_gt_init_mmio(gt); 347 if (ret) 348 goto err_uncore; 349 } 350 351 /* As early as possible, scrub existing GPU state before clobbering */ 352 sanitize_gpu(dev_priv); 353 354 return 0; 355 356 err_uncore: 357 i915_gmch_bar_teardown(dev_priv); 358 359 return ret; 360 } 361 ALLOW_ERROR_INJECTION(i915_driver_mmio_probe, ERRNO); 362 363 /** 364 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe() 365 * @dev_priv: device private 366 */ 367 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv) 368 { 369 i915_gmch_bar_teardown(dev_priv); 370 } 371 372 /** 373 * i915_set_dma_info - set all relevant PCI dma info as configured for the 374 * platform 375 * @i915: valid i915 instance 376 * 377 * Set the dma max segment size, device and coherent masks. The dma mask set 378 * needs to occur before i915_ggtt_probe_hw. 379 * 380 * A couple of platforms have special needs. Address them as well. 381 * 382 */ 383 static int i915_set_dma_info(struct drm_i915_private *i915) 384 { 385 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size; 386 int ret; 387 388 GEM_BUG_ON(!mask_size); 389 390 /* 391 * We don't have a max segment size, so set it to the max so sg's 392 * debugging layer doesn't complain 393 */ 394 dma_set_max_seg_size(i915->drm.dev, UINT_MAX); 395 396 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 397 if (ret) 398 goto mask_err; 399 400 /* overlay on gen2 is broken and can't address above 1G */ 401 if (GRAPHICS_VER(i915) == 2) 402 mask_size = 30; 403 404 /* 405 * 965GM sometimes incorrectly writes to hardware status page (HWS) 406 * using 32bit addressing, overwriting memory if HWS is located 407 * above 4GB. 408 * 409 * The documentation also mentions an issue with undefined 410 * behaviour if any general state is accessed within a page above 4GB, 411 * which also needs to be handled carefully. 412 */ 413 if (IS_I965G(i915) || IS_I965GM(i915)) 414 mask_size = 32; 415 416 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 417 if (ret) 418 goto mask_err; 419 420 return 0; 421 422 mask_err: 423 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret); 424 return ret; 425 } 426 427 /* Wa_14022698537:dg2 */ 428 static void i915_enable_g8(struct drm_i915_private *i915) 429 { 430 if (IS_DG2(i915)) { 431 if (IS_DG2_D(i915) && !intel_match_g8_cpu()) 432 return; 433 434 snb_pcode_write_p(&i915->uncore, PCODE_POWER_SETUP, 435 POWER_SETUP_SUBCOMMAND_G8_ENABLE, 0, 0); 436 } 437 } 438 439 static int i915_pcode_init(struct drm_i915_private *i915) 440 { 441 struct intel_gt *gt; 442 int id, ret; 443 444 for_each_gt(gt, i915, id) { 445 ret = intel_pcode_init(gt->uncore); 446 if (ret) { 447 gt_err(gt, "intel_pcode_init failed %d\n", ret); 448 return ret; 449 } 450 } 451 452 i915_enable_g8(i915); 453 return 0; 454 } 455 456 /** 457 * i915_driver_hw_probe - setup state requiring device access 458 * @dev_priv: device private 459 * 460 * Setup state that requires accessing the device, but doesn't require 461 * exposing the driver via kernel internal or userspace interfaces. 462 */ 463 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) 464 { 465 struct intel_display *display = dev_priv->display; 466 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 467 int ret; 468 469 if (HAS_PPGTT(dev_priv)) { 470 if (intel_vgpu_active(dev_priv) && 471 !intel_vgpu_has_full_ppgtt(dev_priv)) { 472 drm_err(&dev_priv->drm, 473 "incompatible vGPU found, support for isolated ppGTT required\n"); 474 return -ENXIO; 475 } 476 } 477 478 if (HAS_EXECLISTS(dev_priv)) { 479 /* 480 * Older GVT emulation depends upon intercepting CSB mmio, 481 * which we no longer use, preferring to use the HWSP cache 482 * instead. 483 */ 484 if (intel_vgpu_active(dev_priv) && 485 !intel_vgpu_has_hwsp_emulation(dev_priv)) { 486 drm_err(&dev_priv->drm, 487 "old vGPU host found, support for HWSP emulation required\n"); 488 return -ENXIO; 489 } 490 } 491 492 /* needs to be done before ggtt probe */ 493 i915_edram_detect(dev_priv); 494 495 ret = i915_set_dma_info(dev_priv); 496 if (ret) 497 return ret; 498 499 ret = i915_perf_init(dev_priv); 500 if (ret) 501 return ret; 502 503 ret = i915_ggtt_probe_hw(dev_priv); 504 if (ret) 505 goto err_perf; 506 507 ret = aperture_remove_conflicting_pci_devices(pdev, dev_priv->drm.driver->name); 508 if (ret) 509 goto err_ggtt; 510 511 ret = i915_ggtt_init_hw(dev_priv); 512 if (ret) 513 goto err_ggtt; 514 515 /* 516 * Make sure we probe lmem before we probe stolen-lmem. The BAR size 517 * might be different due to bar resizing. 518 */ 519 ret = intel_gt_tiles_init(dev_priv); 520 if (ret) 521 goto err_ggtt; 522 523 ret = intel_memory_regions_hw_probe(dev_priv); 524 if (ret) 525 goto err_ggtt; 526 527 ret = i915_ggtt_enable_hw(dev_priv); 528 if (ret) { 529 drm_err(&dev_priv->drm, "failed to enable GGTT\n"); 530 goto err_mem_regions; 531 } 532 533 pci_set_master(pdev); 534 535 /* On the 945G/GM, the chipset reports the MSI capability on the 536 * integrated graphics even though the support isn't actually there 537 * according to the published specs. It doesn't appear to function 538 * correctly in testing on 945G. 539 * This may be a side effect of MSI having been made available for PEG 540 * and the registers being closely associated. 541 * 542 * According to chipset errata, on the 965GM, MSI interrupts may 543 * be lost or delayed, and was defeatured. MSI interrupts seem to 544 * get lost on g4x as well, and interrupt delivery seems to stay 545 * properly dead afterwards. So we'll just disable them for all 546 * pre-gen5 chipsets. 547 * 548 * dp aux and gmbus irq on gen4 seems to be able to generate legacy 549 * interrupts even when in MSI mode. This results in spurious 550 * interrupt warnings if the legacy irq no. is shared with another 551 * device. The kernel then disables that interrupt source and so 552 * prevents the other device from working properly. 553 */ 554 if (GRAPHICS_VER(dev_priv) >= 5) { 555 if (pci_enable_msi(pdev) < 0) 556 drm_dbg(&dev_priv->drm, "can't enable MSI"); 557 } 558 559 ret = intel_gvt_init(dev_priv); 560 if (ret) 561 goto err_msi; 562 563 intel_opregion_setup(display); 564 565 ret = i915_pcode_init(dev_priv); 566 if (ret) 567 goto err_opregion; 568 569 /* 570 * Fill the dram structure to get the system dram info. This will be 571 * used for memory latency calculation. 572 */ 573 ret = intel_dram_detect(display); 574 if (ret) 575 goto err_opregion; 576 577 intel_bw_init_hw(display); 578 579 return 0; 580 581 err_opregion: 582 intel_opregion_cleanup(display); 583 err_msi: 584 if (pdev->msi_enabled) 585 pci_disable_msi(pdev); 586 err_mem_regions: 587 intel_memory_regions_driver_release(dev_priv); 588 err_ggtt: 589 i915_ggtt_driver_release(dev_priv); 590 i915_gem_drain_freed_objects(dev_priv); 591 i915_ggtt_driver_late_release(dev_priv); 592 err_perf: 593 i915_perf_fini(dev_priv); 594 return ret; 595 } 596 ALLOW_ERROR_INJECTION(i915_driver_hw_probe, ERRNO); 597 598 /** 599 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe() 600 * @dev_priv: device private 601 */ 602 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv) 603 { 604 struct intel_display *display = dev_priv->display; 605 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 606 607 i915_perf_fini(dev_priv); 608 609 intel_opregion_cleanup(display); 610 611 if (pdev->msi_enabled) 612 pci_disable_msi(pdev); 613 } 614 615 /** 616 * i915_driver_register - register the driver with the rest of the system 617 * @dev_priv: device private 618 * 619 * Perform any steps necessary to make the driver available via kernel 620 * internal or userspace interfaces. 621 */ 622 static int i915_driver_register(struct drm_i915_private *dev_priv) 623 { 624 struct intel_display *display = dev_priv->display; 625 struct intel_gt *gt; 626 unsigned int i; 627 int ret; 628 629 i915_gem_driver_register(dev_priv); 630 i915_pmu_register(dev_priv); 631 632 intel_vgpu_register(dev_priv); 633 634 /* Reveal our presence to userspace */ 635 ret = drm_dev_register(&dev_priv->drm, 0); 636 if (ret) { 637 i915_probe_error(dev_priv, 638 "Failed to register driver for userspace access!\n"); 639 drm_dev_unregister(&dev_priv->drm); 640 i915_pmu_unregister(dev_priv); 641 i915_gem_driver_unregister(dev_priv); 642 return ret; 643 } 644 645 i915_debugfs_register(dev_priv); 646 i915_setup_sysfs(dev_priv); 647 648 /* Depends on sysfs having been initialized */ 649 i915_perf_register(dev_priv); 650 651 for_each_gt(gt, dev_priv, i) 652 intel_gt_driver_register(gt); 653 654 intel_pxp_debugfs_register(dev_priv->pxp); 655 656 i915_hwmon_register(dev_priv); 657 658 intel_display_driver_register(display); 659 660 intel_power_domains_enable(display); 661 intel_runtime_pm_enable(&dev_priv->runtime_pm); 662 663 if (i915_switcheroo_register(dev_priv)) 664 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n"); 665 666 return 0; 667 } 668 669 /** 670 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() 671 * @dev_priv: device private 672 */ 673 static void i915_driver_unregister(struct drm_i915_private *dev_priv) 674 { 675 struct intel_display *display = dev_priv->display; 676 struct intel_gt *gt; 677 unsigned int i; 678 679 i915_switcheroo_unregister(dev_priv); 680 681 intel_runtime_pm_disable(&dev_priv->runtime_pm); 682 intel_power_domains_disable(display); 683 684 intel_display_driver_unregister(display); 685 686 intel_pxp_fini(dev_priv); 687 688 for_each_gt(gt, dev_priv, i) 689 intel_gt_driver_unregister(gt); 690 691 i915_hwmon_unregister(dev_priv); 692 693 i915_perf_unregister(dev_priv); 694 i915_pmu_unregister(dev_priv); 695 696 i915_teardown_sysfs(dev_priv); 697 drm_dev_unplug(&dev_priv->drm); 698 699 i915_gem_driver_unregister(dev_priv); 700 } 701 702 void 703 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p) 704 { 705 drm_printf(p, "iommu: %s\n", 706 str_enabled_disabled(i915_vtd_active(i915))); 707 } 708 709 static void i915_welcome_messages(struct drm_i915_private *dev_priv) 710 { 711 if (drm_debug_enabled(DRM_UT_DRIVER)) { 712 struct drm_printer p = drm_dbg_printer(&dev_priv->drm, DRM_UT_DRIVER, 713 "device info:"); 714 struct intel_gt *gt; 715 unsigned int i; 716 717 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n", 718 INTEL_DEVID(dev_priv), 719 INTEL_REVID(dev_priv), 720 intel_platform_name(INTEL_INFO(dev_priv)->platform), 721 intel_subplatform(RUNTIME_INFO(dev_priv), 722 INTEL_INFO(dev_priv)->platform), 723 GRAPHICS_VER(dev_priv)); 724 725 intel_device_info_print(INTEL_INFO(dev_priv), 726 RUNTIME_INFO(dev_priv), &p); 727 i915_print_iommu_status(dev_priv, &p); 728 for_each_gt(gt, dev_priv, i) 729 intel_gt_info_print(>->info, &p); 730 } 731 732 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) 733 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n"); 734 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 735 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n"); 736 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) 737 drm_info(&dev_priv->drm, 738 "DRM_I915_DEBUG_RUNTIME_PM enabled\n"); 739 } 740 741 static void fence_priority_display(struct dma_fence *fence) 742 { 743 if (dma_fence_is_i915(fence)) 744 i915_gem_fence_wait_priority_display(fence); 745 } 746 747 static bool has_auxccs(struct drm_device *drm) 748 { 749 struct drm_i915_private *i915 = to_i915(drm); 750 751 return IS_GRAPHICS_VER(i915, 9, 12) || 752 IS_ALDERLAKE_P(i915) || 753 IS_METEORLAKE(i915); 754 } 755 756 static bool has_fenced_regions(struct drm_device *drm) 757 { 758 return intel_gt_support_legacy_fencing(to_gt(to_i915(drm))); 759 } 760 761 static bool vgpu_active(struct drm_device *drm) 762 { 763 return intel_vgpu_active(to_i915(drm)); 764 } 765 766 static const struct intel_display_parent_interface parent = { 767 .hdcp = &i915_display_hdcp_interface, 768 .initial_plane = &i915_display_initial_plane_interface, 769 .irq = &i915_display_irq_interface, 770 .panic = &i915_display_panic_interface, 771 .pc8 = &i915_display_pc8_interface, 772 .rpm = &i915_display_rpm_interface, 773 .rps = &i915_display_rps_interface, 774 .stolen = &i915_display_stolen_interface, 775 776 .fence_priority_display = fence_priority_display, 777 .has_auxccs = has_auxccs, 778 .has_fenced_regions = has_fenced_regions, 779 .vgpu_active = vgpu_active, 780 }; 781 782 const struct intel_display_parent_interface *i915_driver_parent_interface(void) 783 { 784 return &parent; 785 } 786 787 /* Ensure drm and display members are placed properly. */ 788 INTEL_DISPLAY_MEMBER_STATIC_ASSERT(struct drm_i915_private, drm, display); 789 790 static struct drm_i915_private * 791 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) 792 { 793 const struct intel_device_info *match_info = 794 (struct intel_device_info *)ent->driver_data; 795 struct drm_i915_private *i915; 796 struct intel_display *display; 797 798 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver, 799 struct drm_i915_private, drm); 800 if (IS_ERR(i915)) 801 return i915; 802 803 pci_set_drvdata(pdev, &i915->drm); 804 805 /* Device parameters start as a copy of module parameters. */ 806 i915_params_copy(&i915->params, &i915_modparams); 807 808 /* Set up device info and initial runtime info. */ 809 intel_device_info_driver_create(i915, pdev->device, match_info); 810 811 display = intel_display_device_probe(pdev, &parent); 812 if (IS_ERR(display)) 813 return ERR_CAST(display); 814 815 i915->display = display; 816 817 return i915; 818 } 819 820 /** 821 * i915_driver_probe - setup chip and create an initial config 822 * @pdev: PCI device 823 * @ent: matching PCI ID entry 824 * 825 * The driver probe routine has to do several things: 826 * - drive output discovery via intel_display_driver_probe() 827 * - initialize the memory manager 828 * - allocate initial config memory 829 * - setup the DRM framebuffer with the allocated memory 830 */ 831 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 832 { 833 struct drm_i915_private *i915; 834 struct intel_display *display; 835 int ret; 836 837 ret = pci_enable_device(pdev); 838 if (ret) { 839 pr_err("Failed to enable graphics device: %pe\n", ERR_PTR(ret)); 840 return ret; 841 } 842 843 i915 = i915_driver_create(pdev, ent); 844 if (IS_ERR(i915)) { 845 pci_disable_device(pdev); 846 return PTR_ERR(i915); 847 } 848 849 display = i915->display; 850 851 ret = i915_driver_early_probe(i915); 852 if (ret < 0) 853 goto out_pci_disable; 854 855 disable_rpm_wakeref_asserts(&i915->runtime_pm); 856 857 intel_vgpu_detect(i915); 858 859 ret = intel_gt_probe_all(i915); 860 if (ret < 0) 861 goto out_runtime_pm_put; 862 863 ret = i915_driver_mmio_probe(i915); 864 if (ret < 0) 865 goto out_runtime_pm_put; 866 867 ret = i915_driver_hw_probe(i915); 868 if (ret < 0) 869 goto out_cleanup_mmio; 870 871 ret = intel_display_driver_probe_noirq(display); 872 if (ret < 0) 873 goto out_cleanup_hw; 874 875 ret = intel_irq_install(i915); 876 if (ret) 877 goto out_cleanup_modeset; 878 879 ret = intel_display_driver_probe_nogem(display); 880 if (ret) 881 goto out_cleanup_irq; 882 883 ret = i915_gem_init(i915); 884 if (ret) 885 goto out_cleanup_modeset2; 886 887 ret = intel_pxp_init(i915); 888 if (ret && ret != -ENODEV) 889 drm_dbg(&i915->drm, "pxp init failed with %d\n", ret); 890 891 ret = intel_display_driver_probe(display); 892 if (ret) 893 goto out_cleanup_gem; 894 895 ret = i915_driver_register(i915); 896 if (ret) 897 goto out_cleanup_gem; 898 899 enable_rpm_wakeref_asserts(&i915->runtime_pm); 900 901 i915_welcome_messages(i915); 902 903 i915->do_release = true; 904 905 return 0; 906 907 out_cleanup_gem: 908 intel_pxp_fini(i915); 909 i915_gem_suspend(i915); 910 i915_gem_driver_remove(i915); 911 i915_gem_driver_release(i915); 912 out_cleanup_modeset2: 913 /* FIXME clean up the error path */ 914 intel_display_driver_remove(display); 915 intel_irq_uninstall(i915); 916 intel_display_driver_remove_noirq(display); 917 goto out_cleanup_modeset; 918 out_cleanup_irq: 919 intel_irq_uninstall(i915); 920 out_cleanup_modeset: 921 intel_display_driver_remove_nogem(display); 922 out_cleanup_hw: 923 i915_driver_hw_remove(i915); 924 intel_memory_regions_driver_release(i915); 925 i915_ggtt_driver_release(i915); 926 i915_gem_drain_freed_objects(i915); 927 i915_ggtt_driver_late_release(i915); 928 out_cleanup_mmio: 929 intel_gvt_driver_remove(i915); 930 i915_driver_mmio_release(i915); 931 out_runtime_pm_put: 932 enable_rpm_wakeref_asserts(&i915->runtime_pm); 933 i915_driver_late_release(i915); 934 out_pci_disable: 935 pci_disable_device(pdev); 936 i915_probe_error(i915, "Device initialization failed (%d)\n", ret); 937 return ret; 938 } 939 940 void i915_driver_remove(struct drm_i915_private *i915) 941 { 942 struct intel_display *display = i915->display; 943 intel_wakeref_t wakeref; 944 945 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 946 947 i915_driver_unregister(i915); 948 949 /* Flush any external code that still may be under the RCU lock */ 950 synchronize_rcu(); 951 952 i915_gem_suspend(i915); 953 954 intel_gvt_driver_remove(i915); 955 956 intel_display_driver_remove(display); 957 958 intel_irq_uninstall(i915); 959 960 intel_display_driver_remove_noirq(display); 961 962 i915_reset_error_state(i915); 963 i915_gem_driver_remove(i915); 964 965 intel_display_driver_remove_nogem(display); 966 967 i915_driver_hw_remove(i915); 968 969 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 970 } 971 972 static void i915_driver_release(struct drm_device *dev) 973 { 974 struct drm_i915_private *dev_priv = to_i915(dev); 975 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 976 intel_wakeref_t wakeref; 977 978 if (!dev_priv->do_release) 979 return; 980 981 wakeref = intel_runtime_pm_get(rpm); 982 983 i915_gem_driver_release(dev_priv); 984 985 intel_memory_regions_driver_release(dev_priv); 986 i915_ggtt_driver_release(dev_priv); 987 i915_gem_drain_freed_objects(dev_priv); 988 i915_ggtt_driver_late_release(dev_priv); 989 990 i915_driver_mmio_release(dev_priv); 991 992 intel_runtime_pm_put(rpm, wakeref); 993 994 intel_runtime_pm_driver_release(rpm); 995 996 i915_driver_late_release(dev_priv); 997 } 998 999 static int i915_driver_open(struct drm_device *dev, struct drm_file *file) 1000 { 1001 struct drm_i915_private *i915 = to_i915(dev); 1002 int ret; 1003 1004 ret = i915_gem_open(i915, file); 1005 if (ret) 1006 return ret; 1007 1008 return 0; 1009 } 1010 1011 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) 1012 { 1013 struct drm_i915_file_private *file_priv = file->driver_priv; 1014 1015 i915_gem_context_close(file); 1016 i915_drm_client_put(file_priv->client); 1017 1018 kfree_rcu(file_priv, rcu); 1019 1020 /* Catch up with all the deferred frees from "this" client */ 1021 i915_gem_flush_free_objects(to_i915(dev)); 1022 } 1023 1024 void i915_driver_shutdown(struct drm_i915_private *i915) 1025 { 1026 struct intel_display *display = i915->display; 1027 1028 disable_rpm_wakeref_asserts(&i915->runtime_pm); 1029 intel_runtime_pm_disable(&i915->runtime_pm); 1030 intel_power_domains_disable(display); 1031 1032 drm_client_dev_suspend(&i915->drm); 1033 if (intel_display_device_present(display)) { 1034 drm_kms_helper_poll_disable(&i915->drm); 1035 intel_display_driver_disable_user_access(display); 1036 1037 drm_atomic_helper_shutdown(&i915->drm); 1038 } 1039 1040 intel_dp_mst_suspend(display); 1041 1042 intel_irq_suspend(i915); 1043 intel_hpd_cancel_work(display); 1044 1045 if (intel_display_device_present(display)) 1046 intel_display_driver_suspend_access(display); 1047 1048 intel_encoder_suspend_all(display); 1049 intel_encoder_shutdown_all(display); 1050 1051 intel_dmc_suspend(display); 1052 1053 i915_gem_suspend(i915); 1054 1055 /* 1056 * The only requirement is to reboot with display DC states disabled, 1057 * for now leaving all display power wells in the INIT power domain 1058 * enabled. 1059 * 1060 * TODO: 1061 * - unify the pci_driver::shutdown sequence here with the 1062 * pci_driver.driver.pm.poweroff,poweroff_late sequence. 1063 * - unify the driver remove and system/runtime suspend sequences with 1064 * the above unified shutdown/poweroff sequence. 1065 */ 1066 intel_power_domains_driver_remove(display); 1067 enable_rpm_wakeref_asserts(&i915->runtime_pm); 1068 1069 intel_runtime_pm_driver_last_release(&i915->runtime_pm); 1070 } 1071 1072 static bool suspend_to_idle(struct drm_i915_private *dev_priv) 1073 { 1074 #if IS_ENABLED(CONFIG_ACPI_SLEEP) 1075 if (acpi_target_system_state() < ACPI_STATE_S3) 1076 return true; 1077 #endif 1078 return false; 1079 } 1080 1081 static void i915_drm_complete(struct drm_device *dev) 1082 { 1083 struct drm_i915_private *i915 = to_i915(dev); 1084 1085 intel_pxp_resume_complete(i915->pxp); 1086 } 1087 1088 static int i915_drm_prepare(struct drm_device *dev) 1089 { 1090 struct drm_i915_private *i915 = to_i915(dev); 1091 1092 intel_pxp_suspend_prepare(i915->pxp); 1093 1094 /* 1095 * NB intel_display_driver_suspend() may issue new requests after we've 1096 * ostensibly marked the GPU as ready-to-sleep here. We need to 1097 * split out that work and pull it forward so that after point, 1098 * the GPU is not woken again. 1099 */ 1100 return i915_gem_backup_suspend(i915); 1101 } 1102 1103 static int i915_drm_suspend(struct drm_device *dev) 1104 { 1105 struct drm_i915_private *dev_priv = to_i915(dev); 1106 struct intel_display *display = dev_priv->display; 1107 pci_power_t opregion_target_state; 1108 1109 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1110 1111 /* We do a lot of poking in a lot of registers, make sure they work 1112 * properly. */ 1113 intel_power_domains_disable(display); 1114 drm_client_dev_suspend(dev); 1115 if (intel_display_device_present(display)) { 1116 drm_kms_helper_poll_disable(dev); 1117 intel_display_driver_disable_user_access(display); 1118 } 1119 1120 intel_display_driver_suspend(display); 1121 1122 intel_irq_suspend(dev_priv); 1123 intel_hpd_cancel_work(display); 1124 1125 if (intel_display_device_present(display)) 1126 intel_display_driver_suspend_access(display); 1127 1128 intel_encoder_suspend_all(display); 1129 1130 /* Must be called before GGTT is suspended. */ 1131 intel_dpt_suspend(display); 1132 i915_ggtt_suspend(to_gt(dev_priv)->ggtt); 1133 1134 i9xx_display_sr_save(display); 1135 1136 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; 1137 intel_opregion_suspend(display, opregion_target_state); 1138 1139 dev_priv->suspend_count++; 1140 1141 intel_dmc_suspend(display); 1142 1143 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1144 1145 i915_gem_drain_freed_objects(dev_priv); 1146 1147 return 0; 1148 } 1149 1150 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) 1151 { 1152 struct drm_i915_private *dev_priv = to_i915(dev); 1153 struct intel_display *display = dev_priv->display; 1154 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1155 struct intel_gt *gt; 1156 int ret, i; 1157 bool s2idle = !hibernation && suspend_to_idle(dev_priv); 1158 1159 disable_rpm_wakeref_asserts(rpm); 1160 1161 intel_pxp_suspend(dev_priv->pxp); 1162 1163 i915_gem_suspend_late(dev_priv); 1164 1165 for_each_gt(gt, dev_priv, i) 1166 intel_uncore_suspend(gt->uncore); 1167 1168 intel_display_power_suspend_late(display, s2idle); 1169 1170 ret = vlv_suspend_complete(dev_priv); 1171 if (ret) { 1172 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret); 1173 intel_display_power_resume_early(display); 1174 } 1175 1176 enable_rpm_wakeref_asserts(rpm); 1177 1178 if (!dev_priv->uncore.user_forcewake_count) 1179 intel_runtime_pm_driver_release(rpm); 1180 1181 return ret; 1182 } 1183 1184 static int i915_drm_suspend_noirq(struct drm_device *dev, bool hibernation) 1185 { 1186 struct drm_i915_private *dev_priv = to_i915(dev); 1187 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1188 1189 /* 1190 * During hibernation on some platforms the BIOS may try to access 1191 * the device even though it's already in D3 and hang the machine. So 1192 * leave the device in D0 on those platforms and hope the BIOS will 1193 * power down the device properly. The issue was seen on multiple old 1194 * GENs with different BIOS vendors, so having an explicit blacklist 1195 * is impractical; apply the workaround on everything pre GEN6. The 1196 * platforms where the issue was seen: 1197 * Lenovo Thinkpad X301, X61s, X60, T60, X41 1198 * Fujitsu FSC S7110 1199 * Acer Aspire 1830T 1200 * 1201 * pci_save_state() prevents drivers/pci from 1202 * automagically putting the device into D3. 1203 */ 1204 if (hibernation && GRAPHICS_VER(dev_priv) < 6) 1205 pci_save_state(pdev); 1206 1207 return 0; 1208 } 1209 1210 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915, 1211 pm_message_t state) 1212 { 1213 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 1214 int error; 1215 1216 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND && 1217 state.event != PM_EVENT_FREEZE)) 1218 return -EINVAL; 1219 1220 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1221 return 0; 1222 1223 error = i915_drm_suspend(&i915->drm); 1224 if (error) 1225 return error; 1226 1227 error = i915_drm_suspend_late(&i915->drm, false); 1228 if (error) 1229 return error; 1230 1231 pci_save_state(pdev); 1232 pci_set_power_state(pdev, PCI_D3hot); 1233 1234 return 0; 1235 } 1236 1237 static int i915_drm_resume(struct drm_device *dev) 1238 { 1239 struct drm_i915_private *dev_priv = to_i915(dev); 1240 struct intel_display *display = dev_priv->display; 1241 struct intel_gt *gt; 1242 int ret, i; 1243 1244 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1245 1246 ret = i915_pcode_init(dev_priv); 1247 if (ret) 1248 return ret; 1249 1250 sanitize_gpu(dev_priv); 1251 1252 ret = i915_ggtt_enable_hw(dev_priv); 1253 if (ret) 1254 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n"); 1255 1256 i915_ggtt_resume(to_gt(dev_priv)->ggtt); 1257 1258 for_each_gt(gt, dev_priv, i) 1259 if (GRAPHICS_VER(gt->i915) >= 8) 1260 setup_private_pat(gt); 1261 1262 /* Must be called after GGTT is resumed. */ 1263 intel_dpt_resume(display); 1264 1265 intel_dmc_resume(display); 1266 1267 i9xx_display_sr_restore(display); 1268 1269 intel_gmbus_reset(display); 1270 1271 intel_pps_unlock_regs_wa(display); 1272 1273 intel_init_pch_refclk(display); 1274 1275 /* 1276 * Interrupts have to be enabled before any batches are run. If not the 1277 * GPU will hang. i915_gem_init_hw() will initiate batches to 1278 * update/restore the context. 1279 * 1280 * drm_mode_config_reset() needs AUX interrupts. 1281 * 1282 * Modeset enabling in intel_display_driver_init_hw() also needs working 1283 * interrupts. 1284 */ 1285 intel_irq_resume(dev_priv); 1286 1287 if (intel_display_device_present(display)) 1288 drm_mode_config_reset(dev); 1289 1290 i915_gem_resume(dev_priv); 1291 1292 intel_display_driver_init_hw(display); 1293 1294 intel_clock_gating_init(&dev_priv->drm); 1295 1296 if (intel_display_device_present(display)) 1297 intel_display_driver_resume_access(display); 1298 1299 intel_hpd_init(display); 1300 1301 intel_display_driver_resume(display); 1302 1303 if (intel_display_device_present(display)) { 1304 intel_display_driver_enable_user_access(display); 1305 drm_kms_helper_poll_enable(dev); 1306 } 1307 intel_hpd_poll_disable(display); 1308 1309 intel_opregion_resume(display); 1310 1311 drm_client_dev_resume(dev); 1312 1313 intel_power_domains_enable(display); 1314 1315 intel_gvt_resume(dev_priv); 1316 1317 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1318 1319 return 0; 1320 } 1321 1322 static int i915_drm_resume_early(struct drm_device *dev) 1323 { 1324 struct drm_i915_private *dev_priv = to_i915(dev); 1325 struct intel_display *display = dev_priv->display; 1326 struct intel_gt *gt; 1327 int ret, i; 1328 1329 /* 1330 * We have a resume ordering issue with the snd-hda driver also 1331 * requiring our device to be power up. Due to the lack of a 1332 * parent/child relationship we currently solve this with an early 1333 * resume hook. 1334 * 1335 * FIXME: This should be solved with a special hdmi sink device or 1336 * similar so that power domains can be employed. 1337 */ 1338 1339 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1340 1341 ret = vlv_resume_prepare(dev_priv, false); 1342 if (ret) 1343 drm_err(&dev_priv->drm, 1344 "Resume prepare failed: %d, continuing anyway\n", ret); 1345 1346 for_each_gt(gt, dev_priv, i) 1347 intel_gt_resume_early(gt); 1348 1349 intel_display_power_resume_early(display); 1350 1351 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1352 1353 return ret; 1354 } 1355 1356 int i915_driver_resume_switcheroo(struct drm_i915_private *i915) 1357 { 1358 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 1359 int ret; 1360 1361 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1362 return 0; 1363 1364 ret = pci_set_power_state(pdev, PCI_D0); 1365 if (ret) 1366 return ret; 1367 1368 pci_restore_state(pdev); 1369 1370 ret = i915_drm_resume_early(&i915->drm); 1371 if (ret) 1372 return ret; 1373 1374 return i915_drm_resume(&i915->drm); 1375 } 1376 1377 static int i915_pm_prepare(struct device *kdev) 1378 { 1379 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1380 1381 if (!i915) { 1382 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1383 return -ENODEV; 1384 } 1385 1386 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1387 return 0; 1388 1389 return i915_drm_prepare(&i915->drm); 1390 } 1391 1392 static int i915_pm_suspend(struct device *kdev) 1393 { 1394 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1395 1396 if (!i915) { 1397 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1398 return -ENODEV; 1399 } 1400 1401 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1402 return 0; 1403 1404 return i915_drm_suspend(&i915->drm); 1405 } 1406 1407 static int i915_pm_suspend_late(struct device *kdev) 1408 { 1409 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1410 1411 /* 1412 * We have a suspend ordering issue with the snd-hda driver also 1413 * requiring our device to be power up. Due to the lack of a 1414 * parent/child relationship we currently solve this with an late 1415 * suspend hook. 1416 * 1417 * FIXME: This should be solved with a special hdmi sink device or 1418 * similar so that power domains can be employed. 1419 */ 1420 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1421 return 0; 1422 1423 return i915_drm_suspend_late(&i915->drm, false); 1424 } 1425 1426 static int i915_pm_suspend_noirq(struct device *kdev) 1427 { 1428 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1429 1430 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1431 return 0; 1432 1433 return i915_drm_suspend_noirq(&i915->drm, false); 1434 } 1435 1436 static int i915_pm_poweroff_late(struct device *kdev) 1437 { 1438 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1439 1440 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1441 return 0; 1442 1443 return i915_drm_suspend_late(&i915->drm, true); 1444 } 1445 1446 static int i915_pm_poweroff_noirq(struct device *kdev) 1447 { 1448 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1449 1450 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1451 return 0; 1452 1453 return i915_drm_suspend_noirq(&i915->drm, true); 1454 } 1455 1456 static int i915_pm_resume_early(struct device *kdev) 1457 { 1458 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1459 1460 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1461 return 0; 1462 1463 return i915_drm_resume_early(&i915->drm); 1464 } 1465 1466 static int i915_pm_resume(struct device *kdev) 1467 { 1468 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1469 1470 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1471 return 0; 1472 1473 return i915_drm_resume(&i915->drm); 1474 } 1475 1476 static void i915_pm_complete(struct device *kdev) 1477 { 1478 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1479 1480 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1481 return; 1482 1483 i915_drm_complete(&i915->drm); 1484 } 1485 1486 /* freeze: before creating the hibernation_image */ 1487 static int i915_pm_freeze(struct device *kdev) 1488 { 1489 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1490 int ret; 1491 1492 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1493 ret = i915_drm_suspend(&i915->drm); 1494 if (ret) 1495 return ret; 1496 } 1497 1498 ret = i915_gem_freeze(i915); 1499 if (ret) 1500 return ret; 1501 1502 return 0; 1503 } 1504 1505 static int i915_pm_freeze_late(struct device *kdev) 1506 { 1507 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1508 int ret; 1509 1510 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1511 ret = i915_drm_suspend_late(&i915->drm, true); 1512 if (ret) 1513 return ret; 1514 } 1515 1516 ret = i915_gem_freeze_late(i915); 1517 if (ret) 1518 return ret; 1519 1520 return 0; 1521 } 1522 1523 /* thaw: called after creating the hibernation image, but before turning off. */ 1524 static int i915_pm_thaw_early(struct device *kdev) 1525 { 1526 return i915_pm_resume_early(kdev); 1527 } 1528 1529 static int i915_pm_thaw(struct device *kdev) 1530 { 1531 return i915_pm_resume(kdev); 1532 } 1533 1534 /* restore: called after loading the hibernation image. */ 1535 static int i915_pm_restore_early(struct device *kdev) 1536 { 1537 return i915_pm_resume_early(kdev); 1538 } 1539 1540 static int i915_pm_restore(struct device *kdev) 1541 { 1542 return i915_pm_resume(kdev); 1543 } 1544 1545 static int intel_runtime_suspend(struct device *kdev) 1546 { 1547 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1548 struct intel_display *display = dev_priv->display; 1549 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1550 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1551 struct pci_dev *root_pdev; 1552 struct intel_gt *gt; 1553 int ret, i; 1554 1555 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1556 return -ENODEV; 1557 1558 drm_dbg(&dev_priv->drm, "Suspending device\n"); 1559 1560 disable_rpm_wakeref_asserts(rpm); 1561 1562 /* 1563 * We are safe here against re-faults, since the fault handler takes 1564 * an RPM reference. 1565 */ 1566 i915_gem_runtime_suspend(dev_priv); 1567 1568 intel_pxp_runtime_suspend(dev_priv->pxp); 1569 1570 for_each_gt(gt, dev_priv, i) 1571 intel_gt_runtime_suspend(gt); 1572 1573 intel_irq_suspend(dev_priv); 1574 1575 for_each_gt(gt, dev_priv, i) 1576 intel_uncore_suspend(gt->uncore); 1577 1578 intel_display_power_suspend(display); 1579 1580 ret = vlv_suspend_complete(dev_priv); 1581 if (ret) { 1582 drm_err(&dev_priv->drm, 1583 "Runtime suspend failed, disabling it (%d)\n", ret); 1584 intel_uncore_runtime_resume(&dev_priv->uncore); 1585 1586 intel_irq_resume(dev_priv); 1587 1588 for_each_gt(gt, dev_priv, i) 1589 intel_gt_runtime_resume(gt); 1590 1591 enable_rpm_wakeref_asserts(rpm); 1592 1593 return ret; 1594 } 1595 1596 enable_rpm_wakeref_asserts(rpm); 1597 intel_runtime_pm_driver_release(rpm); 1598 1599 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore)) 1600 drm_err(&dev_priv->drm, 1601 "Unclaimed access detected prior to suspending\n"); 1602 1603 /* 1604 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX 1605 * This should be totally removed when we handle the pci states properly 1606 * on runtime PM. 1607 */ 1608 root_pdev = pcie_find_root_port(pdev); 1609 if (root_pdev) 1610 pci_d3cold_disable(root_pdev); 1611 1612 /* 1613 * FIXME: We really should find a document that references the arguments 1614 * used below! 1615 */ 1616 if (IS_BROADWELL(dev_priv)) { 1617 /* 1618 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop 1619 * being detected, and the call we do at intel_runtime_resume() 1620 * won't be able to restore them. Since PCI_D3hot matches the 1621 * actual specification and appears to be working, use it. 1622 */ 1623 intel_opregion_notify_adapter(display, PCI_D3hot); 1624 } else { 1625 /* 1626 * current versions of firmware which depend on this opregion 1627 * notification have repurposed the D1 definition to mean 1628 * "runtime suspended" vs. what you would normally expect (D3) 1629 * to distinguish it from notifications that might be sent via 1630 * the suspend path. 1631 */ 1632 intel_opregion_notify_adapter(display, PCI_D1); 1633 } 1634 1635 assert_forcewakes_inactive(&dev_priv->uncore); 1636 1637 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) 1638 intel_hpd_poll_enable(display); 1639 1640 drm_dbg(&dev_priv->drm, "Device suspended\n"); 1641 return 0; 1642 } 1643 1644 static int intel_runtime_resume(struct device *kdev) 1645 { 1646 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1647 struct intel_display *display = dev_priv->display; 1648 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1649 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1650 struct pci_dev *root_pdev; 1651 struct intel_gt *gt; 1652 int ret, i; 1653 1654 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1655 return -ENODEV; 1656 1657 drm_dbg(&dev_priv->drm, "Resuming device\n"); 1658 1659 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count)); 1660 disable_rpm_wakeref_asserts(rpm); 1661 1662 intel_opregion_notify_adapter(display, PCI_D0); 1663 1664 root_pdev = pcie_find_root_port(pdev); 1665 if (root_pdev) 1666 pci_d3cold_enable(root_pdev); 1667 1668 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore)) 1669 drm_dbg(&dev_priv->drm, 1670 "Unclaimed access during suspend, bios?\n"); 1671 1672 intel_display_power_resume(display); 1673 1674 ret = vlv_resume_prepare(dev_priv, true); 1675 1676 for_each_gt(gt, dev_priv, i) 1677 intel_uncore_runtime_resume(gt->uncore); 1678 1679 intel_irq_resume(dev_priv); 1680 1681 /* 1682 * No point of rolling back things in case of an error, as the best 1683 * we can do is to hope that things will still work (and disable RPM). 1684 */ 1685 for_each_gt(gt, dev_priv, i) 1686 intel_gt_runtime_resume(gt); 1687 1688 intel_pxp_runtime_resume(dev_priv->pxp); 1689 1690 /* 1691 * On VLV/CHV display interrupts are part of the display 1692 * power well, so hpd is reinitialized from there. For 1693 * everyone else do it here. 1694 */ 1695 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 1696 intel_hpd_init(display); 1697 intel_hpd_poll_disable(display); 1698 } 1699 1700 skl_watermark_ipc_update(display); 1701 1702 enable_rpm_wakeref_asserts(rpm); 1703 1704 if (ret) 1705 drm_err(&dev_priv->drm, 1706 "Runtime resume failed, disabling it (%d)\n", ret); 1707 else 1708 drm_dbg(&dev_priv->drm, "Device resumed\n"); 1709 1710 return ret; 1711 } 1712 1713 const struct dev_pm_ops i915_pm_ops = { 1714 /* 1715 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, 1716 * PMSG_RESUME] 1717 */ 1718 .prepare = i915_pm_prepare, 1719 .suspend = i915_pm_suspend, 1720 .suspend_late = i915_pm_suspend_late, 1721 .suspend_noirq = i915_pm_suspend_noirq, 1722 .resume_early = i915_pm_resume_early, 1723 .resume = i915_pm_resume, 1724 .complete = i915_pm_complete, 1725 1726 /* 1727 * S4 event handlers 1728 * @freeze* : called (1) before creating the 1729 * hibernation image [PMSG_FREEZE] and 1730 * (2) after rebooting, before restoring 1731 * the image [PMSG_QUIESCE] 1732 * @thaw* : called (1) after creating the hibernation 1733 * image, before writing it [PMSG_THAW] 1734 * and (2) after failing to create or 1735 * restore the image [PMSG_RECOVER] 1736 * @poweroff* : called after writing the hibernation 1737 * image, before rebooting [PMSG_HIBERNATE] 1738 * @restore* : called after rebooting and restoring the 1739 * hibernation image [PMSG_RESTORE] 1740 */ 1741 .freeze = i915_pm_freeze, 1742 .freeze_late = i915_pm_freeze_late, 1743 .thaw_early = i915_pm_thaw_early, 1744 .thaw = i915_pm_thaw, 1745 .poweroff = i915_pm_suspend, 1746 .poweroff_late = i915_pm_poweroff_late, 1747 .poweroff_noirq = i915_pm_poweroff_noirq, 1748 .restore_early = i915_pm_restore_early, 1749 .restore = i915_pm_restore, 1750 1751 /* S0ix (via runtime suspend) event handlers */ 1752 .runtime_suspend = intel_runtime_suspend, 1753 .runtime_resume = intel_runtime_resume, 1754 }; 1755 1756 static const struct file_operations i915_driver_fops = { 1757 .owner = THIS_MODULE, 1758 .open = drm_open, 1759 .release = drm_release_noglobal, 1760 .unlocked_ioctl = drm_ioctl, 1761 .mmap = i915_gem_mmap, 1762 .poll = drm_poll, 1763 .read = drm_read, 1764 .compat_ioctl = i915_ioc32_compat_ioctl, 1765 .llseek = noop_llseek, 1766 #ifdef CONFIG_PROC_FS 1767 .show_fdinfo = drm_show_fdinfo, 1768 #endif 1769 .fop_flags = FOP_UNSIGNED_OFFSET, 1770 }; 1771 1772 static int 1773 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, 1774 struct drm_file *file) 1775 { 1776 return -ENODEV; 1777 } 1778 1779 static const struct drm_ioctl_desc i915_ioctls[] = { 1780 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1781 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), 1782 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), 1783 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), 1784 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), 1785 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), 1786 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW), 1787 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1788 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), 1789 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), 1790 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1791 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), 1792 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1793 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1794 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), 1795 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), 1796 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1797 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1798 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH), 1799 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW), 1800 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1801 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1802 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW), 1803 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), 1804 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), 1805 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW), 1806 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1807 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1808 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), 1809 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW), 1810 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), 1811 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), 1812 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), 1813 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW), 1814 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), 1815 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), 1816 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW), 1817 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW), 1818 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), 1819 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_crtc_get_pipe_from_crtc_id_ioctl, 0), 1820 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), 1821 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER), 1822 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER), 1823 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER), 1824 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER), 1825 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW), 1826 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), 1827 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), 1828 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), 1829 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW), 1830 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), 1831 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), 1832 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), 1833 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), 1834 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW), 1835 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW), 1836 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW), 1837 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW), 1838 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW), 1839 }; 1840 1841 /* 1842 * Interface history: 1843 * 1844 * 1.1: Original. 1845 * 1.2: Add Power Management 1846 * 1.3: Add vblank support 1847 * 1.4: Fix cmdbuffer path, add heap destroy 1848 * 1.5: Add vblank pipe configuration 1849 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 1850 * - Support vertical blank on secondary display pipe 1851 */ 1852 #define DRIVER_MAJOR 1 1853 #define DRIVER_MINOR 6 1854 #define DRIVER_PATCHLEVEL 0 1855 1856 static const struct drm_driver i915_drm_driver = { 1857 /* Don't use MTRRs here; the Xserver or userspace app should 1858 * deal with them for Intel hardware. 1859 */ 1860 .driver_features = 1861 DRIVER_GEM | 1862 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ | 1863 DRIVER_SYNCOBJ_TIMELINE, 1864 .release = i915_driver_release, 1865 .open = i915_driver_open, 1866 .postclose = i915_driver_postclose, 1867 .show_fdinfo = PTR_IF(IS_ENABLED(CONFIG_PROC_FS), i915_drm_client_fdinfo), 1868 1869 .gem_prime_import = i915_gem_prime_import, 1870 1871 .dumb_create = i915_gem_dumb_create, 1872 .dumb_map_offset = i915_gem_dumb_mmap_offset, 1873 1874 INTEL_FBDEV_DRIVER_OPS, 1875 1876 .ioctls = i915_ioctls, 1877 .num_ioctls = ARRAY_SIZE(i915_ioctls), 1878 .fops = &i915_driver_fops, 1879 .name = DRIVER_NAME, 1880 .desc = DRIVER_DESC, 1881 .major = DRIVER_MAJOR, 1882 .minor = DRIVER_MINOR, 1883 .patchlevel = DRIVER_PATCHLEVEL, 1884 }; 1885