1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * 27 */ 28 29 #include <linux/sched/mm.h> 30 #include <linux/sort.h> 31 #include <linux/string_helpers.h> 32 33 #include <linux/debugfs.h> 34 #include <drm/drm_debugfs.h> 35 36 #include "gem/i915_gem_context.h" 37 #include "gt/intel_gt.h" 38 #include "gt/intel_gt_buffer_pool.h" 39 #include "gt/intel_gt_clock_utils.h" 40 #include "gt/intel_gt_debugfs.h" 41 #include "gt/intel_gt_pm.h" 42 #include "gt/intel_gt_pm_debugfs.h" 43 #include "gt/intel_gt_regs.h" 44 #include "gt/intel_gt_requests.h" 45 #include "gt/intel_rc6.h" 46 #include "gt/intel_reset.h" 47 #include "gt/intel_rps.h" 48 #include "gt/intel_sseu_debugfs.h" 49 50 #include "i915_debugfs.h" 51 #include "i915_debugfs_params.h" 52 #include "i915_driver.h" 53 #include "i915_gpu_error.h" 54 #include "i915_irq.h" 55 #include "i915_reg.h" 56 #include "i915_scheduler.h" 57 #include "intel_mchbar_regs.h" 58 59 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) 60 { 61 return to_i915(node->minor->dev); 62 } 63 64 static int i915_capabilities(struct seq_file *m, void *data) 65 { 66 struct drm_i915_private *i915 = node_to_i915(m->private); 67 struct drm_printer p = drm_seq_file_printer(m); 68 69 intel_device_info_print(INTEL_INFO(i915), RUNTIME_INFO(i915), &p); 70 i915_print_iommu_status(i915, &p); 71 intel_gt_info_print(&to_gt(i915)->info, &p); 72 intel_driver_caps_print(&i915->caps, &p); 73 74 i915_params_dump(&i915->params, &p); 75 76 return 0; 77 } 78 79 static char get_tiling_flag(struct drm_i915_gem_object *obj) 80 { 81 switch (i915_gem_object_get_tiling(obj)) { 82 default: 83 case I915_TILING_NONE: return ' '; 84 case I915_TILING_X: return 'X'; 85 case I915_TILING_Y: return 'Y'; 86 } 87 } 88 89 static char get_global_flag(struct drm_i915_gem_object *obj) 90 { 91 return READ_ONCE(obj->userfault_count) ? 'g' : ' '; 92 } 93 94 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) 95 { 96 return obj->mm.mapping ? 'M' : ' '; 97 } 98 99 static const char * 100 stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len) 101 { 102 size_t x = 0; 103 104 switch (page_sizes) { 105 case 0: 106 return ""; 107 case I915_GTT_PAGE_SIZE_4K: 108 return "4K"; 109 case I915_GTT_PAGE_SIZE_64K: 110 return "64K"; 111 case I915_GTT_PAGE_SIZE_2M: 112 return "2M"; 113 default: 114 if (!buf) 115 return "M"; 116 117 if (page_sizes & I915_GTT_PAGE_SIZE_2M) 118 x += snprintf(buf + x, len - x, "2M, "); 119 if (page_sizes & I915_GTT_PAGE_SIZE_64K) 120 x += snprintf(buf + x, len - x, "64K, "); 121 if (page_sizes & I915_GTT_PAGE_SIZE_4K) 122 x += snprintf(buf + x, len - x, "4K, "); 123 buf[x-2] = '\0'; 124 125 return buf; 126 } 127 } 128 129 static const char *stringify_vma_type(const struct i915_vma *vma) 130 { 131 if (i915_vma_is_ggtt(vma)) 132 return "ggtt"; 133 134 if (i915_vma_is_dpt(vma)) 135 return "dpt"; 136 137 return "ppgtt"; 138 } 139 140 static const char *i915_cache_level_str(struct drm_i915_gem_object *obj) 141 { 142 struct drm_i915_private *i915 = obj_to_i915(obj); 143 144 if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 74))) { 145 switch (obj->pat_index) { 146 case 0: return " WB"; 147 case 1: return " WT"; 148 case 2: return " UC"; 149 case 3: return " WB (1-Way Coh)"; 150 case 4: return " WB (2-Way Coh)"; 151 default: return " not defined"; 152 } 153 } else if (GRAPHICS_VER(i915) >= 12) { 154 switch (obj->pat_index) { 155 case 0: return " WB"; 156 case 1: return " WC"; 157 case 2: return " WT"; 158 case 3: return " UC"; 159 default: return " not defined"; 160 } 161 } else { 162 switch (obj->pat_index) { 163 case 0: return " UC"; 164 case 1: return HAS_LLC(i915) ? 165 " LLC" : " snooped"; 166 case 2: return " L3+LLC"; 167 case 3: return " WT"; 168 default: return " not defined"; 169 } 170 } 171 } 172 173 void 174 i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) 175 { 176 struct i915_vma *vma; 177 int pin_count = 0; 178 179 seq_printf(m, "%pK: %c%c%c %8zdKiB %02x %02x %s%s%s", 180 &obj->base, 181 get_tiling_flag(obj), 182 get_global_flag(obj), 183 get_pin_mapped_flag(obj), 184 obj->base.size / 1024, 185 obj->read_domains, 186 obj->write_domain, 187 i915_cache_level_str(obj), 188 obj->mm.dirty ? " dirty" : "", 189 obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : ""); 190 if (obj->base.name) 191 seq_printf(m, " (name: %d)", obj->base.name); 192 193 spin_lock(&obj->vma.lock); 194 list_for_each_entry(vma, &obj->vma.list, obj_link) { 195 if (!drm_mm_node_allocated(&vma->node)) 196 continue; 197 198 spin_unlock(&obj->vma.lock); 199 200 if (i915_vma_is_pinned(vma)) 201 pin_count++; 202 203 seq_printf(m, " (%s offset: %08llx, size: %08llx, pages: %s", 204 stringify_vma_type(vma), 205 i915_vma_offset(vma), i915_vma_size(vma), 206 stringify_page_sizes(vma->resource->page_sizes_gtt, 207 NULL, 0)); 208 if (i915_vma_is_ggtt(vma) || i915_vma_is_dpt(vma)) { 209 switch (vma->gtt_view.type) { 210 case I915_GTT_VIEW_NORMAL: 211 seq_puts(m, ", normal"); 212 break; 213 214 case I915_GTT_VIEW_PARTIAL: 215 seq_printf(m, ", partial [%08llx+%x]", 216 vma->gtt_view.partial.offset << PAGE_SHIFT, 217 vma->gtt_view.partial.size << PAGE_SHIFT); 218 break; 219 220 case I915_GTT_VIEW_ROTATED: 221 seq_printf(m, ", rotated [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]", 222 vma->gtt_view.rotated.plane[0].width, 223 vma->gtt_view.rotated.plane[0].height, 224 vma->gtt_view.rotated.plane[0].src_stride, 225 vma->gtt_view.rotated.plane[0].dst_stride, 226 vma->gtt_view.rotated.plane[0].offset, 227 vma->gtt_view.rotated.plane[1].width, 228 vma->gtt_view.rotated.plane[1].height, 229 vma->gtt_view.rotated.plane[1].src_stride, 230 vma->gtt_view.rotated.plane[1].dst_stride, 231 vma->gtt_view.rotated.plane[1].offset); 232 break; 233 234 case I915_GTT_VIEW_REMAPPED: 235 seq_printf(m, ", remapped [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]", 236 vma->gtt_view.remapped.plane[0].width, 237 vma->gtt_view.remapped.plane[0].height, 238 vma->gtt_view.remapped.plane[0].src_stride, 239 vma->gtt_view.remapped.plane[0].dst_stride, 240 vma->gtt_view.remapped.plane[0].offset, 241 vma->gtt_view.remapped.plane[1].width, 242 vma->gtt_view.remapped.plane[1].height, 243 vma->gtt_view.remapped.plane[1].src_stride, 244 vma->gtt_view.remapped.plane[1].dst_stride, 245 vma->gtt_view.remapped.plane[1].offset); 246 break; 247 248 default: 249 MISSING_CASE(vma->gtt_view.type); 250 break; 251 } 252 } 253 if (vma->fence) 254 seq_printf(m, " , fence: %d", vma->fence->id); 255 seq_puts(m, ")"); 256 257 spin_lock(&obj->vma.lock); 258 } 259 spin_unlock(&obj->vma.lock); 260 261 seq_printf(m, " (pinned x %d)", pin_count); 262 if (i915_gem_object_is_stolen(obj)) 263 seq_printf(m, " (stolen: %08llx)", obj->stolen->start); 264 if (i915_gem_object_is_framebuffer(obj)) 265 seq_printf(m, " (fb)"); 266 } 267 268 static int i915_gem_object_info(struct seq_file *m, void *data) 269 { 270 struct drm_i915_private *i915 = node_to_i915(m->private); 271 struct drm_printer p = drm_seq_file_printer(m); 272 struct intel_memory_region *mr; 273 enum intel_region_id id; 274 275 seq_printf(m, "%u shrinkable [%u free] objects, %llu bytes\n", 276 i915->mm.shrink_count, 277 atomic_read(&i915->mm.free_count), 278 i915->mm.shrink_memory); 279 for_each_memory_region(mr, i915, id) 280 intel_memory_region_debug(mr, &p); 281 282 return 0; 283 } 284 285 static int i915_frequency_info(struct seq_file *m, void *unused) 286 { 287 struct drm_i915_private *i915 = node_to_i915(m->private); 288 struct intel_gt *gt = to_gt(i915); 289 struct drm_printer p = drm_seq_file_printer(m); 290 291 intel_gt_pm_frequency_dump(gt, &p); 292 293 return 0; 294 } 295 296 static const char *swizzle_string(unsigned swizzle) 297 { 298 switch (swizzle) { 299 case I915_BIT_6_SWIZZLE_NONE: 300 return "none"; 301 case I915_BIT_6_SWIZZLE_9: 302 return "bit9"; 303 case I915_BIT_6_SWIZZLE_9_10: 304 return "bit9/bit10"; 305 case I915_BIT_6_SWIZZLE_9_11: 306 return "bit9/bit11"; 307 case I915_BIT_6_SWIZZLE_9_10_11: 308 return "bit9/bit10/bit11"; 309 case I915_BIT_6_SWIZZLE_9_17: 310 return "bit9/bit17"; 311 case I915_BIT_6_SWIZZLE_9_10_17: 312 return "bit9/bit10/bit17"; 313 case I915_BIT_6_SWIZZLE_UNKNOWN: 314 return "unknown"; 315 } 316 317 return "bug"; 318 } 319 320 static int i915_swizzle_info(struct seq_file *m, void *data) 321 { 322 struct drm_i915_private *dev_priv = node_to_i915(m->private); 323 struct intel_uncore *uncore = &dev_priv->uncore; 324 intel_wakeref_t wakeref; 325 326 seq_printf(m, "bit6 swizzle for X-tiling = %s\n", 327 swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_x)); 328 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", 329 swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_y)); 330 331 if (dev_priv->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES) 332 seq_puts(m, "L-shaped memory detected\n"); 333 334 /* On BDW+, swizzling is not used. See detect_bit_6_swizzle() */ 335 if (GRAPHICS_VER(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) 336 return 0; 337 338 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 339 340 if (IS_GRAPHICS_VER(dev_priv, 3, 4)) { 341 seq_printf(m, "DDC = 0x%08x\n", 342 intel_uncore_read(uncore, DCC)); 343 seq_printf(m, "DDC2 = 0x%08x\n", 344 intel_uncore_read(uncore, DCC2)); 345 seq_printf(m, "C0DRB3 = 0x%04x\n", 346 intel_uncore_read16(uncore, C0DRB3_BW)); 347 seq_printf(m, "C1DRB3 = 0x%04x\n", 348 intel_uncore_read16(uncore, C1DRB3_BW)); 349 } else if (GRAPHICS_VER(dev_priv) >= 6) { 350 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", 351 intel_uncore_read(uncore, MAD_DIMM_C0)); 352 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", 353 intel_uncore_read(uncore, MAD_DIMM_C1)); 354 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", 355 intel_uncore_read(uncore, MAD_DIMM_C2)); 356 seq_printf(m, "TILECTL = 0x%08x\n", 357 intel_uncore_read(uncore, TILECTL)); 358 if (GRAPHICS_VER(dev_priv) >= 8) 359 seq_printf(m, "GAMTARBMODE = 0x%08x\n", 360 intel_uncore_read(uncore, GAMTARBMODE)); 361 else 362 seq_printf(m, "ARB_MODE = 0x%08x\n", 363 intel_uncore_read(uncore, ARB_MODE)); 364 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", 365 intel_uncore_read(uncore, DISP_ARB_CTL)); 366 } 367 368 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 369 370 return 0; 371 } 372 373 static int i915_rps_boost_info(struct seq_file *m, void *data) 374 { 375 struct drm_i915_private *dev_priv = node_to_i915(m->private); 376 struct intel_rps *rps = &to_gt(dev_priv)->rps; 377 378 seq_printf(m, "RPS enabled? %s\n", 379 str_yes_no(intel_rps_is_enabled(rps))); 380 seq_printf(m, "RPS active? %s\n", 381 str_yes_no(intel_rps_is_active(rps))); 382 seq_printf(m, "GPU busy? %s\n", str_yes_no(to_gt(dev_priv)->awake)); 383 seq_printf(m, "Boosts outstanding? %d\n", 384 atomic_read(&rps->num_waiters)); 385 seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive)); 386 seq_printf(m, "Frequency requested %d, actual %d\n", 387 intel_gpu_freq(rps, rps->cur_freq), 388 intel_rps_read_actual_frequency(rps)); 389 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", 390 intel_gpu_freq(rps, rps->min_freq), 391 intel_gpu_freq(rps, rps->min_freq_softlimit), 392 intel_gpu_freq(rps, rps->max_freq_softlimit), 393 intel_gpu_freq(rps, rps->max_freq)); 394 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", 395 intel_gpu_freq(rps, rps->idle_freq), 396 intel_gpu_freq(rps, rps->efficient_freq), 397 intel_gpu_freq(rps, rps->boost_freq)); 398 399 seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts)); 400 401 return 0; 402 } 403 404 static int i915_runtime_pm_status(struct seq_file *m, void *unused) 405 { 406 struct drm_i915_private *dev_priv = node_to_i915(m->private); 407 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 408 409 if (!HAS_RUNTIME_PM(dev_priv)) 410 seq_puts(m, "Runtime power management not supported\n"); 411 412 seq_printf(m, "GPU idle: %s\n", str_yes_no(!to_gt(dev_priv)->awake)); 413 seq_printf(m, "IRQs disabled: %s\n", 414 str_yes_no(!intel_irqs_enabled(dev_priv))); 415 #ifdef CONFIG_PM 416 seq_printf(m, "Usage count: %d\n", 417 atomic_read(&dev_priv->drm.dev->power.usage_count)); 418 #else 419 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); 420 #endif 421 seq_printf(m, "PCI device power state: %s [%d]\n", 422 pci_power_name(pdev->current_state), 423 pdev->current_state); 424 425 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) { 426 struct drm_printer p = drm_seq_file_printer(m); 427 428 print_intel_runtime_pm_wakeref(&dev_priv->runtime_pm, &p); 429 } 430 431 return 0; 432 } 433 434 static int i915_engine_info(struct seq_file *m, void *unused) 435 { 436 struct drm_i915_private *i915 = node_to_i915(m->private); 437 struct intel_engine_cs *engine; 438 intel_wakeref_t wakeref; 439 struct drm_printer p; 440 441 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 442 443 seq_printf(m, "GT awake? %s [%d], %llums\n", 444 str_yes_no(to_gt(i915)->awake), 445 atomic_read(&to_gt(i915)->wakeref.count), 446 ktime_to_ms(intel_gt_get_awake_time(to_gt(i915)))); 447 seq_printf(m, "CS timestamp frequency: %u Hz, %d ns\n", 448 to_gt(i915)->clock_frequency, 449 to_gt(i915)->clock_period_ns); 450 451 p = drm_seq_file_printer(m); 452 for_each_uabi_engine(engine, i915) 453 intel_engine_dump(engine, &p, "%s\n", engine->name); 454 455 intel_gt_show_timelines(to_gt(i915), &p, i915_request_show_with_schedule); 456 457 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 458 459 return 0; 460 } 461 462 static int i915_wa_registers(struct seq_file *m, void *unused) 463 { 464 struct drm_i915_private *i915 = node_to_i915(m->private); 465 struct intel_engine_cs *engine; 466 467 for_each_uabi_engine(engine, i915) { 468 const struct i915_wa_list *wal = &engine->ctx_wa_list; 469 const struct i915_wa *wa; 470 unsigned int count; 471 472 count = wal->count; 473 if (!count) 474 continue; 475 476 seq_printf(m, "%s: Workarounds applied: %u\n", 477 engine->name, count); 478 479 for (wa = wal->list; count--; wa++) 480 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n", 481 i915_mmio_reg_offset(wa->reg), 482 wa->set, wa->clr); 483 484 seq_printf(m, "\n"); 485 } 486 487 return 0; 488 } 489 490 static int i915_wedged_get(void *data, u64 *val) 491 { 492 struct drm_i915_private *i915 = data; 493 struct intel_gt *gt; 494 unsigned int i; 495 496 *val = 0; 497 498 for_each_gt(gt, i915, i) { 499 int ret; 500 501 ret = intel_gt_debugfs_reset_show(gt, val); 502 if (ret) 503 return ret; 504 505 /* at least one tile should be wedged */ 506 if (*val) 507 break; 508 } 509 510 return 0; 511 } 512 513 static int i915_wedged_set(void *data, u64 val) 514 { 515 struct drm_i915_private *i915 = data; 516 struct intel_gt *gt; 517 unsigned int i; 518 519 for_each_gt(gt, i915, i) 520 intel_gt_debugfs_reset_store(gt, val); 521 522 return 0; 523 } 524 525 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, 526 i915_wedged_get, i915_wedged_set, 527 "%llu\n"); 528 529 static int 530 i915_perf_noa_delay_set(void *data, u64 val) 531 { 532 struct drm_i915_private *i915 = data; 533 534 /* 535 * This would lead to infinite waits as we're doing timestamp 536 * difference on the CS with only 32bits. 537 */ 538 if (intel_gt_ns_to_clock_interval(to_gt(i915), val) > U32_MAX) 539 return -EINVAL; 540 541 atomic64_set(&i915->perf.noa_programming_delay, val); 542 return 0; 543 } 544 545 static int 546 i915_perf_noa_delay_get(void *data, u64 *val) 547 { 548 struct drm_i915_private *i915 = data; 549 550 *val = atomic64_read(&i915->perf.noa_programming_delay); 551 return 0; 552 } 553 554 DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops, 555 i915_perf_noa_delay_get, 556 i915_perf_noa_delay_set, 557 "%llu\n"); 558 559 #define DROP_UNBOUND BIT(0) 560 #define DROP_BOUND BIT(1) 561 #define DROP_RETIRE BIT(2) 562 #define DROP_ACTIVE BIT(3) 563 #define DROP_FREED BIT(4) 564 #define DROP_SHRINK_ALL BIT(5) 565 #define DROP_IDLE BIT(6) 566 #define DROP_RESET_ACTIVE BIT(7) 567 #define DROP_RESET_SEQNO BIT(8) 568 #define DROP_RCU BIT(9) 569 #define DROP_ALL (DROP_UNBOUND | \ 570 DROP_BOUND | \ 571 DROP_RETIRE | \ 572 DROP_ACTIVE | \ 573 DROP_FREED | \ 574 DROP_SHRINK_ALL |\ 575 DROP_IDLE | \ 576 DROP_RESET_ACTIVE | \ 577 DROP_RESET_SEQNO | \ 578 DROP_RCU) 579 static int 580 i915_drop_caches_get(void *data, u64 *val) 581 { 582 *val = DROP_ALL; 583 584 return 0; 585 } 586 587 static int 588 gt_drop_caches(struct intel_gt *gt, u64 val) 589 { 590 int ret; 591 592 if (val & DROP_RESET_ACTIVE && 593 wait_for(intel_engines_are_idle(gt), 200)) 594 intel_gt_set_wedged(gt); 595 596 if (val & DROP_RETIRE) 597 intel_gt_retire_requests(gt); 598 599 if (val & (DROP_IDLE | DROP_ACTIVE)) { 600 ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT); 601 if (ret) 602 return ret; 603 } 604 605 if (val & DROP_IDLE) { 606 ret = intel_gt_pm_wait_for_idle(gt); 607 if (ret) 608 return ret; 609 } 610 611 if (val & DROP_RESET_ACTIVE && intel_gt_terminally_wedged(gt)) 612 intel_gt_handle_error(gt, ALL_ENGINES, 0, NULL); 613 614 if (val & DROP_FREED) 615 intel_gt_flush_buffer_pool(gt); 616 617 return 0; 618 } 619 620 static int 621 i915_drop_caches_set(void *data, u64 val) 622 { 623 struct drm_i915_private *i915 = data; 624 struct intel_gt *gt; 625 unsigned int flags; 626 unsigned int i; 627 int ret; 628 629 drm_dbg(&i915->drm, "Dropping caches: 0x%08llx [0x%08llx]\n", 630 val, val & DROP_ALL); 631 632 for_each_gt(gt, i915, i) { 633 ret = gt_drop_caches(gt, val); 634 if (ret) 635 return ret; 636 } 637 638 fs_reclaim_acquire(GFP_KERNEL); 639 flags = memalloc_noreclaim_save(); 640 if (val & DROP_BOUND) 641 i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_BOUND); 642 643 if (val & DROP_UNBOUND) 644 i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_UNBOUND); 645 646 if (val & DROP_SHRINK_ALL) 647 i915_gem_shrink_all(i915); 648 memalloc_noreclaim_restore(flags); 649 fs_reclaim_release(GFP_KERNEL); 650 651 if (val & DROP_RCU) 652 rcu_barrier(); 653 654 if (val & DROP_FREED) 655 i915_gem_drain_freed_objects(i915); 656 657 return 0; 658 } 659 660 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, 661 i915_drop_caches_get, i915_drop_caches_set, 662 "0x%08llx\n"); 663 664 static int i915_sseu_status(struct seq_file *m, void *unused) 665 { 666 struct drm_i915_private *i915 = node_to_i915(m->private); 667 struct intel_gt *gt = to_gt(i915); 668 669 return intel_sseu_status(m, gt); 670 } 671 672 static int i915_forcewake_open(struct inode *inode, struct file *file) 673 { 674 struct drm_i915_private *i915 = inode->i_private; 675 struct intel_gt *gt; 676 unsigned int i; 677 678 for_each_gt(gt, i915, i) 679 intel_gt_pm_debugfs_forcewake_user_open(gt); 680 681 return 0; 682 } 683 684 static int i915_forcewake_release(struct inode *inode, struct file *file) 685 { 686 struct drm_i915_private *i915 = inode->i_private; 687 struct intel_gt *gt; 688 unsigned int i; 689 690 for_each_gt(gt, i915, i) 691 intel_gt_pm_debugfs_forcewake_user_release(gt); 692 693 return 0; 694 } 695 696 static const struct file_operations i915_forcewake_fops = { 697 .owner = THIS_MODULE, 698 .open = i915_forcewake_open, 699 .release = i915_forcewake_release, 700 }; 701 702 static const struct drm_info_list i915_debugfs_list[] = { 703 {"i915_capabilities", i915_capabilities, 0}, 704 {"i915_gem_objects", i915_gem_object_info, 0}, 705 {"i915_frequency_info", i915_frequency_info, 0}, 706 {"i915_swizzle_info", i915_swizzle_info, 0}, 707 {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, 708 {"i915_engine_info", i915_engine_info, 0}, 709 {"i915_wa_registers", i915_wa_registers, 0}, 710 {"i915_sseu_status", i915_sseu_status, 0}, 711 {"i915_rps_boost_info", i915_rps_boost_info, 0}, 712 }; 713 714 static const struct i915_debugfs_files { 715 const char *name; 716 const struct file_operations *fops; 717 } i915_debugfs_files[] = { 718 {"i915_perf_noa_delay", &i915_perf_noa_delay_fops}, 719 {"i915_wedged", &i915_wedged_fops}, 720 {"i915_gem_drop_caches", &i915_drop_caches_fops}, 721 }; 722 723 void i915_debugfs_register(struct drm_i915_private *dev_priv) 724 { 725 struct drm_minor *minor = dev_priv->drm.primary; 726 int i; 727 728 i915_debugfs_params(dev_priv); 729 730 debugfs_create_file("i915_forcewake_user", S_IRUSR, minor->debugfs_root, 731 to_i915(minor->dev), &i915_forcewake_fops); 732 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { 733 debugfs_create_file(i915_debugfs_files[i].name, 734 S_IRUGO | S_IWUSR, 735 minor->debugfs_root, 736 to_i915(minor->dev), 737 i915_debugfs_files[i].fops); 738 } 739 740 drm_debugfs_create_files(i915_debugfs_list, 741 ARRAY_SIZE(i915_debugfs_list), 742 minor->debugfs_root, minor); 743 744 i915_gpu_error_debugfs_register(dev_priv); 745 } 746