1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * 27 */ 28 29 #include <linux/sched/mm.h> 30 #include <linux/sort.h> 31 #include <linux/string_helpers.h> 32 33 #include <drm/drm_debugfs.h> 34 35 #include "display/intel_display_params.h" 36 37 #include "gem/i915_gem_context.h" 38 #include "gt/intel_gt.h" 39 #include "gt/intel_gt_buffer_pool.h" 40 #include "gt/intel_gt_clock_utils.h" 41 #include "gt/intel_gt_debugfs.h" 42 #include "gt/intel_gt_pm.h" 43 #include "gt/intel_gt_pm_debugfs.h" 44 #include "gt/intel_gt_regs.h" 45 #include "gt/intel_gt_requests.h" 46 #include "gt/intel_rc6.h" 47 #include "gt/intel_reset.h" 48 #include "gt/intel_rps.h" 49 #include "gt/intel_sseu_debugfs.h" 50 51 #include "i915_debugfs.h" 52 #include "i915_debugfs_params.h" 53 #include "i915_driver.h" 54 #include "i915_gpu_error.h" 55 #include "i915_irq.h" 56 #include "i915_reg.h" 57 #include "i915_scheduler.h" 58 #include "intel_mchbar_regs.h" 59 60 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) 61 { 62 return to_i915(node->minor->dev); 63 } 64 65 static int i915_capabilities(struct seq_file *m, void *data) 66 { 67 struct drm_i915_private *i915 = node_to_i915(m->private); 68 struct drm_printer p = drm_seq_file_printer(m); 69 70 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915)); 71 72 intel_device_info_print(INTEL_INFO(i915), RUNTIME_INFO(i915), &p); 73 i915_print_iommu_status(i915, &p); 74 intel_gt_info_print(&to_gt(i915)->info, &p); 75 intel_driver_caps_print(&i915->caps, &p); 76 77 kernel_param_lock(THIS_MODULE); 78 i915_params_dump(&i915->params, &p); 79 intel_display_params_dump(i915, &p); 80 kernel_param_unlock(THIS_MODULE); 81 82 return 0; 83 } 84 85 static char get_tiling_flag(struct drm_i915_gem_object *obj) 86 { 87 switch (i915_gem_object_get_tiling(obj)) { 88 default: 89 case I915_TILING_NONE: return ' '; 90 case I915_TILING_X: return 'X'; 91 case I915_TILING_Y: return 'Y'; 92 } 93 } 94 95 static char get_global_flag(struct drm_i915_gem_object *obj) 96 { 97 return READ_ONCE(obj->userfault_count) ? 'g' : ' '; 98 } 99 100 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) 101 { 102 return obj->mm.mapping ? 'M' : ' '; 103 } 104 105 static const char * 106 stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len) 107 { 108 size_t x = 0; 109 110 switch (page_sizes) { 111 case 0: 112 return ""; 113 case I915_GTT_PAGE_SIZE_4K: 114 return "4K"; 115 case I915_GTT_PAGE_SIZE_64K: 116 return "64K"; 117 case I915_GTT_PAGE_SIZE_2M: 118 return "2M"; 119 default: 120 if (!buf) 121 return "M"; 122 123 if (page_sizes & I915_GTT_PAGE_SIZE_2M) 124 x += snprintf(buf + x, len - x, "2M, "); 125 if (page_sizes & I915_GTT_PAGE_SIZE_64K) 126 x += snprintf(buf + x, len - x, "64K, "); 127 if (page_sizes & I915_GTT_PAGE_SIZE_4K) 128 x += snprintf(buf + x, len - x, "4K, "); 129 buf[x-2] = '\0'; 130 131 return buf; 132 } 133 } 134 135 static const char *stringify_vma_type(const struct i915_vma *vma) 136 { 137 if (i915_vma_is_ggtt(vma)) 138 return "ggtt"; 139 140 if (i915_vma_is_dpt(vma)) 141 return "dpt"; 142 143 return "ppgtt"; 144 } 145 146 static const char *i915_cache_level_str(struct drm_i915_gem_object *obj) 147 { 148 struct drm_i915_private *i915 = obj_to_i915(obj); 149 150 if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 74))) { 151 switch (obj->pat_index) { 152 case 0: return " WB"; 153 case 1: return " WT"; 154 case 2: return " UC"; 155 case 3: return " WB (1-Way Coh)"; 156 case 4: return " WB (2-Way Coh)"; 157 default: return " not defined"; 158 } 159 } else if (GRAPHICS_VER(i915) >= 12) { 160 switch (obj->pat_index) { 161 case 0: return " WB"; 162 case 1: return " WC"; 163 case 2: return " WT"; 164 case 3: return " UC"; 165 default: return " not defined"; 166 } 167 } else { 168 switch (obj->pat_index) { 169 case 0: return " UC"; 170 case 1: return HAS_LLC(i915) ? 171 " LLC" : " snooped"; 172 case 2: return " L3+LLC"; 173 case 3: return " WT"; 174 default: return " not defined"; 175 } 176 } 177 } 178 179 void 180 i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) 181 { 182 struct i915_vma *vma; 183 int pin_count = 0; 184 185 seq_printf(m, "%pK: %c%c%c %8zdKiB %02x %02x %s%s%s", 186 &obj->base, 187 get_tiling_flag(obj), 188 get_global_flag(obj), 189 get_pin_mapped_flag(obj), 190 obj->base.size / 1024, 191 obj->read_domains, 192 obj->write_domain, 193 i915_cache_level_str(obj), 194 obj->mm.dirty ? " dirty" : "", 195 obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : ""); 196 if (obj->base.name) 197 seq_printf(m, " (name: %d)", obj->base.name); 198 199 spin_lock(&obj->vma.lock); 200 list_for_each_entry(vma, &obj->vma.list, obj_link) { 201 if (!drm_mm_node_allocated(&vma->node)) 202 continue; 203 204 spin_unlock(&obj->vma.lock); 205 206 if (i915_vma_is_pinned(vma)) 207 pin_count++; 208 209 seq_printf(m, " (%s offset: %08llx, size: %08llx, pages: %s", 210 stringify_vma_type(vma), 211 i915_vma_offset(vma), i915_vma_size(vma), 212 stringify_page_sizes(vma->resource->page_sizes_gtt, 213 NULL, 0)); 214 if (i915_vma_is_ggtt(vma) || i915_vma_is_dpt(vma)) { 215 switch (vma->gtt_view.type) { 216 case I915_GTT_VIEW_NORMAL: 217 seq_puts(m, ", normal"); 218 break; 219 220 case I915_GTT_VIEW_PARTIAL: 221 seq_printf(m, ", partial [%08llx+%x]", 222 vma->gtt_view.partial.offset << PAGE_SHIFT, 223 vma->gtt_view.partial.size << PAGE_SHIFT); 224 break; 225 226 case I915_GTT_VIEW_ROTATED: 227 seq_printf(m, ", rotated [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]", 228 vma->gtt_view.rotated.plane[0].width, 229 vma->gtt_view.rotated.plane[0].height, 230 vma->gtt_view.rotated.plane[0].src_stride, 231 vma->gtt_view.rotated.plane[0].dst_stride, 232 vma->gtt_view.rotated.plane[0].offset, 233 vma->gtt_view.rotated.plane[1].width, 234 vma->gtt_view.rotated.plane[1].height, 235 vma->gtt_view.rotated.plane[1].src_stride, 236 vma->gtt_view.rotated.plane[1].dst_stride, 237 vma->gtt_view.rotated.plane[1].offset); 238 break; 239 240 case I915_GTT_VIEW_REMAPPED: 241 seq_printf(m, ", remapped [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]", 242 vma->gtt_view.remapped.plane[0].width, 243 vma->gtt_view.remapped.plane[0].height, 244 vma->gtt_view.remapped.plane[0].src_stride, 245 vma->gtt_view.remapped.plane[0].dst_stride, 246 vma->gtt_view.remapped.plane[0].offset, 247 vma->gtt_view.remapped.plane[1].width, 248 vma->gtt_view.remapped.plane[1].height, 249 vma->gtt_view.remapped.plane[1].src_stride, 250 vma->gtt_view.remapped.plane[1].dst_stride, 251 vma->gtt_view.remapped.plane[1].offset); 252 break; 253 254 default: 255 MISSING_CASE(vma->gtt_view.type); 256 break; 257 } 258 } 259 if (vma->fence) 260 seq_printf(m, " , fence: %d", vma->fence->id); 261 seq_puts(m, ")"); 262 263 spin_lock(&obj->vma.lock); 264 } 265 spin_unlock(&obj->vma.lock); 266 267 seq_printf(m, " (pinned x %d)", pin_count); 268 if (i915_gem_object_is_stolen(obj)) 269 seq_printf(m, " (stolen: %08llx)", obj->stolen->start); 270 if (i915_gem_object_is_framebuffer(obj)) 271 seq_printf(m, " (fb)"); 272 } 273 274 static int i915_gem_object_info(struct seq_file *m, void *data) 275 { 276 struct drm_i915_private *i915 = node_to_i915(m->private); 277 struct drm_printer p = drm_seq_file_printer(m); 278 struct intel_memory_region *mr; 279 enum intel_region_id id; 280 281 seq_printf(m, "%u shrinkable [%u free] objects, %llu bytes\n", 282 i915->mm.shrink_count, 283 atomic_read(&i915->mm.free_count), 284 i915->mm.shrink_memory); 285 for_each_memory_region(mr, i915, id) 286 intel_memory_region_debug(mr, &p); 287 288 return 0; 289 } 290 291 static int i915_frequency_info(struct seq_file *m, void *unused) 292 { 293 struct drm_i915_private *i915 = node_to_i915(m->private); 294 struct intel_gt *gt = to_gt(i915); 295 struct drm_printer p = drm_seq_file_printer(m); 296 297 intel_gt_pm_frequency_dump(gt, &p); 298 299 return 0; 300 } 301 302 static const char *swizzle_string(unsigned swizzle) 303 { 304 switch (swizzle) { 305 case I915_BIT_6_SWIZZLE_NONE: 306 return "none"; 307 case I915_BIT_6_SWIZZLE_9: 308 return "bit9"; 309 case I915_BIT_6_SWIZZLE_9_10: 310 return "bit9/bit10"; 311 case I915_BIT_6_SWIZZLE_9_11: 312 return "bit9/bit11"; 313 case I915_BIT_6_SWIZZLE_9_10_11: 314 return "bit9/bit10/bit11"; 315 case I915_BIT_6_SWIZZLE_9_17: 316 return "bit9/bit17"; 317 case I915_BIT_6_SWIZZLE_9_10_17: 318 return "bit9/bit10/bit17"; 319 case I915_BIT_6_SWIZZLE_UNKNOWN: 320 return "unknown"; 321 } 322 323 return "bug"; 324 } 325 326 static int i915_swizzle_info(struct seq_file *m, void *data) 327 { 328 struct drm_i915_private *dev_priv = node_to_i915(m->private); 329 struct intel_uncore *uncore = &dev_priv->uncore; 330 intel_wakeref_t wakeref; 331 332 seq_printf(m, "bit6 swizzle for X-tiling = %s\n", 333 swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_x)); 334 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", 335 swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_y)); 336 337 if (dev_priv->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES) 338 seq_puts(m, "L-shaped memory detected\n"); 339 340 /* On BDW+, swizzling is not used. See detect_bit_6_swizzle() */ 341 if (GRAPHICS_VER(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) 342 return 0; 343 344 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 345 346 if (IS_GRAPHICS_VER(dev_priv, 3, 4)) { 347 seq_printf(m, "DDC = 0x%08x\n", 348 intel_uncore_read(uncore, DCC)); 349 seq_printf(m, "DDC2 = 0x%08x\n", 350 intel_uncore_read(uncore, DCC2)); 351 seq_printf(m, "C0DRB3 = 0x%04x\n", 352 intel_uncore_read16(uncore, C0DRB3_BW)); 353 seq_printf(m, "C1DRB3 = 0x%04x\n", 354 intel_uncore_read16(uncore, C1DRB3_BW)); 355 } else if (GRAPHICS_VER(dev_priv) >= 6) { 356 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", 357 intel_uncore_read(uncore, MAD_DIMM_C0)); 358 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", 359 intel_uncore_read(uncore, MAD_DIMM_C1)); 360 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", 361 intel_uncore_read(uncore, MAD_DIMM_C2)); 362 seq_printf(m, "TILECTL = 0x%08x\n", 363 intel_uncore_read(uncore, TILECTL)); 364 if (GRAPHICS_VER(dev_priv) >= 8) 365 seq_printf(m, "GAMTARBMODE = 0x%08x\n", 366 intel_uncore_read(uncore, GAMTARBMODE)); 367 else 368 seq_printf(m, "ARB_MODE = 0x%08x\n", 369 intel_uncore_read(uncore, ARB_MODE)); 370 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", 371 intel_uncore_read(uncore, DISP_ARB_CTL)); 372 } 373 374 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 375 376 return 0; 377 } 378 379 static int i915_rps_boost_info(struct seq_file *m, void *data) 380 { 381 struct drm_i915_private *dev_priv = node_to_i915(m->private); 382 struct intel_rps *rps = &to_gt(dev_priv)->rps; 383 384 seq_printf(m, "RPS enabled? %s\n", 385 str_yes_no(intel_rps_is_enabled(rps))); 386 seq_printf(m, "RPS active? %s\n", 387 str_yes_no(intel_rps_is_active(rps))); 388 seq_printf(m, "GPU busy? %s\n", str_yes_no(to_gt(dev_priv)->awake)); 389 seq_printf(m, "Boosts outstanding? %d\n", 390 atomic_read(&rps->num_waiters)); 391 seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive)); 392 seq_printf(m, "Frequency requested %d, actual %d\n", 393 intel_gpu_freq(rps, rps->cur_freq), 394 intel_rps_read_actual_frequency(rps)); 395 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", 396 intel_gpu_freq(rps, rps->min_freq), 397 intel_gpu_freq(rps, rps->min_freq_softlimit), 398 intel_gpu_freq(rps, rps->max_freq_softlimit), 399 intel_gpu_freq(rps, rps->max_freq)); 400 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", 401 intel_gpu_freq(rps, rps->idle_freq), 402 intel_gpu_freq(rps, rps->efficient_freq), 403 intel_gpu_freq(rps, rps->boost_freq)); 404 405 seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts)); 406 407 return 0; 408 } 409 410 static int i915_runtime_pm_status(struct seq_file *m, void *unused) 411 { 412 struct drm_i915_private *dev_priv = node_to_i915(m->private); 413 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 414 415 if (!HAS_RUNTIME_PM(dev_priv)) 416 seq_puts(m, "Runtime power management not supported\n"); 417 418 seq_printf(m, "Runtime power status: %s\n", 419 str_enabled_disabled(!dev_priv->display.power.domains.init_wakeref)); 420 421 seq_printf(m, "GPU idle: %s\n", str_yes_no(!to_gt(dev_priv)->awake)); 422 seq_printf(m, "IRQs disabled: %s\n", 423 str_yes_no(!intel_irqs_enabled(dev_priv))); 424 #ifdef CONFIG_PM 425 seq_printf(m, "Usage count: %d\n", 426 atomic_read(&dev_priv->drm.dev->power.usage_count)); 427 #else 428 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); 429 #endif 430 seq_printf(m, "PCI device power state: %s [%d]\n", 431 pci_power_name(pdev->current_state), 432 pdev->current_state); 433 434 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) { 435 struct drm_printer p = drm_seq_file_printer(m); 436 437 print_intel_runtime_pm_wakeref(&dev_priv->runtime_pm, &p); 438 } 439 440 return 0; 441 } 442 443 static int i915_engine_info(struct seq_file *m, void *unused) 444 { 445 struct drm_i915_private *i915 = node_to_i915(m->private); 446 struct intel_engine_cs *engine; 447 intel_wakeref_t wakeref; 448 struct drm_printer p; 449 450 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 451 452 seq_printf(m, "GT awake? %s [%d], %llums\n", 453 str_yes_no(to_gt(i915)->awake), 454 atomic_read(&to_gt(i915)->wakeref.count), 455 ktime_to_ms(intel_gt_get_awake_time(to_gt(i915)))); 456 seq_printf(m, "CS timestamp frequency: %u Hz, %d ns\n", 457 to_gt(i915)->clock_frequency, 458 to_gt(i915)->clock_period_ns); 459 460 p = drm_seq_file_printer(m); 461 for_each_uabi_engine(engine, i915) 462 intel_engine_dump(engine, &p, "%s\n", engine->name); 463 464 intel_gt_show_timelines(to_gt(i915), &p, i915_request_show_with_schedule); 465 466 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 467 468 return 0; 469 } 470 471 static int i915_wa_registers(struct seq_file *m, void *unused) 472 { 473 struct drm_i915_private *i915 = node_to_i915(m->private); 474 struct intel_engine_cs *engine; 475 476 for_each_uabi_engine(engine, i915) { 477 const struct i915_wa_list *wal = &engine->ctx_wa_list; 478 const struct i915_wa *wa; 479 unsigned int count; 480 481 count = wal->count; 482 if (!count) 483 continue; 484 485 seq_printf(m, "%s: Workarounds applied: %u\n", 486 engine->name, count); 487 488 for (wa = wal->list; count--; wa++) 489 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n", 490 i915_mmio_reg_offset(wa->reg), 491 wa->set, wa->clr); 492 493 seq_printf(m, "\n"); 494 } 495 496 return 0; 497 } 498 499 static int i915_wedged_get(void *data, u64 *val) 500 { 501 struct drm_i915_private *i915 = data; 502 struct intel_gt *gt; 503 unsigned int i; 504 505 *val = 0; 506 507 for_each_gt(gt, i915, i) { 508 int ret; 509 510 ret = intel_gt_debugfs_reset_show(gt, val); 511 if (ret) 512 return ret; 513 514 /* at least one tile should be wedged */ 515 if (*val) 516 break; 517 } 518 519 return 0; 520 } 521 522 static int i915_wedged_set(void *data, u64 val) 523 { 524 struct drm_i915_private *i915 = data; 525 struct intel_gt *gt; 526 unsigned int i; 527 528 for_each_gt(gt, i915, i) 529 intel_gt_debugfs_reset_store(gt, val); 530 531 return 0; 532 } 533 534 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, 535 i915_wedged_get, i915_wedged_set, 536 "%llu\n"); 537 538 static int 539 i915_perf_noa_delay_set(void *data, u64 val) 540 { 541 struct drm_i915_private *i915 = data; 542 543 /* 544 * This would lead to infinite waits as we're doing timestamp 545 * difference on the CS with only 32bits. 546 */ 547 if (intel_gt_ns_to_clock_interval(to_gt(i915), val) > U32_MAX) 548 return -EINVAL; 549 550 atomic64_set(&i915->perf.noa_programming_delay, val); 551 return 0; 552 } 553 554 static int 555 i915_perf_noa_delay_get(void *data, u64 *val) 556 { 557 struct drm_i915_private *i915 = data; 558 559 *val = atomic64_read(&i915->perf.noa_programming_delay); 560 return 0; 561 } 562 563 DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops, 564 i915_perf_noa_delay_get, 565 i915_perf_noa_delay_set, 566 "%llu\n"); 567 568 #define DROP_UNBOUND BIT(0) 569 #define DROP_BOUND BIT(1) 570 #define DROP_RETIRE BIT(2) 571 #define DROP_ACTIVE BIT(3) 572 #define DROP_FREED BIT(4) 573 #define DROP_SHRINK_ALL BIT(5) 574 #define DROP_IDLE BIT(6) 575 #define DROP_RESET_ACTIVE BIT(7) 576 #define DROP_RESET_SEQNO BIT(8) 577 #define DROP_RCU BIT(9) 578 #define DROP_ALL (DROP_UNBOUND | \ 579 DROP_BOUND | \ 580 DROP_RETIRE | \ 581 DROP_ACTIVE | \ 582 DROP_FREED | \ 583 DROP_SHRINK_ALL |\ 584 DROP_IDLE | \ 585 DROP_RESET_ACTIVE | \ 586 DROP_RESET_SEQNO | \ 587 DROP_RCU) 588 static int 589 i915_drop_caches_get(void *data, u64 *val) 590 { 591 *val = DROP_ALL; 592 593 return 0; 594 } 595 596 static int 597 gt_drop_caches(struct intel_gt *gt, u64 val) 598 { 599 int ret; 600 601 if (val & DROP_RESET_ACTIVE && 602 wait_for(intel_engines_are_idle(gt), 200)) 603 intel_gt_set_wedged(gt); 604 605 if (val & DROP_RETIRE) 606 intel_gt_retire_requests(gt); 607 608 if (val & (DROP_IDLE | DROP_ACTIVE)) { 609 ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT); 610 if (ret) 611 return ret; 612 } 613 614 if (val & DROP_IDLE) { 615 ret = intel_gt_pm_wait_for_idle(gt); 616 if (ret) 617 return ret; 618 } 619 620 if (val & DROP_RESET_ACTIVE && intel_gt_terminally_wedged(gt)) 621 intel_gt_handle_error(gt, ALL_ENGINES, 0, NULL); 622 623 if (val & DROP_FREED) 624 intel_gt_flush_buffer_pool(gt); 625 626 return 0; 627 } 628 629 static int 630 i915_drop_caches_set(void *data, u64 val) 631 { 632 struct drm_i915_private *i915 = data; 633 struct intel_gt *gt; 634 unsigned int flags; 635 unsigned int i; 636 int ret; 637 638 drm_dbg(&i915->drm, "Dropping caches: 0x%08llx [0x%08llx]\n", 639 val, val & DROP_ALL); 640 641 for_each_gt(gt, i915, i) { 642 ret = gt_drop_caches(gt, val); 643 if (ret) 644 return ret; 645 } 646 647 fs_reclaim_acquire(GFP_KERNEL); 648 flags = memalloc_noreclaim_save(); 649 if (val & DROP_BOUND) 650 i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_BOUND); 651 652 if (val & DROP_UNBOUND) 653 i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_UNBOUND); 654 655 if (val & DROP_SHRINK_ALL) 656 i915_gem_shrink_all(i915); 657 memalloc_noreclaim_restore(flags); 658 fs_reclaim_release(GFP_KERNEL); 659 660 if (val & DROP_RCU) 661 rcu_barrier(); 662 663 if (val & DROP_FREED) 664 i915_gem_drain_freed_objects(i915); 665 666 return 0; 667 } 668 669 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, 670 i915_drop_caches_get, i915_drop_caches_set, 671 "0x%08llx\n"); 672 673 static int i915_sseu_status(struct seq_file *m, void *unused) 674 { 675 struct drm_i915_private *i915 = node_to_i915(m->private); 676 struct intel_gt *gt = to_gt(i915); 677 678 return intel_sseu_status(m, gt); 679 } 680 681 static int i915_forcewake_open(struct inode *inode, struct file *file) 682 { 683 struct drm_i915_private *i915 = inode->i_private; 684 struct intel_gt *gt; 685 unsigned int i; 686 687 for_each_gt(gt, i915, i) 688 intel_gt_pm_debugfs_forcewake_user_open(gt); 689 690 return 0; 691 } 692 693 static int i915_forcewake_release(struct inode *inode, struct file *file) 694 { 695 struct drm_i915_private *i915 = inode->i_private; 696 struct intel_gt *gt; 697 unsigned int i; 698 699 for_each_gt(gt, i915, i) 700 intel_gt_pm_debugfs_forcewake_user_release(gt); 701 702 return 0; 703 } 704 705 static const struct file_operations i915_forcewake_fops = { 706 .owner = THIS_MODULE, 707 .open = i915_forcewake_open, 708 .release = i915_forcewake_release, 709 }; 710 711 static const struct drm_info_list i915_debugfs_list[] = { 712 {"i915_capabilities", i915_capabilities, 0}, 713 {"i915_gem_objects", i915_gem_object_info, 0}, 714 {"i915_frequency_info", i915_frequency_info, 0}, 715 {"i915_swizzle_info", i915_swizzle_info, 0}, 716 {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, 717 {"i915_engine_info", i915_engine_info, 0}, 718 {"i915_wa_registers", i915_wa_registers, 0}, 719 {"i915_sseu_status", i915_sseu_status, 0}, 720 {"i915_rps_boost_info", i915_rps_boost_info, 0}, 721 }; 722 723 static const struct i915_debugfs_files { 724 const char *name; 725 const struct file_operations *fops; 726 } i915_debugfs_files[] = { 727 {"i915_perf_noa_delay", &i915_perf_noa_delay_fops}, 728 {"i915_wedged", &i915_wedged_fops}, 729 {"i915_gem_drop_caches", &i915_drop_caches_fops}, 730 }; 731 732 void i915_debugfs_register(struct drm_i915_private *dev_priv) 733 { 734 struct drm_minor *minor = dev_priv->drm.primary; 735 int i; 736 737 i915_debugfs_params(dev_priv); 738 739 debugfs_create_file("i915_forcewake_user", S_IRUSR, minor->debugfs_root, 740 to_i915(minor->dev), &i915_forcewake_fops); 741 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { 742 debugfs_create_file(i915_debugfs_files[i].name, 743 S_IRUGO | S_IWUSR, 744 minor->debugfs_root, 745 to_i915(minor->dev), 746 i915_debugfs_files[i].fops); 747 } 748 749 drm_debugfs_create_files(i915_debugfs_list, 750 ARRAY_SIZE(i915_debugfs_list), 751 minor->debugfs_root, minor); 752 753 i915_gpu_error_debugfs_register(dev_priv); 754 } 755