1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * 27 */ 28 29 #include <linux/seq_file.h> 30 #include <linux/circ_buf.h> 31 #include <linux/ctype.h> 32 #include <linux/debugfs.h> 33 #include <linux/slab.h> 34 #include <linux/export.h> 35 #include <linux/list_sort.h> 36 #include <asm/msr-index.h> 37 #include <drm/drmP.h> 38 #include "intel_drv.h" 39 #include "intel_ringbuffer.h" 40 #include <drm/i915_drm.h> 41 #include "i915_drv.h" 42 43 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) 44 { 45 return to_i915(node->minor->dev); 46 } 47 48 /* As the drm_debugfs_init() routines are called before dev->dev_private is 49 * allocated we need to hook into the minor for release. */ 50 static int 51 drm_add_fake_info_node(struct drm_minor *minor, 52 struct dentry *ent, 53 const void *key) 54 { 55 struct drm_info_node *node; 56 57 node = kmalloc(sizeof(*node), GFP_KERNEL); 58 if (node == NULL) { 59 debugfs_remove(ent); 60 return -ENOMEM; 61 } 62 63 node->minor = minor; 64 node->dent = ent; 65 node->info_ent = (void *)key; 66 67 mutex_lock(&minor->debugfs_lock); 68 list_add(&node->list, &minor->debugfs_list); 69 mutex_unlock(&minor->debugfs_lock); 70 71 return 0; 72 } 73 74 static int i915_capabilities(struct seq_file *m, void *data) 75 { 76 struct drm_i915_private *dev_priv = node_to_i915(m->private); 77 const struct intel_device_info *info = INTEL_INFO(dev_priv); 78 79 seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv)); 80 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv)); 81 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) 82 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); 83 #undef PRINT_FLAG 84 85 return 0; 86 } 87 88 static char get_active_flag(struct drm_i915_gem_object *obj) 89 { 90 return i915_gem_object_is_active(obj) ? '*' : ' '; 91 } 92 93 static char get_pin_flag(struct drm_i915_gem_object *obj) 94 { 95 return obj->pin_display ? 'p' : ' '; 96 } 97 98 static char get_tiling_flag(struct drm_i915_gem_object *obj) 99 { 100 switch (i915_gem_object_get_tiling(obj)) { 101 default: 102 case I915_TILING_NONE: return ' '; 103 case I915_TILING_X: return 'X'; 104 case I915_TILING_Y: return 'Y'; 105 } 106 } 107 108 static char get_global_flag(struct drm_i915_gem_object *obj) 109 { 110 return obj->fault_mappable ? 'g' : ' '; 111 } 112 113 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) 114 { 115 return obj->mapping ? 'M' : ' '; 116 } 117 118 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) 119 { 120 u64 size = 0; 121 struct i915_vma *vma; 122 123 list_for_each_entry(vma, &obj->vma_list, obj_link) { 124 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node)) 125 size += vma->node.size; 126 } 127 128 return size; 129 } 130 131 static void 132 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) 133 { 134 struct drm_i915_private *dev_priv = to_i915(obj->base.dev); 135 struct intel_engine_cs *engine; 136 struct i915_vma *vma; 137 unsigned int frontbuffer_bits; 138 int pin_count = 0; 139 enum intel_engine_id id; 140 141 lockdep_assert_held(&obj->base.dev->struct_mutex); 142 143 seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ", 144 &obj->base, 145 get_active_flag(obj), 146 get_pin_flag(obj), 147 get_tiling_flag(obj), 148 get_global_flag(obj), 149 get_pin_mapped_flag(obj), 150 obj->base.size / 1024, 151 obj->base.read_domains, 152 obj->base.write_domain); 153 for_each_engine(engine, dev_priv, id) 154 seq_printf(m, "%x ", 155 i915_gem_active_get_seqno(&obj->last_read[id], 156 &obj->base.dev->struct_mutex)); 157 seq_printf(m, "] %x %s%s%s", 158 i915_gem_active_get_seqno(&obj->last_write, 159 &obj->base.dev->struct_mutex), 160 i915_cache_level_str(dev_priv, obj->cache_level), 161 obj->dirty ? " dirty" : "", 162 obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); 163 if (obj->base.name) 164 seq_printf(m, " (name: %d)", obj->base.name); 165 list_for_each_entry(vma, &obj->vma_list, obj_link) { 166 if (i915_vma_is_pinned(vma)) 167 pin_count++; 168 } 169 seq_printf(m, " (pinned x %d)", pin_count); 170 if (obj->pin_display) 171 seq_printf(m, " (display)"); 172 list_for_each_entry(vma, &obj->vma_list, obj_link) { 173 if (!drm_mm_node_allocated(&vma->node)) 174 continue; 175 176 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx", 177 i915_vma_is_ggtt(vma) ? "g" : "pp", 178 vma->node.start, vma->node.size); 179 if (i915_vma_is_ggtt(vma)) 180 seq_printf(m, ", type: %u", vma->ggtt_view.type); 181 if (vma->fence) 182 seq_printf(m, " , fence: %d%s", 183 vma->fence->id, 184 i915_gem_active_isset(&vma->last_fence) ? "*" : ""); 185 seq_puts(m, ")"); 186 } 187 if (obj->stolen) 188 seq_printf(m, " (stolen: %08llx)", obj->stolen->start); 189 190 engine = i915_gem_active_get_engine(&obj->last_write, 191 &dev_priv->drm.struct_mutex); 192 if (engine) 193 seq_printf(m, " (%s)", engine->name); 194 195 frontbuffer_bits = atomic_read(&obj->frontbuffer_bits); 196 if (frontbuffer_bits) 197 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits); 198 } 199 200 static int obj_rank_by_stolen(void *priv, 201 struct list_head *A, struct list_head *B) 202 { 203 struct drm_i915_gem_object *a = 204 container_of(A, struct drm_i915_gem_object, obj_exec_link); 205 struct drm_i915_gem_object *b = 206 container_of(B, struct drm_i915_gem_object, obj_exec_link); 207 208 if (a->stolen->start < b->stolen->start) 209 return -1; 210 if (a->stolen->start > b->stolen->start) 211 return 1; 212 return 0; 213 } 214 215 static int i915_gem_stolen_list_info(struct seq_file *m, void *data) 216 { 217 struct drm_i915_private *dev_priv = node_to_i915(m->private); 218 struct drm_device *dev = &dev_priv->drm; 219 struct drm_i915_gem_object *obj; 220 u64 total_obj_size, total_gtt_size; 221 LIST_HEAD(stolen); 222 int count, ret; 223 224 ret = mutex_lock_interruptible(&dev->struct_mutex); 225 if (ret) 226 return ret; 227 228 total_obj_size = total_gtt_size = count = 0; 229 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 230 if (obj->stolen == NULL) 231 continue; 232 233 list_add(&obj->obj_exec_link, &stolen); 234 235 total_obj_size += obj->base.size; 236 total_gtt_size += i915_gem_obj_total_ggtt_size(obj); 237 count++; 238 } 239 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { 240 if (obj->stolen == NULL) 241 continue; 242 243 list_add(&obj->obj_exec_link, &stolen); 244 245 total_obj_size += obj->base.size; 246 count++; 247 } 248 list_sort(NULL, &stolen, obj_rank_by_stolen); 249 seq_puts(m, "Stolen:\n"); 250 while (!list_empty(&stolen)) { 251 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); 252 seq_puts(m, " "); 253 describe_obj(m, obj); 254 seq_putc(m, '\n'); 255 list_del_init(&obj->obj_exec_link); 256 } 257 mutex_unlock(&dev->struct_mutex); 258 259 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", 260 count, total_obj_size, total_gtt_size); 261 return 0; 262 } 263 264 struct file_stats { 265 struct drm_i915_file_private *file_priv; 266 unsigned long count; 267 u64 total, unbound; 268 u64 global, shared; 269 u64 active, inactive; 270 }; 271 272 static int per_file_stats(int id, void *ptr, void *data) 273 { 274 struct drm_i915_gem_object *obj = ptr; 275 struct file_stats *stats = data; 276 struct i915_vma *vma; 277 278 stats->count++; 279 stats->total += obj->base.size; 280 if (!obj->bind_count) 281 stats->unbound += obj->base.size; 282 if (obj->base.name || obj->base.dma_buf) 283 stats->shared += obj->base.size; 284 285 list_for_each_entry(vma, &obj->vma_list, obj_link) { 286 if (!drm_mm_node_allocated(&vma->node)) 287 continue; 288 289 if (i915_vma_is_ggtt(vma)) { 290 stats->global += vma->node.size; 291 } else { 292 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm); 293 294 if (ppgtt->base.file != stats->file_priv) 295 continue; 296 } 297 298 if (i915_vma_is_active(vma)) 299 stats->active += vma->node.size; 300 else 301 stats->inactive += vma->node.size; 302 } 303 304 return 0; 305 } 306 307 #define print_file_stats(m, name, stats) do { \ 308 if (stats.count) \ 309 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \ 310 name, \ 311 stats.count, \ 312 stats.total, \ 313 stats.active, \ 314 stats.inactive, \ 315 stats.global, \ 316 stats.shared, \ 317 stats.unbound); \ 318 } while (0) 319 320 static void print_batch_pool_stats(struct seq_file *m, 321 struct drm_i915_private *dev_priv) 322 { 323 struct drm_i915_gem_object *obj; 324 struct file_stats stats; 325 struct intel_engine_cs *engine; 326 enum intel_engine_id id; 327 int j; 328 329 memset(&stats, 0, sizeof(stats)); 330 331 for_each_engine(engine, dev_priv, id) { 332 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { 333 list_for_each_entry(obj, 334 &engine->batch_pool.cache_list[j], 335 batch_pool_link) 336 per_file_stats(0, obj, &stats); 337 } 338 } 339 340 print_file_stats(m, "[k]batch pool", stats); 341 } 342 343 static int per_file_ctx_stats(int id, void *ptr, void *data) 344 { 345 struct i915_gem_context *ctx = ptr; 346 int n; 347 348 for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) { 349 if (ctx->engine[n].state) 350 per_file_stats(0, ctx->engine[n].state->obj, data); 351 if (ctx->engine[n].ring) 352 per_file_stats(0, ctx->engine[n].ring->vma->obj, data); 353 } 354 355 return 0; 356 } 357 358 static void print_context_stats(struct seq_file *m, 359 struct drm_i915_private *dev_priv) 360 { 361 struct drm_device *dev = &dev_priv->drm; 362 struct file_stats stats; 363 struct drm_file *file; 364 365 memset(&stats, 0, sizeof(stats)); 366 367 mutex_lock(&dev->struct_mutex); 368 if (dev_priv->kernel_context) 369 per_file_ctx_stats(0, dev_priv->kernel_context, &stats); 370 371 list_for_each_entry(file, &dev->filelist, lhead) { 372 struct drm_i915_file_private *fpriv = file->driver_priv; 373 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats); 374 } 375 mutex_unlock(&dev->struct_mutex); 376 377 print_file_stats(m, "[k]contexts", stats); 378 } 379 380 static int i915_gem_object_info(struct seq_file *m, void *data) 381 { 382 struct drm_i915_private *dev_priv = node_to_i915(m->private); 383 struct drm_device *dev = &dev_priv->drm; 384 struct i915_ggtt *ggtt = &dev_priv->ggtt; 385 u32 count, mapped_count, purgeable_count, dpy_count; 386 u64 size, mapped_size, purgeable_size, dpy_size; 387 struct drm_i915_gem_object *obj; 388 struct drm_file *file; 389 int ret; 390 391 ret = mutex_lock_interruptible(&dev->struct_mutex); 392 if (ret) 393 return ret; 394 395 seq_printf(m, "%u objects, %llu bytes\n", 396 dev_priv->mm.object_count, 397 dev_priv->mm.object_memory); 398 399 size = count = 0; 400 mapped_size = mapped_count = 0; 401 purgeable_size = purgeable_count = 0; 402 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { 403 size += obj->base.size; 404 ++count; 405 406 if (obj->madv == I915_MADV_DONTNEED) { 407 purgeable_size += obj->base.size; 408 ++purgeable_count; 409 } 410 411 if (obj->mapping) { 412 mapped_count++; 413 mapped_size += obj->base.size; 414 } 415 } 416 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); 417 418 size = count = dpy_size = dpy_count = 0; 419 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 420 size += obj->base.size; 421 ++count; 422 423 if (obj->pin_display) { 424 dpy_size += obj->base.size; 425 ++dpy_count; 426 } 427 428 if (obj->madv == I915_MADV_DONTNEED) { 429 purgeable_size += obj->base.size; 430 ++purgeable_count; 431 } 432 433 if (obj->mapping) { 434 mapped_count++; 435 mapped_size += obj->base.size; 436 } 437 } 438 seq_printf(m, "%u bound objects, %llu bytes\n", 439 count, size); 440 seq_printf(m, "%u purgeable objects, %llu bytes\n", 441 purgeable_count, purgeable_size); 442 seq_printf(m, "%u mapped objects, %llu bytes\n", 443 mapped_count, mapped_size); 444 seq_printf(m, "%u display objects (pinned), %llu bytes\n", 445 dpy_count, dpy_size); 446 447 seq_printf(m, "%llu [%llu] gtt total\n", 448 ggtt->base.total, ggtt->mappable_end - ggtt->base.start); 449 450 seq_putc(m, '\n'); 451 print_batch_pool_stats(m, dev_priv); 452 mutex_unlock(&dev->struct_mutex); 453 454 mutex_lock(&dev->filelist_mutex); 455 print_context_stats(m, dev_priv); 456 list_for_each_entry_reverse(file, &dev->filelist, lhead) { 457 struct file_stats stats; 458 struct drm_i915_file_private *file_priv = file->driver_priv; 459 struct drm_i915_gem_request *request; 460 struct task_struct *task; 461 462 memset(&stats, 0, sizeof(stats)); 463 stats.file_priv = file->driver_priv; 464 spin_lock(&file->table_lock); 465 idr_for_each(&file->object_idr, per_file_stats, &stats); 466 spin_unlock(&file->table_lock); 467 /* 468 * Although we have a valid reference on file->pid, that does 469 * not guarantee that the task_struct who called get_pid() is 470 * still alive (e.g. get_pid(current) => fork() => exit()). 471 * Therefore, we need to protect this ->comm access using RCU. 472 */ 473 mutex_lock(&dev->struct_mutex); 474 request = list_first_entry_or_null(&file_priv->mm.request_list, 475 struct drm_i915_gem_request, 476 client_list); 477 rcu_read_lock(); 478 task = pid_task(request && request->ctx->pid ? 479 request->ctx->pid : file->pid, 480 PIDTYPE_PID); 481 print_file_stats(m, task ? task->comm : "<unknown>", stats); 482 rcu_read_unlock(); 483 mutex_unlock(&dev->struct_mutex); 484 } 485 mutex_unlock(&dev->filelist_mutex); 486 487 return 0; 488 } 489 490 static int i915_gem_gtt_info(struct seq_file *m, void *data) 491 { 492 struct drm_info_node *node = m->private; 493 struct drm_i915_private *dev_priv = node_to_i915(node); 494 struct drm_device *dev = &dev_priv->drm; 495 bool show_pin_display_only = !!node->info_ent->data; 496 struct drm_i915_gem_object *obj; 497 u64 total_obj_size, total_gtt_size; 498 int count, ret; 499 500 ret = mutex_lock_interruptible(&dev->struct_mutex); 501 if (ret) 502 return ret; 503 504 total_obj_size = total_gtt_size = count = 0; 505 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 506 if (show_pin_display_only && !obj->pin_display) 507 continue; 508 509 seq_puts(m, " "); 510 describe_obj(m, obj); 511 seq_putc(m, '\n'); 512 total_obj_size += obj->base.size; 513 total_gtt_size += i915_gem_obj_total_ggtt_size(obj); 514 count++; 515 } 516 517 mutex_unlock(&dev->struct_mutex); 518 519 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", 520 count, total_obj_size, total_gtt_size); 521 522 return 0; 523 } 524 525 static int i915_gem_pageflip_info(struct seq_file *m, void *data) 526 { 527 struct drm_i915_private *dev_priv = node_to_i915(m->private); 528 struct drm_device *dev = &dev_priv->drm; 529 struct intel_crtc *crtc; 530 int ret; 531 532 ret = mutex_lock_interruptible(&dev->struct_mutex); 533 if (ret) 534 return ret; 535 536 for_each_intel_crtc(dev, crtc) { 537 const char pipe = pipe_name(crtc->pipe); 538 const char plane = plane_name(crtc->plane); 539 struct intel_flip_work *work; 540 541 spin_lock_irq(&dev->event_lock); 542 work = crtc->flip_work; 543 if (work == NULL) { 544 seq_printf(m, "No flip due on pipe %c (plane %c)\n", 545 pipe, plane); 546 } else { 547 u32 pending; 548 u32 addr; 549 550 pending = atomic_read(&work->pending); 551 if (pending) { 552 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n", 553 pipe, plane); 554 } else { 555 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", 556 pipe, plane); 557 } 558 if (work->flip_queued_req) { 559 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req); 560 561 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n", 562 engine->name, 563 i915_gem_request_get_seqno(work->flip_queued_req), 564 dev_priv->next_seqno, 565 intel_engine_get_seqno(engine), 566 i915_gem_request_completed(work->flip_queued_req)); 567 } else 568 seq_printf(m, "Flip not associated with any ring\n"); 569 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", 570 work->flip_queued_vblank, 571 work->flip_ready_vblank, 572 intel_crtc_get_vblank_counter(crtc)); 573 seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); 574 575 if (INTEL_GEN(dev_priv) >= 4) 576 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); 577 else 578 addr = I915_READ(DSPADDR(crtc->plane)); 579 seq_printf(m, "Current scanout address 0x%08x\n", addr); 580 581 if (work->pending_flip_obj) { 582 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); 583 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); 584 } 585 } 586 spin_unlock_irq(&dev->event_lock); 587 } 588 589 mutex_unlock(&dev->struct_mutex); 590 591 return 0; 592 } 593 594 static int i915_gem_batch_pool_info(struct seq_file *m, void *data) 595 { 596 struct drm_i915_private *dev_priv = node_to_i915(m->private); 597 struct drm_device *dev = &dev_priv->drm; 598 struct drm_i915_gem_object *obj; 599 struct intel_engine_cs *engine; 600 enum intel_engine_id id; 601 int total = 0; 602 int ret, j; 603 604 ret = mutex_lock_interruptible(&dev->struct_mutex); 605 if (ret) 606 return ret; 607 608 for_each_engine(engine, dev_priv, id) { 609 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { 610 int count; 611 612 count = 0; 613 list_for_each_entry(obj, 614 &engine->batch_pool.cache_list[j], 615 batch_pool_link) 616 count++; 617 seq_printf(m, "%s cache[%d]: %d objects\n", 618 engine->name, j, count); 619 620 list_for_each_entry(obj, 621 &engine->batch_pool.cache_list[j], 622 batch_pool_link) { 623 seq_puts(m, " "); 624 describe_obj(m, obj); 625 seq_putc(m, '\n'); 626 } 627 628 total += count; 629 } 630 } 631 632 seq_printf(m, "total: %d\n", total); 633 634 mutex_unlock(&dev->struct_mutex); 635 636 return 0; 637 } 638 639 static void print_request(struct seq_file *m, 640 struct drm_i915_gem_request *rq, 641 const char *prefix) 642 { 643 struct pid *pid = rq->ctx->pid; 644 struct task_struct *task; 645 646 rcu_read_lock(); 647 task = pid ? pid_task(pid, PIDTYPE_PID) : NULL; 648 seq_printf(m, "%s%x [%x:%x] @ %d: %s [%d]\n", prefix, 649 rq->fence.seqno, rq->ctx->hw_id, rq->fence.seqno, 650 jiffies_to_msecs(jiffies - rq->emitted_jiffies), 651 task ? task->comm : "<unknown>", 652 task ? task->pid : -1); 653 rcu_read_unlock(); 654 } 655 656 static int i915_gem_request_info(struct seq_file *m, void *data) 657 { 658 struct drm_i915_private *dev_priv = node_to_i915(m->private); 659 struct drm_device *dev = &dev_priv->drm; 660 struct drm_i915_gem_request *req; 661 struct intel_engine_cs *engine; 662 enum intel_engine_id id; 663 int ret, any; 664 665 ret = mutex_lock_interruptible(&dev->struct_mutex); 666 if (ret) 667 return ret; 668 669 any = 0; 670 for_each_engine(engine, dev_priv, id) { 671 int count; 672 673 count = 0; 674 list_for_each_entry(req, &engine->request_list, link) 675 count++; 676 if (count == 0) 677 continue; 678 679 seq_printf(m, "%s requests: %d\n", engine->name, count); 680 list_for_each_entry(req, &engine->request_list, link) 681 print_request(m, req, " "); 682 683 any++; 684 } 685 mutex_unlock(&dev->struct_mutex); 686 687 if (any == 0) 688 seq_puts(m, "No requests\n"); 689 690 return 0; 691 } 692 693 static void i915_ring_seqno_info(struct seq_file *m, 694 struct intel_engine_cs *engine) 695 { 696 struct intel_breadcrumbs *b = &engine->breadcrumbs; 697 struct rb_node *rb; 698 699 seq_printf(m, "Current sequence (%s): %x\n", 700 engine->name, intel_engine_get_seqno(engine)); 701 702 spin_lock(&b->lock); 703 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { 704 struct intel_wait *w = container_of(rb, typeof(*w), node); 705 706 seq_printf(m, "Waiting (%s): %s [%d] on %x\n", 707 engine->name, w->tsk->comm, w->tsk->pid, w->seqno); 708 } 709 spin_unlock(&b->lock); 710 } 711 712 static int i915_gem_seqno_info(struct seq_file *m, void *data) 713 { 714 struct drm_i915_private *dev_priv = node_to_i915(m->private); 715 struct intel_engine_cs *engine; 716 enum intel_engine_id id; 717 718 for_each_engine(engine, dev_priv, id) 719 i915_ring_seqno_info(m, engine); 720 721 return 0; 722 } 723 724 725 static int i915_interrupt_info(struct seq_file *m, void *data) 726 { 727 struct drm_i915_private *dev_priv = node_to_i915(m->private); 728 struct intel_engine_cs *engine; 729 enum intel_engine_id id; 730 int i, pipe; 731 732 intel_runtime_pm_get(dev_priv); 733 734 if (IS_CHERRYVIEW(dev_priv)) { 735 seq_printf(m, "Master Interrupt Control:\t%08x\n", 736 I915_READ(GEN8_MASTER_IRQ)); 737 738 seq_printf(m, "Display IER:\t%08x\n", 739 I915_READ(VLV_IER)); 740 seq_printf(m, "Display IIR:\t%08x\n", 741 I915_READ(VLV_IIR)); 742 seq_printf(m, "Display IIR_RW:\t%08x\n", 743 I915_READ(VLV_IIR_RW)); 744 seq_printf(m, "Display IMR:\t%08x\n", 745 I915_READ(VLV_IMR)); 746 for_each_pipe(dev_priv, pipe) 747 seq_printf(m, "Pipe %c stat:\t%08x\n", 748 pipe_name(pipe), 749 I915_READ(PIPESTAT(pipe))); 750 751 seq_printf(m, "Port hotplug:\t%08x\n", 752 I915_READ(PORT_HOTPLUG_EN)); 753 seq_printf(m, "DPFLIPSTAT:\t%08x\n", 754 I915_READ(VLV_DPFLIPSTAT)); 755 seq_printf(m, "DPINVGTT:\t%08x\n", 756 I915_READ(DPINVGTT)); 757 758 for (i = 0; i < 4; i++) { 759 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", 760 i, I915_READ(GEN8_GT_IMR(i))); 761 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", 762 i, I915_READ(GEN8_GT_IIR(i))); 763 seq_printf(m, "GT Interrupt IER %d:\t%08x\n", 764 i, I915_READ(GEN8_GT_IER(i))); 765 } 766 767 seq_printf(m, "PCU interrupt mask:\t%08x\n", 768 I915_READ(GEN8_PCU_IMR)); 769 seq_printf(m, "PCU interrupt identity:\t%08x\n", 770 I915_READ(GEN8_PCU_IIR)); 771 seq_printf(m, "PCU interrupt enable:\t%08x\n", 772 I915_READ(GEN8_PCU_IER)); 773 } else if (INTEL_GEN(dev_priv) >= 8) { 774 seq_printf(m, "Master Interrupt Control:\t%08x\n", 775 I915_READ(GEN8_MASTER_IRQ)); 776 777 for (i = 0; i < 4; i++) { 778 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", 779 i, I915_READ(GEN8_GT_IMR(i))); 780 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", 781 i, I915_READ(GEN8_GT_IIR(i))); 782 seq_printf(m, "GT Interrupt IER %d:\t%08x\n", 783 i, I915_READ(GEN8_GT_IER(i))); 784 } 785 786 for_each_pipe(dev_priv, pipe) { 787 enum intel_display_power_domain power_domain; 788 789 power_domain = POWER_DOMAIN_PIPE(pipe); 790 if (!intel_display_power_get_if_enabled(dev_priv, 791 power_domain)) { 792 seq_printf(m, "Pipe %c power disabled\n", 793 pipe_name(pipe)); 794 continue; 795 } 796 seq_printf(m, "Pipe %c IMR:\t%08x\n", 797 pipe_name(pipe), 798 I915_READ(GEN8_DE_PIPE_IMR(pipe))); 799 seq_printf(m, "Pipe %c IIR:\t%08x\n", 800 pipe_name(pipe), 801 I915_READ(GEN8_DE_PIPE_IIR(pipe))); 802 seq_printf(m, "Pipe %c IER:\t%08x\n", 803 pipe_name(pipe), 804 I915_READ(GEN8_DE_PIPE_IER(pipe))); 805 806 intel_display_power_put(dev_priv, power_domain); 807 } 808 809 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", 810 I915_READ(GEN8_DE_PORT_IMR)); 811 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", 812 I915_READ(GEN8_DE_PORT_IIR)); 813 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", 814 I915_READ(GEN8_DE_PORT_IER)); 815 816 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", 817 I915_READ(GEN8_DE_MISC_IMR)); 818 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", 819 I915_READ(GEN8_DE_MISC_IIR)); 820 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", 821 I915_READ(GEN8_DE_MISC_IER)); 822 823 seq_printf(m, "PCU interrupt mask:\t%08x\n", 824 I915_READ(GEN8_PCU_IMR)); 825 seq_printf(m, "PCU interrupt identity:\t%08x\n", 826 I915_READ(GEN8_PCU_IIR)); 827 seq_printf(m, "PCU interrupt enable:\t%08x\n", 828 I915_READ(GEN8_PCU_IER)); 829 } else if (IS_VALLEYVIEW(dev_priv)) { 830 seq_printf(m, "Display IER:\t%08x\n", 831 I915_READ(VLV_IER)); 832 seq_printf(m, "Display IIR:\t%08x\n", 833 I915_READ(VLV_IIR)); 834 seq_printf(m, "Display IIR_RW:\t%08x\n", 835 I915_READ(VLV_IIR_RW)); 836 seq_printf(m, "Display IMR:\t%08x\n", 837 I915_READ(VLV_IMR)); 838 for_each_pipe(dev_priv, pipe) 839 seq_printf(m, "Pipe %c stat:\t%08x\n", 840 pipe_name(pipe), 841 I915_READ(PIPESTAT(pipe))); 842 843 seq_printf(m, "Master IER:\t%08x\n", 844 I915_READ(VLV_MASTER_IER)); 845 846 seq_printf(m, "Render IER:\t%08x\n", 847 I915_READ(GTIER)); 848 seq_printf(m, "Render IIR:\t%08x\n", 849 I915_READ(GTIIR)); 850 seq_printf(m, "Render IMR:\t%08x\n", 851 I915_READ(GTIMR)); 852 853 seq_printf(m, "PM IER:\t\t%08x\n", 854 I915_READ(GEN6_PMIER)); 855 seq_printf(m, "PM IIR:\t\t%08x\n", 856 I915_READ(GEN6_PMIIR)); 857 seq_printf(m, "PM IMR:\t\t%08x\n", 858 I915_READ(GEN6_PMIMR)); 859 860 seq_printf(m, "Port hotplug:\t%08x\n", 861 I915_READ(PORT_HOTPLUG_EN)); 862 seq_printf(m, "DPFLIPSTAT:\t%08x\n", 863 I915_READ(VLV_DPFLIPSTAT)); 864 seq_printf(m, "DPINVGTT:\t%08x\n", 865 I915_READ(DPINVGTT)); 866 867 } else if (!HAS_PCH_SPLIT(dev_priv)) { 868 seq_printf(m, "Interrupt enable: %08x\n", 869 I915_READ(IER)); 870 seq_printf(m, "Interrupt identity: %08x\n", 871 I915_READ(IIR)); 872 seq_printf(m, "Interrupt mask: %08x\n", 873 I915_READ(IMR)); 874 for_each_pipe(dev_priv, pipe) 875 seq_printf(m, "Pipe %c stat: %08x\n", 876 pipe_name(pipe), 877 I915_READ(PIPESTAT(pipe))); 878 } else { 879 seq_printf(m, "North Display Interrupt enable: %08x\n", 880 I915_READ(DEIER)); 881 seq_printf(m, "North Display Interrupt identity: %08x\n", 882 I915_READ(DEIIR)); 883 seq_printf(m, "North Display Interrupt mask: %08x\n", 884 I915_READ(DEIMR)); 885 seq_printf(m, "South Display Interrupt enable: %08x\n", 886 I915_READ(SDEIER)); 887 seq_printf(m, "South Display Interrupt identity: %08x\n", 888 I915_READ(SDEIIR)); 889 seq_printf(m, "South Display Interrupt mask: %08x\n", 890 I915_READ(SDEIMR)); 891 seq_printf(m, "Graphics Interrupt enable: %08x\n", 892 I915_READ(GTIER)); 893 seq_printf(m, "Graphics Interrupt identity: %08x\n", 894 I915_READ(GTIIR)); 895 seq_printf(m, "Graphics Interrupt mask: %08x\n", 896 I915_READ(GTIMR)); 897 } 898 for_each_engine(engine, dev_priv, id) { 899 if (INTEL_GEN(dev_priv) >= 6) { 900 seq_printf(m, 901 "Graphics Interrupt mask (%s): %08x\n", 902 engine->name, I915_READ_IMR(engine)); 903 } 904 i915_ring_seqno_info(m, engine); 905 } 906 intel_runtime_pm_put(dev_priv); 907 908 return 0; 909 } 910 911 static int i915_gem_fence_regs_info(struct seq_file *m, void *data) 912 { 913 struct drm_i915_private *dev_priv = node_to_i915(m->private); 914 struct drm_device *dev = &dev_priv->drm; 915 int i, ret; 916 917 ret = mutex_lock_interruptible(&dev->struct_mutex); 918 if (ret) 919 return ret; 920 921 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); 922 for (i = 0; i < dev_priv->num_fence_regs; i++) { 923 struct i915_vma *vma = dev_priv->fence_regs[i].vma; 924 925 seq_printf(m, "Fence %d, pin count = %d, object = ", 926 i, dev_priv->fence_regs[i].pin_count); 927 if (!vma) 928 seq_puts(m, "unused"); 929 else 930 describe_obj(m, vma->obj); 931 seq_putc(m, '\n'); 932 } 933 934 mutex_unlock(&dev->struct_mutex); 935 return 0; 936 } 937 938 static int i915_hws_info(struct seq_file *m, void *data) 939 { 940 struct drm_info_node *node = m->private; 941 struct drm_i915_private *dev_priv = node_to_i915(node); 942 struct intel_engine_cs *engine; 943 const u32 *hws; 944 int i; 945 946 engine = dev_priv->engine[(uintptr_t)node->info_ent->data]; 947 hws = engine->status_page.page_addr; 948 if (hws == NULL) 949 return 0; 950 951 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { 952 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", 953 i * 4, 954 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); 955 } 956 return 0; 957 } 958 959 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 960 961 static ssize_t 962 i915_error_state_write(struct file *filp, 963 const char __user *ubuf, 964 size_t cnt, 965 loff_t *ppos) 966 { 967 struct i915_error_state_file_priv *error_priv = filp->private_data; 968 969 DRM_DEBUG_DRIVER("Resetting error state\n"); 970 i915_destroy_error_state(error_priv->dev); 971 972 return cnt; 973 } 974 975 static int i915_error_state_open(struct inode *inode, struct file *file) 976 { 977 struct drm_i915_private *dev_priv = inode->i_private; 978 struct i915_error_state_file_priv *error_priv; 979 980 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); 981 if (!error_priv) 982 return -ENOMEM; 983 984 error_priv->dev = &dev_priv->drm; 985 986 i915_error_state_get(&dev_priv->drm, error_priv); 987 988 file->private_data = error_priv; 989 990 return 0; 991 } 992 993 static int i915_error_state_release(struct inode *inode, struct file *file) 994 { 995 struct i915_error_state_file_priv *error_priv = file->private_data; 996 997 i915_error_state_put(error_priv); 998 kfree(error_priv); 999 1000 return 0; 1001 } 1002 1003 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, 1004 size_t count, loff_t *pos) 1005 { 1006 struct i915_error_state_file_priv *error_priv = file->private_data; 1007 struct drm_i915_error_state_buf error_str; 1008 loff_t tmp_pos = 0; 1009 ssize_t ret_count = 0; 1010 int ret; 1011 1012 ret = i915_error_state_buf_init(&error_str, 1013 to_i915(error_priv->dev), count, *pos); 1014 if (ret) 1015 return ret; 1016 1017 ret = i915_error_state_to_str(&error_str, error_priv); 1018 if (ret) 1019 goto out; 1020 1021 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, 1022 error_str.buf, 1023 error_str.bytes); 1024 1025 if (ret_count < 0) 1026 ret = ret_count; 1027 else 1028 *pos = error_str.start + ret_count; 1029 out: 1030 i915_error_state_buf_release(&error_str); 1031 return ret ?: ret_count; 1032 } 1033 1034 static const struct file_operations i915_error_state_fops = { 1035 .owner = THIS_MODULE, 1036 .open = i915_error_state_open, 1037 .read = i915_error_state_read, 1038 .write = i915_error_state_write, 1039 .llseek = default_llseek, 1040 .release = i915_error_state_release, 1041 }; 1042 1043 #endif 1044 1045 static int 1046 i915_next_seqno_get(void *data, u64 *val) 1047 { 1048 struct drm_i915_private *dev_priv = data; 1049 int ret; 1050 1051 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); 1052 if (ret) 1053 return ret; 1054 1055 *val = dev_priv->next_seqno; 1056 mutex_unlock(&dev_priv->drm.struct_mutex); 1057 1058 return 0; 1059 } 1060 1061 static int 1062 i915_next_seqno_set(void *data, u64 val) 1063 { 1064 struct drm_i915_private *dev_priv = data; 1065 struct drm_device *dev = &dev_priv->drm; 1066 int ret; 1067 1068 ret = mutex_lock_interruptible(&dev->struct_mutex); 1069 if (ret) 1070 return ret; 1071 1072 ret = i915_gem_set_seqno(dev, val); 1073 mutex_unlock(&dev->struct_mutex); 1074 1075 return ret; 1076 } 1077 1078 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, 1079 i915_next_seqno_get, i915_next_seqno_set, 1080 "0x%llx\n"); 1081 1082 static int i915_frequency_info(struct seq_file *m, void *unused) 1083 { 1084 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1085 struct drm_device *dev = &dev_priv->drm; 1086 int ret = 0; 1087 1088 intel_runtime_pm_get(dev_priv); 1089 1090 if (IS_GEN5(dev_priv)) { 1091 u16 rgvswctl = I915_READ16(MEMSWCTL); 1092 u16 rgvstat = I915_READ16(MEMSTAT_ILK); 1093 1094 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); 1095 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); 1096 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> 1097 MEMSTAT_VID_SHIFT); 1098 seq_printf(m, "Current P-state: %d\n", 1099 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); 1100 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1101 u32 freq_sts; 1102 1103 mutex_lock(&dev_priv->rps.hw_lock); 1104 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 1105 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); 1106 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); 1107 1108 seq_printf(m, "actual GPU freq: %d MHz\n", 1109 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); 1110 1111 seq_printf(m, "current GPU freq: %d MHz\n", 1112 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); 1113 1114 seq_printf(m, "max GPU freq: %d MHz\n", 1115 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); 1116 1117 seq_printf(m, "min GPU freq: %d MHz\n", 1118 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); 1119 1120 seq_printf(m, "idle GPU freq: %d MHz\n", 1121 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); 1122 1123 seq_printf(m, 1124 "efficient (RPe) frequency: %d MHz\n", 1125 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); 1126 mutex_unlock(&dev_priv->rps.hw_lock); 1127 } else if (INTEL_GEN(dev_priv) >= 6) { 1128 u32 rp_state_limits; 1129 u32 gt_perf_status; 1130 u32 rp_state_cap; 1131 u32 rpmodectl, rpinclimit, rpdeclimit; 1132 u32 rpstat, cagf, reqf; 1133 u32 rpupei, rpcurup, rpprevup; 1134 u32 rpdownei, rpcurdown, rpprevdown; 1135 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; 1136 int max_freq; 1137 1138 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); 1139 if (IS_BROXTON(dev_priv)) { 1140 rp_state_cap = I915_READ(BXT_RP_STATE_CAP); 1141 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); 1142 } else { 1143 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); 1144 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); 1145 } 1146 1147 /* RPSTAT1 is in the GT power well */ 1148 ret = mutex_lock_interruptible(&dev->struct_mutex); 1149 if (ret) 1150 goto out; 1151 1152 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 1153 1154 reqf = I915_READ(GEN6_RPNSWREQ); 1155 if (IS_GEN9(dev_priv)) 1156 reqf >>= 23; 1157 else { 1158 reqf &= ~GEN6_TURBO_DISABLE; 1159 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 1160 reqf >>= 24; 1161 else 1162 reqf >>= 25; 1163 } 1164 reqf = intel_gpu_freq(dev_priv, reqf); 1165 1166 rpmodectl = I915_READ(GEN6_RP_CONTROL); 1167 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); 1168 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); 1169 1170 rpstat = I915_READ(GEN6_RPSTAT1); 1171 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; 1172 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; 1173 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; 1174 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; 1175 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; 1176 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; 1177 if (IS_GEN9(dev_priv)) 1178 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; 1179 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 1180 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; 1181 else 1182 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; 1183 cagf = intel_gpu_freq(dev_priv, cagf); 1184 1185 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 1186 mutex_unlock(&dev->struct_mutex); 1187 1188 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { 1189 pm_ier = I915_READ(GEN6_PMIER); 1190 pm_imr = I915_READ(GEN6_PMIMR); 1191 pm_isr = I915_READ(GEN6_PMISR); 1192 pm_iir = I915_READ(GEN6_PMIIR); 1193 pm_mask = I915_READ(GEN6_PMINTRMSK); 1194 } else { 1195 pm_ier = I915_READ(GEN8_GT_IER(2)); 1196 pm_imr = I915_READ(GEN8_GT_IMR(2)); 1197 pm_isr = I915_READ(GEN8_GT_ISR(2)); 1198 pm_iir = I915_READ(GEN8_GT_IIR(2)); 1199 pm_mask = I915_READ(GEN6_PMINTRMSK); 1200 } 1201 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", 1202 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); 1203 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep); 1204 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); 1205 seq_printf(m, "Render p-state ratio: %d\n", 1206 (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8); 1207 seq_printf(m, "Render p-state VID: %d\n", 1208 gt_perf_status & 0xff); 1209 seq_printf(m, "Render p-state limit: %d\n", 1210 rp_state_limits & 0xff); 1211 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); 1212 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); 1213 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); 1214 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); 1215 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); 1216 seq_printf(m, "CAGF: %dMHz\n", cagf); 1217 seq_printf(m, "RP CUR UP EI: %d (%dus)\n", 1218 rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei)); 1219 seq_printf(m, "RP CUR UP: %d (%dus)\n", 1220 rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup)); 1221 seq_printf(m, "RP PREV UP: %d (%dus)\n", 1222 rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup)); 1223 seq_printf(m, "Up threshold: %d%%\n", 1224 dev_priv->rps.up_threshold); 1225 1226 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n", 1227 rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei)); 1228 seq_printf(m, "RP CUR DOWN: %d (%dus)\n", 1229 rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown)); 1230 seq_printf(m, "RP PREV DOWN: %d (%dus)\n", 1231 rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown)); 1232 seq_printf(m, "Down threshold: %d%%\n", 1233 dev_priv->rps.down_threshold); 1234 1235 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 : 1236 rp_state_cap >> 16) & 0xff; 1237 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? 1238 GEN9_FREQ_SCALER : 1); 1239 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", 1240 intel_gpu_freq(dev_priv, max_freq)); 1241 1242 max_freq = (rp_state_cap & 0xff00) >> 8; 1243 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? 1244 GEN9_FREQ_SCALER : 1); 1245 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", 1246 intel_gpu_freq(dev_priv, max_freq)); 1247 1248 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 : 1249 rp_state_cap >> 0) & 0xff; 1250 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? 1251 GEN9_FREQ_SCALER : 1); 1252 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", 1253 intel_gpu_freq(dev_priv, max_freq)); 1254 seq_printf(m, "Max overclocked frequency: %dMHz\n", 1255 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); 1256 1257 seq_printf(m, "Current freq: %d MHz\n", 1258 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); 1259 seq_printf(m, "Actual freq: %d MHz\n", cagf); 1260 seq_printf(m, "Idle freq: %d MHz\n", 1261 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); 1262 seq_printf(m, "Min freq: %d MHz\n", 1263 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); 1264 seq_printf(m, "Boost freq: %d MHz\n", 1265 intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); 1266 seq_printf(m, "Max freq: %d MHz\n", 1267 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); 1268 seq_printf(m, 1269 "efficient (RPe) frequency: %d MHz\n", 1270 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); 1271 } else { 1272 seq_puts(m, "no P-state info available\n"); 1273 } 1274 1275 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq); 1276 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); 1277 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); 1278 1279 out: 1280 intel_runtime_pm_put(dev_priv); 1281 return ret; 1282 } 1283 1284 static void i915_instdone_info(struct drm_i915_private *dev_priv, 1285 struct seq_file *m, 1286 struct intel_instdone *instdone) 1287 { 1288 int slice; 1289 int subslice; 1290 1291 seq_printf(m, "\t\tINSTDONE: 0x%08x\n", 1292 instdone->instdone); 1293 1294 if (INTEL_GEN(dev_priv) <= 3) 1295 return; 1296 1297 seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n", 1298 instdone->slice_common); 1299 1300 if (INTEL_GEN(dev_priv) <= 6) 1301 return; 1302 1303 for_each_instdone_slice_subslice(dev_priv, slice, subslice) 1304 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n", 1305 slice, subslice, instdone->sampler[slice][subslice]); 1306 1307 for_each_instdone_slice_subslice(dev_priv, slice, subslice) 1308 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n", 1309 slice, subslice, instdone->row[slice][subslice]); 1310 } 1311 1312 static int i915_hangcheck_info(struct seq_file *m, void *unused) 1313 { 1314 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1315 struct intel_engine_cs *engine; 1316 u64 acthd[I915_NUM_ENGINES]; 1317 u32 seqno[I915_NUM_ENGINES]; 1318 struct intel_instdone instdone; 1319 enum intel_engine_id id; 1320 1321 if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags)) 1322 seq_printf(m, "Wedged\n"); 1323 if (test_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags)) 1324 seq_printf(m, "Reset in progress\n"); 1325 if (waitqueue_active(&dev_priv->gpu_error.wait_queue)) 1326 seq_printf(m, "Waiter holding struct mutex\n"); 1327 if (waitqueue_active(&dev_priv->gpu_error.reset_queue)) 1328 seq_printf(m, "struct_mutex blocked for reset\n"); 1329 1330 if (!i915.enable_hangcheck) { 1331 seq_printf(m, "Hangcheck disabled\n"); 1332 return 0; 1333 } 1334 1335 intel_runtime_pm_get(dev_priv); 1336 1337 for_each_engine(engine, dev_priv, id) { 1338 acthd[id] = intel_engine_get_active_head(engine); 1339 seqno[id] = intel_engine_get_seqno(engine); 1340 } 1341 1342 intel_engine_get_instdone(dev_priv->engine[RCS], &instdone); 1343 1344 intel_runtime_pm_put(dev_priv); 1345 1346 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) { 1347 seq_printf(m, "Hangcheck active, fires in %dms\n", 1348 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - 1349 jiffies)); 1350 } else 1351 seq_printf(m, "Hangcheck inactive\n"); 1352 1353 for_each_engine(engine, dev_priv, id) { 1354 struct intel_breadcrumbs *b = &engine->breadcrumbs; 1355 struct rb_node *rb; 1356 1357 seq_printf(m, "%s:\n", engine->name); 1358 seq_printf(m, "\tseqno = %x [current %x, last %x]\n", 1359 engine->hangcheck.seqno, 1360 seqno[id], 1361 engine->last_submitted_seqno); 1362 seq_printf(m, "\twaiters? %s, fake irq active? %s\n", 1363 yesno(intel_engine_has_waiter(engine)), 1364 yesno(test_bit(engine->id, 1365 &dev_priv->gpu_error.missed_irq_rings))); 1366 spin_lock(&b->lock); 1367 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { 1368 struct intel_wait *w = container_of(rb, typeof(*w), node); 1369 1370 seq_printf(m, "\t%s [%d] waiting for %x\n", 1371 w->tsk->comm, w->tsk->pid, w->seqno); 1372 } 1373 spin_unlock(&b->lock); 1374 1375 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", 1376 (long long)engine->hangcheck.acthd, 1377 (long long)acthd[id]); 1378 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score); 1379 seq_printf(m, "\taction = %d\n", engine->hangcheck.action); 1380 1381 if (engine->id == RCS) { 1382 seq_puts(m, "\tinstdone read =\n"); 1383 1384 i915_instdone_info(dev_priv, m, &instdone); 1385 1386 seq_puts(m, "\tinstdone accu =\n"); 1387 1388 i915_instdone_info(dev_priv, m, 1389 &engine->hangcheck.instdone); 1390 } 1391 } 1392 1393 return 0; 1394 } 1395 1396 static int ironlake_drpc_info(struct seq_file *m) 1397 { 1398 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1399 struct drm_device *dev = &dev_priv->drm; 1400 u32 rgvmodectl, rstdbyctl; 1401 u16 crstandvid; 1402 int ret; 1403 1404 ret = mutex_lock_interruptible(&dev->struct_mutex); 1405 if (ret) 1406 return ret; 1407 intel_runtime_pm_get(dev_priv); 1408 1409 rgvmodectl = I915_READ(MEMMODECTL); 1410 rstdbyctl = I915_READ(RSTDBYCTL); 1411 crstandvid = I915_READ16(CRSTANDVID); 1412 1413 intel_runtime_pm_put(dev_priv); 1414 mutex_unlock(&dev->struct_mutex); 1415 1416 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); 1417 seq_printf(m, "Boost freq: %d\n", 1418 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> 1419 MEMMODE_BOOST_FREQ_SHIFT); 1420 seq_printf(m, "HW control enabled: %s\n", 1421 yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); 1422 seq_printf(m, "SW control enabled: %s\n", 1423 yesno(rgvmodectl & MEMMODE_SWMODE_EN)); 1424 seq_printf(m, "Gated voltage change: %s\n", 1425 yesno(rgvmodectl & MEMMODE_RCLK_GATE)); 1426 seq_printf(m, "Starting frequency: P%d\n", 1427 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); 1428 seq_printf(m, "Max P-state: P%d\n", 1429 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); 1430 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); 1431 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); 1432 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); 1433 seq_printf(m, "Render standby enabled: %s\n", 1434 yesno(!(rstdbyctl & RCX_SW_EXIT))); 1435 seq_puts(m, "Current RS state: "); 1436 switch (rstdbyctl & RSX_STATUS_MASK) { 1437 case RSX_STATUS_ON: 1438 seq_puts(m, "on\n"); 1439 break; 1440 case RSX_STATUS_RC1: 1441 seq_puts(m, "RC1\n"); 1442 break; 1443 case RSX_STATUS_RC1E: 1444 seq_puts(m, "RC1E\n"); 1445 break; 1446 case RSX_STATUS_RS1: 1447 seq_puts(m, "RS1\n"); 1448 break; 1449 case RSX_STATUS_RS2: 1450 seq_puts(m, "RS2 (RC6)\n"); 1451 break; 1452 case RSX_STATUS_RS3: 1453 seq_puts(m, "RC3 (RC6+)\n"); 1454 break; 1455 default: 1456 seq_puts(m, "unknown\n"); 1457 break; 1458 } 1459 1460 return 0; 1461 } 1462 1463 static int i915_forcewake_domains(struct seq_file *m, void *data) 1464 { 1465 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1466 struct intel_uncore_forcewake_domain *fw_domain; 1467 1468 spin_lock_irq(&dev_priv->uncore.lock); 1469 for_each_fw_domain(fw_domain, dev_priv) { 1470 seq_printf(m, "%s.wake_count = %u\n", 1471 intel_uncore_forcewake_domain_to_str(fw_domain->id), 1472 fw_domain->wake_count); 1473 } 1474 spin_unlock_irq(&dev_priv->uncore.lock); 1475 1476 return 0; 1477 } 1478 1479 static int vlv_drpc_info(struct seq_file *m) 1480 { 1481 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1482 u32 rpmodectl1, rcctl1, pw_status; 1483 1484 intel_runtime_pm_get(dev_priv); 1485 1486 pw_status = I915_READ(VLV_GTLC_PW_STATUS); 1487 rpmodectl1 = I915_READ(GEN6_RP_CONTROL); 1488 rcctl1 = I915_READ(GEN6_RC_CONTROL); 1489 1490 intel_runtime_pm_put(dev_priv); 1491 1492 seq_printf(m, "Video Turbo Mode: %s\n", 1493 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); 1494 seq_printf(m, "Turbo enabled: %s\n", 1495 yesno(rpmodectl1 & GEN6_RP_ENABLE)); 1496 seq_printf(m, "HW control enabled: %s\n", 1497 yesno(rpmodectl1 & GEN6_RP_ENABLE)); 1498 seq_printf(m, "SW control enabled: %s\n", 1499 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == 1500 GEN6_RP_MEDIA_SW_MODE)); 1501 seq_printf(m, "RC6 Enabled: %s\n", 1502 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | 1503 GEN6_RC_CTL_EI_MODE(1)))); 1504 seq_printf(m, "Render Power Well: %s\n", 1505 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); 1506 seq_printf(m, "Media Power Well: %s\n", 1507 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); 1508 1509 seq_printf(m, "Render RC6 residency since boot: %u\n", 1510 I915_READ(VLV_GT_RENDER_RC6)); 1511 seq_printf(m, "Media RC6 residency since boot: %u\n", 1512 I915_READ(VLV_GT_MEDIA_RC6)); 1513 1514 return i915_forcewake_domains(m, NULL); 1515 } 1516 1517 static int gen6_drpc_info(struct seq_file *m) 1518 { 1519 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1520 struct drm_device *dev = &dev_priv->drm; 1521 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; 1522 u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; 1523 unsigned forcewake_count; 1524 int count = 0, ret; 1525 1526 ret = mutex_lock_interruptible(&dev->struct_mutex); 1527 if (ret) 1528 return ret; 1529 intel_runtime_pm_get(dev_priv); 1530 1531 spin_lock_irq(&dev_priv->uncore.lock); 1532 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count; 1533 spin_unlock_irq(&dev_priv->uncore.lock); 1534 1535 if (forcewake_count) { 1536 seq_puts(m, "RC information inaccurate because somebody " 1537 "holds a forcewake reference \n"); 1538 } else { 1539 /* NB: we cannot use forcewake, else we read the wrong values */ 1540 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) 1541 udelay(10); 1542 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); 1543 } 1544 1545 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); 1546 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); 1547 1548 rpmodectl1 = I915_READ(GEN6_RP_CONTROL); 1549 rcctl1 = I915_READ(GEN6_RC_CONTROL); 1550 if (INTEL_GEN(dev_priv) >= 9) { 1551 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE); 1552 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS); 1553 } 1554 mutex_unlock(&dev->struct_mutex); 1555 mutex_lock(&dev_priv->rps.hw_lock); 1556 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); 1557 mutex_unlock(&dev_priv->rps.hw_lock); 1558 1559 intel_runtime_pm_put(dev_priv); 1560 1561 seq_printf(m, "Video Turbo Mode: %s\n", 1562 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); 1563 seq_printf(m, "HW control enabled: %s\n", 1564 yesno(rpmodectl1 & GEN6_RP_ENABLE)); 1565 seq_printf(m, "SW control enabled: %s\n", 1566 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == 1567 GEN6_RP_MEDIA_SW_MODE)); 1568 seq_printf(m, "RC1e Enabled: %s\n", 1569 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); 1570 seq_printf(m, "RC6 Enabled: %s\n", 1571 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); 1572 if (INTEL_GEN(dev_priv) >= 9) { 1573 seq_printf(m, "Render Well Gating Enabled: %s\n", 1574 yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); 1575 seq_printf(m, "Media Well Gating Enabled: %s\n", 1576 yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE)); 1577 } 1578 seq_printf(m, "Deep RC6 Enabled: %s\n", 1579 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); 1580 seq_printf(m, "Deepest RC6 Enabled: %s\n", 1581 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); 1582 seq_puts(m, "Current RC state: "); 1583 switch (gt_core_status & GEN6_RCn_MASK) { 1584 case GEN6_RC0: 1585 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) 1586 seq_puts(m, "Core Power Down\n"); 1587 else 1588 seq_puts(m, "on\n"); 1589 break; 1590 case GEN6_RC3: 1591 seq_puts(m, "RC3\n"); 1592 break; 1593 case GEN6_RC6: 1594 seq_puts(m, "RC6\n"); 1595 break; 1596 case GEN6_RC7: 1597 seq_puts(m, "RC7\n"); 1598 break; 1599 default: 1600 seq_puts(m, "Unknown\n"); 1601 break; 1602 } 1603 1604 seq_printf(m, "Core Power Down: %s\n", 1605 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); 1606 if (INTEL_GEN(dev_priv) >= 9) { 1607 seq_printf(m, "Render Power Well: %s\n", 1608 (gen9_powergate_status & 1609 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); 1610 seq_printf(m, "Media Power Well: %s\n", 1611 (gen9_powergate_status & 1612 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); 1613 } 1614 1615 /* Not exactly sure what this is */ 1616 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", 1617 I915_READ(GEN6_GT_GFX_RC6_LOCKED)); 1618 seq_printf(m, "RC6 residency since boot: %u\n", 1619 I915_READ(GEN6_GT_GFX_RC6)); 1620 seq_printf(m, "RC6+ residency since boot: %u\n", 1621 I915_READ(GEN6_GT_GFX_RC6p)); 1622 seq_printf(m, "RC6++ residency since boot: %u\n", 1623 I915_READ(GEN6_GT_GFX_RC6pp)); 1624 1625 seq_printf(m, "RC6 voltage: %dmV\n", 1626 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); 1627 seq_printf(m, "RC6+ voltage: %dmV\n", 1628 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); 1629 seq_printf(m, "RC6++ voltage: %dmV\n", 1630 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); 1631 return i915_forcewake_domains(m, NULL); 1632 } 1633 1634 static int i915_drpc_info(struct seq_file *m, void *unused) 1635 { 1636 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1637 1638 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1639 return vlv_drpc_info(m); 1640 else if (INTEL_GEN(dev_priv) >= 6) 1641 return gen6_drpc_info(m); 1642 else 1643 return ironlake_drpc_info(m); 1644 } 1645 1646 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) 1647 { 1648 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1649 1650 seq_printf(m, "FB tracking busy bits: 0x%08x\n", 1651 dev_priv->fb_tracking.busy_bits); 1652 1653 seq_printf(m, "FB tracking flip bits: 0x%08x\n", 1654 dev_priv->fb_tracking.flip_bits); 1655 1656 return 0; 1657 } 1658 1659 static int i915_fbc_status(struct seq_file *m, void *unused) 1660 { 1661 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1662 1663 if (!HAS_FBC(dev_priv)) { 1664 seq_puts(m, "FBC unsupported on this chipset\n"); 1665 return 0; 1666 } 1667 1668 intel_runtime_pm_get(dev_priv); 1669 mutex_lock(&dev_priv->fbc.lock); 1670 1671 if (intel_fbc_is_active(dev_priv)) 1672 seq_puts(m, "FBC enabled\n"); 1673 else 1674 seq_printf(m, "FBC disabled: %s\n", 1675 dev_priv->fbc.no_fbc_reason); 1676 1677 if (intel_fbc_is_active(dev_priv) && 1678 INTEL_GEN(dev_priv) >= 7) 1679 seq_printf(m, "Compressing: %s\n", 1680 yesno(I915_READ(FBC_STATUS2) & 1681 FBC_COMPRESSION_MASK)); 1682 1683 mutex_unlock(&dev_priv->fbc.lock); 1684 intel_runtime_pm_put(dev_priv); 1685 1686 return 0; 1687 } 1688 1689 static int i915_fbc_fc_get(void *data, u64 *val) 1690 { 1691 struct drm_i915_private *dev_priv = data; 1692 1693 if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) 1694 return -ENODEV; 1695 1696 *val = dev_priv->fbc.false_color; 1697 1698 return 0; 1699 } 1700 1701 static int i915_fbc_fc_set(void *data, u64 val) 1702 { 1703 struct drm_i915_private *dev_priv = data; 1704 u32 reg; 1705 1706 if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) 1707 return -ENODEV; 1708 1709 mutex_lock(&dev_priv->fbc.lock); 1710 1711 reg = I915_READ(ILK_DPFC_CONTROL); 1712 dev_priv->fbc.false_color = val; 1713 1714 I915_WRITE(ILK_DPFC_CONTROL, val ? 1715 (reg | FBC_CTL_FALSE_COLOR) : 1716 (reg & ~FBC_CTL_FALSE_COLOR)); 1717 1718 mutex_unlock(&dev_priv->fbc.lock); 1719 return 0; 1720 } 1721 1722 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, 1723 i915_fbc_fc_get, i915_fbc_fc_set, 1724 "%llu\n"); 1725 1726 static int i915_ips_status(struct seq_file *m, void *unused) 1727 { 1728 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1729 1730 if (!HAS_IPS(dev_priv)) { 1731 seq_puts(m, "not supported\n"); 1732 return 0; 1733 } 1734 1735 intel_runtime_pm_get(dev_priv); 1736 1737 seq_printf(m, "Enabled by kernel parameter: %s\n", 1738 yesno(i915.enable_ips)); 1739 1740 if (INTEL_GEN(dev_priv) >= 8) { 1741 seq_puts(m, "Currently: unknown\n"); 1742 } else { 1743 if (I915_READ(IPS_CTL) & IPS_ENABLE) 1744 seq_puts(m, "Currently: enabled\n"); 1745 else 1746 seq_puts(m, "Currently: disabled\n"); 1747 } 1748 1749 intel_runtime_pm_put(dev_priv); 1750 1751 return 0; 1752 } 1753 1754 static int i915_sr_status(struct seq_file *m, void *unused) 1755 { 1756 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1757 bool sr_enabled = false; 1758 1759 intel_runtime_pm_get(dev_priv); 1760 1761 if (HAS_PCH_SPLIT(dev_priv)) 1762 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; 1763 else if (IS_CRESTLINE(dev_priv) || IS_G4X(dev_priv) || 1764 IS_I945G(dev_priv) || IS_I945GM(dev_priv)) 1765 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; 1766 else if (IS_I915GM(dev_priv)) 1767 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; 1768 else if (IS_PINEVIEW(dev_priv)) 1769 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; 1770 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1771 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; 1772 1773 intel_runtime_pm_put(dev_priv); 1774 1775 seq_printf(m, "self-refresh: %s\n", 1776 sr_enabled ? "enabled" : "disabled"); 1777 1778 return 0; 1779 } 1780 1781 static int i915_emon_status(struct seq_file *m, void *unused) 1782 { 1783 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1784 struct drm_device *dev = &dev_priv->drm; 1785 unsigned long temp, chipset, gfx; 1786 int ret; 1787 1788 if (!IS_GEN5(dev_priv)) 1789 return -ENODEV; 1790 1791 ret = mutex_lock_interruptible(&dev->struct_mutex); 1792 if (ret) 1793 return ret; 1794 1795 temp = i915_mch_val(dev_priv); 1796 chipset = i915_chipset_val(dev_priv); 1797 gfx = i915_gfx_val(dev_priv); 1798 mutex_unlock(&dev->struct_mutex); 1799 1800 seq_printf(m, "GMCH temp: %ld\n", temp); 1801 seq_printf(m, "Chipset power: %ld\n", chipset); 1802 seq_printf(m, "GFX power: %ld\n", gfx); 1803 seq_printf(m, "Total power: %ld\n", chipset + gfx); 1804 1805 return 0; 1806 } 1807 1808 static int i915_ring_freq_table(struct seq_file *m, void *unused) 1809 { 1810 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1811 int ret = 0; 1812 int gpu_freq, ia_freq; 1813 unsigned int max_gpu_freq, min_gpu_freq; 1814 1815 if (!HAS_LLC(dev_priv)) { 1816 seq_puts(m, "unsupported on this chipset\n"); 1817 return 0; 1818 } 1819 1820 intel_runtime_pm_get(dev_priv); 1821 1822 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); 1823 if (ret) 1824 goto out; 1825 1826 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 1827 /* Convert GT frequency to 50 HZ units */ 1828 min_gpu_freq = 1829 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; 1830 max_gpu_freq = 1831 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER; 1832 } else { 1833 min_gpu_freq = dev_priv->rps.min_freq_softlimit; 1834 max_gpu_freq = dev_priv->rps.max_freq_softlimit; 1835 } 1836 1837 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); 1838 1839 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { 1840 ia_freq = gpu_freq; 1841 sandybridge_pcode_read(dev_priv, 1842 GEN6_PCODE_READ_MIN_FREQ_TABLE, 1843 &ia_freq); 1844 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", 1845 intel_gpu_freq(dev_priv, (gpu_freq * 1846 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? 1847 GEN9_FREQ_SCALER : 1))), 1848 ((ia_freq >> 0) & 0xff) * 100, 1849 ((ia_freq >> 8) & 0xff) * 100); 1850 } 1851 1852 mutex_unlock(&dev_priv->rps.hw_lock); 1853 1854 out: 1855 intel_runtime_pm_put(dev_priv); 1856 return ret; 1857 } 1858 1859 static int i915_opregion(struct seq_file *m, void *unused) 1860 { 1861 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1862 struct drm_device *dev = &dev_priv->drm; 1863 struct intel_opregion *opregion = &dev_priv->opregion; 1864 int ret; 1865 1866 ret = mutex_lock_interruptible(&dev->struct_mutex); 1867 if (ret) 1868 goto out; 1869 1870 if (opregion->header) 1871 seq_write(m, opregion->header, OPREGION_SIZE); 1872 1873 mutex_unlock(&dev->struct_mutex); 1874 1875 out: 1876 return 0; 1877 } 1878 1879 static int i915_vbt(struct seq_file *m, void *unused) 1880 { 1881 struct intel_opregion *opregion = &node_to_i915(m->private)->opregion; 1882 1883 if (opregion->vbt) 1884 seq_write(m, opregion->vbt, opregion->vbt_size); 1885 1886 return 0; 1887 } 1888 1889 static int i915_gem_framebuffer_info(struct seq_file *m, void *data) 1890 { 1891 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1892 struct drm_device *dev = &dev_priv->drm; 1893 struct intel_framebuffer *fbdev_fb = NULL; 1894 struct drm_framebuffer *drm_fb; 1895 int ret; 1896 1897 ret = mutex_lock_interruptible(&dev->struct_mutex); 1898 if (ret) 1899 return ret; 1900 1901 #ifdef CONFIG_DRM_FBDEV_EMULATION 1902 if (dev_priv->fbdev) { 1903 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb); 1904 1905 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", 1906 fbdev_fb->base.width, 1907 fbdev_fb->base.height, 1908 fbdev_fb->base.depth, 1909 fbdev_fb->base.bits_per_pixel, 1910 fbdev_fb->base.modifier[0], 1911 drm_framebuffer_read_refcount(&fbdev_fb->base)); 1912 describe_obj(m, fbdev_fb->obj); 1913 seq_putc(m, '\n'); 1914 } 1915 #endif 1916 1917 mutex_lock(&dev->mode_config.fb_lock); 1918 drm_for_each_fb(drm_fb, dev) { 1919 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); 1920 if (fb == fbdev_fb) 1921 continue; 1922 1923 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", 1924 fb->base.width, 1925 fb->base.height, 1926 fb->base.depth, 1927 fb->base.bits_per_pixel, 1928 fb->base.modifier[0], 1929 drm_framebuffer_read_refcount(&fb->base)); 1930 describe_obj(m, fb->obj); 1931 seq_putc(m, '\n'); 1932 } 1933 mutex_unlock(&dev->mode_config.fb_lock); 1934 mutex_unlock(&dev->struct_mutex); 1935 1936 return 0; 1937 } 1938 1939 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring) 1940 { 1941 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", 1942 ring->space, ring->head, ring->tail, 1943 ring->last_retired_head); 1944 } 1945 1946 static int i915_context_status(struct seq_file *m, void *unused) 1947 { 1948 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1949 struct drm_device *dev = &dev_priv->drm; 1950 struct intel_engine_cs *engine; 1951 struct i915_gem_context *ctx; 1952 enum intel_engine_id id; 1953 int ret; 1954 1955 ret = mutex_lock_interruptible(&dev->struct_mutex); 1956 if (ret) 1957 return ret; 1958 1959 list_for_each_entry(ctx, &dev_priv->context_list, link) { 1960 seq_printf(m, "HW context %u ", ctx->hw_id); 1961 if (ctx->pid) { 1962 struct task_struct *task; 1963 1964 task = get_pid_task(ctx->pid, PIDTYPE_PID); 1965 if (task) { 1966 seq_printf(m, "(%s [%d]) ", 1967 task->comm, task->pid); 1968 put_task_struct(task); 1969 } 1970 } else if (IS_ERR(ctx->file_priv)) { 1971 seq_puts(m, "(deleted) "); 1972 } else { 1973 seq_puts(m, "(kernel) "); 1974 } 1975 1976 seq_putc(m, ctx->remap_slice ? 'R' : 'r'); 1977 seq_putc(m, '\n'); 1978 1979 for_each_engine(engine, dev_priv, id) { 1980 struct intel_context *ce = &ctx->engine[engine->id]; 1981 1982 seq_printf(m, "%s: ", engine->name); 1983 seq_putc(m, ce->initialised ? 'I' : 'i'); 1984 if (ce->state) 1985 describe_obj(m, ce->state->obj); 1986 if (ce->ring) 1987 describe_ctx_ring(m, ce->ring); 1988 seq_putc(m, '\n'); 1989 } 1990 1991 seq_putc(m, '\n'); 1992 } 1993 1994 mutex_unlock(&dev->struct_mutex); 1995 1996 return 0; 1997 } 1998 1999 static void i915_dump_lrc_obj(struct seq_file *m, 2000 struct i915_gem_context *ctx, 2001 struct intel_engine_cs *engine) 2002 { 2003 struct i915_vma *vma = ctx->engine[engine->id].state; 2004 struct page *page; 2005 int j; 2006 2007 seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id); 2008 2009 if (!vma) { 2010 seq_puts(m, "\tFake context\n"); 2011 return; 2012 } 2013 2014 if (vma->flags & I915_VMA_GLOBAL_BIND) 2015 seq_printf(m, "\tBound in GGTT at 0x%08x\n", 2016 i915_ggtt_offset(vma)); 2017 2018 if (i915_gem_object_get_pages(vma->obj)) { 2019 seq_puts(m, "\tFailed to get pages for context object\n\n"); 2020 return; 2021 } 2022 2023 page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN); 2024 if (page) { 2025 u32 *reg_state = kmap_atomic(page); 2026 2027 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { 2028 seq_printf(m, 2029 "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n", 2030 j * 4, 2031 reg_state[j], reg_state[j + 1], 2032 reg_state[j + 2], reg_state[j + 3]); 2033 } 2034 kunmap_atomic(reg_state); 2035 } 2036 2037 seq_putc(m, '\n'); 2038 } 2039 2040 static int i915_dump_lrc(struct seq_file *m, void *unused) 2041 { 2042 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2043 struct drm_device *dev = &dev_priv->drm; 2044 struct intel_engine_cs *engine; 2045 struct i915_gem_context *ctx; 2046 enum intel_engine_id id; 2047 int ret; 2048 2049 if (!i915.enable_execlists) { 2050 seq_printf(m, "Logical Ring Contexts are disabled\n"); 2051 return 0; 2052 } 2053 2054 ret = mutex_lock_interruptible(&dev->struct_mutex); 2055 if (ret) 2056 return ret; 2057 2058 list_for_each_entry(ctx, &dev_priv->context_list, link) 2059 for_each_engine(engine, dev_priv, id) 2060 i915_dump_lrc_obj(m, ctx, engine); 2061 2062 mutex_unlock(&dev->struct_mutex); 2063 2064 return 0; 2065 } 2066 2067 static const char *swizzle_string(unsigned swizzle) 2068 { 2069 switch (swizzle) { 2070 case I915_BIT_6_SWIZZLE_NONE: 2071 return "none"; 2072 case I915_BIT_6_SWIZZLE_9: 2073 return "bit9"; 2074 case I915_BIT_6_SWIZZLE_9_10: 2075 return "bit9/bit10"; 2076 case I915_BIT_6_SWIZZLE_9_11: 2077 return "bit9/bit11"; 2078 case I915_BIT_6_SWIZZLE_9_10_11: 2079 return "bit9/bit10/bit11"; 2080 case I915_BIT_6_SWIZZLE_9_17: 2081 return "bit9/bit17"; 2082 case I915_BIT_6_SWIZZLE_9_10_17: 2083 return "bit9/bit10/bit17"; 2084 case I915_BIT_6_SWIZZLE_UNKNOWN: 2085 return "unknown"; 2086 } 2087 2088 return "bug"; 2089 } 2090 2091 static int i915_swizzle_info(struct seq_file *m, void *data) 2092 { 2093 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2094 struct drm_device *dev = &dev_priv->drm; 2095 int ret; 2096 2097 ret = mutex_lock_interruptible(&dev->struct_mutex); 2098 if (ret) 2099 return ret; 2100 intel_runtime_pm_get(dev_priv); 2101 2102 seq_printf(m, "bit6 swizzle for X-tiling = %s\n", 2103 swizzle_string(dev_priv->mm.bit_6_swizzle_x)); 2104 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", 2105 swizzle_string(dev_priv->mm.bit_6_swizzle_y)); 2106 2107 if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) { 2108 seq_printf(m, "DDC = 0x%08x\n", 2109 I915_READ(DCC)); 2110 seq_printf(m, "DDC2 = 0x%08x\n", 2111 I915_READ(DCC2)); 2112 seq_printf(m, "C0DRB3 = 0x%04x\n", 2113 I915_READ16(C0DRB3)); 2114 seq_printf(m, "C1DRB3 = 0x%04x\n", 2115 I915_READ16(C1DRB3)); 2116 } else if (INTEL_GEN(dev_priv) >= 6) { 2117 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", 2118 I915_READ(MAD_DIMM_C0)); 2119 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", 2120 I915_READ(MAD_DIMM_C1)); 2121 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", 2122 I915_READ(MAD_DIMM_C2)); 2123 seq_printf(m, "TILECTL = 0x%08x\n", 2124 I915_READ(TILECTL)); 2125 if (INTEL_GEN(dev_priv) >= 8) 2126 seq_printf(m, "GAMTARBMODE = 0x%08x\n", 2127 I915_READ(GAMTARBMODE)); 2128 else 2129 seq_printf(m, "ARB_MODE = 0x%08x\n", 2130 I915_READ(ARB_MODE)); 2131 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", 2132 I915_READ(DISP_ARB_CTL)); 2133 } 2134 2135 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) 2136 seq_puts(m, "L-shaped memory detected\n"); 2137 2138 intel_runtime_pm_put(dev_priv); 2139 mutex_unlock(&dev->struct_mutex); 2140 2141 return 0; 2142 } 2143 2144 static int per_file_ctx(int id, void *ptr, void *data) 2145 { 2146 struct i915_gem_context *ctx = ptr; 2147 struct seq_file *m = data; 2148 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; 2149 2150 if (!ppgtt) { 2151 seq_printf(m, " no ppgtt for context %d\n", 2152 ctx->user_handle); 2153 return 0; 2154 } 2155 2156 if (i915_gem_context_is_default(ctx)) 2157 seq_puts(m, " default context:\n"); 2158 else 2159 seq_printf(m, " context %d:\n", ctx->user_handle); 2160 ppgtt->debug_dump(ppgtt, m); 2161 2162 return 0; 2163 } 2164 2165 static void gen8_ppgtt_info(struct seq_file *m, 2166 struct drm_i915_private *dev_priv) 2167 { 2168 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; 2169 struct intel_engine_cs *engine; 2170 enum intel_engine_id id; 2171 int i; 2172 2173 if (!ppgtt) 2174 return; 2175 2176 for_each_engine(engine, dev_priv, id) { 2177 seq_printf(m, "%s\n", engine->name); 2178 for (i = 0; i < 4; i++) { 2179 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i)); 2180 pdp <<= 32; 2181 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i)); 2182 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); 2183 } 2184 } 2185 } 2186 2187 static void gen6_ppgtt_info(struct seq_file *m, 2188 struct drm_i915_private *dev_priv) 2189 { 2190 struct intel_engine_cs *engine; 2191 enum intel_engine_id id; 2192 2193 if (IS_GEN6(dev_priv)) 2194 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); 2195 2196 for_each_engine(engine, dev_priv, id) { 2197 seq_printf(m, "%s\n", engine->name); 2198 if (IS_GEN7(dev_priv)) 2199 seq_printf(m, "GFX_MODE: 0x%08x\n", 2200 I915_READ(RING_MODE_GEN7(engine))); 2201 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", 2202 I915_READ(RING_PP_DIR_BASE(engine))); 2203 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", 2204 I915_READ(RING_PP_DIR_BASE_READ(engine))); 2205 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", 2206 I915_READ(RING_PP_DIR_DCLV(engine))); 2207 } 2208 if (dev_priv->mm.aliasing_ppgtt) { 2209 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; 2210 2211 seq_puts(m, "aliasing PPGTT:\n"); 2212 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); 2213 2214 ppgtt->debug_dump(ppgtt, m); 2215 } 2216 2217 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); 2218 } 2219 2220 static int i915_ppgtt_info(struct seq_file *m, void *data) 2221 { 2222 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2223 struct drm_device *dev = &dev_priv->drm; 2224 struct drm_file *file; 2225 int ret; 2226 2227 mutex_lock(&dev->filelist_mutex); 2228 ret = mutex_lock_interruptible(&dev->struct_mutex); 2229 if (ret) 2230 goto out_unlock; 2231 2232 intel_runtime_pm_get(dev_priv); 2233 2234 if (INTEL_GEN(dev_priv) >= 8) 2235 gen8_ppgtt_info(m, dev_priv); 2236 else if (INTEL_GEN(dev_priv) >= 6) 2237 gen6_ppgtt_info(m, dev_priv); 2238 2239 list_for_each_entry_reverse(file, &dev->filelist, lhead) { 2240 struct drm_i915_file_private *file_priv = file->driver_priv; 2241 struct task_struct *task; 2242 2243 task = get_pid_task(file->pid, PIDTYPE_PID); 2244 if (!task) { 2245 ret = -ESRCH; 2246 goto out_rpm; 2247 } 2248 seq_printf(m, "\nproc: %s\n", task->comm); 2249 put_task_struct(task); 2250 idr_for_each(&file_priv->context_idr, per_file_ctx, 2251 (void *)(unsigned long)m); 2252 } 2253 2254 out_rpm: 2255 intel_runtime_pm_put(dev_priv); 2256 mutex_unlock(&dev->struct_mutex); 2257 out_unlock: 2258 mutex_unlock(&dev->filelist_mutex); 2259 return ret; 2260 } 2261 2262 static int count_irq_waiters(struct drm_i915_private *i915) 2263 { 2264 struct intel_engine_cs *engine; 2265 enum intel_engine_id id; 2266 int count = 0; 2267 2268 for_each_engine(engine, i915, id) 2269 count += intel_engine_has_waiter(engine); 2270 2271 return count; 2272 } 2273 2274 static const char *rps_power_to_str(unsigned int power) 2275 { 2276 static const char * const strings[] = { 2277 [LOW_POWER] = "low power", 2278 [BETWEEN] = "mixed", 2279 [HIGH_POWER] = "high power", 2280 }; 2281 2282 if (power >= ARRAY_SIZE(strings) || !strings[power]) 2283 return "unknown"; 2284 2285 return strings[power]; 2286 } 2287 2288 static int i915_rps_boost_info(struct seq_file *m, void *data) 2289 { 2290 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2291 struct drm_device *dev = &dev_priv->drm; 2292 struct drm_file *file; 2293 2294 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); 2295 seq_printf(m, "GPU busy? %s [%x]\n", 2296 yesno(dev_priv->gt.awake), dev_priv->gt.active_engines); 2297 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); 2298 seq_printf(m, "Frequency requested %d\n", 2299 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); 2300 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", 2301 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), 2302 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), 2303 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), 2304 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); 2305 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", 2306 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq), 2307 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 2308 intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); 2309 2310 mutex_lock(&dev->filelist_mutex); 2311 spin_lock(&dev_priv->rps.client_lock); 2312 list_for_each_entry_reverse(file, &dev->filelist, lhead) { 2313 struct drm_i915_file_private *file_priv = file->driver_priv; 2314 struct task_struct *task; 2315 2316 rcu_read_lock(); 2317 task = pid_task(file->pid, PIDTYPE_PID); 2318 seq_printf(m, "%s [%d]: %d boosts%s\n", 2319 task ? task->comm : "<unknown>", 2320 task ? task->pid : -1, 2321 file_priv->rps.boosts, 2322 list_empty(&file_priv->rps.link) ? "" : ", active"); 2323 rcu_read_unlock(); 2324 } 2325 seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts); 2326 spin_unlock(&dev_priv->rps.client_lock); 2327 mutex_unlock(&dev->filelist_mutex); 2328 2329 if (INTEL_GEN(dev_priv) >= 6 && 2330 dev_priv->rps.enabled && 2331 dev_priv->gt.active_engines) { 2332 u32 rpup, rpupei; 2333 u32 rpdown, rpdownei; 2334 2335 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 2336 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; 2337 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; 2338 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; 2339 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; 2340 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 2341 2342 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", 2343 rps_power_to_str(dev_priv->rps.power)); 2344 seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", 2345 100 * rpup / rpupei, 2346 dev_priv->rps.up_threshold); 2347 seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", 2348 100 * rpdown / rpdownei, 2349 dev_priv->rps.down_threshold); 2350 } else { 2351 seq_puts(m, "\nRPS Autotuning inactive\n"); 2352 } 2353 2354 return 0; 2355 } 2356 2357 static int i915_llc(struct seq_file *m, void *data) 2358 { 2359 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2360 const bool edram = INTEL_GEN(dev_priv) > 8; 2361 2362 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv))); 2363 seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", 2364 intel_uncore_edram_size(dev_priv)/1024/1024); 2365 2366 return 0; 2367 } 2368 2369 static int i915_guc_load_status_info(struct seq_file *m, void *data) 2370 { 2371 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2372 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; 2373 u32 tmp, i; 2374 2375 if (!HAS_GUC_UCODE(dev_priv)) 2376 return 0; 2377 2378 seq_printf(m, "GuC firmware status:\n"); 2379 seq_printf(m, "\tpath: %s\n", 2380 guc_fw->guc_fw_path); 2381 seq_printf(m, "\tfetch: %s\n", 2382 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status)); 2383 seq_printf(m, "\tload: %s\n", 2384 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); 2385 seq_printf(m, "\tversion wanted: %d.%d\n", 2386 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); 2387 seq_printf(m, "\tversion found: %d.%d\n", 2388 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found); 2389 seq_printf(m, "\theader: offset is %d; size = %d\n", 2390 guc_fw->header_offset, guc_fw->header_size); 2391 seq_printf(m, "\tuCode: offset is %d; size = %d\n", 2392 guc_fw->ucode_offset, guc_fw->ucode_size); 2393 seq_printf(m, "\tRSA: offset is %d; size = %d\n", 2394 guc_fw->rsa_offset, guc_fw->rsa_size); 2395 2396 tmp = I915_READ(GUC_STATUS); 2397 2398 seq_printf(m, "\nGuC status 0x%08x:\n", tmp); 2399 seq_printf(m, "\tBootrom status = 0x%x\n", 2400 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); 2401 seq_printf(m, "\tuKernel status = 0x%x\n", 2402 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); 2403 seq_printf(m, "\tMIA Core status = 0x%x\n", 2404 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); 2405 seq_puts(m, "\nScratch registers:\n"); 2406 for (i = 0; i < 16; i++) 2407 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); 2408 2409 return 0; 2410 } 2411 2412 static void i915_guc_client_info(struct seq_file *m, 2413 struct drm_i915_private *dev_priv, 2414 struct i915_guc_client *client) 2415 { 2416 struct intel_engine_cs *engine; 2417 enum intel_engine_id id; 2418 uint64_t tot = 0; 2419 2420 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n", 2421 client->priority, client->ctx_index, client->proc_desc_offset); 2422 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n", 2423 client->doorbell_id, client->doorbell_offset, client->cookie); 2424 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n", 2425 client->wq_size, client->wq_offset, client->wq_tail); 2426 2427 seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space); 2428 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail); 2429 seq_printf(m, "\tLast submission result: %d\n", client->retcode); 2430 2431 for_each_engine(engine, dev_priv, id) { 2432 u64 submissions = client->submissions[id]; 2433 tot += submissions; 2434 seq_printf(m, "\tSubmissions: %llu %s\n", 2435 submissions, engine->name); 2436 } 2437 seq_printf(m, "\tTotal: %llu\n", tot); 2438 } 2439 2440 static int i915_guc_info(struct seq_file *m, void *data) 2441 { 2442 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2443 struct drm_device *dev = &dev_priv->drm; 2444 struct intel_guc guc; 2445 struct i915_guc_client client = {}; 2446 struct intel_engine_cs *engine; 2447 enum intel_engine_id id; 2448 u64 total = 0; 2449 2450 if (!HAS_GUC_SCHED(dev_priv)) 2451 return 0; 2452 2453 if (mutex_lock_interruptible(&dev->struct_mutex)) 2454 return 0; 2455 2456 /* Take a local copy of the GuC data, so we can dump it at leisure */ 2457 guc = dev_priv->guc; 2458 if (guc.execbuf_client) 2459 client = *guc.execbuf_client; 2460 2461 mutex_unlock(&dev->struct_mutex); 2462 2463 seq_printf(m, "Doorbell map:\n"); 2464 seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap); 2465 seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline); 2466 2467 seq_printf(m, "GuC total action count: %llu\n", guc.action_count); 2468 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail); 2469 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd); 2470 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status); 2471 seq_printf(m, "GuC last action error code: %d\n", guc.action_err); 2472 2473 seq_printf(m, "\nGuC submissions:\n"); 2474 for_each_engine(engine, dev_priv, id) { 2475 u64 submissions = guc.submissions[id]; 2476 total += submissions; 2477 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n", 2478 engine->name, submissions, guc.last_seqno[id]); 2479 } 2480 seq_printf(m, "\t%s: %llu\n", "Total", total); 2481 2482 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client); 2483 i915_guc_client_info(m, dev_priv, &client); 2484 2485 /* Add more as required ... */ 2486 2487 return 0; 2488 } 2489 2490 static int i915_guc_log_dump(struct seq_file *m, void *data) 2491 { 2492 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2493 struct drm_i915_gem_object *obj; 2494 int i = 0, pg; 2495 2496 if (!dev_priv->guc.log_vma) 2497 return 0; 2498 2499 obj = dev_priv->guc.log_vma->obj; 2500 for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) { 2501 u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg)); 2502 2503 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4) 2504 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", 2505 *(log + i), *(log + i + 1), 2506 *(log + i + 2), *(log + i + 3)); 2507 2508 kunmap_atomic(log); 2509 } 2510 2511 seq_putc(m, '\n'); 2512 2513 return 0; 2514 } 2515 2516 static int i915_edp_psr_status(struct seq_file *m, void *data) 2517 { 2518 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2519 u32 psrperf = 0; 2520 u32 stat[3]; 2521 enum pipe pipe; 2522 bool enabled = false; 2523 2524 if (!HAS_PSR(dev_priv)) { 2525 seq_puts(m, "PSR not supported\n"); 2526 return 0; 2527 } 2528 2529 intel_runtime_pm_get(dev_priv); 2530 2531 mutex_lock(&dev_priv->psr.lock); 2532 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); 2533 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); 2534 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); 2535 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); 2536 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", 2537 dev_priv->psr.busy_frontbuffer_bits); 2538 seq_printf(m, "Re-enable work scheduled: %s\n", 2539 yesno(work_busy(&dev_priv->psr.work.work))); 2540 2541 if (HAS_DDI(dev_priv)) 2542 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; 2543 else { 2544 for_each_pipe(dev_priv, pipe) { 2545 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & 2546 VLV_EDP_PSR_CURR_STATE_MASK; 2547 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || 2548 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) 2549 enabled = true; 2550 } 2551 } 2552 2553 seq_printf(m, "Main link in standby mode: %s\n", 2554 yesno(dev_priv->psr.link_standby)); 2555 2556 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); 2557 2558 if (!HAS_DDI(dev_priv)) 2559 for_each_pipe(dev_priv, pipe) { 2560 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || 2561 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) 2562 seq_printf(m, " pipe %c", pipe_name(pipe)); 2563 } 2564 seq_puts(m, "\n"); 2565 2566 /* 2567 * VLV/CHV PSR has no kind of performance counter 2568 * SKL+ Perf counter is reset to 0 everytime DC state is entered 2569 */ 2570 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 2571 psrperf = I915_READ(EDP_PSR_PERF_CNT) & 2572 EDP_PSR_PERF_CNT_MASK; 2573 2574 seq_printf(m, "Performance_Counter: %u\n", psrperf); 2575 } 2576 mutex_unlock(&dev_priv->psr.lock); 2577 2578 intel_runtime_pm_put(dev_priv); 2579 return 0; 2580 } 2581 2582 static int i915_sink_crc(struct seq_file *m, void *data) 2583 { 2584 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2585 struct drm_device *dev = &dev_priv->drm; 2586 struct intel_connector *connector; 2587 struct intel_dp *intel_dp = NULL; 2588 int ret; 2589 u8 crc[6]; 2590 2591 drm_modeset_lock_all(dev); 2592 for_each_intel_connector(dev, connector) { 2593 struct drm_crtc *crtc; 2594 2595 if (!connector->base.state->best_encoder) 2596 continue; 2597 2598 crtc = connector->base.state->crtc; 2599 if (!crtc->state->active) 2600 continue; 2601 2602 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) 2603 continue; 2604 2605 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder); 2606 2607 ret = intel_dp_sink_crc(intel_dp, crc); 2608 if (ret) 2609 goto out; 2610 2611 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", 2612 crc[0], crc[1], crc[2], 2613 crc[3], crc[4], crc[5]); 2614 goto out; 2615 } 2616 ret = -ENODEV; 2617 out: 2618 drm_modeset_unlock_all(dev); 2619 return ret; 2620 } 2621 2622 static int i915_energy_uJ(struct seq_file *m, void *data) 2623 { 2624 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2625 u64 power; 2626 u32 units; 2627 2628 if (INTEL_GEN(dev_priv) < 6) 2629 return -ENODEV; 2630 2631 intel_runtime_pm_get(dev_priv); 2632 2633 rdmsrl(MSR_RAPL_POWER_UNIT, power); 2634 power = (power & 0x1f00) >> 8; 2635 units = 1000000 / (1 << power); /* convert to uJ */ 2636 power = I915_READ(MCH_SECP_NRG_STTS); 2637 power *= units; 2638 2639 intel_runtime_pm_put(dev_priv); 2640 2641 seq_printf(m, "%llu", (long long unsigned)power); 2642 2643 return 0; 2644 } 2645 2646 static int i915_runtime_pm_status(struct seq_file *m, void *unused) 2647 { 2648 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2649 struct pci_dev *pdev = dev_priv->drm.pdev; 2650 2651 if (!HAS_RUNTIME_PM(dev_priv)) 2652 seq_puts(m, "Runtime power management not supported\n"); 2653 2654 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake)); 2655 seq_printf(m, "IRQs disabled: %s\n", 2656 yesno(!intel_irqs_enabled(dev_priv))); 2657 #ifdef CONFIG_PM 2658 seq_printf(m, "Usage count: %d\n", 2659 atomic_read(&dev_priv->drm.dev->power.usage_count)); 2660 #else 2661 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); 2662 #endif 2663 seq_printf(m, "PCI device power state: %s [%d]\n", 2664 pci_power_name(pdev->current_state), 2665 pdev->current_state); 2666 2667 return 0; 2668 } 2669 2670 static int i915_power_domain_info(struct seq_file *m, void *unused) 2671 { 2672 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2673 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2674 int i; 2675 2676 mutex_lock(&power_domains->lock); 2677 2678 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); 2679 for (i = 0; i < power_domains->power_well_count; i++) { 2680 struct i915_power_well *power_well; 2681 enum intel_display_power_domain power_domain; 2682 2683 power_well = &power_domains->power_wells[i]; 2684 seq_printf(m, "%-25s %d\n", power_well->name, 2685 power_well->count); 2686 2687 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; 2688 power_domain++) { 2689 if (!(BIT(power_domain) & power_well->domains)) 2690 continue; 2691 2692 seq_printf(m, " %-23s %d\n", 2693 intel_display_power_domain_str(power_domain), 2694 power_domains->domain_use_count[power_domain]); 2695 } 2696 } 2697 2698 mutex_unlock(&power_domains->lock); 2699 2700 return 0; 2701 } 2702 2703 static int i915_dmc_info(struct seq_file *m, void *unused) 2704 { 2705 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2706 struct intel_csr *csr; 2707 2708 if (!HAS_CSR(dev_priv)) { 2709 seq_puts(m, "not supported\n"); 2710 return 0; 2711 } 2712 2713 csr = &dev_priv->csr; 2714 2715 intel_runtime_pm_get(dev_priv); 2716 2717 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); 2718 seq_printf(m, "path: %s\n", csr->fw_path); 2719 2720 if (!csr->dmc_payload) 2721 goto out; 2722 2723 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), 2724 CSR_VERSION_MINOR(csr->version)); 2725 2726 if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) { 2727 seq_printf(m, "DC3 -> DC5 count: %d\n", 2728 I915_READ(SKL_CSR_DC3_DC5_COUNT)); 2729 seq_printf(m, "DC5 -> DC6 count: %d\n", 2730 I915_READ(SKL_CSR_DC5_DC6_COUNT)); 2731 } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) { 2732 seq_printf(m, "DC3 -> DC5 count: %d\n", 2733 I915_READ(BXT_CSR_DC3_DC5_COUNT)); 2734 } 2735 2736 out: 2737 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); 2738 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); 2739 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); 2740 2741 intel_runtime_pm_put(dev_priv); 2742 2743 return 0; 2744 } 2745 2746 static void intel_seq_print_mode(struct seq_file *m, int tabs, 2747 struct drm_display_mode *mode) 2748 { 2749 int i; 2750 2751 for (i = 0; i < tabs; i++) 2752 seq_putc(m, '\t'); 2753 2754 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", 2755 mode->base.id, mode->name, 2756 mode->vrefresh, mode->clock, 2757 mode->hdisplay, mode->hsync_start, 2758 mode->hsync_end, mode->htotal, 2759 mode->vdisplay, mode->vsync_start, 2760 mode->vsync_end, mode->vtotal, 2761 mode->type, mode->flags); 2762 } 2763 2764 static void intel_encoder_info(struct seq_file *m, 2765 struct intel_crtc *intel_crtc, 2766 struct intel_encoder *intel_encoder) 2767 { 2768 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2769 struct drm_device *dev = &dev_priv->drm; 2770 struct drm_crtc *crtc = &intel_crtc->base; 2771 struct intel_connector *intel_connector; 2772 struct drm_encoder *encoder; 2773 2774 encoder = &intel_encoder->base; 2775 seq_printf(m, "\tencoder %d: type: %s, connectors:\n", 2776 encoder->base.id, encoder->name); 2777 for_each_connector_on_encoder(dev, encoder, intel_connector) { 2778 struct drm_connector *connector = &intel_connector->base; 2779 seq_printf(m, "\t\tconnector %d: type: %s, status: %s", 2780 connector->base.id, 2781 connector->name, 2782 drm_get_connector_status_name(connector->status)); 2783 if (connector->status == connector_status_connected) { 2784 struct drm_display_mode *mode = &crtc->mode; 2785 seq_printf(m, ", mode:\n"); 2786 intel_seq_print_mode(m, 2, mode); 2787 } else { 2788 seq_putc(m, '\n'); 2789 } 2790 } 2791 } 2792 2793 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) 2794 { 2795 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2796 struct drm_device *dev = &dev_priv->drm; 2797 struct drm_crtc *crtc = &intel_crtc->base; 2798 struct intel_encoder *intel_encoder; 2799 struct drm_plane_state *plane_state = crtc->primary->state; 2800 struct drm_framebuffer *fb = plane_state->fb; 2801 2802 if (fb) 2803 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", 2804 fb->base.id, plane_state->src_x >> 16, 2805 plane_state->src_y >> 16, fb->width, fb->height); 2806 else 2807 seq_puts(m, "\tprimary plane disabled\n"); 2808 for_each_encoder_on_crtc(dev, crtc, intel_encoder) 2809 intel_encoder_info(m, intel_crtc, intel_encoder); 2810 } 2811 2812 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) 2813 { 2814 struct drm_display_mode *mode = panel->fixed_mode; 2815 2816 seq_printf(m, "\tfixed mode:\n"); 2817 intel_seq_print_mode(m, 2, mode); 2818 } 2819 2820 static void intel_dp_info(struct seq_file *m, 2821 struct intel_connector *intel_connector) 2822 { 2823 struct intel_encoder *intel_encoder = intel_connector->encoder; 2824 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 2825 2826 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); 2827 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); 2828 if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) 2829 intel_panel_info(m, &intel_connector->panel); 2830 2831 drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports, 2832 &intel_dp->aux); 2833 } 2834 2835 static void intel_hdmi_info(struct seq_file *m, 2836 struct intel_connector *intel_connector) 2837 { 2838 struct intel_encoder *intel_encoder = intel_connector->encoder; 2839 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); 2840 2841 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); 2842 } 2843 2844 static void intel_lvds_info(struct seq_file *m, 2845 struct intel_connector *intel_connector) 2846 { 2847 intel_panel_info(m, &intel_connector->panel); 2848 } 2849 2850 static void intel_connector_info(struct seq_file *m, 2851 struct drm_connector *connector) 2852 { 2853 struct intel_connector *intel_connector = to_intel_connector(connector); 2854 struct intel_encoder *intel_encoder = intel_connector->encoder; 2855 struct drm_display_mode *mode; 2856 2857 seq_printf(m, "connector %d: type %s, status: %s\n", 2858 connector->base.id, connector->name, 2859 drm_get_connector_status_name(connector->status)); 2860 if (connector->status == connector_status_connected) { 2861 seq_printf(m, "\tname: %s\n", connector->display_info.name); 2862 seq_printf(m, "\tphysical dimensions: %dx%dmm\n", 2863 connector->display_info.width_mm, 2864 connector->display_info.height_mm); 2865 seq_printf(m, "\tsubpixel order: %s\n", 2866 drm_get_subpixel_order_name(connector->display_info.subpixel_order)); 2867 seq_printf(m, "\tCEA rev: %d\n", 2868 connector->display_info.cea_rev); 2869 } 2870 2871 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) 2872 return; 2873 2874 switch (connector->connector_type) { 2875 case DRM_MODE_CONNECTOR_DisplayPort: 2876 case DRM_MODE_CONNECTOR_eDP: 2877 intel_dp_info(m, intel_connector); 2878 break; 2879 case DRM_MODE_CONNECTOR_LVDS: 2880 if (intel_encoder->type == INTEL_OUTPUT_LVDS) 2881 intel_lvds_info(m, intel_connector); 2882 break; 2883 case DRM_MODE_CONNECTOR_HDMIA: 2884 if (intel_encoder->type == INTEL_OUTPUT_HDMI || 2885 intel_encoder->type == INTEL_OUTPUT_UNKNOWN) 2886 intel_hdmi_info(m, intel_connector); 2887 break; 2888 default: 2889 break; 2890 } 2891 2892 seq_printf(m, "\tmodes:\n"); 2893 list_for_each_entry(mode, &connector->modes, head) 2894 intel_seq_print_mode(m, 2, mode); 2895 } 2896 2897 static bool cursor_active(struct drm_i915_private *dev_priv, int pipe) 2898 { 2899 u32 state; 2900 2901 if (IS_845G(dev_priv) || IS_I865G(dev_priv)) 2902 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; 2903 else 2904 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; 2905 2906 return state; 2907 } 2908 2909 static bool cursor_position(struct drm_i915_private *dev_priv, 2910 int pipe, int *x, int *y) 2911 { 2912 u32 pos; 2913 2914 pos = I915_READ(CURPOS(pipe)); 2915 2916 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; 2917 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) 2918 *x = -*x; 2919 2920 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; 2921 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) 2922 *y = -*y; 2923 2924 return cursor_active(dev_priv, pipe); 2925 } 2926 2927 static const char *plane_type(enum drm_plane_type type) 2928 { 2929 switch (type) { 2930 case DRM_PLANE_TYPE_OVERLAY: 2931 return "OVL"; 2932 case DRM_PLANE_TYPE_PRIMARY: 2933 return "PRI"; 2934 case DRM_PLANE_TYPE_CURSOR: 2935 return "CUR"; 2936 /* 2937 * Deliberately omitting default: to generate compiler warnings 2938 * when a new drm_plane_type gets added. 2939 */ 2940 } 2941 2942 return "unknown"; 2943 } 2944 2945 static const char *plane_rotation(unsigned int rotation) 2946 { 2947 static char buf[48]; 2948 /* 2949 * According to doc only one DRM_ROTATE_ is allowed but this 2950 * will print them all to visualize if the values are misused 2951 */ 2952 snprintf(buf, sizeof(buf), 2953 "%s%s%s%s%s%s(0x%08x)", 2954 (rotation & DRM_ROTATE_0) ? "0 " : "", 2955 (rotation & DRM_ROTATE_90) ? "90 " : "", 2956 (rotation & DRM_ROTATE_180) ? "180 " : "", 2957 (rotation & DRM_ROTATE_270) ? "270 " : "", 2958 (rotation & DRM_REFLECT_X) ? "FLIPX " : "", 2959 (rotation & DRM_REFLECT_Y) ? "FLIPY " : "", 2960 rotation); 2961 2962 return buf; 2963 } 2964 2965 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc) 2966 { 2967 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2968 struct drm_device *dev = &dev_priv->drm; 2969 struct intel_plane *intel_plane; 2970 2971 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { 2972 struct drm_plane_state *state; 2973 struct drm_plane *plane = &intel_plane->base; 2974 char *format_name; 2975 2976 if (!plane->state) { 2977 seq_puts(m, "plane->state is NULL!\n"); 2978 continue; 2979 } 2980 2981 state = plane->state; 2982 2983 if (state->fb) { 2984 format_name = drm_get_format_name(state->fb->pixel_format); 2985 } else { 2986 format_name = kstrdup("N/A", GFP_KERNEL); 2987 } 2988 2989 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n", 2990 plane->base.id, 2991 plane_type(intel_plane->base.type), 2992 state->crtc_x, state->crtc_y, 2993 state->crtc_w, state->crtc_h, 2994 (state->src_x >> 16), 2995 ((state->src_x & 0xffff) * 15625) >> 10, 2996 (state->src_y >> 16), 2997 ((state->src_y & 0xffff) * 15625) >> 10, 2998 (state->src_w >> 16), 2999 ((state->src_w & 0xffff) * 15625) >> 10, 3000 (state->src_h >> 16), 3001 ((state->src_h & 0xffff) * 15625) >> 10, 3002 format_name, 3003 plane_rotation(state->rotation)); 3004 3005 kfree(format_name); 3006 } 3007 } 3008 3009 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc) 3010 { 3011 struct intel_crtc_state *pipe_config; 3012 int num_scalers = intel_crtc->num_scalers; 3013 int i; 3014 3015 pipe_config = to_intel_crtc_state(intel_crtc->base.state); 3016 3017 /* Not all platformas have a scaler */ 3018 if (num_scalers) { 3019 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", 3020 num_scalers, 3021 pipe_config->scaler_state.scaler_users, 3022 pipe_config->scaler_state.scaler_id); 3023 3024 for (i = 0; i < SKL_NUM_SCALERS; i++) { 3025 struct intel_scaler *sc = 3026 &pipe_config->scaler_state.scalers[i]; 3027 3028 seq_printf(m, ", scalers[%d]: use=%s, mode=%x", 3029 i, yesno(sc->in_use), sc->mode); 3030 } 3031 seq_puts(m, "\n"); 3032 } else { 3033 seq_puts(m, "\tNo scalers available on this platform\n"); 3034 } 3035 } 3036 3037 static int i915_display_info(struct seq_file *m, void *unused) 3038 { 3039 struct drm_i915_private *dev_priv = node_to_i915(m->private); 3040 struct drm_device *dev = &dev_priv->drm; 3041 struct intel_crtc *crtc; 3042 struct drm_connector *connector; 3043 3044 intel_runtime_pm_get(dev_priv); 3045 drm_modeset_lock_all(dev); 3046 seq_printf(m, "CRTC info\n"); 3047 seq_printf(m, "---------\n"); 3048 for_each_intel_crtc(dev, crtc) { 3049 bool active; 3050 struct intel_crtc_state *pipe_config; 3051 int x, y; 3052 3053 pipe_config = to_intel_crtc_state(crtc->base.state); 3054 3055 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", 3056 crtc->base.base.id, pipe_name(crtc->pipe), 3057 yesno(pipe_config->base.active), 3058 pipe_config->pipe_src_w, pipe_config->pipe_src_h, 3059 yesno(pipe_config->dither), pipe_config->pipe_bpp); 3060 3061 if (pipe_config->base.active) { 3062 intel_crtc_info(m, crtc); 3063 3064 active = cursor_position(dev_priv, crtc->pipe, &x, &y); 3065 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", 3066 yesno(crtc->cursor_base), 3067 x, y, crtc->base.cursor->state->crtc_w, 3068 crtc->base.cursor->state->crtc_h, 3069 crtc->cursor_addr, yesno(active)); 3070 intel_scaler_info(m, crtc); 3071 intel_plane_info(m, crtc); 3072 } 3073 3074 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", 3075 yesno(!crtc->cpu_fifo_underrun_disabled), 3076 yesno(!crtc->pch_fifo_underrun_disabled)); 3077 } 3078 3079 seq_printf(m, "\n"); 3080 seq_printf(m, "Connector info\n"); 3081 seq_printf(m, "--------------\n"); 3082 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 3083 intel_connector_info(m, connector); 3084 } 3085 drm_modeset_unlock_all(dev); 3086 intel_runtime_pm_put(dev_priv); 3087 3088 return 0; 3089 } 3090 3091 static int i915_engine_info(struct seq_file *m, void *unused) 3092 { 3093 struct drm_i915_private *dev_priv = node_to_i915(m->private); 3094 struct intel_engine_cs *engine; 3095 enum intel_engine_id id; 3096 3097 for_each_engine(engine, dev_priv, id) { 3098 struct intel_breadcrumbs *b = &engine->breadcrumbs; 3099 struct drm_i915_gem_request *rq; 3100 struct rb_node *rb; 3101 u64 addr; 3102 3103 seq_printf(m, "%s\n", engine->name); 3104 seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [score %d]\n", 3105 intel_engine_get_seqno(engine), 3106 engine->last_submitted_seqno, 3107 engine->hangcheck.seqno, 3108 engine->hangcheck.score); 3109 3110 rcu_read_lock(); 3111 3112 seq_printf(m, "\tRequests:\n"); 3113 3114 rq = list_first_entry(&engine->request_list, 3115 struct drm_i915_gem_request, link); 3116 if (&rq->link != &engine->request_list) 3117 print_request(m, rq, "\t\tfirst "); 3118 3119 rq = list_last_entry(&engine->request_list, 3120 struct drm_i915_gem_request, link); 3121 if (&rq->link != &engine->request_list) 3122 print_request(m, rq, "\t\tlast "); 3123 3124 rq = i915_gem_find_active_request(engine); 3125 if (rq) { 3126 print_request(m, rq, "\t\tactive "); 3127 seq_printf(m, 3128 "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n", 3129 rq->head, rq->postfix, rq->tail, 3130 rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u, 3131 rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u); 3132 } 3133 3134 seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n", 3135 I915_READ(RING_START(engine->mmio_base)), 3136 rq ? i915_ggtt_offset(rq->ring->vma) : 0); 3137 seq_printf(m, "\tRING_HEAD: 0x%08x [0x%08x]\n", 3138 I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR, 3139 rq ? rq->ring->head : 0); 3140 seq_printf(m, "\tRING_TAIL: 0x%08x [0x%08x]\n", 3141 I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR, 3142 rq ? rq->ring->tail : 0); 3143 seq_printf(m, "\tRING_CTL: 0x%08x [%s]\n", 3144 I915_READ(RING_CTL(engine->mmio_base)), 3145 I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : ""); 3146 3147 rcu_read_unlock(); 3148 3149 addr = intel_engine_get_active_head(engine); 3150 seq_printf(m, "\tACTHD: 0x%08x_%08x\n", 3151 upper_32_bits(addr), lower_32_bits(addr)); 3152 addr = intel_engine_get_last_batch_head(engine); 3153 seq_printf(m, "\tBBADDR: 0x%08x_%08x\n", 3154 upper_32_bits(addr), lower_32_bits(addr)); 3155 3156 if (i915.enable_execlists) { 3157 u32 ptr, read, write; 3158 3159 seq_printf(m, "\tExeclist status: 0x%08x %08x\n", 3160 I915_READ(RING_EXECLIST_STATUS_LO(engine)), 3161 I915_READ(RING_EXECLIST_STATUS_HI(engine))); 3162 3163 ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine)); 3164 read = GEN8_CSB_READ_PTR(ptr); 3165 write = GEN8_CSB_WRITE_PTR(ptr); 3166 seq_printf(m, "\tExeclist CSB read %d, write %d\n", 3167 read, write); 3168 if (read >= GEN8_CSB_ENTRIES) 3169 read = 0; 3170 if (write >= GEN8_CSB_ENTRIES) 3171 write = 0; 3172 if (read > write) 3173 write += GEN8_CSB_ENTRIES; 3174 while (read < write) { 3175 unsigned int idx = ++read % GEN8_CSB_ENTRIES; 3176 3177 seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n", 3178 idx, 3179 I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)), 3180 I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx))); 3181 } 3182 3183 rcu_read_lock(); 3184 rq = READ_ONCE(engine->execlist_port[0].request); 3185 if (rq) 3186 print_request(m, rq, "\t\tELSP[0] "); 3187 else 3188 seq_printf(m, "\t\tELSP[0] idle\n"); 3189 rq = READ_ONCE(engine->execlist_port[1].request); 3190 if (rq) 3191 print_request(m, rq, "\t\tELSP[1] "); 3192 else 3193 seq_printf(m, "\t\tELSP[1] idle\n"); 3194 rcu_read_unlock(); 3195 } else if (INTEL_GEN(dev_priv) > 6) { 3196 seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n", 3197 I915_READ(RING_PP_DIR_BASE(engine))); 3198 seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n", 3199 I915_READ(RING_PP_DIR_BASE_READ(engine))); 3200 seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n", 3201 I915_READ(RING_PP_DIR_DCLV(engine))); 3202 } 3203 3204 spin_lock(&b->lock); 3205 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { 3206 struct intel_wait *w = container_of(rb, typeof(*w), node); 3207 3208 seq_printf(m, "\t%s [%d] waiting for %x\n", 3209 w->tsk->comm, w->tsk->pid, w->seqno); 3210 } 3211 spin_unlock(&b->lock); 3212 3213 seq_puts(m, "\n"); 3214 } 3215 3216 return 0; 3217 } 3218 3219 static int i915_semaphore_status(struct seq_file *m, void *unused) 3220 { 3221 struct drm_i915_private *dev_priv = node_to_i915(m->private); 3222 struct drm_device *dev = &dev_priv->drm; 3223 struct intel_engine_cs *engine; 3224 int num_rings = INTEL_INFO(dev_priv)->num_rings; 3225 enum intel_engine_id id; 3226 int j, ret; 3227 3228 if (!i915.semaphores) { 3229 seq_puts(m, "Semaphores are disabled\n"); 3230 return 0; 3231 } 3232 3233 ret = mutex_lock_interruptible(&dev->struct_mutex); 3234 if (ret) 3235 return ret; 3236 intel_runtime_pm_get(dev_priv); 3237 3238 if (IS_BROADWELL(dev_priv)) { 3239 struct page *page; 3240 uint64_t *seqno; 3241 3242 page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0); 3243 3244 seqno = (uint64_t *)kmap_atomic(page); 3245 for_each_engine(engine, dev_priv, id) { 3246 uint64_t offset; 3247 3248 seq_printf(m, "%s\n", engine->name); 3249 3250 seq_puts(m, " Last signal:"); 3251 for (j = 0; j < num_rings; j++) { 3252 offset = id * I915_NUM_ENGINES + j; 3253 seq_printf(m, "0x%08llx (0x%02llx) ", 3254 seqno[offset], offset * 8); 3255 } 3256 seq_putc(m, '\n'); 3257 3258 seq_puts(m, " Last wait: "); 3259 for (j = 0; j < num_rings; j++) { 3260 offset = id + (j * I915_NUM_ENGINES); 3261 seq_printf(m, "0x%08llx (0x%02llx) ", 3262 seqno[offset], offset * 8); 3263 } 3264 seq_putc(m, '\n'); 3265 3266 } 3267 kunmap_atomic(seqno); 3268 } else { 3269 seq_puts(m, " Last signal:"); 3270 for_each_engine(engine, dev_priv, id) 3271 for (j = 0; j < num_rings; j++) 3272 seq_printf(m, "0x%08x\n", 3273 I915_READ(engine->semaphore.mbox.signal[j])); 3274 seq_putc(m, '\n'); 3275 } 3276 3277 seq_puts(m, "\nSync seqno:\n"); 3278 for_each_engine(engine, dev_priv, id) { 3279 for (j = 0; j < num_rings; j++) 3280 seq_printf(m, " 0x%08x ", 3281 engine->semaphore.sync_seqno[j]); 3282 seq_putc(m, '\n'); 3283 } 3284 seq_putc(m, '\n'); 3285 3286 intel_runtime_pm_put(dev_priv); 3287 mutex_unlock(&dev->struct_mutex); 3288 return 0; 3289 } 3290 3291 static int i915_shared_dplls_info(struct seq_file *m, void *unused) 3292 { 3293 struct drm_i915_private *dev_priv = node_to_i915(m->private); 3294 struct drm_device *dev = &dev_priv->drm; 3295 int i; 3296 3297 drm_modeset_lock_all(dev); 3298 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 3299 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; 3300 3301 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); 3302 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", 3303 pll->config.crtc_mask, pll->active_mask, yesno(pll->on)); 3304 seq_printf(m, " tracked hardware state:\n"); 3305 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll); 3306 seq_printf(m, " dpll_md: 0x%08x\n", 3307 pll->config.hw_state.dpll_md); 3308 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0); 3309 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1); 3310 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll); 3311 } 3312 drm_modeset_unlock_all(dev); 3313 3314 return 0; 3315 } 3316 3317 static int i915_wa_registers(struct seq_file *m, void *unused) 3318 { 3319 int i; 3320 int ret; 3321 struct intel_engine_cs *engine; 3322 struct drm_i915_private *dev_priv = node_to_i915(m->private); 3323 struct drm_device *dev = &dev_priv->drm; 3324 struct i915_workarounds *workarounds = &dev_priv->workarounds; 3325 enum intel_engine_id id; 3326 3327 ret = mutex_lock_interruptible(&dev->struct_mutex); 3328 if (ret) 3329 return ret; 3330 3331 intel_runtime_pm_get(dev_priv); 3332 3333 seq_printf(m, "Workarounds applied: %d\n", workarounds->count); 3334 for_each_engine(engine, dev_priv, id) 3335 seq_printf(m, "HW whitelist count for %s: %d\n", 3336 engine->name, workarounds->hw_whitelist_count[id]); 3337 for (i = 0; i < workarounds->count; ++i) { 3338 i915_reg_t addr; 3339 u32 mask, value, read; 3340 bool ok; 3341 3342 addr = workarounds->reg[i].addr; 3343 mask = workarounds->reg[i].mask; 3344 value = workarounds->reg[i].value; 3345 read = I915_READ(addr); 3346 ok = (value & mask) == (read & mask); 3347 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", 3348 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); 3349 } 3350 3351 intel_runtime_pm_put(dev_priv); 3352 mutex_unlock(&dev->struct_mutex); 3353 3354 return 0; 3355 } 3356 3357 static int i915_ddb_info(struct seq_file *m, void *unused) 3358 { 3359 struct drm_i915_private *dev_priv = node_to_i915(m->private); 3360 struct drm_device *dev = &dev_priv->drm; 3361 struct skl_ddb_allocation *ddb; 3362 struct skl_ddb_entry *entry; 3363 enum pipe pipe; 3364 int plane; 3365 3366 if (INTEL_GEN(dev_priv) < 9) 3367 return 0; 3368 3369 drm_modeset_lock_all(dev); 3370 3371 ddb = &dev_priv->wm.skl_hw.ddb; 3372 3373 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); 3374 3375 for_each_pipe(dev_priv, pipe) { 3376 seq_printf(m, "Pipe %c\n", pipe_name(pipe)); 3377 3378 for_each_plane(dev_priv, pipe, plane) { 3379 entry = &ddb->plane[pipe][plane]; 3380 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, 3381 entry->start, entry->end, 3382 skl_ddb_entry_size(entry)); 3383 } 3384 3385 entry = &ddb->plane[pipe][PLANE_CURSOR]; 3386 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, 3387 entry->end, skl_ddb_entry_size(entry)); 3388 } 3389 3390 drm_modeset_unlock_all(dev); 3391 3392 return 0; 3393 } 3394 3395 static void drrs_status_per_crtc(struct seq_file *m, 3396 struct drm_device *dev, 3397 struct intel_crtc *intel_crtc) 3398 { 3399 struct drm_i915_private *dev_priv = to_i915(dev); 3400 struct i915_drrs *drrs = &dev_priv->drrs; 3401 int vrefresh = 0; 3402 struct drm_connector *connector; 3403 3404 drm_for_each_connector(connector, dev) { 3405 if (connector->state->crtc != &intel_crtc->base) 3406 continue; 3407 3408 seq_printf(m, "%s:\n", connector->name); 3409 } 3410 3411 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) 3412 seq_puts(m, "\tVBT: DRRS_type: Static"); 3413 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) 3414 seq_puts(m, "\tVBT: DRRS_type: Seamless"); 3415 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) 3416 seq_puts(m, "\tVBT: DRRS_type: None"); 3417 else 3418 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); 3419 3420 seq_puts(m, "\n\n"); 3421 3422 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { 3423 struct intel_panel *panel; 3424 3425 mutex_lock(&drrs->mutex); 3426 /* DRRS Supported */ 3427 seq_puts(m, "\tDRRS Supported: Yes\n"); 3428 3429 /* disable_drrs() will make drrs->dp NULL */ 3430 if (!drrs->dp) { 3431 seq_puts(m, "Idleness DRRS: Disabled"); 3432 mutex_unlock(&drrs->mutex); 3433 return; 3434 } 3435 3436 panel = &drrs->dp->attached_connector->panel; 3437 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", 3438 drrs->busy_frontbuffer_bits); 3439 3440 seq_puts(m, "\n\t\t"); 3441 if (drrs->refresh_rate_type == DRRS_HIGH_RR) { 3442 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); 3443 vrefresh = panel->fixed_mode->vrefresh; 3444 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { 3445 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); 3446 vrefresh = panel->downclock_mode->vrefresh; 3447 } else { 3448 seq_printf(m, "DRRS_State: Unknown(%d)\n", 3449 drrs->refresh_rate_type); 3450 mutex_unlock(&drrs->mutex); 3451 return; 3452 } 3453 seq_printf(m, "\t\tVrefresh: %d", vrefresh); 3454 3455 seq_puts(m, "\n\t\t"); 3456 mutex_unlock(&drrs->mutex); 3457 } else { 3458 /* DRRS not supported. Print the VBT parameter*/ 3459 seq_puts(m, "\tDRRS Supported : No"); 3460 } 3461 seq_puts(m, "\n"); 3462 } 3463 3464 static int i915_drrs_status(struct seq_file *m, void *unused) 3465 { 3466 struct drm_i915_private *dev_priv = node_to_i915(m->private); 3467 struct drm_device *dev = &dev_priv->drm; 3468 struct intel_crtc *intel_crtc; 3469 int active_crtc_cnt = 0; 3470 3471 drm_modeset_lock_all(dev); 3472 for_each_intel_crtc(dev, intel_crtc) { 3473 if (intel_crtc->base.state->active) { 3474 active_crtc_cnt++; 3475 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); 3476 3477 drrs_status_per_crtc(m, dev, intel_crtc); 3478 } 3479 } 3480 drm_modeset_unlock_all(dev); 3481 3482 if (!active_crtc_cnt) 3483 seq_puts(m, "No active crtc found\n"); 3484 3485 return 0; 3486 } 3487 3488 struct pipe_crc_info { 3489 const char *name; 3490 struct drm_i915_private *dev_priv; 3491 enum pipe pipe; 3492 }; 3493 3494 static int i915_dp_mst_info(struct seq_file *m, void *unused) 3495 { 3496 struct drm_i915_private *dev_priv = node_to_i915(m->private); 3497 struct drm_device *dev = &dev_priv->drm; 3498 struct intel_encoder *intel_encoder; 3499 struct intel_digital_port *intel_dig_port; 3500 struct drm_connector *connector; 3501 3502 drm_modeset_lock_all(dev); 3503 drm_for_each_connector(connector, dev) { 3504 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 3505 continue; 3506 3507 intel_encoder = intel_attached_encoder(connector); 3508 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) 3509 continue; 3510 3511 intel_dig_port = enc_to_dig_port(&intel_encoder->base); 3512 if (!intel_dig_port->dp.can_mst) 3513 continue; 3514 3515 seq_printf(m, "MST Source Port %c\n", 3516 port_name(intel_dig_port->port)); 3517 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); 3518 } 3519 drm_modeset_unlock_all(dev); 3520 return 0; 3521 } 3522 3523 static int i915_pipe_crc_open(struct inode *inode, struct file *filep) 3524 { 3525 struct pipe_crc_info *info = inode->i_private; 3526 struct drm_i915_private *dev_priv = info->dev_priv; 3527 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; 3528 3529 if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes) 3530 return -ENODEV; 3531 3532 spin_lock_irq(&pipe_crc->lock); 3533 3534 if (pipe_crc->opened) { 3535 spin_unlock_irq(&pipe_crc->lock); 3536 return -EBUSY; /* already open */ 3537 } 3538 3539 pipe_crc->opened = true; 3540 filep->private_data = inode->i_private; 3541 3542 spin_unlock_irq(&pipe_crc->lock); 3543 3544 return 0; 3545 } 3546 3547 static int i915_pipe_crc_release(struct inode *inode, struct file *filep) 3548 { 3549 struct pipe_crc_info *info = inode->i_private; 3550 struct drm_i915_private *dev_priv = info->dev_priv; 3551 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; 3552 3553 spin_lock_irq(&pipe_crc->lock); 3554 pipe_crc->opened = false; 3555 spin_unlock_irq(&pipe_crc->lock); 3556 3557 return 0; 3558 } 3559 3560 /* (6 fields, 8 chars each, space separated (5) + '\n') */ 3561 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) 3562 /* account for \'0' */ 3563 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) 3564 3565 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) 3566 { 3567 assert_spin_locked(&pipe_crc->lock); 3568 return CIRC_CNT(pipe_crc->head, pipe_crc->tail, 3569 INTEL_PIPE_CRC_ENTRIES_NR); 3570 } 3571 3572 static ssize_t 3573 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, 3574 loff_t *pos) 3575 { 3576 struct pipe_crc_info *info = filep->private_data; 3577 struct drm_i915_private *dev_priv = info->dev_priv; 3578 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; 3579 char buf[PIPE_CRC_BUFFER_LEN]; 3580 int n_entries; 3581 ssize_t bytes_read; 3582 3583 /* 3584 * Don't allow user space to provide buffers not big enough to hold 3585 * a line of data. 3586 */ 3587 if (count < PIPE_CRC_LINE_LEN) 3588 return -EINVAL; 3589 3590 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) 3591 return 0; 3592 3593 /* nothing to read */ 3594 spin_lock_irq(&pipe_crc->lock); 3595 while (pipe_crc_data_count(pipe_crc) == 0) { 3596 int ret; 3597 3598 if (filep->f_flags & O_NONBLOCK) { 3599 spin_unlock_irq(&pipe_crc->lock); 3600 return -EAGAIN; 3601 } 3602 3603 ret = wait_event_interruptible_lock_irq(pipe_crc->wq, 3604 pipe_crc_data_count(pipe_crc), pipe_crc->lock); 3605 if (ret) { 3606 spin_unlock_irq(&pipe_crc->lock); 3607 return ret; 3608 } 3609 } 3610 3611 /* We now have one or more entries to read */ 3612 n_entries = count / PIPE_CRC_LINE_LEN; 3613 3614 bytes_read = 0; 3615 while (n_entries > 0) { 3616 struct intel_pipe_crc_entry *entry = 3617 &pipe_crc->entries[pipe_crc->tail]; 3618 3619 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail, 3620 INTEL_PIPE_CRC_ENTRIES_NR) < 1) 3621 break; 3622 3623 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); 3624 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); 3625 3626 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, 3627 "%8u %8x %8x %8x %8x %8x\n", 3628 entry->frame, entry->crc[0], 3629 entry->crc[1], entry->crc[2], 3630 entry->crc[3], entry->crc[4]); 3631 3632 spin_unlock_irq(&pipe_crc->lock); 3633 3634 if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN)) 3635 return -EFAULT; 3636 3637 user_buf += PIPE_CRC_LINE_LEN; 3638 n_entries--; 3639 3640 spin_lock_irq(&pipe_crc->lock); 3641 } 3642 3643 spin_unlock_irq(&pipe_crc->lock); 3644 3645 return bytes_read; 3646 } 3647 3648 static const struct file_operations i915_pipe_crc_fops = { 3649 .owner = THIS_MODULE, 3650 .open = i915_pipe_crc_open, 3651 .read = i915_pipe_crc_read, 3652 .release = i915_pipe_crc_release, 3653 }; 3654 3655 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { 3656 { 3657 .name = "i915_pipe_A_crc", 3658 .pipe = PIPE_A, 3659 }, 3660 { 3661 .name = "i915_pipe_B_crc", 3662 .pipe = PIPE_B, 3663 }, 3664 { 3665 .name = "i915_pipe_C_crc", 3666 .pipe = PIPE_C, 3667 }, 3668 }; 3669 3670 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, 3671 enum pipe pipe) 3672 { 3673 struct drm_i915_private *dev_priv = to_i915(minor->dev); 3674 struct dentry *ent; 3675 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; 3676 3677 info->dev_priv = dev_priv; 3678 ent = debugfs_create_file(info->name, S_IRUGO, root, info, 3679 &i915_pipe_crc_fops); 3680 if (!ent) 3681 return -ENOMEM; 3682 3683 return drm_add_fake_info_node(minor, ent, info); 3684 } 3685 3686 static const char * const pipe_crc_sources[] = { 3687 "none", 3688 "plane1", 3689 "plane2", 3690 "pf", 3691 "pipe", 3692 "TV", 3693 "DP-B", 3694 "DP-C", 3695 "DP-D", 3696 "auto", 3697 }; 3698 3699 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) 3700 { 3701 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); 3702 return pipe_crc_sources[source]; 3703 } 3704 3705 static int display_crc_ctl_show(struct seq_file *m, void *data) 3706 { 3707 struct drm_i915_private *dev_priv = m->private; 3708 int i; 3709 3710 for (i = 0; i < I915_MAX_PIPES; i++) 3711 seq_printf(m, "%c %s\n", pipe_name(i), 3712 pipe_crc_source_name(dev_priv->pipe_crc[i].source)); 3713 3714 return 0; 3715 } 3716 3717 static int display_crc_ctl_open(struct inode *inode, struct file *file) 3718 { 3719 return single_open(file, display_crc_ctl_show, inode->i_private); 3720 } 3721 3722 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, 3723 uint32_t *val) 3724 { 3725 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) 3726 *source = INTEL_PIPE_CRC_SOURCE_PIPE; 3727 3728 switch (*source) { 3729 case INTEL_PIPE_CRC_SOURCE_PIPE: 3730 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; 3731 break; 3732 case INTEL_PIPE_CRC_SOURCE_NONE: 3733 *val = 0; 3734 break; 3735 default: 3736 return -EINVAL; 3737 } 3738 3739 return 0; 3740 } 3741 3742 static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv, 3743 enum pipe pipe, 3744 enum intel_pipe_crc_source *source) 3745 { 3746 struct drm_device *dev = &dev_priv->drm; 3747 struct intel_encoder *encoder; 3748 struct intel_crtc *crtc; 3749 struct intel_digital_port *dig_port; 3750 int ret = 0; 3751 3752 *source = INTEL_PIPE_CRC_SOURCE_PIPE; 3753 3754 drm_modeset_lock_all(dev); 3755 for_each_intel_encoder(dev, encoder) { 3756 if (!encoder->base.crtc) 3757 continue; 3758 3759 crtc = to_intel_crtc(encoder->base.crtc); 3760 3761 if (crtc->pipe != pipe) 3762 continue; 3763 3764 switch (encoder->type) { 3765 case INTEL_OUTPUT_TVOUT: 3766 *source = INTEL_PIPE_CRC_SOURCE_TV; 3767 break; 3768 case INTEL_OUTPUT_DP: 3769 case INTEL_OUTPUT_EDP: 3770 dig_port = enc_to_dig_port(&encoder->base); 3771 switch (dig_port->port) { 3772 case PORT_B: 3773 *source = INTEL_PIPE_CRC_SOURCE_DP_B; 3774 break; 3775 case PORT_C: 3776 *source = INTEL_PIPE_CRC_SOURCE_DP_C; 3777 break; 3778 case PORT_D: 3779 *source = INTEL_PIPE_CRC_SOURCE_DP_D; 3780 break; 3781 default: 3782 WARN(1, "nonexisting DP port %c\n", 3783 port_name(dig_port->port)); 3784 break; 3785 } 3786 break; 3787 default: 3788 break; 3789 } 3790 } 3791 drm_modeset_unlock_all(dev); 3792 3793 return ret; 3794 } 3795 3796 static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, 3797 enum pipe pipe, 3798 enum intel_pipe_crc_source *source, 3799 uint32_t *val) 3800 { 3801 bool need_stable_symbols = false; 3802 3803 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { 3804 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source); 3805 if (ret) 3806 return ret; 3807 } 3808 3809 switch (*source) { 3810 case INTEL_PIPE_CRC_SOURCE_PIPE: 3811 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; 3812 break; 3813 case INTEL_PIPE_CRC_SOURCE_DP_B: 3814 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; 3815 need_stable_symbols = true; 3816 break; 3817 case INTEL_PIPE_CRC_SOURCE_DP_C: 3818 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; 3819 need_stable_symbols = true; 3820 break; 3821 case INTEL_PIPE_CRC_SOURCE_DP_D: 3822 if (!IS_CHERRYVIEW(dev_priv)) 3823 return -EINVAL; 3824 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; 3825 need_stable_symbols = true; 3826 break; 3827 case INTEL_PIPE_CRC_SOURCE_NONE: 3828 *val = 0; 3829 break; 3830 default: 3831 return -EINVAL; 3832 } 3833 3834 /* 3835 * When the pipe CRC tap point is after the transcoders we need 3836 * to tweak symbol-level features to produce a deterministic series of 3837 * symbols for a given frame. We need to reset those features only once 3838 * a frame (instead of every nth symbol): 3839 * - DC-balance: used to ensure a better clock recovery from the data 3840 * link (SDVO) 3841 * - DisplayPort scrambling: used for EMI reduction 3842 */ 3843 if (need_stable_symbols) { 3844 uint32_t tmp = I915_READ(PORT_DFT2_G4X); 3845 3846 tmp |= DC_BALANCE_RESET_VLV; 3847 switch (pipe) { 3848 case PIPE_A: 3849 tmp |= PIPE_A_SCRAMBLE_RESET; 3850 break; 3851 case PIPE_B: 3852 tmp |= PIPE_B_SCRAMBLE_RESET; 3853 break; 3854 case PIPE_C: 3855 tmp |= PIPE_C_SCRAMBLE_RESET; 3856 break; 3857 default: 3858 return -EINVAL; 3859 } 3860 I915_WRITE(PORT_DFT2_G4X, tmp); 3861 } 3862 3863 return 0; 3864 } 3865 3866 static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, 3867 enum pipe pipe, 3868 enum intel_pipe_crc_source *source, 3869 uint32_t *val) 3870 { 3871 bool need_stable_symbols = false; 3872 3873 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { 3874 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source); 3875 if (ret) 3876 return ret; 3877 } 3878 3879 switch (*source) { 3880 case INTEL_PIPE_CRC_SOURCE_PIPE: 3881 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; 3882 break; 3883 case INTEL_PIPE_CRC_SOURCE_TV: 3884 if (!SUPPORTS_TV(dev_priv)) 3885 return -EINVAL; 3886 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; 3887 break; 3888 case INTEL_PIPE_CRC_SOURCE_DP_B: 3889 if (!IS_G4X(dev_priv)) 3890 return -EINVAL; 3891 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; 3892 need_stable_symbols = true; 3893 break; 3894 case INTEL_PIPE_CRC_SOURCE_DP_C: 3895 if (!IS_G4X(dev_priv)) 3896 return -EINVAL; 3897 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; 3898 need_stable_symbols = true; 3899 break; 3900 case INTEL_PIPE_CRC_SOURCE_DP_D: 3901 if (!IS_G4X(dev_priv)) 3902 return -EINVAL; 3903 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; 3904 need_stable_symbols = true; 3905 break; 3906 case INTEL_PIPE_CRC_SOURCE_NONE: 3907 *val = 0; 3908 break; 3909 default: 3910 return -EINVAL; 3911 } 3912 3913 /* 3914 * When the pipe CRC tap point is after the transcoders we need 3915 * to tweak symbol-level features to produce a deterministic series of 3916 * symbols for a given frame. We need to reset those features only once 3917 * a frame (instead of every nth symbol): 3918 * - DC-balance: used to ensure a better clock recovery from the data 3919 * link (SDVO) 3920 * - DisplayPort scrambling: used for EMI reduction 3921 */ 3922 if (need_stable_symbols) { 3923 uint32_t tmp = I915_READ(PORT_DFT2_G4X); 3924 3925 WARN_ON(!IS_G4X(dev_priv)); 3926 3927 I915_WRITE(PORT_DFT_I9XX, 3928 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); 3929 3930 if (pipe == PIPE_A) 3931 tmp |= PIPE_A_SCRAMBLE_RESET; 3932 else 3933 tmp |= PIPE_B_SCRAMBLE_RESET; 3934 3935 I915_WRITE(PORT_DFT2_G4X, tmp); 3936 } 3937 3938 return 0; 3939 } 3940 3941 static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv, 3942 enum pipe pipe) 3943 { 3944 uint32_t tmp = I915_READ(PORT_DFT2_G4X); 3945 3946 switch (pipe) { 3947 case PIPE_A: 3948 tmp &= ~PIPE_A_SCRAMBLE_RESET; 3949 break; 3950 case PIPE_B: 3951 tmp &= ~PIPE_B_SCRAMBLE_RESET; 3952 break; 3953 case PIPE_C: 3954 tmp &= ~PIPE_C_SCRAMBLE_RESET; 3955 break; 3956 default: 3957 return; 3958 } 3959 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) 3960 tmp &= ~DC_BALANCE_RESET_VLV; 3961 I915_WRITE(PORT_DFT2_G4X, tmp); 3962 3963 } 3964 3965 static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv, 3966 enum pipe pipe) 3967 { 3968 uint32_t tmp = I915_READ(PORT_DFT2_G4X); 3969 3970 if (pipe == PIPE_A) 3971 tmp &= ~PIPE_A_SCRAMBLE_RESET; 3972 else 3973 tmp &= ~PIPE_B_SCRAMBLE_RESET; 3974 I915_WRITE(PORT_DFT2_G4X, tmp); 3975 3976 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { 3977 I915_WRITE(PORT_DFT_I9XX, 3978 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); 3979 } 3980 } 3981 3982 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, 3983 uint32_t *val) 3984 { 3985 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) 3986 *source = INTEL_PIPE_CRC_SOURCE_PIPE; 3987 3988 switch (*source) { 3989 case INTEL_PIPE_CRC_SOURCE_PLANE1: 3990 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; 3991 break; 3992 case INTEL_PIPE_CRC_SOURCE_PLANE2: 3993 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; 3994 break; 3995 case INTEL_PIPE_CRC_SOURCE_PIPE: 3996 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; 3997 break; 3998 case INTEL_PIPE_CRC_SOURCE_NONE: 3999 *val = 0; 4000 break; 4001 default: 4002 return -EINVAL; 4003 } 4004 4005 return 0; 4006 } 4007 4008 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv, 4009 bool enable) 4010 { 4011 struct drm_device *dev = &dev_priv->drm; 4012 struct intel_crtc *crtc = 4013 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); 4014 struct intel_crtc_state *pipe_config; 4015 struct drm_atomic_state *state; 4016 int ret = 0; 4017 4018 drm_modeset_lock_all(dev); 4019 state = drm_atomic_state_alloc(dev); 4020 if (!state) { 4021 ret = -ENOMEM; 4022 goto out; 4023 } 4024 4025 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base); 4026 pipe_config = intel_atomic_get_crtc_state(state, crtc); 4027 if (IS_ERR(pipe_config)) { 4028 ret = PTR_ERR(pipe_config); 4029 goto out; 4030 } 4031 4032 pipe_config->pch_pfit.force_thru = enable; 4033 if (pipe_config->cpu_transcoder == TRANSCODER_EDP && 4034 pipe_config->pch_pfit.enabled != enable) 4035 pipe_config->base.connectors_changed = true; 4036 4037 ret = drm_atomic_commit(state); 4038 out: 4039 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret); 4040 drm_modeset_unlock_all(dev); 4041 drm_atomic_state_put(state); 4042 } 4043 4044 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, 4045 enum pipe pipe, 4046 enum intel_pipe_crc_source *source, 4047 uint32_t *val) 4048 { 4049 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) 4050 *source = INTEL_PIPE_CRC_SOURCE_PF; 4051 4052 switch (*source) { 4053 case INTEL_PIPE_CRC_SOURCE_PLANE1: 4054 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; 4055 break; 4056 case INTEL_PIPE_CRC_SOURCE_PLANE2: 4057 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; 4058 break; 4059 case INTEL_PIPE_CRC_SOURCE_PF: 4060 if (IS_HASWELL(dev_priv) && pipe == PIPE_A) 4061 hsw_trans_edp_pipe_A_crc_wa(dev_priv, true); 4062 4063 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; 4064 break; 4065 case INTEL_PIPE_CRC_SOURCE_NONE: 4066 *val = 0; 4067 break; 4068 default: 4069 return -EINVAL; 4070 } 4071 4072 return 0; 4073 } 4074 4075 static int pipe_crc_set_source(struct drm_i915_private *dev_priv, 4076 enum pipe pipe, 4077 enum intel_pipe_crc_source source) 4078 { 4079 struct drm_device *dev = &dev_priv->drm; 4080 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; 4081 struct intel_crtc *crtc = 4082 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); 4083 enum intel_display_power_domain power_domain; 4084 u32 val = 0; /* shut up gcc */ 4085 int ret; 4086 4087 if (pipe_crc->source == source) 4088 return 0; 4089 4090 /* forbid changing the source without going back to 'none' */ 4091 if (pipe_crc->source && source) 4092 return -EINVAL; 4093 4094 power_domain = POWER_DOMAIN_PIPE(pipe); 4095 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) { 4096 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n"); 4097 return -EIO; 4098 } 4099 4100 if (IS_GEN2(dev_priv)) 4101 ret = i8xx_pipe_crc_ctl_reg(&source, &val); 4102 else if (INTEL_GEN(dev_priv) < 5) 4103 ret = i9xx_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val); 4104 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 4105 ret = vlv_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val); 4106 else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) 4107 ret = ilk_pipe_crc_ctl_reg(&source, &val); 4108 else 4109 ret = ivb_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val); 4110 4111 if (ret != 0) 4112 goto out; 4113 4114 /* none -> real source transition */ 4115 if (source) { 4116 struct intel_pipe_crc_entry *entries; 4117 4118 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", 4119 pipe_name(pipe), pipe_crc_source_name(source)); 4120 4121 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR, 4122 sizeof(pipe_crc->entries[0]), 4123 GFP_KERNEL); 4124 if (!entries) { 4125 ret = -ENOMEM; 4126 goto out; 4127 } 4128 4129 /* 4130 * When IPS gets enabled, the pipe CRC changes. Since IPS gets 4131 * enabled and disabled dynamically based on package C states, 4132 * user space can't make reliable use of the CRCs, so let's just 4133 * completely disable it. 4134 */ 4135 hsw_disable_ips(crtc); 4136 4137 spin_lock_irq(&pipe_crc->lock); 4138 kfree(pipe_crc->entries); 4139 pipe_crc->entries = entries; 4140 pipe_crc->head = 0; 4141 pipe_crc->tail = 0; 4142 spin_unlock_irq(&pipe_crc->lock); 4143 } 4144 4145 pipe_crc->source = source; 4146 4147 I915_WRITE(PIPE_CRC_CTL(pipe), val); 4148 POSTING_READ(PIPE_CRC_CTL(pipe)); 4149 4150 /* real source -> none transition */ 4151 if (source == INTEL_PIPE_CRC_SOURCE_NONE) { 4152 struct intel_pipe_crc_entry *entries; 4153 struct intel_crtc *crtc = 4154 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 4155 4156 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", 4157 pipe_name(pipe)); 4158 4159 drm_modeset_lock(&crtc->base.mutex, NULL); 4160 if (crtc->base.state->active) 4161 intel_wait_for_vblank(dev, pipe); 4162 drm_modeset_unlock(&crtc->base.mutex); 4163 4164 spin_lock_irq(&pipe_crc->lock); 4165 entries = pipe_crc->entries; 4166 pipe_crc->entries = NULL; 4167 pipe_crc->head = 0; 4168 pipe_crc->tail = 0; 4169 spin_unlock_irq(&pipe_crc->lock); 4170 4171 kfree(entries); 4172 4173 if (IS_G4X(dev_priv)) 4174 g4x_undo_pipe_scramble_reset(dev_priv, pipe); 4175 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 4176 vlv_undo_pipe_scramble_reset(dev_priv, pipe); 4177 else if (IS_HASWELL(dev_priv) && pipe == PIPE_A) 4178 hsw_trans_edp_pipe_A_crc_wa(dev_priv, false); 4179 4180 hsw_enable_ips(crtc); 4181 } 4182 4183 ret = 0; 4184 4185 out: 4186 intel_display_power_put(dev_priv, power_domain); 4187 4188 return ret; 4189 } 4190 4191 /* 4192 * Parse pipe CRC command strings: 4193 * command: wsp* object wsp+ name wsp+ source wsp* 4194 * object: 'pipe' 4195 * name: (A | B | C) 4196 * source: (none | plane1 | plane2 | pf) 4197 * wsp: (#0x20 | #0x9 | #0xA)+ 4198 * 4199 * eg.: 4200 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A 4201 * "pipe A none" -> Stop CRC 4202 */ 4203 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) 4204 { 4205 int n_words = 0; 4206 4207 while (*buf) { 4208 char *end; 4209 4210 /* skip leading white space */ 4211 buf = skip_spaces(buf); 4212 if (!*buf) 4213 break; /* end of buffer */ 4214 4215 /* find end of word */ 4216 for (end = buf; *end && !isspace(*end); end++) 4217 ; 4218 4219 if (n_words == max_words) { 4220 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", 4221 max_words); 4222 return -EINVAL; /* ran out of words[] before bytes */ 4223 } 4224 4225 if (*end) 4226 *end++ = '\0'; 4227 words[n_words++] = buf; 4228 buf = end; 4229 } 4230 4231 return n_words; 4232 } 4233 4234 enum intel_pipe_crc_object { 4235 PIPE_CRC_OBJECT_PIPE, 4236 }; 4237 4238 static const char * const pipe_crc_objects[] = { 4239 "pipe", 4240 }; 4241 4242 static int 4243 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) 4244 { 4245 int i; 4246 4247 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) 4248 if (!strcmp(buf, pipe_crc_objects[i])) { 4249 *o = i; 4250 return 0; 4251 } 4252 4253 return -EINVAL; 4254 } 4255 4256 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) 4257 { 4258 const char name = buf[0]; 4259 4260 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) 4261 return -EINVAL; 4262 4263 *pipe = name - 'A'; 4264 4265 return 0; 4266 } 4267 4268 static int 4269 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) 4270 { 4271 int i; 4272 4273 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) 4274 if (!strcmp(buf, pipe_crc_sources[i])) { 4275 *s = i; 4276 return 0; 4277 } 4278 4279 return -EINVAL; 4280 } 4281 4282 static int display_crc_ctl_parse(struct drm_i915_private *dev_priv, 4283 char *buf, size_t len) 4284 { 4285 #define N_WORDS 3 4286 int n_words; 4287 char *words[N_WORDS]; 4288 enum pipe pipe; 4289 enum intel_pipe_crc_object object; 4290 enum intel_pipe_crc_source source; 4291 4292 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); 4293 if (n_words != N_WORDS) { 4294 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", 4295 N_WORDS); 4296 return -EINVAL; 4297 } 4298 4299 if (display_crc_ctl_parse_object(words[0], &object) < 0) { 4300 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); 4301 return -EINVAL; 4302 } 4303 4304 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { 4305 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); 4306 return -EINVAL; 4307 } 4308 4309 if (display_crc_ctl_parse_source(words[2], &source) < 0) { 4310 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); 4311 return -EINVAL; 4312 } 4313 4314 return pipe_crc_set_source(dev_priv, pipe, source); 4315 } 4316 4317 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, 4318 size_t len, loff_t *offp) 4319 { 4320 struct seq_file *m = file->private_data; 4321 struct drm_i915_private *dev_priv = m->private; 4322 char *tmpbuf; 4323 int ret; 4324 4325 if (len == 0) 4326 return 0; 4327 4328 if (len > PAGE_SIZE - 1) { 4329 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", 4330 PAGE_SIZE); 4331 return -E2BIG; 4332 } 4333 4334 tmpbuf = kmalloc(len + 1, GFP_KERNEL); 4335 if (!tmpbuf) 4336 return -ENOMEM; 4337 4338 if (copy_from_user(tmpbuf, ubuf, len)) { 4339 ret = -EFAULT; 4340 goto out; 4341 } 4342 tmpbuf[len] = '\0'; 4343 4344 ret = display_crc_ctl_parse(dev_priv, tmpbuf, len); 4345 4346 out: 4347 kfree(tmpbuf); 4348 if (ret < 0) 4349 return ret; 4350 4351 *offp += len; 4352 return len; 4353 } 4354 4355 static const struct file_operations i915_display_crc_ctl_fops = { 4356 .owner = THIS_MODULE, 4357 .open = display_crc_ctl_open, 4358 .read = seq_read, 4359 .llseek = seq_lseek, 4360 .release = single_release, 4361 .write = display_crc_ctl_write 4362 }; 4363 4364 static ssize_t i915_displayport_test_active_write(struct file *file, 4365 const char __user *ubuf, 4366 size_t len, loff_t *offp) 4367 { 4368 char *input_buffer; 4369 int status = 0; 4370 struct drm_device *dev; 4371 struct drm_connector *connector; 4372 struct list_head *connector_list; 4373 struct intel_dp *intel_dp; 4374 int val = 0; 4375 4376 dev = ((struct seq_file *)file->private_data)->private; 4377 4378 connector_list = &dev->mode_config.connector_list; 4379 4380 if (len == 0) 4381 return 0; 4382 4383 input_buffer = kmalloc(len + 1, GFP_KERNEL); 4384 if (!input_buffer) 4385 return -ENOMEM; 4386 4387 if (copy_from_user(input_buffer, ubuf, len)) { 4388 status = -EFAULT; 4389 goto out; 4390 } 4391 4392 input_buffer[len] = '\0'; 4393 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); 4394 4395 list_for_each_entry(connector, connector_list, head) { 4396 if (connector->connector_type != 4397 DRM_MODE_CONNECTOR_DisplayPort) 4398 continue; 4399 4400 if (connector->status == connector_status_connected && 4401 connector->encoder != NULL) { 4402 intel_dp = enc_to_intel_dp(connector->encoder); 4403 status = kstrtoint(input_buffer, 10, &val); 4404 if (status < 0) 4405 goto out; 4406 DRM_DEBUG_DRIVER("Got %d for test active\n", val); 4407 /* To prevent erroneous activation of the compliance 4408 * testing code, only accept an actual value of 1 here 4409 */ 4410 if (val == 1) 4411 intel_dp->compliance_test_active = 1; 4412 else 4413 intel_dp->compliance_test_active = 0; 4414 } 4415 } 4416 out: 4417 kfree(input_buffer); 4418 if (status < 0) 4419 return status; 4420 4421 *offp += len; 4422 return len; 4423 } 4424 4425 static int i915_displayport_test_active_show(struct seq_file *m, void *data) 4426 { 4427 struct drm_device *dev = m->private; 4428 struct drm_connector *connector; 4429 struct list_head *connector_list = &dev->mode_config.connector_list; 4430 struct intel_dp *intel_dp; 4431 4432 list_for_each_entry(connector, connector_list, head) { 4433 if (connector->connector_type != 4434 DRM_MODE_CONNECTOR_DisplayPort) 4435 continue; 4436 4437 if (connector->status == connector_status_connected && 4438 connector->encoder != NULL) { 4439 intel_dp = enc_to_intel_dp(connector->encoder); 4440 if (intel_dp->compliance_test_active) 4441 seq_puts(m, "1"); 4442 else 4443 seq_puts(m, "0"); 4444 } else 4445 seq_puts(m, "0"); 4446 } 4447 4448 return 0; 4449 } 4450 4451 static int i915_displayport_test_active_open(struct inode *inode, 4452 struct file *file) 4453 { 4454 struct drm_i915_private *dev_priv = inode->i_private; 4455 4456 return single_open(file, i915_displayport_test_active_show, 4457 &dev_priv->drm); 4458 } 4459 4460 static const struct file_operations i915_displayport_test_active_fops = { 4461 .owner = THIS_MODULE, 4462 .open = i915_displayport_test_active_open, 4463 .read = seq_read, 4464 .llseek = seq_lseek, 4465 .release = single_release, 4466 .write = i915_displayport_test_active_write 4467 }; 4468 4469 static int i915_displayport_test_data_show(struct seq_file *m, void *data) 4470 { 4471 struct drm_device *dev = m->private; 4472 struct drm_connector *connector; 4473 struct list_head *connector_list = &dev->mode_config.connector_list; 4474 struct intel_dp *intel_dp; 4475 4476 list_for_each_entry(connector, connector_list, head) { 4477 if (connector->connector_type != 4478 DRM_MODE_CONNECTOR_DisplayPort) 4479 continue; 4480 4481 if (connector->status == connector_status_connected && 4482 connector->encoder != NULL) { 4483 intel_dp = enc_to_intel_dp(connector->encoder); 4484 seq_printf(m, "%lx", intel_dp->compliance_test_data); 4485 } else 4486 seq_puts(m, "0"); 4487 } 4488 4489 return 0; 4490 } 4491 static int i915_displayport_test_data_open(struct inode *inode, 4492 struct file *file) 4493 { 4494 struct drm_i915_private *dev_priv = inode->i_private; 4495 4496 return single_open(file, i915_displayport_test_data_show, 4497 &dev_priv->drm); 4498 } 4499 4500 static const struct file_operations i915_displayport_test_data_fops = { 4501 .owner = THIS_MODULE, 4502 .open = i915_displayport_test_data_open, 4503 .read = seq_read, 4504 .llseek = seq_lseek, 4505 .release = single_release 4506 }; 4507 4508 static int i915_displayport_test_type_show(struct seq_file *m, void *data) 4509 { 4510 struct drm_device *dev = m->private; 4511 struct drm_connector *connector; 4512 struct list_head *connector_list = &dev->mode_config.connector_list; 4513 struct intel_dp *intel_dp; 4514 4515 list_for_each_entry(connector, connector_list, head) { 4516 if (connector->connector_type != 4517 DRM_MODE_CONNECTOR_DisplayPort) 4518 continue; 4519 4520 if (connector->status == connector_status_connected && 4521 connector->encoder != NULL) { 4522 intel_dp = enc_to_intel_dp(connector->encoder); 4523 seq_printf(m, "%02lx", intel_dp->compliance_test_type); 4524 } else 4525 seq_puts(m, "0"); 4526 } 4527 4528 return 0; 4529 } 4530 4531 static int i915_displayport_test_type_open(struct inode *inode, 4532 struct file *file) 4533 { 4534 struct drm_i915_private *dev_priv = inode->i_private; 4535 4536 return single_open(file, i915_displayport_test_type_show, 4537 &dev_priv->drm); 4538 } 4539 4540 static const struct file_operations i915_displayport_test_type_fops = { 4541 .owner = THIS_MODULE, 4542 .open = i915_displayport_test_type_open, 4543 .read = seq_read, 4544 .llseek = seq_lseek, 4545 .release = single_release 4546 }; 4547 4548 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) 4549 { 4550 struct drm_i915_private *dev_priv = m->private; 4551 struct drm_device *dev = &dev_priv->drm; 4552 int level; 4553 int num_levels; 4554 4555 if (IS_CHERRYVIEW(dev_priv)) 4556 num_levels = 3; 4557 else if (IS_VALLEYVIEW(dev_priv)) 4558 num_levels = 1; 4559 else 4560 num_levels = ilk_wm_max_level(dev_priv) + 1; 4561 4562 drm_modeset_lock_all(dev); 4563 4564 for (level = 0; level < num_levels; level++) { 4565 unsigned int latency = wm[level]; 4566 4567 /* 4568 * - WM1+ latency values in 0.5us units 4569 * - latencies are in us on gen9/vlv/chv 4570 */ 4571 if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) || 4572 IS_CHERRYVIEW(dev_priv)) 4573 latency *= 10; 4574 else if (level > 0) 4575 latency *= 5; 4576 4577 seq_printf(m, "WM%d %u (%u.%u usec)\n", 4578 level, wm[level], latency / 10, latency % 10); 4579 } 4580 4581 drm_modeset_unlock_all(dev); 4582 } 4583 4584 static int pri_wm_latency_show(struct seq_file *m, void *data) 4585 { 4586 struct drm_i915_private *dev_priv = m->private; 4587 const uint16_t *latencies; 4588 4589 if (INTEL_GEN(dev_priv) >= 9) 4590 latencies = dev_priv->wm.skl_latency; 4591 else 4592 latencies = dev_priv->wm.pri_latency; 4593 4594 wm_latency_show(m, latencies); 4595 4596 return 0; 4597 } 4598 4599 static int spr_wm_latency_show(struct seq_file *m, void *data) 4600 { 4601 struct drm_i915_private *dev_priv = m->private; 4602 const uint16_t *latencies; 4603 4604 if (INTEL_GEN(dev_priv) >= 9) 4605 latencies = dev_priv->wm.skl_latency; 4606 else 4607 latencies = dev_priv->wm.spr_latency; 4608 4609 wm_latency_show(m, latencies); 4610 4611 return 0; 4612 } 4613 4614 static int cur_wm_latency_show(struct seq_file *m, void *data) 4615 { 4616 struct drm_i915_private *dev_priv = m->private; 4617 const uint16_t *latencies; 4618 4619 if (INTEL_GEN(dev_priv) >= 9) 4620 latencies = dev_priv->wm.skl_latency; 4621 else 4622 latencies = dev_priv->wm.cur_latency; 4623 4624 wm_latency_show(m, latencies); 4625 4626 return 0; 4627 } 4628 4629 static int pri_wm_latency_open(struct inode *inode, struct file *file) 4630 { 4631 struct drm_i915_private *dev_priv = inode->i_private; 4632 4633 if (INTEL_GEN(dev_priv) < 5) 4634 return -ENODEV; 4635 4636 return single_open(file, pri_wm_latency_show, dev_priv); 4637 } 4638 4639 static int spr_wm_latency_open(struct inode *inode, struct file *file) 4640 { 4641 struct drm_i915_private *dev_priv = inode->i_private; 4642 4643 if (HAS_GMCH_DISPLAY(dev_priv)) 4644 return -ENODEV; 4645 4646 return single_open(file, spr_wm_latency_show, dev_priv); 4647 } 4648 4649 static int cur_wm_latency_open(struct inode *inode, struct file *file) 4650 { 4651 struct drm_i915_private *dev_priv = inode->i_private; 4652 4653 if (HAS_GMCH_DISPLAY(dev_priv)) 4654 return -ENODEV; 4655 4656 return single_open(file, cur_wm_latency_show, dev_priv); 4657 } 4658 4659 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, 4660 size_t len, loff_t *offp, uint16_t wm[8]) 4661 { 4662 struct seq_file *m = file->private_data; 4663 struct drm_i915_private *dev_priv = m->private; 4664 struct drm_device *dev = &dev_priv->drm; 4665 uint16_t new[8] = { 0 }; 4666 int num_levels; 4667 int level; 4668 int ret; 4669 char tmp[32]; 4670 4671 if (IS_CHERRYVIEW(dev_priv)) 4672 num_levels = 3; 4673 else if (IS_VALLEYVIEW(dev_priv)) 4674 num_levels = 1; 4675 else 4676 num_levels = ilk_wm_max_level(dev_priv) + 1; 4677 4678 if (len >= sizeof(tmp)) 4679 return -EINVAL; 4680 4681 if (copy_from_user(tmp, ubuf, len)) 4682 return -EFAULT; 4683 4684 tmp[len] = '\0'; 4685 4686 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", 4687 &new[0], &new[1], &new[2], &new[3], 4688 &new[4], &new[5], &new[6], &new[7]); 4689 if (ret != num_levels) 4690 return -EINVAL; 4691 4692 drm_modeset_lock_all(dev); 4693 4694 for (level = 0; level < num_levels; level++) 4695 wm[level] = new[level]; 4696 4697 drm_modeset_unlock_all(dev); 4698 4699 return len; 4700 } 4701 4702 4703 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, 4704 size_t len, loff_t *offp) 4705 { 4706 struct seq_file *m = file->private_data; 4707 struct drm_i915_private *dev_priv = m->private; 4708 uint16_t *latencies; 4709 4710 if (INTEL_GEN(dev_priv) >= 9) 4711 latencies = dev_priv->wm.skl_latency; 4712 else 4713 latencies = dev_priv->wm.pri_latency; 4714 4715 return wm_latency_write(file, ubuf, len, offp, latencies); 4716 } 4717 4718 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, 4719 size_t len, loff_t *offp) 4720 { 4721 struct seq_file *m = file->private_data; 4722 struct drm_i915_private *dev_priv = m->private; 4723 uint16_t *latencies; 4724 4725 if (INTEL_GEN(dev_priv) >= 9) 4726 latencies = dev_priv->wm.skl_latency; 4727 else 4728 latencies = dev_priv->wm.spr_latency; 4729 4730 return wm_latency_write(file, ubuf, len, offp, latencies); 4731 } 4732 4733 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, 4734 size_t len, loff_t *offp) 4735 { 4736 struct seq_file *m = file->private_data; 4737 struct drm_i915_private *dev_priv = m->private; 4738 uint16_t *latencies; 4739 4740 if (INTEL_GEN(dev_priv) >= 9) 4741 latencies = dev_priv->wm.skl_latency; 4742 else 4743 latencies = dev_priv->wm.cur_latency; 4744 4745 return wm_latency_write(file, ubuf, len, offp, latencies); 4746 } 4747 4748 static const struct file_operations i915_pri_wm_latency_fops = { 4749 .owner = THIS_MODULE, 4750 .open = pri_wm_latency_open, 4751 .read = seq_read, 4752 .llseek = seq_lseek, 4753 .release = single_release, 4754 .write = pri_wm_latency_write 4755 }; 4756 4757 static const struct file_operations i915_spr_wm_latency_fops = { 4758 .owner = THIS_MODULE, 4759 .open = spr_wm_latency_open, 4760 .read = seq_read, 4761 .llseek = seq_lseek, 4762 .release = single_release, 4763 .write = spr_wm_latency_write 4764 }; 4765 4766 static const struct file_operations i915_cur_wm_latency_fops = { 4767 .owner = THIS_MODULE, 4768 .open = cur_wm_latency_open, 4769 .read = seq_read, 4770 .llseek = seq_lseek, 4771 .release = single_release, 4772 .write = cur_wm_latency_write 4773 }; 4774 4775 static int 4776 i915_wedged_get(void *data, u64 *val) 4777 { 4778 struct drm_i915_private *dev_priv = data; 4779 4780 *val = i915_terminally_wedged(&dev_priv->gpu_error); 4781 4782 return 0; 4783 } 4784 4785 static int 4786 i915_wedged_set(void *data, u64 val) 4787 { 4788 struct drm_i915_private *dev_priv = data; 4789 4790 /* 4791 * There is no safeguard against this debugfs entry colliding 4792 * with the hangcheck calling same i915_handle_error() in 4793 * parallel, causing an explosion. For now we assume that the 4794 * test harness is responsible enough not to inject gpu hangs 4795 * while it is writing to 'i915_wedged' 4796 */ 4797 4798 if (i915_reset_in_progress(&dev_priv->gpu_error)) 4799 return -EAGAIN; 4800 4801 intel_runtime_pm_get(dev_priv); 4802 4803 i915_handle_error(dev_priv, val, 4804 "Manually setting wedged to %llu", val); 4805 4806 intel_runtime_pm_put(dev_priv); 4807 4808 return 0; 4809 } 4810 4811 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, 4812 i915_wedged_get, i915_wedged_set, 4813 "%llu\n"); 4814 4815 static int 4816 i915_ring_missed_irq_get(void *data, u64 *val) 4817 { 4818 struct drm_i915_private *dev_priv = data; 4819 4820 *val = dev_priv->gpu_error.missed_irq_rings; 4821 return 0; 4822 } 4823 4824 static int 4825 i915_ring_missed_irq_set(void *data, u64 val) 4826 { 4827 struct drm_i915_private *dev_priv = data; 4828 struct drm_device *dev = &dev_priv->drm; 4829 int ret; 4830 4831 /* Lock against concurrent debugfs callers */ 4832 ret = mutex_lock_interruptible(&dev->struct_mutex); 4833 if (ret) 4834 return ret; 4835 dev_priv->gpu_error.missed_irq_rings = val; 4836 mutex_unlock(&dev->struct_mutex); 4837 4838 return 0; 4839 } 4840 4841 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, 4842 i915_ring_missed_irq_get, i915_ring_missed_irq_set, 4843 "0x%08llx\n"); 4844 4845 static int 4846 i915_ring_test_irq_get(void *data, u64 *val) 4847 { 4848 struct drm_i915_private *dev_priv = data; 4849 4850 *val = dev_priv->gpu_error.test_irq_rings; 4851 4852 return 0; 4853 } 4854 4855 static int 4856 i915_ring_test_irq_set(void *data, u64 val) 4857 { 4858 struct drm_i915_private *dev_priv = data; 4859 4860 val &= INTEL_INFO(dev_priv)->ring_mask; 4861 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); 4862 dev_priv->gpu_error.test_irq_rings = val; 4863 4864 return 0; 4865 } 4866 4867 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, 4868 i915_ring_test_irq_get, i915_ring_test_irq_set, 4869 "0x%08llx\n"); 4870 4871 #define DROP_UNBOUND 0x1 4872 #define DROP_BOUND 0x2 4873 #define DROP_RETIRE 0x4 4874 #define DROP_ACTIVE 0x8 4875 #define DROP_ALL (DROP_UNBOUND | \ 4876 DROP_BOUND | \ 4877 DROP_RETIRE | \ 4878 DROP_ACTIVE) 4879 static int 4880 i915_drop_caches_get(void *data, u64 *val) 4881 { 4882 *val = DROP_ALL; 4883 4884 return 0; 4885 } 4886 4887 static int 4888 i915_drop_caches_set(void *data, u64 val) 4889 { 4890 struct drm_i915_private *dev_priv = data; 4891 struct drm_device *dev = &dev_priv->drm; 4892 int ret; 4893 4894 DRM_DEBUG("Dropping caches: 0x%08llx\n", val); 4895 4896 /* No need to check and wait for gpu resets, only libdrm auto-restarts 4897 * on ioctls on -EAGAIN. */ 4898 ret = mutex_lock_interruptible(&dev->struct_mutex); 4899 if (ret) 4900 return ret; 4901 4902 if (val & DROP_ACTIVE) { 4903 ret = i915_gem_wait_for_idle(dev_priv, 4904 I915_WAIT_INTERRUPTIBLE | 4905 I915_WAIT_LOCKED); 4906 if (ret) 4907 goto unlock; 4908 } 4909 4910 if (val & (DROP_RETIRE | DROP_ACTIVE)) 4911 i915_gem_retire_requests(dev_priv); 4912 4913 if (val & DROP_BOUND) 4914 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); 4915 4916 if (val & DROP_UNBOUND) 4917 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); 4918 4919 unlock: 4920 mutex_unlock(&dev->struct_mutex); 4921 4922 return ret; 4923 } 4924 4925 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, 4926 i915_drop_caches_get, i915_drop_caches_set, 4927 "0x%08llx\n"); 4928 4929 static int 4930 i915_max_freq_get(void *data, u64 *val) 4931 { 4932 struct drm_i915_private *dev_priv = data; 4933 4934 if (INTEL_GEN(dev_priv) < 6) 4935 return -ENODEV; 4936 4937 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); 4938 return 0; 4939 } 4940 4941 static int 4942 i915_max_freq_set(void *data, u64 val) 4943 { 4944 struct drm_i915_private *dev_priv = data; 4945 u32 hw_max, hw_min; 4946 int ret; 4947 4948 if (INTEL_GEN(dev_priv) < 6) 4949 return -ENODEV; 4950 4951 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); 4952 4953 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); 4954 if (ret) 4955 return ret; 4956 4957 /* 4958 * Turbo will still be enabled, but won't go above the set value. 4959 */ 4960 val = intel_freq_opcode(dev_priv, val); 4961 4962 hw_max = dev_priv->rps.max_freq; 4963 hw_min = dev_priv->rps.min_freq; 4964 4965 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { 4966 mutex_unlock(&dev_priv->rps.hw_lock); 4967 return -EINVAL; 4968 } 4969 4970 dev_priv->rps.max_freq_softlimit = val; 4971 4972 intel_set_rps(dev_priv, val); 4973 4974 mutex_unlock(&dev_priv->rps.hw_lock); 4975 4976 return 0; 4977 } 4978 4979 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, 4980 i915_max_freq_get, i915_max_freq_set, 4981 "%llu\n"); 4982 4983 static int 4984 i915_min_freq_get(void *data, u64 *val) 4985 { 4986 struct drm_i915_private *dev_priv = data; 4987 4988 if (INTEL_GEN(dev_priv) < 6) 4989 return -ENODEV; 4990 4991 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); 4992 return 0; 4993 } 4994 4995 static int 4996 i915_min_freq_set(void *data, u64 val) 4997 { 4998 struct drm_i915_private *dev_priv = data; 4999 u32 hw_max, hw_min; 5000 int ret; 5001 5002 if (INTEL_GEN(dev_priv) < 6) 5003 return -ENODEV; 5004 5005 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); 5006 5007 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); 5008 if (ret) 5009 return ret; 5010 5011 /* 5012 * Turbo will still be enabled, but won't go below the set value. 5013 */ 5014 val = intel_freq_opcode(dev_priv, val); 5015 5016 hw_max = dev_priv->rps.max_freq; 5017 hw_min = dev_priv->rps.min_freq; 5018 5019 if (val < hw_min || 5020 val > hw_max || val > dev_priv->rps.max_freq_softlimit) { 5021 mutex_unlock(&dev_priv->rps.hw_lock); 5022 return -EINVAL; 5023 } 5024 5025 dev_priv->rps.min_freq_softlimit = val; 5026 5027 intel_set_rps(dev_priv, val); 5028 5029 mutex_unlock(&dev_priv->rps.hw_lock); 5030 5031 return 0; 5032 } 5033 5034 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, 5035 i915_min_freq_get, i915_min_freq_set, 5036 "%llu\n"); 5037 5038 static int 5039 i915_cache_sharing_get(void *data, u64 *val) 5040 { 5041 struct drm_i915_private *dev_priv = data; 5042 struct drm_device *dev = &dev_priv->drm; 5043 u32 snpcr; 5044 int ret; 5045 5046 if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) 5047 return -ENODEV; 5048 5049 ret = mutex_lock_interruptible(&dev->struct_mutex); 5050 if (ret) 5051 return ret; 5052 intel_runtime_pm_get(dev_priv); 5053 5054 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); 5055 5056 intel_runtime_pm_put(dev_priv); 5057 mutex_unlock(&dev->struct_mutex); 5058 5059 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; 5060 5061 return 0; 5062 } 5063 5064 static int 5065 i915_cache_sharing_set(void *data, u64 val) 5066 { 5067 struct drm_i915_private *dev_priv = data; 5068 u32 snpcr; 5069 5070 if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) 5071 return -ENODEV; 5072 5073 if (val > 3) 5074 return -EINVAL; 5075 5076 intel_runtime_pm_get(dev_priv); 5077 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); 5078 5079 /* Update the cache sharing policy here as well */ 5080 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); 5081 snpcr &= ~GEN6_MBC_SNPCR_MASK; 5082 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); 5083 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); 5084 5085 intel_runtime_pm_put(dev_priv); 5086 return 0; 5087 } 5088 5089 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, 5090 i915_cache_sharing_get, i915_cache_sharing_set, 5091 "%llu\n"); 5092 5093 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, 5094 struct sseu_dev_info *sseu) 5095 { 5096 int ss_max = 2; 5097 int ss; 5098 u32 sig1[ss_max], sig2[ss_max]; 5099 5100 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); 5101 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); 5102 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); 5103 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); 5104 5105 for (ss = 0; ss < ss_max; ss++) { 5106 unsigned int eu_cnt; 5107 5108 if (sig1[ss] & CHV_SS_PG_ENABLE) 5109 /* skip disabled subslice */ 5110 continue; 5111 5112 sseu->slice_mask = BIT(0); 5113 sseu->subslice_mask |= BIT(ss); 5114 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + 5115 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + 5116 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + 5117 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); 5118 sseu->eu_total += eu_cnt; 5119 sseu->eu_per_subslice = max_t(unsigned int, 5120 sseu->eu_per_subslice, eu_cnt); 5121 } 5122 } 5123 5124 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, 5125 struct sseu_dev_info *sseu) 5126 { 5127 int s_max = 3, ss_max = 4; 5128 int s, ss; 5129 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; 5130 5131 /* BXT has a single slice and at most 3 subslices. */ 5132 if (IS_BROXTON(dev_priv)) { 5133 s_max = 1; 5134 ss_max = 3; 5135 } 5136 5137 for (s = 0; s < s_max; s++) { 5138 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); 5139 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); 5140 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); 5141 } 5142 5143 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | 5144 GEN9_PGCTL_SSA_EU19_ACK | 5145 GEN9_PGCTL_SSA_EU210_ACK | 5146 GEN9_PGCTL_SSA_EU311_ACK; 5147 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | 5148 GEN9_PGCTL_SSB_EU19_ACK | 5149 GEN9_PGCTL_SSB_EU210_ACK | 5150 GEN9_PGCTL_SSB_EU311_ACK; 5151 5152 for (s = 0; s < s_max; s++) { 5153 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) 5154 /* skip disabled slice */ 5155 continue; 5156 5157 sseu->slice_mask |= BIT(s); 5158 5159 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) 5160 sseu->subslice_mask = 5161 INTEL_INFO(dev_priv)->sseu.subslice_mask; 5162 5163 for (ss = 0; ss < ss_max; ss++) { 5164 unsigned int eu_cnt; 5165 5166 if (IS_BROXTON(dev_priv)) { 5167 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) 5168 /* skip disabled subslice */ 5169 continue; 5170 5171 sseu->subslice_mask |= BIT(ss); 5172 } 5173 5174 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & 5175 eu_mask[ss%2]); 5176 sseu->eu_total += eu_cnt; 5177 sseu->eu_per_subslice = max_t(unsigned int, 5178 sseu->eu_per_subslice, 5179 eu_cnt); 5180 } 5181 } 5182 } 5183 5184 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, 5185 struct sseu_dev_info *sseu) 5186 { 5187 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); 5188 int s; 5189 5190 sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; 5191 5192 if (sseu->slice_mask) { 5193 sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask; 5194 sseu->eu_per_subslice = 5195 INTEL_INFO(dev_priv)->sseu.eu_per_subslice; 5196 sseu->eu_total = sseu->eu_per_subslice * 5197 sseu_subslice_total(sseu); 5198 5199 /* subtract fused off EU(s) from enabled slice(s) */ 5200 for (s = 0; s < fls(sseu->slice_mask); s++) { 5201 u8 subslice_7eu = 5202 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s]; 5203 5204 sseu->eu_total -= hweight8(subslice_7eu); 5205 } 5206 } 5207 } 5208 5209 static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, 5210 const struct sseu_dev_info *sseu) 5211 { 5212 struct drm_i915_private *dev_priv = node_to_i915(m->private); 5213 const char *type = is_available_info ? "Available" : "Enabled"; 5214 5215 seq_printf(m, " %s Slice Mask: %04x\n", type, 5216 sseu->slice_mask); 5217 seq_printf(m, " %s Slice Total: %u\n", type, 5218 hweight8(sseu->slice_mask)); 5219 seq_printf(m, " %s Subslice Total: %u\n", type, 5220 sseu_subslice_total(sseu)); 5221 seq_printf(m, " %s Subslice Mask: %04x\n", type, 5222 sseu->subslice_mask); 5223 seq_printf(m, " %s Subslice Per Slice: %u\n", type, 5224 hweight8(sseu->subslice_mask)); 5225 seq_printf(m, " %s EU Total: %u\n", type, 5226 sseu->eu_total); 5227 seq_printf(m, " %s EU Per Subslice: %u\n", type, 5228 sseu->eu_per_subslice); 5229 5230 if (!is_available_info) 5231 return; 5232 5233 seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv))); 5234 if (HAS_POOLED_EU(dev_priv)) 5235 seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool); 5236 5237 seq_printf(m, " Has Slice Power Gating: %s\n", 5238 yesno(sseu->has_slice_pg)); 5239 seq_printf(m, " Has Subslice Power Gating: %s\n", 5240 yesno(sseu->has_subslice_pg)); 5241 seq_printf(m, " Has EU Power Gating: %s\n", 5242 yesno(sseu->has_eu_pg)); 5243 } 5244 5245 static int i915_sseu_status(struct seq_file *m, void *unused) 5246 { 5247 struct drm_i915_private *dev_priv = node_to_i915(m->private); 5248 struct sseu_dev_info sseu; 5249 5250 if (INTEL_GEN(dev_priv) < 8) 5251 return -ENODEV; 5252 5253 seq_puts(m, "SSEU Device Info\n"); 5254 i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu); 5255 5256 seq_puts(m, "SSEU Device Status\n"); 5257 memset(&sseu, 0, sizeof(sseu)); 5258 5259 intel_runtime_pm_get(dev_priv); 5260 5261 if (IS_CHERRYVIEW(dev_priv)) { 5262 cherryview_sseu_device_status(dev_priv, &sseu); 5263 } else if (IS_BROADWELL(dev_priv)) { 5264 broadwell_sseu_device_status(dev_priv, &sseu); 5265 } else if (INTEL_GEN(dev_priv) >= 9) { 5266 gen9_sseu_device_status(dev_priv, &sseu); 5267 } 5268 5269 intel_runtime_pm_put(dev_priv); 5270 5271 i915_print_sseu_info(m, false, &sseu); 5272 5273 return 0; 5274 } 5275 5276 static int i915_forcewake_open(struct inode *inode, struct file *file) 5277 { 5278 struct drm_i915_private *dev_priv = inode->i_private; 5279 5280 if (INTEL_GEN(dev_priv) < 6) 5281 return 0; 5282 5283 intel_runtime_pm_get(dev_priv); 5284 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 5285 5286 return 0; 5287 } 5288 5289 static int i915_forcewake_release(struct inode *inode, struct file *file) 5290 { 5291 struct drm_i915_private *dev_priv = inode->i_private; 5292 5293 if (INTEL_GEN(dev_priv) < 6) 5294 return 0; 5295 5296 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 5297 intel_runtime_pm_put(dev_priv); 5298 5299 return 0; 5300 } 5301 5302 static const struct file_operations i915_forcewake_fops = { 5303 .owner = THIS_MODULE, 5304 .open = i915_forcewake_open, 5305 .release = i915_forcewake_release, 5306 }; 5307 5308 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) 5309 { 5310 struct dentry *ent; 5311 5312 ent = debugfs_create_file("i915_forcewake_user", 5313 S_IRUSR, 5314 root, to_i915(minor->dev), 5315 &i915_forcewake_fops); 5316 if (!ent) 5317 return -ENOMEM; 5318 5319 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); 5320 } 5321 5322 static int i915_debugfs_create(struct dentry *root, 5323 struct drm_minor *minor, 5324 const char *name, 5325 const struct file_operations *fops) 5326 { 5327 struct dentry *ent; 5328 5329 ent = debugfs_create_file(name, 5330 S_IRUGO | S_IWUSR, 5331 root, to_i915(minor->dev), 5332 fops); 5333 if (!ent) 5334 return -ENOMEM; 5335 5336 return drm_add_fake_info_node(minor, ent, fops); 5337 } 5338 5339 static const struct drm_info_list i915_debugfs_list[] = { 5340 {"i915_capabilities", i915_capabilities, 0}, 5341 {"i915_gem_objects", i915_gem_object_info, 0}, 5342 {"i915_gem_gtt", i915_gem_gtt_info, 0}, 5343 {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1}, 5344 {"i915_gem_stolen", i915_gem_stolen_list_info }, 5345 {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, 5346 {"i915_gem_request", i915_gem_request_info, 0}, 5347 {"i915_gem_seqno", i915_gem_seqno_info, 0}, 5348 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, 5349 {"i915_gem_interrupt", i915_interrupt_info, 0}, 5350 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, 5351 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, 5352 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, 5353 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, 5354 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, 5355 {"i915_guc_info", i915_guc_info, 0}, 5356 {"i915_guc_load_status", i915_guc_load_status_info, 0}, 5357 {"i915_guc_log_dump", i915_guc_log_dump, 0}, 5358 {"i915_frequency_info", i915_frequency_info, 0}, 5359 {"i915_hangcheck_info", i915_hangcheck_info, 0}, 5360 {"i915_drpc_info", i915_drpc_info, 0}, 5361 {"i915_emon_status", i915_emon_status, 0}, 5362 {"i915_ring_freq_table", i915_ring_freq_table, 0}, 5363 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, 5364 {"i915_fbc_status", i915_fbc_status, 0}, 5365 {"i915_ips_status", i915_ips_status, 0}, 5366 {"i915_sr_status", i915_sr_status, 0}, 5367 {"i915_opregion", i915_opregion, 0}, 5368 {"i915_vbt", i915_vbt, 0}, 5369 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, 5370 {"i915_context_status", i915_context_status, 0}, 5371 {"i915_dump_lrc", i915_dump_lrc, 0}, 5372 {"i915_forcewake_domains", i915_forcewake_domains, 0}, 5373 {"i915_swizzle_info", i915_swizzle_info, 0}, 5374 {"i915_ppgtt_info", i915_ppgtt_info, 0}, 5375 {"i915_llc", i915_llc, 0}, 5376 {"i915_edp_psr_status", i915_edp_psr_status, 0}, 5377 {"i915_sink_crc_eDP1", i915_sink_crc, 0}, 5378 {"i915_energy_uJ", i915_energy_uJ, 0}, 5379 {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, 5380 {"i915_power_domain_info", i915_power_domain_info, 0}, 5381 {"i915_dmc_info", i915_dmc_info, 0}, 5382 {"i915_display_info", i915_display_info, 0}, 5383 {"i915_engine_info", i915_engine_info, 0}, 5384 {"i915_semaphore_status", i915_semaphore_status, 0}, 5385 {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, 5386 {"i915_dp_mst_info", i915_dp_mst_info, 0}, 5387 {"i915_wa_registers", i915_wa_registers, 0}, 5388 {"i915_ddb_info", i915_ddb_info, 0}, 5389 {"i915_sseu_status", i915_sseu_status, 0}, 5390 {"i915_drrs_status", i915_drrs_status, 0}, 5391 {"i915_rps_boost_info", i915_rps_boost_info, 0}, 5392 }; 5393 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) 5394 5395 static const struct i915_debugfs_files { 5396 const char *name; 5397 const struct file_operations *fops; 5398 } i915_debugfs_files[] = { 5399 {"i915_wedged", &i915_wedged_fops}, 5400 {"i915_max_freq", &i915_max_freq_fops}, 5401 {"i915_min_freq", &i915_min_freq_fops}, 5402 {"i915_cache_sharing", &i915_cache_sharing_fops}, 5403 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, 5404 {"i915_ring_test_irq", &i915_ring_test_irq_fops}, 5405 {"i915_gem_drop_caches", &i915_drop_caches_fops}, 5406 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 5407 {"i915_error_state", &i915_error_state_fops}, 5408 #endif 5409 {"i915_next_seqno", &i915_next_seqno_fops}, 5410 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, 5411 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, 5412 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, 5413 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, 5414 {"i915_fbc_false_color", &i915_fbc_fc_fops}, 5415 {"i915_dp_test_data", &i915_displayport_test_data_fops}, 5416 {"i915_dp_test_type", &i915_displayport_test_type_fops}, 5417 {"i915_dp_test_active", &i915_displayport_test_active_fops} 5418 }; 5419 5420 void intel_display_crc_init(struct drm_i915_private *dev_priv) 5421 { 5422 enum pipe pipe; 5423 5424 for_each_pipe(dev_priv, pipe) { 5425 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; 5426 5427 pipe_crc->opened = false; 5428 spin_lock_init(&pipe_crc->lock); 5429 init_waitqueue_head(&pipe_crc->wq); 5430 } 5431 } 5432 5433 int i915_debugfs_register(struct drm_i915_private *dev_priv) 5434 { 5435 struct drm_minor *minor = dev_priv->drm.primary; 5436 int ret, i; 5437 5438 ret = i915_forcewake_create(minor->debugfs_root, minor); 5439 if (ret) 5440 return ret; 5441 5442 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { 5443 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); 5444 if (ret) 5445 return ret; 5446 } 5447 5448 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { 5449 ret = i915_debugfs_create(minor->debugfs_root, minor, 5450 i915_debugfs_files[i].name, 5451 i915_debugfs_files[i].fops); 5452 if (ret) 5453 return ret; 5454 } 5455 5456 return drm_debugfs_create_files(i915_debugfs_list, 5457 I915_DEBUGFS_ENTRIES, 5458 minor->debugfs_root, minor); 5459 } 5460 5461 void i915_debugfs_unregister(struct drm_i915_private *dev_priv) 5462 { 5463 struct drm_minor *minor = dev_priv->drm.primary; 5464 int i; 5465 5466 drm_debugfs_remove_files(i915_debugfs_list, 5467 I915_DEBUGFS_ENTRIES, minor); 5468 5469 drm_debugfs_remove_files((struct drm_info_list *)&i915_forcewake_fops, 5470 1, minor); 5471 5472 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { 5473 struct drm_info_list *info_list = 5474 (struct drm_info_list *)&i915_pipe_crc_data[i]; 5475 5476 drm_debugfs_remove_files(info_list, 1, minor); 5477 } 5478 5479 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { 5480 struct drm_info_list *info_list = 5481 (struct drm_info_list *)i915_debugfs_files[i].fops; 5482 5483 drm_debugfs_remove_files(info_list, 1, minor); 5484 } 5485 } 5486 5487 struct dpcd_block { 5488 /* DPCD dump start address. */ 5489 unsigned int offset; 5490 /* DPCD dump end address, inclusive. If unset, .size will be used. */ 5491 unsigned int end; 5492 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ 5493 size_t size; 5494 /* Only valid for eDP. */ 5495 bool edp; 5496 }; 5497 5498 static const struct dpcd_block i915_dpcd_debug[] = { 5499 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, 5500 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, 5501 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, 5502 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, 5503 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, 5504 { .offset = DP_SET_POWER }, 5505 { .offset = DP_EDP_DPCD_REV }, 5506 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, 5507 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, 5508 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, 5509 }; 5510 5511 static int i915_dpcd_show(struct seq_file *m, void *data) 5512 { 5513 struct drm_connector *connector = m->private; 5514 struct intel_dp *intel_dp = 5515 enc_to_intel_dp(&intel_attached_encoder(connector)->base); 5516 uint8_t buf[16]; 5517 ssize_t err; 5518 int i; 5519 5520 if (connector->status != connector_status_connected) 5521 return -ENODEV; 5522 5523 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { 5524 const struct dpcd_block *b = &i915_dpcd_debug[i]; 5525 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); 5526 5527 if (b->edp && 5528 connector->connector_type != DRM_MODE_CONNECTOR_eDP) 5529 continue; 5530 5531 /* low tech for now */ 5532 if (WARN_ON(size > sizeof(buf))) 5533 continue; 5534 5535 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); 5536 if (err <= 0) { 5537 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", 5538 size, b->offset, err); 5539 continue; 5540 } 5541 5542 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); 5543 } 5544 5545 return 0; 5546 } 5547 5548 static int i915_dpcd_open(struct inode *inode, struct file *file) 5549 { 5550 return single_open(file, i915_dpcd_show, inode->i_private); 5551 } 5552 5553 static const struct file_operations i915_dpcd_fops = { 5554 .owner = THIS_MODULE, 5555 .open = i915_dpcd_open, 5556 .read = seq_read, 5557 .llseek = seq_lseek, 5558 .release = single_release, 5559 }; 5560 5561 static int i915_panel_show(struct seq_file *m, void *data) 5562 { 5563 struct drm_connector *connector = m->private; 5564 struct intel_dp *intel_dp = 5565 enc_to_intel_dp(&intel_attached_encoder(connector)->base); 5566 5567 if (connector->status != connector_status_connected) 5568 return -ENODEV; 5569 5570 seq_printf(m, "Panel power up delay: %d\n", 5571 intel_dp->panel_power_up_delay); 5572 seq_printf(m, "Panel power down delay: %d\n", 5573 intel_dp->panel_power_down_delay); 5574 seq_printf(m, "Backlight on delay: %d\n", 5575 intel_dp->backlight_on_delay); 5576 seq_printf(m, "Backlight off delay: %d\n", 5577 intel_dp->backlight_off_delay); 5578 5579 return 0; 5580 } 5581 5582 static int i915_panel_open(struct inode *inode, struct file *file) 5583 { 5584 return single_open(file, i915_panel_show, inode->i_private); 5585 } 5586 5587 static const struct file_operations i915_panel_fops = { 5588 .owner = THIS_MODULE, 5589 .open = i915_panel_open, 5590 .read = seq_read, 5591 .llseek = seq_lseek, 5592 .release = single_release, 5593 }; 5594 5595 /** 5596 * i915_debugfs_connector_add - add i915 specific connector debugfs files 5597 * @connector: pointer to a registered drm_connector 5598 * 5599 * Cleanup will be done by drm_connector_unregister() through a call to 5600 * drm_debugfs_connector_remove(). 5601 * 5602 * Returns 0 on success, negative error codes on error. 5603 */ 5604 int i915_debugfs_connector_add(struct drm_connector *connector) 5605 { 5606 struct dentry *root = connector->debugfs_entry; 5607 5608 /* The connector must have been registered beforehands. */ 5609 if (!root) 5610 return -ENODEV; 5611 5612 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 5613 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 5614 debugfs_create_file("i915_dpcd", S_IRUGO, root, 5615 connector, &i915_dpcd_fops); 5616 5617 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 5618 debugfs_create_file("i915_panel_timings", S_IRUGO, root, 5619 connector, &i915_panel_fops); 5620 5621 return 0; 5622 } 5623