1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * 27 */ 28 29 #include <linux/sched/mm.h> 30 #include <linux/sort.h> 31 #include <linux/string_helpers.h> 32 33 #include <drm/drm_debugfs.h> 34 35 #include "display/intel_display_params.h" 36 37 #include "gem/i915_gem_context.h" 38 #include "gt/intel_gt.h" 39 #include "gt/intel_gt_buffer_pool.h" 40 #include "gt/intel_gt_clock_utils.h" 41 #include "gt/intel_gt_debugfs.h" 42 #include "gt/intel_gt_pm.h" 43 #include "gt/intel_gt_pm_debugfs.h" 44 #include "gt/intel_gt_regs.h" 45 #include "gt/intel_gt_requests.h" 46 #include "gt/intel_rc6.h" 47 #include "gt/intel_reset.h" 48 #include "gt/intel_rps.h" 49 #include "gt/intel_sseu_debugfs.h" 50 51 #include "i915_debugfs.h" 52 #include "i915_debugfs_params.h" 53 #include "i915_driver.h" 54 #include "i915_irq.h" 55 #include "i915_reg.h" 56 #include "i915_scheduler.h" 57 #include "intel_mchbar_regs.h" 58 59 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) 60 { 61 return to_i915(node->minor->dev); 62 } 63 64 static int i915_capabilities(struct seq_file *m, void *data) 65 { 66 struct drm_i915_private *i915 = node_to_i915(m->private); 67 struct drm_printer p = drm_seq_file_printer(m); 68 69 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915)); 70 71 intel_device_info_print(INTEL_INFO(i915), RUNTIME_INFO(i915), &p); 72 i915_print_iommu_status(i915, &p); 73 intel_gt_info_print(&to_gt(i915)->info, &p); 74 intel_driver_caps_print(&i915->caps, &p); 75 76 kernel_param_lock(THIS_MODULE); 77 i915_params_dump(&i915->params, &p); 78 intel_display_params_dump(i915, &p); 79 kernel_param_unlock(THIS_MODULE); 80 81 return 0; 82 } 83 84 static char get_tiling_flag(struct drm_i915_gem_object *obj) 85 { 86 switch (i915_gem_object_get_tiling(obj)) { 87 default: 88 case I915_TILING_NONE: return ' '; 89 case I915_TILING_X: return 'X'; 90 case I915_TILING_Y: return 'Y'; 91 } 92 } 93 94 static char get_global_flag(struct drm_i915_gem_object *obj) 95 { 96 return READ_ONCE(obj->userfault_count) ? 'g' : ' '; 97 } 98 99 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) 100 { 101 return obj->mm.mapping ? 'M' : ' '; 102 } 103 104 static const char * 105 stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len) 106 { 107 size_t x = 0; 108 109 switch (page_sizes) { 110 case 0: 111 return ""; 112 case I915_GTT_PAGE_SIZE_4K: 113 return "4K"; 114 case I915_GTT_PAGE_SIZE_64K: 115 return "64K"; 116 case I915_GTT_PAGE_SIZE_2M: 117 return "2M"; 118 default: 119 if (!buf) 120 return "M"; 121 122 if (page_sizes & I915_GTT_PAGE_SIZE_2M) 123 x += snprintf(buf + x, len - x, "2M, "); 124 if (page_sizes & I915_GTT_PAGE_SIZE_64K) 125 x += snprintf(buf + x, len - x, "64K, "); 126 if (page_sizes & I915_GTT_PAGE_SIZE_4K) 127 x += snprintf(buf + x, len - x, "4K, "); 128 buf[x-2] = '\0'; 129 130 return buf; 131 } 132 } 133 134 static const char *stringify_vma_type(const struct i915_vma *vma) 135 { 136 if (i915_vma_is_ggtt(vma)) 137 return "ggtt"; 138 139 if (i915_vma_is_dpt(vma)) 140 return "dpt"; 141 142 return "ppgtt"; 143 } 144 145 static const char *i915_cache_level_str(struct drm_i915_gem_object *obj) 146 { 147 struct drm_i915_private *i915 = obj_to_i915(obj); 148 149 if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 71))) { 150 switch (obj->pat_index) { 151 case 0: return " WB"; 152 case 1: return " WT"; 153 case 2: return " UC"; 154 case 3: return " WB (1-Way Coh)"; 155 case 4: return " WB (2-Way Coh)"; 156 default: return " not defined"; 157 } 158 } else if (IS_PONTEVECCHIO(i915)) { 159 switch (obj->pat_index) { 160 case 0: return " UC"; 161 case 1: return " WC"; 162 case 2: return " WT"; 163 case 3: return " WB"; 164 case 4: return " WT (CLOS1)"; 165 case 5: return " WB (CLOS1)"; 166 case 6: return " WT (CLOS2)"; 167 case 7: return " WT (CLOS2)"; 168 default: return " not defined"; 169 } 170 } else if (GRAPHICS_VER(i915) >= 12) { 171 switch (obj->pat_index) { 172 case 0: return " WB"; 173 case 1: return " WC"; 174 case 2: return " WT"; 175 case 3: return " UC"; 176 default: return " not defined"; 177 } 178 } else { 179 switch (obj->pat_index) { 180 case 0: return " UC"; 181 case 1: return HAS_LLC(i915) ? 182 " LLC" : " snooped"; 183 case 2: return " L3+LLC"; 184 case 3: return " WT"; 185 default: return " not defined"; 186 } 187 } 188 } 189 190 void 191 i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) 192 { 193 struct i915_vma *vma; 194 int pin_count = 0; 195 196 seq_printf(m, "%pK: %c%c%c %8zdKiB %02x %02x %s%s%s", 197 &obj->base, 198 get_tiling_flag(obj), 199 get_global_flag(obj), 200 get_pin_mapped_flag(obj), 201 obj->base.size / 1024, 202 obj->read_domains, 203 obj->write_domain, 204 i915_cache_level_str(obj), 205 obj->mm.dirty ? " dirty" : "", 206 obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : ""); 207 if (obj->base.name) 208 seq_printf(m, " (name: %d)", obj->base.name); 209 210 spin_lock(&obj->vma.lock); 211 list_for_each_entry(vma, &obj->vma.list, obj_link) { 212 if (!drm_mm_node_allocated(&vma->node)) 213 continue; 214 215 spin_unlock(&obj->vma.lock); 216 217 if (i915_vma_is_pinned(vma)) 218 pin_count++; 219 220 seq_printf(m, " (%s offset: %08llx, size: %08llx, pages: %s", 221 stringify_vma_type(vma), 222 i915_vma_offset(vma), i915_vma_size(vma), 223 stringify_page_sizes(vma->resource->page_sizes_gtt, 224 NULL, 0)); 225 if (i915_vma_is_ggtt(vma) || i915_vma_is_dpt(vma)) { 226 switch (vma->gtt_view.type) { 227 case I915_GTT_VIEW_NORMAL: 228 seq_puts(m, ", normal"); 229 break; 230 231 case I915_GTT_VIEW_PARTIAL: 232 seq_printf(m, ", partial [%08llx+%x]", 233 vma->gtt_view.partial.offset << PAGE_SHIFT, 234 vma->gtt_view.partial.size << PAGE_SHIFT); 235 break; 236 237 case I915_GTT_VIEW_ROTATED: 238 seq_printf(m, ", rotated [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]", 239 vma->gtt_view.rotated.plane[0].width, 240 vma->gtt_view.rotated.plane[0].height, 241 vma->gtt_view.rotated.plane[0].src_stride, 242 vma->gtt_view.rotated.plane[0].dst_stride, 243 vma->gtt_view.rotated.plane[0].offset, 244 vma->gtt_view.rotated.plane[1].width, 245 vma->gtt_view.rotated.plane[1].height, 246 vma->gtt_view.rotated.plane[1].src_stride, 247 vma->gtt_view.rotated.plane[1].dst_stride, 248 vma->gtt_view.rotated.plane[1].offset); 249 break; 250 251 case I915_GTT_VIEW_REMAPPED: 252 seq_printf(m, ", remapped [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]", 253 vma->gtt_view.remapped.plane[0].width, 254 vma->gtt_view.remapped.plane[0].height, 255 vma->gtt_view.remapped.plane[0].src_stride, 256 vma->gtt_view.remapped.plane[0].dst_stride, 257 vma->gtt_view.remapped.plane[0].offset, 258 vma->gtt_view.remapped.plane[1].width, 259 vma->gtt_view.remapped.plane[1].height, 260 vma->gtt_view.remapped.plane[1].src_stride, 261 vma->gtt_view.remapped.plane[1].dst_stride, 262 vma->gtt_view.remapped.plane[1].offset); 263 break; 264 265 default: 266 MISSING_CASE(vma->gtt_view.type); 267 break; 268 } 269 } 270 if (vma->fence) 271 seq_printf(m, " , fence: %d", vma->fence->id); 272 seq_puts(m, ")"); 273 274 spin_lock(&obj->vma.lock); 275 } 276 spin_unlock(&obj->vma.lock); 277 278 seq_printf(m, " (pinned x %d)", pin_count); 279 if (i915_gem_object_is_stolen(obj)) 280 seq_printf(m, " (stolen: %08llx)", obj->stolen->start); 281 if (i915_gem_object_is_framebuffer(obj)) 282 seq_printf(m, " (fb)"); 283 } 284 285 static int i915_gem_object_info(struct seq_file *m, void *data) 286 { 287 struct drm_i915_private *i915 = node_to_i915(m->private); 288 struct drm_printer p = drm_seq_file_printer(m); 289 struct intel_memory_region *mr; 290 enum intel_region_id id; 291 292 seq_printf(m, "%u shrinkable [%u free] objects, %llu bytes\n", 293 i915->mm.shrink_count, 294 atomic_read(&i915->mm.free_count), 295 i915->mm.shrink_memory); 296 for_each_memory_region(mr, i915, id) 297 intel_memory_region_debug(mr, &p); 298 299 return 0; 300 } 301 302 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 303 static ssize_t gpu_state_read(struct file *file, char __user *ubuf, 304 size_t count, loff_t *pos) 305 { 306 struct i915_gpu_coredump *error; 307 ssize_t ret; 308 void *buf; 309 310 error = file->private_data; 311 if (!error) 312 return 0; 313 314 /* Bounce buffer required because of kernfs __user API convenience. */ 315 buf = kmalloc(count, GFP_KERNEL); 316 if (!buf) 317 return -ENOMEM; 318 319 ret = i915_gpu_coredump_copy_to_buffer(error, buf, *pos, count); 320 if (ret <= 0) 321 goto out; 322 323 if (!copy_to_user(ubuf, buf, ret)) 324 *pos += ret; 325 else 326 ret = -EFAULT; 327 328 out: 329 kfree(buf); 330 return ret; 331 } 332 333 static int gpu_state_release(struct inode *inode, struct file *file) 334 { 335 i915_gpu_coredump_put(file->private_data); 336 return 0; 337 } 338 339 static int i915_gpu_info_open(struct inode *inode, struct file *file) 340 { 341 struct drm_i915_private *i915 = inode->i_private; 342 struct i915_gpu_coredump *gpu; 343 intel_wakeref_t wakeref; 344 345 gpu = NULL; 346 with_intel_runtime_pm(&i915->runtime_pm, wakeref) 347 gpu = i915_gpu_coredump(to_gt(i915), ALL_ENGINES, CORE_DUMP_FLAG_NONE); 348 349 if (IS_ERR(gpu)) 350 return PTR_ERR(gpu); 351 352 file->private_data = gpu; 353 return 0; 354 } 355 356 static const struct file_operations i915_gpu_info_fops = { 357 .owner = THIS_MODULE, 358 .open = i915_gpu_info_open, 359 .read = gpu_state_read, 360 .llseek = default_llseek, 361 .release = gpu_state_release, 362 }; 363 364 static ssize_t 365 i915_error_state_write(struct file *filp, 366 const char __user *ubuf, 367 size_t cnt, 368 loff_t *ppos) 369 { 370 struct i915_gpu_coredump *error = filp->private_data; 371 372 if (!error) 373 return 0; 374 375 drm_dbg(&error->i915->drm, "Resetting error state\n"); 376 i915_reset_error_state(error->i915); 377 378 return cnt; 379 } 380 381 static int i915_error_state_open(struct inode *inode, struct file *file) 382 { 383 struct i915_gpu_coredump *error; 384 385 error = i915_first_error_state(inode->i_private); 386 if (IS_ERR(error)) 387 return PTR_ERR(error); 388 389 file->private_data = error; 390 return 0; 391 } 392 393 static const struct file_operations i915_error_state_fops = { 394 .owner = THIS_MODULE, 395 .open = i915_error_state_open, 396 .read = gpu_state_read, 397 .write = i915_error_state_write, 398 .llseek = default_llseek, 399 .release = gpu_state_release, 400 }; 401 #endif 402 403 static int i915_frequency_info(struct seq_file *m, void *unused) 404 { 405 struct drm_i915_private *i915 = node_to_i915(m->private); 406 struct intel_gt *gt = to_gt(i915); 407 struct drm_printer p = drm_seq_file_printer(m); 408 409 intel_gt_pm_frequency_dump(gt, &p); 410 411 return 0; 412 } 413 414 static const char *swizzle_string(unsigned swizzle) 415 { 416 switch (swizzle) { 417 case I915_BIT_6_SWIZZLE_NONE: 418 return "none"; 419 case I915_BIT_6_SWIZZLE_9: 420 return "bit9"; 421 case I915_BIT_6_SWIZZLE_9_10: 422 return "bit9/bit10"; 423 case I915_BIT_6_SWIZZLE_9_11: 424 return "bit9/bit11"; 425 case I915_BIT_6_SWIZZLE_9_10_11: 426 return "bit9/bit10/bit11"; 427 case I915_BIT_6_SWIZZLE_9_17: 428 return "bit9/bit17"; 429 case I915_BIT_6_SWIZZLE_9_10_17: 430 return "bit9/bit10/bit17"; 431 case I915_BIT_6_SWIZZLE_UNKNOWN: 432 return "unknown"; 433 } 434 435 return "bug"; 436 } 437 438 static int i915_swizzle_info(struct seq_file *m, void *data) 439 { 440 struct drm_i915_private *dev_priv = node_to_i915(m->private); 441 struct intel_uncore *uncore = &dev_priv->uncore; 442 intel_wakeref_t wakeref; 443 444 seq_printf(m, "bit6 swizzle for X-tiling = %s\n", 445 swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_x)); 446 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", 447 swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_y)); 448 449 if (dev_priv->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES) 450 seq_puts(m, "L-shaped memory detected\n"); 451 452 /* On BDW+, swizzling is not used. See detect_bit_6_swizzle() */ 453 if (GRAPHICS_VER(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) 454 return 0; 455 456 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 457 458 if (IS_GRAPHICS_VER(dev_priv, 3, 4)) { 459 seq_printf(m, "DDC = 0x%08x\n", 460 intel_uncore_read(uncore, DCC)); 461 seq_printf(m, "DDC2 = 0x%08x\n", 462 intel_uncore_read(uncore, DCC2)); 463 seq_printf(m, "C0DRB3 = 0x%04x\n", 464 intel_uncore_read16(uncore, C0DRB3_BW)); 465 seq_printf(m, "C1DRB3 = 0x%04x\n", 466 intel_uncore_read16(uncore, C1DRB3_BW)); 467 } else if (GRAPHICS_VER(dev_priv) >= 6) { 468 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", 469 intel_uncore_read(uncore, MAD_DIMM_C0)); 470 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", 471 intel_uncore_read(uncore, MAD_DIMM_C1)); 472 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", 473 intel_uncore_read(uncore, MAD_DIMM_C2)); 474 seq_printf(m, "TILECTL = 0x%08x\n", 475 intel_uncore_read(uncore, TILECTL)); 476 if (GRAPHICS_VER(dev_priv) >= 8) 477 seq_printf(m, "GAMTARBMODE = 0x%08x\n", 478 intel_uncore_read(uncore, GAMTARBMODE)); 479 else 480 seq_printf(m, "ARB_MODE = 0x%08x\n", 481 intel_uncore_read(uncore, ARB_MODE)); 482 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", 483 intel_uncore_read(uncore, DISP_ARB_CTL)); 484 } 485 486 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 487 488 return 0; 489 } 490 491 static int i915_rps_boost_info(struct seq_file *m, void *data) 492 { 493 struct drm_i915_private *dev_priv = node_to_i915(m->private); 494 struct intel_rps *rps = &to_gt(dev_priv)->rps; 495 496 seq_printf(m, "RPS enabled? %s\n", 497 str_yes_no(intel_rps_is_enabled(rps))); 498 seq_printf(m, "RPS active? %s\n", 499 str_yes_no(intel_rps_is_active(rps))); 500 seq_printf(m, "GPU busy? %s\n", str_yes_no(to_gt(dev_priv)->awake)); 501 seq_printf(m, "Boosts outstanding? %d\n", 502 atomic_read(&rps->num_waiters)); 503 seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive)); 504 seq_printf(m, "Frequency requested %d, actual %d\n", 505 intel_gpu_freq(rps, rps->cur_freq), 506 intel_rps_read_actual_frequency(rps)); 507 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", 508 intel_gpu_freq(rps, rps->min_freq), 509 intel_gpu_freq(rps, rps->min_freq_softlimit), 510 intel_gpu_freq(rps, rps->max_freq_softlimit), 511 intel_gpu_freq(rps, rps->max_freq)); 512 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", 513 intel_gpu_freq(rps, rps->idle_freq), 514 intel_gpu_freq(rps, rps->efficient_freq), 515 intel_gpu_freq(rps, rps->boost_freq)); 516 517 seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts)); 518 519 return 0; 520 } 521 522 static int i915_runtime_pm_status(struct seq_file *m, void *unused) 523 { 524 struct drm_i915_private *dev_priv = node_to_i915(m->private); 525 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 526 527 if (!HAS_RUNTIME_PM(dev_priv)) 528 seq_puts(m, "Runtime power management not supported\n"); 529 530 seq_printf(m, "Runtime power status: %s\n", 531 str_enabled_disabled(!dev_priv->display.power.domains.init_wakeref)); 532 533 seq_printf(m, "GPU idle: %s\n", str_yes_no(!to_gt(dev_priv)->awake)); 534 seq_printf(m, "IRQs disabled: %s\n", 535 str_yes_no(!intel_irqs_enabled(dev_priv))); 536 #ifdef CONFIG_PM 537 seq_printf(m, "Usage count: %d\n", 538 atomic_read(&dev_priv->drm.dev->power.usage_count)); 539 #else 540 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); 541 #endif 542 seq_printf(m, "PCI device power state: %s [%d]\n", 543 pci_power_name(pdev->current_state), 544 pdev->current_state); 545 546 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) { 547 struct drm_printer p = drm_seq_file_printer(m); 548 549 print_intel_runtime_pm_wakeref(&dev_priv->runtime_pm, &p); 550 } 551 552 return 0; 553 } 554 555 static int i915_engine_info(struct seq_file *m, void *unused) 556 { 557 struct drm_i915_private *i915 = node_to_i915(m->private); 558 struct intel_engine_cs *engine; 559 intel_wakeref_t wakeref; 560 struct drm_printer p; 561 562 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 563 564 seq_printf(m, "GT awake? %s [%d], %llums\n", 565 str_yes_no(to_gt(i915)->awake), 566 atomic_read(&to_gt(i915)->wakeref.count), 567 ktime_to_ms(intel_gt_get_awake_time(to_gt(i915)))); 568 seq_printf(m, "CS timestamp frequency: %u Hz, %d ns\n", 569 to_gt(i915)->clock_frequency, 570 to_gt(i915)->clock_period_ns); 571 572 p = drm_seq_file_printer(m); 573 for_each_uabi_engine(engine, i915) 574 intel_engine_dump(engine, &p, "%s\n", engine->name); 575 576 intel_gt_show_timelines(to_gt(i915), &p, i915_request_show_with_schedule); 577 578 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 579 580 return 0; 581 } 582 583 static int i915_wa_registers(struct seq_file *m, void *unused) 584 { 585 struct drm_i915_private *i915 = node_to_i915(m->private); 586 struct intel_engine_cs *engine; 587 588 for_each_uabi_engine(engine, i915) { 589 const struct i915_wa_list *wal = &engine->ctx_wa_list; 590 const struct i915_wa *wa; 591 unsigned int count; 592 593 count = wal->count; 594 if (!count) 595 continue; 596 597 seq_printf(m, "%s: Workarounds applied: %u\n", 598 engine->name, count); 599 600 for (wa = wal->list; count--; wa++) 601 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n", 602 i915_mmio_reg_offset(wa->reg), 603 wa->set, wa->clr); 604 605 seq_printf(m, "\n"); 606 } 607 608 return 0; 609 } 610 611 static int i915_wedged_get(void *data, u64 *val) 612 { 613 struct drm_i915_private *i915 = data; 614 struct intel_gt *gt; 615 unsigned int i; 616 617 *val = 0; 618 619 for_each_gt(gt, i915, i) { 620 int ret; 621 622 ret = intel_gt_debugfs_reset_show(gt, val); 623 if (ret) 624 return ret; 625 626 /* at least one tile should be wedged */ 627 if (*val) 628 break; 629 } 630 631 return 0; 632 } 633 634 static int i915_wedged_set(void *data, u64 val) 635 { 636 struct drm_i915_private *i915 = data; 637 struct intel_gt *gt; 638 unsigned int i; 639 640 for_each_gt(gt, i915, i) 641 intel_gt_debugfs_reset_store(gt, val); 642 643 return 0; 644 } 645 646 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, 647 i915_wedged_get, i915_wedged_set, 648 "%llu\n"); 649 650 static int 651 i915_perf_noa_delay_set(void *data, u64 val) 652 { 653 struct drm_i915_private *i915 = data; 654 655 /* 656 * This would lead to infinite waits as we're doing timestamp 657 * difference on the CS with only 32bits. 658 */ 659 if (intel_gt_ns_to_clock_interval(to_gt(i915), val) > U32_MAX) 660 return -EINVAL; 661 662 atomic64_set(&i915->perf.noa_programming_delay, val); 663 return 0; 664 } 665 666 static int 667 i915_perf_noa_delay_get(void *data, u64 *val) 668 { 669 struct drm_i915_private *i915 = data; 670 671 *val = atomic64_read(&i915->perf.noa_programming_delay); 672 return 0; 673 } 674 675 DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops, 676 i915_perf_noa_delay_get, 677 i915_perf_noa_delay_set, 678 "%llu\n"); 679 680 #define DROP_UNBOUND BIT(0) 681 #define DROP_BOUND BIT(1) 682 #define DROP_RETIRE BIT(2) 683 #define DROP_ACTIVE BIT(3) 684 #define DROP_FREED BIT(4) 685 #define DROP_SHRINK_ALL BIT(5) 686 #define DROP_IDLE BIT(6) 687 #define DROP_RESET_ACTIVE BIT(7) 688 #define DROP_RESET_SEQNO BIT(8) 689 #define DROP_RCU BIT(9) 690 #define DROP_ALL (DROP_UNBOUND | \ 691 DROP_BOUND | \ 692 DROP_RETIRE | \ 693 DROP_ACTIVE | \ 694 DROP_FREED | \ 695 DROP_SHRINK_ALL |\ 696 DROP_IDLE | \ 697 DROP_RESET_ACTIVE | \ 698 DROP_RESET_SEQNO | \ 699 DROP_RCU) 700 static int 701 i915_drop_caches_get(void *data, u64 *val) 702 { 703 *val = DROP_ALL; 704 705 return 0; 706 } 707 708 static int 709 gt_drop_caches(struct intel_gt *gt, u64 val) 710 { 711 int ret; 712 713 if (val & DROP_RESET_ACTIVE && 714 wait_for(intel_engines_are_idle(gt), 200)) 715 intel_gt_set_wedged(gt); 716 717 if (val & DROP_RETIRE) 718 intel_gt_retire_requests(gt); 719 720 if (val & (DROP_IDLE | DROP_ACTIVE)) { 721 ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT); 722 if (ret) 723 return ret; 724 } 725 726 if (val & DROP_IDLE) { 727 ret = intel_gt_pm_wait_for_idle(gt); 728 if (ret) 729 return ret; 730 } 731 732 if (val & DROP_RESET_ACTIVE && intel_gt_terminally_wedged(gt)) 733 intel_gt_handle_error(gt, ALL_ENGINES, 0, NULL); 734 735 if (val & DROP_FREED) 736 intel_gt_flush_buffer_pool(gt); 737 738 return 0; 739 } 740 741 static int 742 i915_drop_caches_set(void *data, u64 val) 743 { 744 struct drm_i915_private *i915 = data; 745 struct intel_gt *gt; 746 unsigned int flags; 747 unsigned int i; 748 int ret; 749 750 drm_dbg(&i915->drm, "Dropping caches: 0x%08llx [0x%08llx]\n", 751 val, val & DROP_ALL); 752 753 for_each_gt(gt, i915, i) { 754 ret = gt_drop_caches(gt, val); 755 if (ret) 756 return ret; 757 } 758 759 fs_reclaim_acquire(GFP_KERNEL); 760 flags = memalloc_noreclaim_save(); 761 if (val & DROP_BOUND) 762 i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_BOUND); 763 764 if (val & DROP_UNBOUND) 765 i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_UNBOUND); 766 767 if (val & DROP_SHRINK_ALL) 768 i915_gem_shrink_all(i915); 769 memalloc_noreclaim_restore(flags); 770 fs_reclaim_release(GFP_KERNEL); 771 772 if (val & DROP_RCU) 773 rcu_barrier(); 774 775 if (val & DROP_FREED) 776 i915_gem_drain_freed_objects(i915); 777 778 return 0; 779 } 780 781 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, 782 i915_drop_caches_get, i915_drop_caches_set, 783 "0x%08llx\n"); 784 785 static int i915_sseu_status(struct seq_file *m, void *unused) 786 { 787 struct drm_i915_private *i915 = node_to_i915(m->private); 788 struct intel_gt *gt = to_gt(i915); 789 790 return intel_sseu_status(m, gt); 791 } 792 793 static int i915_forcewake_open(struct inode *inode, struct file *file) 794 { 795 struct drm_i915_private *i915 = inode->i_private; 796 struct intel_gt *gt; 797 unsigned int i; 798 799 for_each_gt(gt, i915, i) 800 intel_gt_pm_debugfs_forcewake_user_open(gt); 801 802 return 0; 803 } 804 805 static int i915_forcewake_release(struct inode *inode, struct file *file) 806 { 807 struct drm_i915_private *i915 = inode->i_private; 808 struct intel_gt *gt; 809 unsigned int i; 810 811 for_each_gt(gt, i915, i) 812 intel_gt_pm_debugfs_forcewake_user_release(gt); 813 814 return 0; 815 } 816 817 static const struct file_operations i915_forcewake_fops = { 818 .owner = THIS_MODULE, 819 .open = i915_forcewake_open, 820 .release = i915_forcewake_release, 821 }; 822 823 static const struct drm_info_list i915_debugfs_list[] = { 824 {"i915_capabilities", i915_capabilities, 0}, 825 {"i915_gem_objects", i915_gem_object_info, 0}, 826 {"i915_frequency_info", i915_frequency_info, 0}, 827 {"i915_swizzle_info", i915_swizzle_info, 0}, 828 {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, 829 {"i915_engine_info", i915_engine_info, 0}, 830 {"i915_wa_registers", i915_wa_registers, 0}, 831 {"i915_sseu_status", i915_sseu_status, 0}, 832 {"i915_rps_boost_info", i915_rps_boost_info, 0}, 833 }; 834 835 static const struct i915_debugfs_files { 836 const char *name; 837 const struct file_operations *fops; 838 } i915_debugfs_files[] = { 839 {"i915_perf_noa_delay", &i915_perf_noa_delay_fops}, 840 {"i915_wedged", &i915_wedged_fops}, 841 {"i915_gem_drop_caches", &i915_drop_caches_fops}, 842 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 843 {"i915_error_state", &i915_error_state_fops}, 844 {"i915_gpu_info", &i915_gpu_info_fops}, 845 #endif 846 }; 847 848 void i915_debugfs_register(struct drm_i915_private *dev_priv) 849 { 850 struct drm_minor *minor = dev_priv->drm.primary; 851 int i; 852 853 i915_debugfs_params(dev_priv); 854 855 debugfs_create_file("i915_forcewake_user", S_IRUSR, minor->debugfs_root, 856 to_i915(minor->dev), &i915_forcewake_fops); 857 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { 858 debugfs_create_file(i915_debugfs_files[i].name, 859 S_IRUGO | S_IWUSR, 860 minor->debugfs_root, 861 to_i915(minor->dev), 862 i915_debugfs_files[i].fops); 863 } 864 865 drm_debugfs_create_files(i915_debugfs_list, 866 ARRAY_SIZE(i915_debugfs_list), 867 minor->debugfs_root, minor); 868 } 869