1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * 27 */ 28 29 #include <linux/debugfs.h> 30 #include <linux/sched/mm.h> 31 #include <linux/sort.h> 32 #include <linux/string_helpers.h> 33 34 #include <drm/drm_debugfs.h> 35 #include <drm/drm_print.h> 36 #include <drm/intel/intel_gmd_misc_regs.h> 37 38 #include "gem/i915_gem_context.h" 39 #include "gt/intel_gt.h" 40 #include "gt/intel_gt_buffer_pool.h" 41 #include "gt/intel_gt_clock_utils.h" 42 #include "gt/intel_gt_debugfs.h" 43 #include "gt/intel_gt_pm.h" 44 #include "gt/intel_gt_pm_debugfs.h" 45 #include "gt/intel_gt_regs.h" 46 #include "gt/intel_gt_requests.h" 47 #include "gt/intel_rc6.h" 48 #include "gt/intel_reset.h" 49 #include "gt/intel_rps.h" 50 #include "gt/intel_sseu_debugfs.h" 51 52 #include "i915_debugfs.h" 53 #include "i915_debugfs_params.h" 54 #include "i915_driver.h" 55 #include "i915_gpu_error.h" 56 #include "i915_irq.h" 57 #include "i915_reg.h" 58 #include "i915_scheduler.h" 59 #include "i915_wait_util.h" 60 #include "intel_mchbar_regs.h" 61 62 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) 63 { 64 return to_i915(node->minor->dev); 65 } 66 67 static int i915_capabilities(struct seq_file *m, void *data) 68 { 69 struct drm_i915_private *i915 = node_to_i915(m->private); 70 struct drm_printer p = drm_seq_file_printer(m); 71 72 intel_device_info_print(INTEL_INFO(i915), RUNTIME_INFO(i915), &p); 73 i915_print_iommu_status(i915, &p); 74 intel_gt_info_print(&to_gt(i915)->info, &p); 75 intel_driver_caps_print(&i915->caps, &p); 76 77 i915_params_dump(&i915->params, &p); 78 79 return 0; 80 } 81 82 static char get_tiling_flag(struct drm_i915_gem_object *obj) 83 { 84 switch (i915_gem_object_get_tiling(obj)) { 85 default: 86 case I915_TILING_NONE: return ' '; 87 case I915_TILING_X: return 'X'; 88 case I915_TILING_Y: return 'Y'; 89 } 90 } 91 92 static char get_global_flag(struct drm_i915_gem_object *obj) 93 { 94 return READ_ONCE(obj->userfault_count) ? 'g' : ' '; 95 } 96 97 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) 98 { 99 return obj->mm.mapping ? 'M' : ' '; 100 } 101 102 static const char * 103 stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len) 104 { 105 size_t x = 0; 106 107 switch (page_sizes) { 108 case 0: 109 return ""; 110 case I915_GTT_PAGE_SIZE_4K: 111 return "4K"; 112 case I915_GTT_PAGE_SIZE_64K: 113 return "64K"; 114 case I915_GTT_PAGE_SIZE_2M: 115 return "2M"; 116 default: 117 if (!buf) 118 return "M"; 119 120 if (page_sizes & I915_GTT_PAGE_SIZE_2M) 121 x += snprintf(buf + x, len - x, "2M, "); 122 if (page_sizes & I915_GTT_PAGE_SIZE_64K) 123 x += snprintf(buf + x, len - x, "64K, "); 124 if (page_sizes & I915_GTT_PAGE_SIZE_4K) 125 x += snprintf(buf + x, len - x, "4K, "); 126 buf[x-2] = '\0'; 127 128 return buf; 129 } 130 } 131 132 static const char *stringify_vma_type(const struct i915_vma *vma) 133 { 134 if (i915_vma_is_ggtt(vma)) 135 return "ggtt"; 136 137 if (i915_vma_is_dpt(vma)) 138 return "dpt"; 139 140 return "ppgtt"; 141 } 142 143 static const char *i915_cache_level_str(struct drm_i915_gem_object *obj) 144 { 145 struct drm_i915_private *i915 = obj_to_i915(obj); 146 147 if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 74))) { 148 switch (obj->pat_index) { 149 case 0: return " WB"; 150 case 1: return " WT"; 151 case 2: return " UC"; 152 case 3: return " WB (1-Way Coh)"; 153 case 4: return " WB (2-Way Coh)"; 154 default: return " not defined"; 155 } 156 } else if (GRAPHICS_VER(i915) >= 12) { 157 switch (obj->pat_index) { 158 case 0: return " WB"; 159 case 1: return " WC"; 160 case 2: return " WT"; 161 case 3: return " UC"; 162 default: return " not defined"; 163 } 164 } else { 165 switch (obj->pat_index) { 166 case 0: return " UC"; 167 case 1: return HAS_LLC(i915) ? 168 " LLC" : " snooped"; 169 case 2: return " L3+LLC"; 170 case 3: return " WT"; 171 default: return " not defined"; 172 } 173 } 174 } 175 176 void 177 i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) 178 { 179 struct i915_vma *vma; 180 int pin_count = 0; 181 182 seq_printf(m, "%pK: %c%c%c %8zdKiB %02x %02x %s%s%s", 183 &obj->base, 184 get_tiling_flag(obj), 185 get_global_flag(obj), 186 get_pin_mapped_flag(obj), 187 obj->base.size / 1024, 188 obj->read_domains, 189 obj->write_domain, 190 i915_cache_level_str(obj), 191 obj->mm.dirty ? " dirty" : "", 192 obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : ""); 193 if (obj->base.name) 194 seq_printf(m, " (name: %d)", obj->base.name); 195 196 spin_lock(&obj->vma.lock); 197 list_for_each_entry(vma, &obj->vma.list, obj_link) { 198 if (!drm_mm_node_allocated(&vma->node)) 199 continue; 200 201 spin_unlock(&obj->vma.lock); 202 203 if (i915_vma_is_pinned(vma)) 204 pin_count++; 205 206 seq_printf(m, " (%s offset: %08llx, size: %08llx, pages: %s", 207 stringify_vma_type(vma), 208 i915_vma_offset(vma), i915_vma_size(vma), 209 stringify_page_sizes(vma->resource->page_sizes_gtt, 210 NULL, 0)); 211 if (i915_vma_is_ggtt(vma) || i915_vma_is_dpt(vma)) { 212 switch (vma->gtt_view.type) { 213 case I915_GTT_VIEW_NORMAL: 214 seq_puts(m, ", normal"); 215 break; 216 217 case I915_GTT_VIEW_PARTIAL: 218 seq_printf(m, ", partial [%08llx+%x]", 219 vma->gtt_view.partial.offset << PAGE_SHIFT, 220 vma->gtt_view.partial.size << PAGE_SHIFT); 221 break; 222 223 case I915_GTT_VIEW_ROTATED: 224 seq_printf(m, ", rotated [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]", 225 vma->gtt_view.rotated.plane[0].width, 226 vma->gtt_view.rotated.plane[0].height, 227 vma->gtt_view.rotated.plane[0].src_stride, 228 vma->gtt_view.rotated.plane[0].dst_stride, 229 vma->gtt_view.rotated.plane[0].offset, 230 vma->gtt_view.rotated.plane[1].width, 231 vma->gtt_view.rotated.plane[1].height, 232 vma->gtt_view.rotated.plane[1].src_stride, 233 vma->gtt_view.rotated.plane[1].dst_stride, 234 vma->gtt_view.rotated.plane[1].offset); 235 break; 236 237 case I915_GTT_VIEW_REMAPPED: 238 seq_printf(m, ", remapped [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]", 239 vma->gtt_view.remapped.plane[0].width, 240 vma->gtt_view.remapped.plane[0].height, 241 vma->gtt_view.remapped.plane[0].src_stride, 242 vma->gtt_view.remapped.plane[0].dst_stride, 243 vma->gtt_view.remapped.plane[0].offset, 244 vma->gtt_view.remapped.plane[1].width, 245 vma->gtt_view.remapped.plane[1].height, 246 vma->gtt_view.remapped.plane[1].src_stride, 247 vma->gtt_view.remapped.plane[1].dst_stride, 248 vma->gtt_view.remapped.plane[1].offset); 249 break; 250 251 default: 252 MISSING_CASE(vma->gtt_view.type); 253 break; 254 } 255 } 256 if (vma->fence) 257 seq_printf(m, " , fence: %d", vma->fence->id); 258 seq_puts(m, ")"); 259 260 spin_lock(&obj->vma.lock); 261 } 262 spin_unlock(&obj->vma.lock); 263 264 seq_printf(m, " (pinned x %d)", pin_count); 265 if (i915_gem_object_is_stolen(obj)) 266 seq_printf(m, " (stolen: %08llx)", obj->stolen->start); 267 if (i915_gem_object_is_framebuffer(obj)) 268 seq_printf(m, " (fb)"); 269 } 270 271 static int i915_gem_object_info(struct seq_file *m, void *data) 272 { 273 struct drm_i915_private *i915 = node_to_i915(m->private); 274 struct drm_printer p = drm_seq_file_printer(m); 275 struct intel_memory_region *mr; 276 enum intel_region_id id; 277 278 seq_printf(m, "%u shrinkable [%u free] objects, %llu bytes\n", 279 i915->mm.shrink_count, 280 atomic_read(&i915->mm.free_count), 281 i915->mm.shrink_memory); 282 for_each_memory_region(mr, i915, id) 283 intel_memory_region_debug(mr, &p); 284 285 return 0; 286 } 287 288 static int i915_frequency_info(struct seq_file *m, void *unused) 289 { 290 struct drm_i915_private *i915 = node_to_i915(m->private); 291 struct intel_gt *gt = to_gt(i915); 292 struct drm_printer p = drm_seq_file_printer(m); 293 294 intel_gt_pm_frequency_dump(gt, &p); 295 296 return 0; 297 } 298 299 static const char *swizzle_string(unsigned swizzle) 300 { 301 switch (swizzle) { 302 case I915_BIT_6_SWIZZLE_NONE: 303 return "none"; 304 case I915_BIT_6_SWIZZLE_9: 305 return "bit9"; 306 case I915_BIT_6_SWIZZLE_9_10: 307 return "bit9/bit10"; 308 case I915_BIT_6_SWIZZLE_9_11: 309 return "bit9/bit11"; 310 case I915_BIT_6_SWIZZLE_9_10_11: 311 return "bit9/bit10/bit11"; 312 case I915_BIT_6_SWIZZLE_9_17: 313 return "bit9/bit17"; 314 case I915_BIT_6_SWIZZLE_9_10_17: 315 return "bit9/bit10/bit17"; 316 case I915_BIT_6_SWIZZLE_UNKNOWN: 317 return "unknown"; 318 } 319 320 return "bug"; 321 } 322 323 static int i915_swizzle_info(struct seq_file *m, void *data) 324 { 325 struct drm_i915_private *dev_priv = node_to_i915(m->private); 326 struct intel_uncore *uncore = &dev_priv->uncore; 327 intel_wakeref_t wakeref; 328 329 seq_printf(m, "bit6 swizzle for X-tiling = %s\n", 330 swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_x)); 331 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", 332 swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_y)); 333 334 if (dev_priv->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES) 335 seq_puts(m, "L-shaped memory detected\n"); 336 337 /* On BDW+, swizzling is not used. See detect_bit_6_swizzle() */ 338 if (GRAPHICS_VER(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) 339 return 0; 340 341 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 342 343 if (IS_GRAPHICS_VER(dev_priv, 3, 4)) { 344 seq_printf(m, "DDC = 0x%08x\n", 345 intel_uncore_read(uncore, DCC)); 346 seq_printf(m, "DDC2 = 0x%08x\n", 347 intel_uncore_read(uncore, DCC2)); 348 seq_printf(m, "C0DRB3 = 0x%04x\n", 349 intel_uncore_read16(uncore, C0DRB3_BW)); 350 seq_printf(m, "C1DRB3 = 0x%04x\n", 351 intel_uncore_read16(uncore, C1DRB3_BW)); 352 } else if (GRAPHICS_VER(dev_priv) >= 6) { 353 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", 354 intel_uncore_read(uncore, MAD_DIMM_C0)); 355 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", 356 intel_uncore_read(uncore, MAD_DIMM_C1)); 357 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", 358 intel_uncore_read(uncore, MAD_DIMM_C2)); 359 seq_printf(m, "TILECTL = 0x%08x\n", 360 intel_uncore_read(uncore, TILECTL)); 361 if (GRAPHICS_VER(dev_priv) >= 8) 362 seq_printf(m, "GAMTARBMODE = 0x%08x\n", 363 intel_uncore_read(uncore, GAMTARBMODE)); 364 else 365 seq_printf(m, "ARB_MODE = 0x%08x\n", 366 intel_uncore_read(uncore, ARB_MODE)); 367 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", 368 intel_uncore_read(uncore, DISP_ARB_CTL)); 369 } 370 371 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 372 373 return 0; 374 } 375 376 static int i915_rps_boost_info(struct seq_file *m, void *data) 377 { 378 struct drm_i915_private *dev_priv = node_to_i915(m->private); 379 struct intel_rps *rps = &to_gt(dev_priv)->rps; 380 381 seq_printf(m, "RPS enabled? %s\n", 382 str_yes_no(intel_rps_is_enabled(rps))); 383 seq_printf(m, "RPS active? %s\n", 384 str_yes_no(intel_rps_is_active(rps))); 385 seq_printf(m, "GPU busy? %s\n", str_yes_no(to_gt(dev_priv)->awake)); 386 seq_printf(m, "Boosts outstanding? %d\n", 387 atomic_read(&rps->num_waiters)); 388 seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive)); 389 seq_printf(m, "Frequency requested %d, actual %d\n", 390 intel_gpu_freq(rps, rps->cur_freq), 391 intel_rps_read_actual_frequency(rps)); 392 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", 393 intel_gpu_freq(rps, rps->min_freq), 394 intel_gpu_freq(rps, rps->min_freq_softlimit), 395 intel_gpu_freq(rps, rps->max_freq_softlimit), 396 intel_gpu_freq(rps, rps->max_freq)); 397 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", 398 intel_gpu_freq(rps, rps->idle_freq), 399 intel_gpu_freq(rps, rps->efficient_freq), 400 intel_gpu_freq(rps, rps->boost_freq)); 401 402 seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts)); 403 404 return 0; 405 } 406 407 static int i915_runtime_pm_status(struct seq_file *m, void *unused) 408 { 409 struct drm_i915_private *dev_priv = node_to_i915(m->private); 410 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 411 412 if (!HAS_RUNTIME_PM(dev_priv)) 413 seq_puts(m, "Runtime power management not supported\n"); 414 415 seq_printf(m, "GPU idle: %s\n", str_yes_no(!to_gt(dev_priv)->awake)); 416 seq_printf(m, "IRQs disabled: %s\n", 417 str_yes_no(!intel_irqs_enabled(dev_priv))); 418 #ifdef CONFIG_PM 419 seq_printf(m, "Usage count: %d\n", 420 atomic_read(&dev_priv->drm.dev->power.usage_count)); 421 #else 422 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); 423 #endif 424 seq_printf(m, "PCI device power state: %s [%d]\n", 425 pci_power_name(pdev->current_state), 426 pdev->current_state); 427 428 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) { 429 struct drm_printer p = drm_seq_file_printer(m); 430 431 print_intel_runtime_pm_wakeref(&dev_priv->runtime_pm, &p); 432 } 433 434 return 0; 435 } 436 437 static int i915_engine_info(struct seq_file *m, void *unused) 438 { 439 struct drm_i915_private *i915 = node_to_i915(m->private); 440 struct intel_engine_cs *engine; 441 intel_wakeref_t wakeref; 442 struct drm_printer p; 443 444 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 445 446 seq_printf(m, "GT awake? %s [%d], %llums\n", 447 str_yes_no(to_gt(i915)->awake), 448 atomic_read(&to_gt(i915)->wakeref.count), 449 ktime_to_ms(intel_gt_get_awake_time(to_gt(i915)))); 450 seq_printf(m, "CS timestamp frequency: %u Hz, %d ns\n", 451 to_gt(i915)->clock_frequency, 452 to_gt(i915)->clock_period_ns); 453 454 p = drm_seq_file_printer(m); 455 for_each_uabi_engine(engine, i915) 456 intel_engine_dump(engine, &p, "%s\n", engine->name); 457 458 intel_gt_show_timelines(to_gt(i915), &p, i915_request_show_with_schedule); 459 460 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 461 462 return 0; 463 } 464 465 static int i915_wa_registers(struct seq_file *m, void *unused) 466 { 467 struct drm_i915_private *i915 = node_to_i915(m->private); 468 struct intel_engine_cs *engine; 469 470 for_each_uabi_engine(engine, i915) { 471 const struct i915_wa_list *wal = &engine->ctx_wa_list; 472 const struct i915_wa *wa; 473 unsigned int count; 474 475 count = wal->count; 476 if (!count) 477 continue; 478 479 seq_printf(m, "%s: Workarounds applied: %u\n", 480 engine->name, count); 481 482 for (wa = wal->list; count--; wa++) 483 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n", 484 i915_mmio_reg_offset(wa->reg), 485 wa->set, wa->clr); 486 487 seq_printf(m, "\n"); 488 } 489 490 return 0; 491 } 492 493 static int i915_wedged_get(void *data, u64 *val) 494 { 495 struct drm_i915_private *i915 = data; 496 struct intel_gt *gt; 497 unsigned int i; 498 499 *val = 0; 500 501 for_each_gt(gt, i915, i) { 502 int ret; 503 504 ret = intel_gt_debugfs_reset_show(gt, val); 505 if (ret) 506 return ret; 507 508 /* at least one tile should be wedged */ 509 if (*val) 510 break; 511 } 512 513 return 0; 514 } 515 516 static int i915_wedged_set(void *data, u64 val) 517 { 518 struct drm_i915_private *i915 = data; 519 struct intel_gt *gt; 520 unsigned int i; 521 522 for_each_gt(gt, i915, i) 523 intel_gt_debugfs_reset_store(gt, val); 524 525 return 0; 526 } 527 528 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, 529 i915_wedged_get, i915_wedged_set, 530 "%llu\n"); 531 532 static int 533 i915_perf_noa_delay_set(void *data, u64 val) 534 { 535 struct drm_i915_private *i915 = data; 536 537 /* 538 * This would lead to infinite waits as we're doing timestamp 539 * difference on the CS with only 32bits. 540 */ 541 if (intel_gt_ns_to_clock_interval(to_gt(i915), val) > U32_MAX) 542 return -EINVAL; 543 544 atomic64_set(&i915->perf.noa_programming_delay, val); 545 return 0; 546 } 547 548 static int 549 i915_perf_noa_delay_get(void *data, u64 *val) 550 { 551 struct drm_i915_private *i915 = data; 552 553 *val = atomic64_read(&i915->perf.noa_programming_delay); 554 return 0; 555 } 556 557 DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops, 558 i915_perf_noa_delay_get, 559 i915_perf_noa_delay_set, 560 "%llu\n"); 561 562 #define DROP_UNBOUND BIT(0) 563 #define DROP_BOUND BIT(1) 564 #define DROP_RETIRE BIT(2) 565 #define DROP_ACTIVE BIT(3) 566 #define DROP_FREED BIT(4) 567 #define DROP_SHRINK_ALL BIT(5) 568 #define DROP_IDLE BIT(6) 569 #define DROP_RESET_ACTIVE BIT(7) 570 #define DROP_RESET_SEQNO BIT(8) 571 #define DROP_RCU BIT(9) 572 #define DROP_ALL (DROP_UNBOUND | \ 573 DROP_BOUND | \ 574 DROP_RETIRE | \ 575 DROP_ACTIVE | \ 576 DROP_FREED | \ 577 DROP_SHRINK_ALL |\ 578 DROP_IDLE | \ 579 DROP_RESET_ACTIVE | \ 580 DROP_RESET_SEQNO | \ 581 DROP_RCU) 582 static int 583 i915_drop_caches_get(void *data, u64 *val) 584 { 585 *val = DROP_ALL; 586 587 return 0; 588 } 589 590 static int 591 gt_drop_caches(struct intel_gt *gt, u64 val) 592 { 593 int ret; 594 595 if (val & DROP_RESET_ACTIVE && 596 wait_for(intel_engines_are_idle(gt), 200)) 597 intel_gt_set_wedged(gt); 598 599 if (val & DROP_RETIRE) 600 intel_gt_retire_requests(gt); 601 602 if (val & (DROP_IDLE | DROP_ACTIVE)) { 603 ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT); 604 if (ret) 605 return ret; 606 } 607 608 if (val & DROP_IDLE) { 609 ret = intel_gt_pm_wait_for_idle(gt); 610 if (ret) 611 return ret; 612 } 613 614 if (val & DROP_RESET_ACTIVE && intel_gt_terminally_wedged(gt)) 615 intel_gt_handle_error(gt, ALL_ENGINES, 0, NULL); 616 617 if (val & DROP_FREED) 618 intel_gt_flush_buffer_pool(gt); 619 620 return 0; 621 } 622 623 static int 624 i915_drop_caches_set(void *data, u64 val) 625 { 626 struct drm_i915_private *i915 = data; 627 struct intel_gt *gt; 628 unsigned int flags; 629 unsigned int i; 630 int ret; 631 632 drm_dbg(&i915->drm, "Dropping caches: 0x%08llx [0x%08llx]\n", 633 val, val & DROP_ALL); 634 635 for_each_gt(gt, i915, i) { 636 ret = gt_drop_caches(gt, val); 637 if (ret) 638 return ret; 639 } 640 641 fs_reclaim_acquire(GFP_KERNEL); 642 flags = memalloc_noreclaim_save(); 643 if (val & DROP_BOUND) 644 i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_BOUND); 645 646 if (val & DROP_UNBOUND) 647 i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_UNBOUND); 648 649 if (val & DROP_SHRINK_ALL) 650 i915_gem_shrink_all(i915); 651 memalloc_noreclaim_restore(flags); 652 fs_reclaim_release(GFP_KERNEL); 653 654 if (val & DROP_RCU) 655 rcu_barrier(); 656 657 if (val & DROP_FREED) 658 i915_gem_drain_freed_objects(i915); 659 660 return 0; 661 } 662 663 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, 664 i915_drop_caches_get, i915_drop_caches_set, 665 "0x%08llx\n"); 666 667 static int i915_sseu_status(struct seq_file *m, void *unused) 668 { 669 struct drm_i915_private *i915 = node_to_i915(m->private); 670 struct intel_gt *gt = to_gt(i915); 671 672 return intel_sseu_status(m, gt); 673 } 674 675 static int i915_forcewake_open(struct inode *inode, struct file *file) 676 { 677 struct drm_i915_private *i915 = inode->i_private; 678 struct intel_gt *gt; 679 unsigned int i; 680 681 for_each_gt(gt, i915, i) 682 intel_gt_pm_debugfs_forcewake_user_open(gt); 683 684 return 0; 685 } 686 687 static int i915_forcewake_release(struct inode *inode, struct file *file) 688 { 689 struct drm_i915_private *i915 = inode->i_private; 690 struct intel_gt *gt; 691 unsigned int i; 692 693 for_each_gt(gt, i915, i) 694 intel_gt_pm_debugfs_forcewake_user_release(gt); 695 696 return 0; 697 } 698 699 static const struct file_operations i915_forcewake_fops = { 700 .owner = THIS_MODULE, 701 .open = i915_forcewake_open, 702 .release = i915_forcewake_release, 703 }; 704 705 static const struct drm_info_list i915_debugfs_list[] = { 706 {"i915_capabilities", i915_capabilities, 0}, 707 {"i915_gem_objects", i915_gem_object_info, 0}, 708 {"i915_frequency_info", i915_frequency_info, 0}, 709 {"i915_swizzle_info", i915_swizzle_info, 0}, 710 {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, 711 {"i915_engine_info", i915_engine_info, 0}, 712 {"i915_wa_registers", i915_wa_registers, 0}, 713 {"i915_sseu_status", i915_sseu_status, 0}, 714 {"i915_rps_boost_info", i915_rps_boost_info, 0}, 715 }; 716 717 static const struct i915_debugfs_files { 718 const char *name; 719 const struct file_operations *fops; 720 } i915_debugfs_files[] = { 721 {"i915_perf_noa_delay", &i915_perf_noa_delay_fops}, 722 {"i915_wedged", &i915_wedged_fops}, 723 {"i915_gem_drop_caches", &i915_drop_caches_fops}, 724 }; 725 726 void i915_debugfs_register(struct drm_i915_private *i915) 727 { 728 struct dentry *debugfs_root = i915->drm.debugfs_root; 729 int i; 730 731 i915_debugfs_params(i915); 732 733 debugfs_create_file("i915_forcewake_user", S_IRUSR, debugfs_root, 734 i915, &i915_forcewake_fops); 735 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { 736 debugfs_create_file(i915_debugfs_files[i].name, S_IRUGO | S_IWUSR, 737 debugfs_root, i915, 738 i915_debugfs_files[i].fops); 739 } 740 741 drm_debugfs_create_files(i915_debugfs_list, 742 ARRAY_SIZE(i915_debugfs_list), 743 debugfs_root, i915->drm.primary); 744 745 i915_gpu_error_debugfs_register(i915); 746 } 747