1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * 27 */ 28 29 #include <linux/sched/mm.h> 30 #include <linux/sort.h> 31 #include <linux/string_helpers.h> 32 33 #include <linux/debugfs.h> 34 #include <drm/drm_debugfs.h> 35 36 #include "display/intel_display_params.h" 37 38 #include "gem/i915_gem_context.h" 39 #include "gt/intel_gt.h" 40 #include "gt/intel_gt_buffer_pool.h" 41 #include "gt/intel_gt_clock_utils.h" 42 #include "gt/intel_gt_debugfs.h" 43 #include "gt/intel_gt_pm.h" 44 #include "gt/intel_gt_pm_debugfs.h" 45 #include "gt/intel_gt_regs.h" 46 #include "gt/intel_gt_requests.h" 47 #include "gt/intel_rc6.h" 48 #include "gt/intel_reset.h" 49 #include "gt/intel_rps.h" 50 #include "gt/intel_sseu_debugfs.h" 51 52 #include "i915_debugfs.h" 53 #include "i915_debugfs_params.h" 54 #include "i915_driver.h" 55 #include "i915_gpu_error.h" 56 #include "i915_irq.h" 57 #include "i915_reg.h" 58 #include "i915_scheduler.h" 59 #include "intel_mchbar_regs.h" 60 61 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) 62 { 63 return to_i915(node->minor->dev); 64 } 65 66 static int i915_capabilities(struct seq_file *m, void *data) 67 { 68 struct drm_i915_private *i915 = node_to_i915(m->private); 69 struct drm_printer p = drm_seq_file_printer(m); 70 71 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915)); 72 73 intel_device_info_print(INTEL_INFO(i915), RUNTIME_INFO(i915), &p); 74 i915_print_iommu_status(i915, &p); 75 intel_gt_info_print(&to_gt(i915)->info, &p); 76 intel_driver_caps_print(&i915->caps, &p); 77 78 kernel_param_lock(THIS_MODULE); 79 i915_params_dump(&i915->params, &p); 80 intel_display_params_dump(i915, &p); 81 kernel_param_unlock(THIS_MODULE); 82 83 return 0; 84 } 85 86 static char get_tiling_flag(struct drm_i915_gem_object *obj) 87 { 88 switch (i915_gem_object_get_tiling(obj)) { 89 default: 90 case I915_TILING_NONE: return ' '; 91 case I915_TILING_X: return 'X'; 92 case I915_TILING_Y: return 'Y'; 93 } 94 } 95 96 static char get_global_flag(struct drm_i915_gem_object *obj) 97 { 98 return READ_ONCE(obj->userfault_count) ? 'g' : ' '; 99 } 100 101 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) 102 { 103 return obj->mm.mapping ? 'M' : ' '; 104 } 105 106 static const char * 107 stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len) 108 { 109 size_t x = 0; 110 111 switch (page_sizes) { 112 case 0: 113 return ""; 114 case I915_GTT_PAGE_SIZE_4K: 115 return "4K"; 116 case I915_GTT_PAGE_SIZE_64K: 117 return "64K"; 118 case I915_GTT_PAGE_SIZE_2M: 119 return "2M"; 120 default: 121 if (!buf) 122 return "M"; 123 124 if (page_sizes & I915_GTT_PAGE_SIZE_2M) 125 x += snprintf(buf + x, len - x, "2M, "); 126 if (page_sizes & I915_GTT_PAGE_SIZE_64K) 127 x += snprintf(buf + x, len - x, "64K, "); 128 if (page_sizes & I915_GTT_PAGE_SIZE_4K) 129 x += snprintf(buf + x, len - x, "4K, "); 130 buf[x-2] = '\0'; 131 132 return buf; 133 } 134 } 135 136 static const char *stringify_vma_type(const struct i915_vma *vma) 137 { 138 if (i915_vma_is_ggtt(vma)) 139 return "ggtt"; 140 141 if (i915_vma_is_dpt(vma)) 142 return "dpt"; 143 144 return "ppgtt"; 145 } 146 147 static const char *i915_cache_level_str(struct drm_i915_gem_object *obj) 148 { 149 struct drm_i915_private *i915 = obj_to_i915(obj); 150 151 if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 74))) { 152 switch (obj->pat_index) { 153 case 0: return " WB"; 154 case 1: return " WT"; 155 case 2: return " UC"; 156 case 3: return " WB (1-Way Coh)"; 157 case 4: return " WB (2-Way Coh)"; 158 default: return " not defined"; 159 } 160 } else if (GRAPHICS_VER(i915) >= 12) { 161 switch (obj->pat_index) { 162 case 0: return " WB"; 163 case 1: return " WC"; 164 case 2: return " WT"; 165 case 3: return " UC"; 166 default: return " not defined"; 167 } 168 } else { 169 switch (obj->pat_index) { 170 case 0: return " UC"; 171 case 1: return HAS_LLC(i915) ? 172 " LLC" : " snooped"; 173 case 2: return " L3+LLC"; 174 case 3: return " WT"; 175 default: return " not defined"; 176 } 177 } 178 } 179 180 void 181 i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) 182 { 183 struct i915_vma *vma; 184 int pin_count = 0; 185 186 seq_printf(m, "%pK: %c%c%c %8zdKiB %02x %02x %s%s%s", 187 &obj->base, 188 get_tiling_flag(obj), 189 get_global_flag(obj), 190 get_pin_mapped_flag(obj), 191 obj->base.size / 1024, 192 obj->read_domains, 193 obj->write_domain, 194 i915_cache_level_str(obj), 195 obj->mm.dirty ? " dirty" : "", 196 obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : ""); 197 if (obj->base.name) 198 seq_printf(m, " (name: %d)", obj->base.name); 199 200 spin_lock(&obj->vma.lock); 201 list_for_each_entry(vma, &obj->vma.list, obj_link) { 202 if (!drm_mm_node_allocated(&vma->node)) 203 continue; 204 205 spin_unlock(&obj->vma.lock); 206 207 if (i915_vma_is_pinned(vma)) 208 pin_count++; 209 210 seq_printf(m, " (%s offset: %08llx, size: %08llx, pages: %s", 211 stringify_vma_type(vma), 212 i915_vma_offset(vma), i915_vma_size(vma), 213 stringify_page_sizes(vma->resource->page_sizes_gtt, 214 NULL, 0)); 215 if (i915_vma_is_ggtt(vma) || i915_vma_is_dpt(vma)) { 216 switch (vma->gtt_view.type) { 217 case I915_GTT_VIEW_NORMAL: 218 seq_puts(m, ", normal"); 219 break; 220 221 case I915_GTT_VIEW_PARTIAL: 222 seq_printf(m, ", partial [%08llx+%x]", 223 vma->gtt_view.partial.offset << PAGE_SHIFT, 224 vma->gtt_view.partial.size << PAGE_SHIFT); 225 break; 226 227 case I915_GTT_VIEW_ROTATED: 228 seq_printf(m, ", rotated [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]", 229 vma->gtt_view.rotated.plane[0].width, 230 vma->gtt_view.rotated.plane[0].height, 231 vma->gtt_view.rotated.plane[0].src_stride, 232 vma->gtt_view.rotated.plane[0].dst_stride, 233 vma->gtt_view.rotated.plane[0].offset, 234 vma->gtt_view.rotated.plane[1].width, 235 vma->gtt_view.rotated.plane[1].height, 236 vma->gtt_view.rotated.plane[1].src_stride, 237 vma->gtt_view.rotated.plane[1].dst_stride, 238 vma->gtt_view.rotated.plane[1].offset); 239 break; 240 241 case I915_GTT_VIEW_REMAPPED: 242 seq_printf(m, ", remapped [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]", 243 vma->gtt_view.remapped.plane[0].width, 244 vma->gtt_view.remapped.plane[0].height, 245 vma->gtt_view.remapped.plane[0].src_stride, 246 vma->gtt_view.remapped.plane[0].dst_stride, 247 vma->gtt_view.remapped.plane[0].offset, 248 vma->gtt_view.remapped.plane[1].width, 249 vma->gtt_view.remapped.plane[1].height, 250 vma->gtt_view.remapped.plane[1].src_stride, 251 vma->gtt_view.remapped.plane[1].dst_stride, 252 vma->gtt_view.remapped.plane[1].offset); 253 break; 254 255 default: 256 MISSING_CASE(vma->gtt_view.type); 257 break; 258 } 259 } 260 if (vma->fence) 261 seq_printf(m, " , fence: %d", vma->fence->id); 262 seq_puts(m, ")"); 263 264 spin_lock(&obj->vma.lock); 265 } 266 spin_unlock(&obj->vma.lock); 267 268 seq_printf(m, " (pinned x %d)", pin_count); 269 if (i915_gem_object_is_stolen(obj)) 270 seq_printf(m, " (stolen: %08llx)", obj->stolen->start); 271 if (i915_gem_object_is_framebuffer(obj)) 272 seq_printf(m, " (fb)"); 273 } 274 275 static int i915_gem_object_info(struct seq_file *m, void *data) 276 { 277 struct drm_i915_private *i915 = node_to_i915(m->private); 278 struct drm_printer p = drm_seq_file_printer(m); 279 struct intel_memory_region *mr; 280 enum intel_region_id id; 281 282 seq_printf(m, "%u shrinkable [%u free] objects, %llu bytes\n", 283 i915->mm.shrink_count, 284 atomic_read(&i915->mm.free_count), 285 i915->mm.shrink_memory); 286 for_each_memory_region(mr, i915, id) 287 intel_memory_region_debug(mr, &p); 288 289 return 0; 290 } 291 292 static int i915_frequency_info(struct seq_file *m, void *unused) 293 { 294 struct drm_i915_private *i915 = node_to_i915(m->private); 295 struct intel_gt *gt = to_gt(i915); 296 struct drm_printer p = drm_seq_file_printer(m); 297 298 intel_gt_pm_frequency_dump(gt, &p); 299 300 return 0; 301 } 302 303 static const char *swizzle_string(unsigned swizzle) 304 { 305 switch (swizzle) { 306 case I915_BIT_6_SWIZZLE_NONE: 307 return "none"; 308 case I915_BIT_6_SWIZZLE_9: 309 return "bit9"; 310 case I915_BIT_6_SWIZZLE_9_10: 311 return "bit9/bit10"; 312 case I915_BIT_6_SWIZZLE_9_11: 313 return "bit9/bit11"; 314 case I915_BIT_6_SWIZZLE_9_10_11: 315 return "bit9/bit10/bit11"; 316 case I915_BIT_6_SWIZZLE_9_17: 317 return "bit9/bit17"; 318 case I915_BIT_6_SWIZZLE_9_10_17: 319 return "bit9/bit10/bit17"; 320 case I915_BIT_6_SWIZZLE_UNKNOWN: 321 return "unknown"; 322 } 323 324 return "bug"; 325 } 326 327 static int i915_swizzle_info(struct seq_file *m, void *data) 328 { 329 struct drm_i915_private *dev_priv = node_to_i915(m->private); 330 struct intel_uncore *uncore = &dev_priv->uncore; 331 intel_wakeref_t wakeref; 332 333 seq_printf(m, "bit6 swizzle for X-tiling = %s\n", 334 swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_x)); 335 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", 336 swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_y)); 337 338 if (dev_priv->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES) 339 seq_puts(m, "L-shaped memory detected\n"); 340 341 /* On BDW+, swizzling is not used. See detect_bit_6_swizzle() */ 342 if (GRAPHICS_VER(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) 343 return 0; 344 345 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 346 347 if (IS_GRAPHICS_VER(dev_priv, 3, 4)) { 348 seq_printf(m, "DDC = 0x%08x\n", 349 intel_uncore_read(uncore, DCC)); 350 seq_printf(m, "DDC2 = 0x%08x\n", 351 intel_uncore_read(uncore, DCC2)); 352 seq_printf(m, "C0DRB3 = 0x%04x\n", 353 intel_uncore_read16(uncore, C0DRB3_BW)); 354 seq_printf(m, "C1DRB3 = 0x%04x\n", 355 intel_uncore_read16(uncore, C1DRB3_BW)); 356 } else if (GRAPHICS_VER(dev_priv) >= 6) { 357 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", 358 intel_uncore_read(uncore, MAD_DIMM_C0)); 359 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", 360 intel_uncore_read(uncore, MAD_DIMM_C1)); 361 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", 362 intel_uncore_read(uncore, MAD_DIMM_C2)); 363 seq_printf(m, "TILECTL = 0x%08x\n", 364 intel_uncore_read(uncore, TILECTL)); 365 if (GRAPHICS_VER(dev_priv) >= 8) 366 seq_printf(m, "GAMTARBMODE = 0x%08x\n", 367 intel_uncore_read(uncore, GAMTARBMODE)); 368 else 369 seq_printf(m, "ARB_MODE = 0x%08x\n", 370 intel_uncore_read(uncore, ARB_MODE)); 371 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", 372 intel_uncore_read(uncore, DISP_ARB_CTL)); 373 } 374 375 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 376 377 return 0; 378 } 379 380 static int i915_rps_boost_info(struct seq_file *m, void *data) 381 { 382 struct drm_i915_private *dev_priv = node_to_i915(m->private); 383 struct intel_rps *rps = &to_gt(dev_priv)->rps; 384 385 seq_printf(m, "RPS enabled? %s\n", 386 str_yes_no(intel_rps_is_enabled(rps))); 387 seq_printf(m, "RPS active? %s\n", 388 str_yes_no(intel_rps_is_active(rps))); 389 seq_printf(m, "GPU busy? %s\n", str_yes_no(to_gt(dev_priv)->awake)); 390 seq_printf(m, "Boosts outstanding? %d\n", 391 atomic_read(&rps->num_waiters)); 392 seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive)); 393 seq_printf(m, "Frequency requested %d, actual %d\n", 394 intel_gpu_freq(rps, rps->cur_freq), 395 intel_rps_read_actual_frequency(rps)); 396 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", 397 intel_gpu_freq(rps, rps->min_freq), 398 intel_gpu_freq(rps, rps->min_freq_softlimit), 399 intel_gpu_freq(rps, rps->max_freq_softlimit), 400 intel_gpu_freq(rps, rps->max_freq)); 401 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", 402 intel_gpu_freq(rps, rps->idle_freq), 403 intel_gpu_freq(rps, rps->efficient_freq), 404 intel_gpu_freq(rps, rps->boost_freq)); 405 406 seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts)); 407 408 return 0; 409 } 410 411 static int i915_runtime_pm_status(struct seq_file *m, void *unused) 412 { 413 struct drm_i915_private *dev_priv = node_to_i915(m->private); 414 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 415 416 if (!HAS_RUNTIME_PM(dev_priv)) 417 seq_puts(m, "Runtime power management not supported\n"); 418 419 seq_printf(m, "Runtime power status: %s\n", 420 str_enabled_disabled(!dev_priv->display.power.domains.init_wakeref)); 421 422 seq_printf(m, "GPU idle: %s\n", str_yes_no(!to_gt(dev_priv)->awake)); 423 seq_printf(m, "IRQs disabled: %s\n", 424 str_yes_no(!intel_irqs_enabled(dev_priv))); 425 #ifdef CONFIG_PM 426 seq_printf(m, "Usage count: %d\n", 427 atomic_read(&dev_priv->drm.dev->power.usage_count)); 428 #else 429 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); 430 #endif 431 seq_printf(m, "PCI device power state: %s [%d]\n", 432 pci_power_name(pdev->current_state), 433 pdev->current_state); 434 435 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) { 436 struct drm_printer p = drm_seq_file_printer(m); 437 438 print_intel_runtime_pm_wakeref(&dev_priv->runtime_pm, &p); 439 } 440 441 return 0; 442 } 443 444 static int i915_engine_info(struct seq_file *m, void *unused) 445 { 446 struct drm_i915_private *i915 = node_to_i915(m->private); 447 struct intel_engine_cs *engine; 448 intel_wakeref_t wakeref; 449 struct drm_printer p; 450 451 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 452 453 seq_printf(m, "GT awake? %s [%d], %llums\n", 454 str_yes_no(to_gt(i915)->awake), 455 atomic_read(&to_gt(i915)->wakeref.count), 456 ktime_to_ms(intel_gt_get_awake_time(to_gt(i915)))); 457 seq_printf(m, "CS timestamp frequency: %u Hz, %d ns\n", 458 to_gt(i915)->clock_frequency, 459 to_gt(i915)->clock_period_ns); 460 461 p = drm_seq_file_printer(m); 462 for_each_uabi_engine(engine, i915) 463 intel_engine_dump(engine, &p, "%s\n", engine->name); 464 465 intel_gt_show_timelines(to_gt(i915), &p, i915_request_show_with_schedule); 466 467 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 468 469 return 0; 470 } 471 472 static int i915_wa_registers(struct seq_file *m, void *unused) 473 { 474 struct drm_i915_private *i915 = node_to_i915(m->private); 475 struct intel_engine_cs *engine; 476 477 for_each_uabi_engine(engine, i915) { 478 const struct i915_wa_list *wal = &engine->ctx_wa_list; 479 const struct i915_wa *wa; 480 unsigned int count; 481 482 count = wal->count; 483 if (!count) 484 continue; 485 486 seq_printf(m, "%s: Workarounds applied: %u\n", 487 engine->name, count); 488 489 for (wa = wal->list; count--; wa++) 490 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n", 491 i915_mmio_reg_offset(wa->reg), 492 wa->set, wa->clr); 493 494 seq_printf(m, "\n"); 495 } 496 497 return 0; 498 } 499 500 static int i915_wedged_get(void *data, u64 *val) 501 { 502 struct drm_i915_private *i915 = data; 503 struct intel_gt *gt; 504 unsigned int i; 505 506 *val = 0; 507 508 for_each_gt(gt, i915, i) { 509 int ret; 510 511 ret = intel_gt_debugfs_reset_show(gt, val); 512 if (ret) 513 return ret; 514 515 /* at least one tile should be wedged */ 516 if (*val) 517 break; 518 } 519 520 return 0; 521 } 522 523 static int i915_wedged_set(void *data, u64 val) 524 { 525 struct drm_i915_private *i915 = data; 526 struct intel_gt *gt; 527 unsigned int i; 528 529 for_each_gt(gt, i915, i) 530 intel_gt_debugfs_reset_store(gt, val); 531 532 return 0; 533 } 534 535 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, 536 i915_wedged_get, i915_wedged_set, 537 "%llu\n"); 538 539 static int 540 i915_perf_noa_delay_set(void *data, u64 val) 541 { 542 struct drm_i915_private *i915 = data; 543 544 /* 545 * This would lead to infinite waits as we're doing timestamp 546 * difference on the CS with only 32bits. 547 */ 548 if (intel_gt_ns_to_clock_interval(to_gt(i915), val) > U32_MAX) 549 return -EINVAL; 550 551 atomic64_set(&i915->perf.noa_programming_delay, val); 552 return 0; 553 } 554 555 static int 556 i915_perf_noa_delay_get(void *data, u64 *val) 557 { 558 struct drm_i915_private *i915 = data; 559 560 *val = atomic64_read(&i915->perf.noa_programming_delay); 561 return 0; 562 } 563 564 DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops, 565 i915_perf_noa_delay_get, 566 i915_perf_noa_delay_set, 567 "%llu\n"); 568 569 #define DROP_UNBOUND BIT(0) 570 #define DROP_BOUND BIT(1) 571 #define DROP_RETIRE BIT(2) 572 #define DROP_ACTIVE BIT(3) 573 #define DROP_FREED BIT(4) 574 #define DROP_SHRINK_ALL BIT(5) 575 #define DROP_IDLE BIT(6) 576 #define DROP_RESET_ACTIVE BIT(7) 577 #define DROP_RESET_SEQNO BIT(8) 578 #define DROP_RCU BIT(9) 579 #define DROP_ALL (DROP_UNBOUND | \ 580 DROP_BOUND | \ 581 DROP_RETIRE | \ 582 DROP_ACTIVE | \ 583 DROP_FREED | \ 584 DROP_SHRINK_ALL |\ 585 DROP_IDLE | \ 586 DROP_RESET_ACTIVE | \ 587 DROP_RESET_SEQNO | \ 588 DROP_RCU) 589 static int 590 i915_drop_caches_get(void *data, u64 *val) 591 { 592 *val = DROP_ALL; 593 594 return 0; 595 } 596 597 static int 598 gt_drop_caches(struct intel_gt *gt, u64 val) 599 { 600 int ret; 601 602 if (val & DROP_RESET_ACTIVE && 603 wait_for(intel_engines_are_idle(gt), 200)) 604 intel_gt_set_wedged(gt); 605 606 if (val & DROP_RETIRE) 607 intel_gt_retire_requests(gt); 608 609 if (val & (DROP_IDLE | DROP_ACTIVE)) { 610 ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT); 611 if (ret) 612 return ret; 613 } 614 615 if (val & DROP_IDLE) { 616 ret = intel_gt_pm_wait_for_idle(gt); 617 if (ret) 618 return ret; 619 } 620 621 if (val & DROP_RESET_ACTIVE && intel_gt_terminally_wedged(gt)) 622 intel_gt_handle_error(gt, ALL_ENGINES, 0, NULL); 623 624 if (val & DROP_FREED) 625 intel_gt_flush_buffer_pool(gt); 626 627 return 0; 628 } 629 630 static int 631 i915_drop_caches_set(void *data, u64 val) 632 { 633 struct drm_i915_private *i915 = data; 634 struct intel_gt *gt; 635 unsigned int flags; 636 unsigned int i; 637 int ret; 638 639 drm_dbg(&i915->drm, "Dropping caches: 0x%08llx [0x%08llx]\n", 640 val, val & DROP_ALL); 641 642 for_each_gt(gt, i915, i) { 643 ret = gt_drop_caches(gt, val); 644 if (ret) 645 return ret; 646 } 647 648 fs_reclaim_acquire(GFP_KERNEL); 649 flags = memalloc_noreclaim_save(); 650 if (val & DROP_BOUND) 651 i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_BOUND); 652 653 if (val & DROP_UNBOUND) 654 i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_UNBOUND); 655 656 if (val & DROP_SHRINK_ALL) 657 i915_gem_shrink_all(i915); 658 memalloc_noreclaim_restore(flags); 659 fs_reclaim_release(GFP_KERNEL); 660 661 if (val & DROP_RCU) 662 rcu_barrier(); 663 664 if (val & DROP_FREED) 665 i915_gem_drain_freed_objects(i915); 666 667 return 0; 668 } 669 670 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, 671 i915_drop_caches_get, i915_drop_caches_set, 672 "0x%08llx\n"); 673 674 static int i915_sseu_status(struct seq_file *m, void *unused) 675 { 676 struct drm_i915_private *i915 = node_to_i915(m->private); 677 struct intel_gt *gt = to_gt(i915); 678 679 return intel_sseu_status(m, gt); 680 } 681 682 static int i915_forcewake_open(struct inode *inode, struct file *file) 683 { 684 struct drm_i915_private *i915 = inode->i_private; 685 struct intel_gt *gt; 686 unsigned int i; 687 688 for_each_gt(gt, i915, i) 689 intel_gt_pm_debugfs_forcewake_user_open(gt); 690 691 return 0; 692 } 693 694 static int i915_forcewake_release(struct inode *inode, struct file *file) 695 { 696 struct drm_i915_private *i915 = inode->i_private; 697 struct intel_gt *gt; 698 unsigned int i; 699 700 for_each_gt(gt, i915, i) 701 intel_gt_pm_debugfs_forcewake_user_release(gt); 702 703 return 0; 704 } 705 706 static const struct file_operations i915_forcewake_fops = { 707 .owner = THIS_MODULE, 708 .open = i915_forcewake_open, 709 .release = i915_forcewake_release, 710 }; 711 712 static const struct drm_info_list i915_debugfs_list[] = { 713 {"i915_capabilities", i915_capabilities, 0}, 714 {"i915_gem_objects", i915_gem_object_info, 0}, 715 {"i915_frequency_info", i915_frequency_info, 0}, 716 {"i915_swizzle_info", i915_swizzle_info, 0}, 717 {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, 718 {"i915_engine_info", i915_engine_info, 0}, 719 {"i915_wa_registers", i915_wa_registers, 0}, 720 {"i915_sseu_status", i915_sseu_status, 0}, 721 {"i915_rps_boost_info", i915_rps_boost_info, 0}, 722 }; 723 724 static const struct i915_debugfs_files { 725 const char *name; 726 const struct file_operations *fops; 727 } i915_debugfs_files[] = { 728 {"i915_perf_noa_delay", &i915_perf_noa_delay_fops}, 729 {"i915_wedged", &i915_wedged_fops}, 730 {"i915_gem_drop_caches", &i915_drop_caches_fops}, 731 }; 732 733 void i915_debugfs_register(struct drm_i915_private *dev_priv) 734 { 735 struct drm_minor *minor = dev_priv->drm.primary; 736 int i; 737 738 i915_debugfs_params(dev_priv); 739 740 debugfs_create_file("i915_forcewake_user", S_IRUSR, minor->debugfs_root, 741 to_i915(minor->dev), &i915_forcewake_fops); 742 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { 743 debugfs_create_file(i915_debugfs_files[i].name, 744 S_IRUGO | S_IWUSR, 745 minor->debugfs_root, 746 to_i915(minor->dev), 747 i915_debugfs_files[i].fops); 748 } 749 750 drm_debugfs_create_files(i915_debugfs_list, 751 ARRAY_SIZE(i915_debugfs_list), 752 minor->debugfs_root, minor); 753 754 i915_gpu_error_debugfs_register(dev_priv); 755 } 756