1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * 27 */ 28 29 #include <linux/seq_file.h> 30 #include <linux/debugfs.h> 31 #include <linux/slab.h> 32 #include "drmP.h" 33 #include "drm.h" 34 #include "i915_drm.h" 35 #include "i915_drv.h" 36 37 #define DRM_I915_RING_DEBUG 1 38 39 40 #if defined(CONFIG_DEBUG_FS) 41 42 #define ACTIVE_LIST 1 43 #define FLUSHING_LIST 2 44 #define INACTIVE_LIST 3 45 46 static const char *get_pin_flag(struct drm_i915_gem_object *obj_priv) 47 { 48 if (obj_priv->user_pin_count > 0) 49 return "P"; 50 else if (obj_priv->pin_count > 0) 51 return "p"; 52 else 53 return " "; 54 } 55 56 static const char *get_tiling_flag(struct drm_i915_gem_object *obj_priv) 57 { 58 switch (obj_priv->tiling_mode) { 59 default: 60 case I915_TILING_NONE: return " "; 61 case I915_TILING_X: return "X"; 62 case I915_TILING_Y: return "Y"; 63 } 64 } 65 66 static int i915_gem_object_list_info(struct seq_file *m, void *data) 67 { 68 struct drm_info_node *node = (struct drm_info_node *) m->private; 69 uintptr_t list = (uintptr_t) node->info_ent->data; 70 struct list_head *head; 71 struct drm_device *dev = node->minor->dev; 72 drm_i915_private_t *dev_priv = dev->dev_private; 73 struct drm_i915_gem_object *obj_priv; 74 spinlock_t *lock = NULL; 75 76 switch (list) { 77 case ACTIVE_LIST: 78 seq_printf(m, "Active:\n"); 79 lock = &dev_priv->mm.active_list_lock; 80 head = &dev_priv->render_ring.active_list; 81 break; 82 case INACTIVE_LIST: 83 seq_printf(m, "Inactive:\n"); 84 head = &dev_priv->mm.inactive_list; 85 break; 86 case FLUSHING_LIST: 87 seq_printf(m, "Flushing:\n"); 88 head = &dev_priv->mm.flushing_list; 89 break; 90 default: 91 DRM_INFO("Ooops, unexpected list\n"); 92 return 0; 93 } 94 95 if (lock) 96 spin_lock(lock); 97 list_for_each_entry(obj_priv, head, list) 98 { 99 seq_printf(m, " %p: %s %8zd %08x %08x %d%s%s", 100 &obj_priv->base, 101 get_pin_flag(obj_priv), 102 obj_priv->base.size, 103 obj_priv->base.read_domains, 104 obj_priv->base.write_domain, 105 obj_priv->last_rendering_seqno, 106 obj_priv->dirty ? " dirty" : "", 107 obj_priv->madv == I915_MADV_DONTNEED ? " purgeable" : ""); 108 109 if (obj_priv->base.name) 110 seq_printf(m, " (name: %d)", obj_priv->base.name); 111 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) 112 seq_printf(m, " (fence: %d)", obj_priv->fence_reg); 113 if (obj_priv->gtt_space != NULL) 114 seq_printf(m, " (gtt_offset: %08x)", obj_priv->gtt_offset); 115 116 seq_printf(m, "\n"); 117 } 118 119 if (lock) 120 spin_unlock(lock); 121 return 0; 122 } 123 124 static int i915_gem_request_info(struct seq_file *m, void *data) 125 { 126 struct drm_info_node *node = (struct drm_info_node *) m->private; 127 struct drm_device *dev = node->minor->dev; 128 drm_i915_private_t *dev_priv = dev->dev_private; 129 struct drm_i915_gem_request *gem_request; 130 131 seq_printf(m, "Request:\n"); 132 list_for_each_entry(gem_request, &dev_priv->render_ring.request_list, 133 list) { 134 seq_printf(m, " %d @ %d\n", 135 gem_request->seqno, 136 (int) (jiffies - gem_request->emitted_jiffies)); 137 } 138 return 0; 139 } 140 141 static int i915_gem_seqno_info(struct seq_file *m, void *data) 142 { 143 struct drm_info_node *node = (struct drm_info_node *) m->private; 144 struct drm_device *dev = node->minor->dev; 145 drm_i915_private_t *dev_priv = dev->dev_private; 146 147 if (dev_priv->render_ring.status_page.page_addr != NULL) { 148 seq_printf(m, "Current sequence: %d\n", 149 i915_get_gem_seqno(dev, &dev_priv->render_ring)); 150 } else { 151 seq_printf(m, "Current sequence: hws uninitialized\n"); 152 } 153 seq_printf(m, "Waiter sequence: %d\n", 154 dev_priv->mm.waiting_gem_seqno); 155 seq_printf(m, "IRQ sequence: %d\n", dev_priv->mm.irq_gem_seqno); 156 return 0; 157 } 158 159 160 static int i915_interrupt_info(struct seq_file *m, void *data) 161 { 162 struct drm_info_node *node = (struct drm_info_node *) m->private; 163 struct drm_device *dev = node->minor->dev; 164 drm_i915_private_t *dev_priv = dev->dev_private; 165 166 if (!HAS_PCH_SPLIT(dev)) { 167 seq_printf(m, "Interrupt enable: %08x\n", 168 I915_READ(IER)); 169 seq_printf(m, "Interrupt identity: %08x\n", 170 I915_READ(IIR)); 171 seq_printf(m, "Interrupt mask: %08x\n", 172 I915_READ(IMR)); 173 seq_printf(m, "Pipe A stat: %08x\n", 174 I915_READ(PIPEASTAT)); 175 seq_printf(m, "Pipe B stat: %08x\n", 176 I915_READ(PIPEBSTAT)); 177 } else { 178 seq_printf(m, "North Display Interrupt enable: %08x\n", 179 I915_READ(DEIER)); 180 seq_printf(m, "North Display Interrupt identity: %08x\n", 181 I915_READ(DEIIR)); 182 seq_printf(m, "North Display Interrupt mask: %08x\n", 183 I915_READ(DEIMR)); 184 seq_printf(m, "South Display Interrupt enable: %08x\n", 185 I915_READ(SDEIER)); 186 seq_printf(m, "South Display Interrupt identity: %08x\n", 187 I915_READ(SDEIIR)); 188 seq_printf(m, "South Display Interrupt mask: %08x\n", 189 I915_READ(SDEIMR)); 190 seq_printf(m, "Graphics Interrupt enable: %08x\n", 191 I915_READ(GTIER)); 192 seq_printf(m, "Graphics Interrupt identity: %08x\n", 193 I915_READ(GTIIR)); 194 seq_printf(m, "Graphics Interrupt mask: %08x\n", 195 I915_READ(GTIMR)); 196 } 197 seq_printf(m, "Interrupts received: %d\n", 198 atomic_read(&dev_priv->irq_received)); 199 if (dev_priv->render_ring.status_page.page_addr != NULL) { 200 seq_printf(m, "Current sequence: %d\n", 201 i915_get_gem_seqno(dev, &dev_priv->render_ring)); 202 } else { 203 seq_printf(m, "Current sequence: hws uninitialized\n"); 204 } 205 seq_printf(m, "Waiter sequence: %d\n", 206 dev_priv->mm.waiting_gem_seqno); 207 seq_printf(m, "IRQ sequence: %d\n", 208 dev_priv->mm.irq_gem_seqno); 209 return 0; 210 } 211 212 static int i915_gem_fence_regs_info(struct seq_file *m, void *data) 213 { 214 struct drm_info_node *node = (struct drm_info_node *) m->private; 215 struct drm_device *dev = node->minor->dev; 216 drm_i915_private_t *dev_priv = dev->dev_private; 217 int i; 218 219 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); 220 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); 221 for (i = 0; i < dev_priv->num_fence_regs; i++) { 222 struct drm_gem_object *obj = dev_priv->fence_regs[i].obj; 223 224 if (obj == NULL) { 225 seq_printf(m, "Fenced object[%2d] = unused\n", i); 226 } else { 227 struct drm_i915_gem_object *obj_priv; 228 229 obj_priv = to_intel_bo(obj); 230 seq_printf(m, "Fenced object[%2d] = %p: %s " 231 "%08x %08zx %08x %s %08x %08x %d", 232 i, obj, get_pin_flag(obj_priv), 233 obj_priv->gtt_offset, 234 obj->size, obj_priv->stride, 235 get_tiling_flag(obj_priv), 236 obj->read_domains, obj->write_domain, 237 obj_priv->last_rendering_seqno); 238 if (obj->name) 239 seq_printf(m, " (name: %d)", obj->name); 240 seq_printf(m, "\n"); 241 } 242 } 243 244 return 0; 245 } 246 247 static int i915_hws_info(struct seq_file *m, void *data) 248 { 249 struct drm_info_node *node = (struct drm_info_node *) m->private; 250 struct drm_device *dev = node->minor->dev; 251 drm_i915_private_t *dev_priv = dev->dev_private; 252 int i; 253 volatile u32 *hws; 254 255 hws = (volatile u32 *)dev_priv->render_ring.status_page.page_addr; 256 if (hws == NULL) 257 return 0; 258 259 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { 260 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", 261 i * 4, 262 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); 263 } 264 return 0; 265 } 266 267 static void i915_dump_pages(struct seq_file *m, struct page **pages, int page_count) 268 { 269 int page, i; 270 uint32_t *mem; 271 272 for (page = 0; page < page_count; page++) { 273 mem = kmap_atomic(pages[page], KM_USER0); 274 for (i = 0; i < PAGE_SIZE; i += 4) 275 seq_printf(m, "%08x : %08x\n", i, mem[i / 4]); 276 kunmap_atomic(mem, KM_USER0); 277 } 278 } 279 280 static int i915_batchbuffer_info(struct seq_file *m, void *data) 281 { 282 struct drm_info_node *node = (struct drm_info_node *) m->private; 283 struct drm_device *dev = node->minor->dev; 284 drm_i915_private_t *dev_priv = dev->dev_private; 285 struct drm_gem_object *obj; 286 struct drm_i915_gem_object *obj_priv; 287 int ret; 288 289 spin_lock(&dev_priv->mm.active_list_lock); 290 291 list_for_each_entry(obj_priv, &dev_priv->render_ring.active_list, 292 list) { 293 obj = &obj_priv->base; 294 if (obj->read_domains & I915_GEM_DOMAIN_COMMAND) { 295 ret = i915_gem_object_get_pages(obj, 0); 296 if (ret) { 297 DRM_ERROR("Failed to get pages: %d\n", ret); 298 spin_unlock(&dev_priv->mm.active_list_lock); 299 return ret; 300 } 301 302 seq_printf(m, "--- gtt_offset = 0x%08x\n", obj_priv->gtt_offset); 303 i915_dump_pages(m, obj_priv->pages, obj->size / PAGE_SIZE); 304 305 i915_gem_object_put_pages(obj); 306 } 307 } 308 309 spin_unlock(&dev_priv->mm.active_list_lock); 310 311 return 0; 312 } 313 314 static int i915_ringbuffer_data(struct seq_file *m, void *data) 315 { 316 struct drm_info_node *node = (struct drm_info_node *) m->private; 317 struct drm_device *dev = node->minor->dev; 318 drm_i915_private_t *dev_priv = dev->dev_private; 319 u8 *virt; 320 uint32_t *ptr, off; 321 322 if (!dev_priv->render_ring.gem_object) { 323 seq_printf(m, "No ringbuffer setup\n"); 324 return 0; 325 } 326 327 virt = dev_priv->render_ring.virtual_start; 328 329 for (off = 0; off < dev_priv->render_ring.size; off += 4) { 330 ptr = (uint32_t *)(virt + off); 331 seq_printf(m, "%08x : %08x\n", off, *ptr); 332 } 333 334 return 0; 335 } 336 337 static int i915_ringbuffer_info(struct seq_file *m, void *data) 338 { 339 struct drm_info_node *node = (struct drm_info_node *) m->private; 340 struct drm_device *dev = node->minor->dev; 341 drm_i915_private_t *dev_priv = dev->dev_private; 342 unsigned int head, tail; 343 344 head = I915_READ(PRB0_HEAD) & HEAD_ADDR; 345 tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; 346 347 seq_printf(m, "RingHead : %08x\n", head); 348 seq_printf(m, "RingTail : %08x\n", tail); 349 seq_printf(m, "RingSize : %08lx\n", dev_priv->render_ring.size); 350 seq_printf(m, "Acthd : %08x\n", I915_READ(IS_I965G(dev) ? ACTHD_I965 : ACTHD)); 351 352 return 0; 353 } 354 355 static const char *pin_flag(int pinned) 356 { 357 if (pinned > 0) 358 return " P"; 359 else if (pinned < 0) 360 return " p"; 361 else 362 return ""; 363 } 364 365 static const char *tiling_flag(int tiling) 366 { 367 switch (tiling) { 368 default: 369 case I915_TILING_NONE: return ""; 370 case I915_TILING_X: return " X"; 371 case I915_TILING_Y: return " Y"; 372 } 373 } 374 375 static const char *dirty_flag(int dirty) 376 { 377 return dirty ? " dirty" : ""; 378 } 379 380 static const char *purgeable_flag(int purgeable) 381 { 382 return purgeable ? " purgeable" : ""; 383 } 384 385 static int i915_error_state(struct seq_file *m, void *unused) 386 { 387 struct drm_info_node *node = (struct drm_info_node *) m->private; 388 struct drm_device *dev = node->minor->dev; 389 drm_i915_private_t *dev_priv = dev->dev_private; 390 struct drm_i915_error_state *error; 391 unsigned long flags; 392 int i, page, offset, elt; 393 394 spin_lock_irqsave(&dev_priv->error_lock, flags); 395 if (!dev_priv->first_error) { 396 seq_printf(m, "no error state collected\n"); 397 goto out; 398 } 399 400 error = dev_priv->first_error; 401 402 seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, 403 error->time.tv_usec); 404 seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device); 405 seq_printf(m, "EIR: 0x%08x\n", error->eir); 406 seq_printf(m, " PGTBL_ER: 0x%08x\n", error->pgtbl_er); 407 seq_printf(m, " INSTPM: 0x%08x\n", error->instpm); 408 seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir); 409 seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr); 410 seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone); 411 seq_printf(m, " ACTHD: 0x%08x\n", error->acthd); 412 if (IS_I965G(dev)) { 413 seq_printf(m, " INSTPS: 0x%08x\n", error->instps); 414 seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1); 415 } 416 seq_printf(m, "seqno: 0x%08x\n", error->seqno); 417 418 if (error->active_bo_count) { 419 seq_printf(m, "Buffers [%d]:\n", error->active_bo_count); 420 421 for (i = 0; i < error->active_bo_count; i++) { 422 seq_printf(m, " %08x %8zd %08x %08x %08x%s%s%s%s", 423 error->active_bo[i].gtt_offset, 424 error->active_bo[i].size, 425 error->active_bo[i].read_domains, 426 error->active_bo[i].write_domain, 427 error->active_bo[i].seqno, 428 pin_flag(error->active_bo[i].pinned), 429 tiling_flag(error->active_bo[i].tiling), 430 dirty_flag(error->active_bo[i].dirty), 431 purgeable_flag(error->active_bo[i].purgeable)); 432 433 if (error->active_bo[i].name) 434 seq_printf(m, " (name: %d)", error->active_bo[i].name); 435 if (error->active_bo[i].fence_reg != I915_FENCE_REG_NONE) 436 seq_printf(m, " (fence: %d)", error->active_bo[i].fence_reg); 437 438 seq_printf(m, "\n"); 439 } 440 } 441 442 for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) { 443 if (error->batchbuffer[i]) { 444 struct drm_i915_error_object *obj = error->batchbuffer[i]; 445 446 seq_printf(m, "--- gtt_offset = 0x%08x\n", obj->gtt_offset); 447 offset = 0; 448 for (page = 0; page < obj->page_count; page++) { 449 for (elt = 0; elt < PAGE_SIZE/4; elt++) { 450 seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]); 451 offset += 4; 452 } 453 } 454 } 455 } 456 457 if (error->ringbuffer) { 458 struct drm_i915_error_object *obj = error->ringbuffer; 459 460 seq_printf(m, "--- ringbuffer = 0x%08x\n", obj->gtt_offset); 461 offset = 0; 462 for (page = 0; page < obj->page_count; page++) { 463 for (elt = 0; elt < PAGE_SIZE/4; elt++) { 464 seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]); 465 offset += 4; 466 } 467 } 468 } 469 470 if (error->overlay) 471 intel_overlay_print_error_state(m, error->overlay); 472 473 out: 474 spin_unlock_irqrestore(&dev_priv->error_lock, flags); 475 476 return 0; 477 } 478 479 static int i915_rstdby_delays(struct seq_file *m, void *unused) 480 { 481 struct drm_info_node *node = (struct drm_info_node *) m->private; 482 struct drm_device *dev = node->minor->dev; 483 drm_i915_private_t *dev_priv = dev->dev_private; 484 u16 crstanddelay = I915_READ16(CRSTANDVID); 485 486 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); 487 488 return 0; 489 } 490 491 static int i915_cur_delayinfo(struct seq_file *m, void *unused) 492 { 493 struct drm_info_node *node = (struct drm_info_node *) m->private; 494 struct drm_device *dev = node->minor->dev; 495 drm_i915_private_t *dev_priv = dev->dev_private; 496 u16 rgvswctl = I915_READ16(MEMSWCTL); 497 u16 rgvstat = I915_READ16(MEMSTAT_ILK); 498 499 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); 500 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); 501 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> 502 MEMSTAT_VID_SHIFT); 503 seq_printf(m, "Current P-state: %d\n", 504 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); 505 506 return 0; 507 } 508 509 static int i915_delayfreq_table(struct seq_file *m, void *unused) 510 { 511 struct drm_info_node *node = (struct drm_info_node *) m->private; 512 struct drm_device *dev = node->minor->dev; 513 drm_i915_private_t *dev_priv = dev->dev_private; 514 u32 delayfreq; 515 int i; 516 517 for (i = 0; i < 16; i++) { 518 delayfreq = I915_READ(PXVFREQ_BASE + i * 4); 519 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, 520 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); 521 } 522 523 return 0; 524 } 525 526 static inline int MAP_TO_MV(int map) 527 { 528 return 1250 - (map * 25); 529 } 530 531 static int i915_inttoext_table(struct seq_file *m, void *unused) 532 { 533 struct drm_info_node *node = (struct drm_info_node *) m->private; 534 struct drm_device *dev = node->minor->dev; 535 drm_i915_private_t *dev_priv = dev->dev_private; 536 u32 inttoext; 537 int i; 538 539 for (i = 1; i <= 32; i++) { 540 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); 541 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); 542 } 543 544 return 0; 545 } 546 547 static int i915_drpc_info(struct seq_file *m, void *unused) 548 { 549 struct drm_info_node *node = (struct drm_info_node *) m->private; 550 struct drm_device *dev = node->minor->dev; 551 drm_i915_private_t *dev_priv = dev->dev_private; 552 u32 rgvmodectl = I915_READ(MEMMODECTL); 553 u32 rstdbyctl = I915_READ(MCHBAR_RENDER_STANDBY); 554 u16 crstandvid = I915_READ16(CRSTANDVID); 555 556 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? 557 "yes" : "no"); 558 seq_printf(m, "Boost freq: %d\n", 559 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> 560 MEMMODE_BOOST_FREQ_SHIFT); 561 seq_printf(m, "HW control enabled: %s\n", 562 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); 563 seq_printf(m, "SW control enabled: %s\n", 564 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); 565 seq_printf(m, "Gated voltage change: %s\n", 566 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); 567 seq_printf(m, "Starting frequency: P%d\n", 568 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); 569 seq_printf(m, "Max P-state: P%d\n", 570 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); 571 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); 572 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); 573 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); 574 seq_printf(m, "Render standby enabled: %s\n", 575 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); 576 577 return 0; 578 } 579 580 static int i915_fbc_status(struct seq_file *m, void *unused) 581 { 582 struct drm_info_node *node = (struct drm_info_node *) m->private; 583 struct drm_device *dev = node->minor->dev; 584 drm_i915_private_t *dev_priv = dev->dev_private; 585 586 if (!I915_HAS_FBC(dev)) { 587 seq_printf(m, "FBC unsupported on this chipset\n"); 588 return 0; 589 } 590 591 if (intel_fbc_enabled(dev)) { 592 seq_printf(m, "FBC enabled\n"); 593 } else { 594 seq_printf(m, "FBC disabled: "); 595 switch (dev_priv->no_fbc_reason) { 596 case FBC_STOLEN_TOO_SMALL: 597 seq_printf(m, "not enough stolen memory"); 598 break; 599 case FBC_UNSUPPORTED_MODE: 600 seq_printf(m, "mode not supported"); 601 break; 602 case FBC_MODE_TOO_LARGE: 603 seq_printf(m, "mode too large"); 604 break; 605 case FBC_BAD_PLANE: 606 seq_printf(m, "FBC unsupported on plane"); 607 break; 608 case FBC_NOT_TILED: 609 seq_printf(m, "scanout buffer not tiled"); 610 break; 611 case FBC_MULTIPLE_PIPES: 612 seq_printf(m, "multiple pipes are enabled"); 613 break; 614 default: 615 seq_printf(m, "unknown reason"); 616 } 617 seq_printf(m, "\n"); 618 } 619 return 0; 620 } 621 622 static int i915_sr_status(struct seq_file *m, void *unused) 623 { 624 struct drm_info_node *node = (struct drm_info_node *) m->private; 625 struct drm_device *dev = node->minor->dev; 626 drm_i915_private_t *dev_priv = dev->dev_private; 627 bool sr_enabled = false; 628 629 if (IS_I965GM(dev) || IS_I945G(dev) || IS_I945GM(dev)) 630 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; 631 else if (IS_I915GM(dev)) 632 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; 633 else if (IS_PINEVIEW(dev)) 634 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; 635 636 seq_printf(m, "self-refresh: %s\n", sr_enabled ? "enabled" : 637 "disabled"); 638 639 return 0; 640 } 641 642 static int i915_emon_status(struct seq_file *m, void *unused) 643 { 644 struct drm_info_node *node = (struct drm_info_node *) m->private; 645 struct drm_device *dev = node->minor->dev; 646 drm_i915_private_t *dev_priv = dev->dev_private; 647 unsigned long temp, chipset, gfx; 648 649 temp = i915_mch_val(dev_priv); 650 chipset = i915_chipset_val(dev_priv); 651 gfx = i915_gfx_val(dev_priv); 652 653 seq_printf(m, "GMCH temp: %ld\n", temp); 654 seq_printf(m, "Chipset power: %ld\n", chipset); 655 seq_printf(m, "GFX power: %ld\n", gfx); 656 seq_printf(m, "Total power: %ld\n", chipset + gfx); 657 658 return 0; 659 } 660 661 static int i915_gfxec(struct seq_file *m, void *unused) 662 { 663 struct drm_info_node *node = (struct drm_info_node *) m->private; 664 struct drm_device *dev = node->minor->dev; 665 drm_i915_private_t *dev_priv = dev->dev_private; 666 667 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); 668 669 return 0; 670 } 671 672 static int 673 i915_wedged_open(struct inode *inode, 674 struct file *filp) 675 { 676 filp->private_data = inode->i_private; 677 return 0; 678 } 679 680 static ssize_t 681 i915_wedged_read(struct file *filp, 682 char __user *ubuf, 683 size_t max, 684 loff_t *ppos) 685 { 686 struct drm_device *dev = filp->private_data; 687 drm_i915_private_t *dev_priv = dev->dev_private; 688 char buf[80]; 689 int len; 690 691 len = snprintf(buf, sizeof (buf), 692 "wedged : %d\n", 693 atomic_read(&dev_priv->mm.wedged)); 694 695 return simple_read_from_buffer(ubuf, max, ppos, buf, len); 696 } 697 698 static ssize_t 699 i915_wedged_write(struct file *filp, 700 const char __user *ubuf, 701 size_t cnt, 702 loff_t *ppos) 703 { 704 struct drm_device *dev = filp->private_data; 705 drm_i915_private_t *dev_priv = dev->dev_private; 706 char buf[20]; 707 int val = 1; 708 709 if (cnt > 0) { 710 if (cnt > sizeof (buf) - 1) 711 return -EINVAL; 712 713 if (copy_from_user(buf, ubuf, cnt)) 714 return -EFAULT; 715 buf[cnt] = 0; 716 717 val = simple_strtoul(buf, NULL, 0); 718 } 719 720 DRM_INFO("Manually setting wedged to %d\n", val); 721 722 atomic_set(&dev_priv->mm.wedged, val); 723 if (val) { 724 DRM_WAKEUP(&dev_priv->irq_queue); 725 queue_work(dev_priv->wq, &dev_priv->error_work); 726 } 727 728 return cnt; 729 } 730 731 static const struct file_operations i915_wedged_fops = { 732 .owner = THIS_MODULE, 733 .open = i915_wedged_open, 734 .read = i915_wedged_read, 735 .write = i915_wedged_write, 736 }; 737 738 /* As the drm_debugfs_init() routines are called before dev->dev_private is 739 * allocated we need to hook into the minor for release. */ 740 static int 741 drm_add_fake_info_node(struct drm_minor *minor, 742 struct dentry *ent, 743 const void *key) 744 { 745 struct drm_info_node *node; 746 747 node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL); 748 if (node == NULL) { 749 debugfs_remove(ent); 750 return -ENOMEM; 751 } 752 753 node->minor = minor; 754 node->dent = ent; 755 node->info_ent = (void *) key; 756 list_add(&node->list, &minor->debugfs_nodes.list); 757 758 return 0; 759 } 760 761 static int i915_wedged_create(struct dentry *root, struct drm_minor *minor) 762 { 763 struct drm_device *dev = minor->dev; 764 struct dentry *ent; 765 766 ent = debugfs_create_file("i915_wedged", 767 S_IRUGO | S_IWUSR, 768 root, dev, 769 &i915_wedged_fops); 770 if (IS_ERR(ent)) 771 return PTR_ERR(ent); 772 773 return drm_add_fake_info_node(minor, ent, &i915_wedged_fops); 774 } 775 776 static struct drm_info_list i915_debugfs_list[] = { 777 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, 778 {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST}, 779 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, 780 {"i915_gem_request", i915_gem_request_info, 0}, 781 {"i915_gem_seqno", i915_gem_seqno_info, 0}, 782 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, 783 {"i915_gem_interrupt", i915_interrupt_info, 0}, 784 {"i915_gem_hws", i915_hws_info, 0}, 785 {"i915_ringbuffer_data", i915_ringbuffer_data, 0}, 786 {"i915_ringbuffer_info", i915_ringbuffer_info, 0}, 787 {"i915_batchbuffers", i915_batchbuffer_info, 0}, 788 {"i915_error_state", i915_error_state, 0}, 789 {"i915_rstdby_delays", i915_rstdby_delays, 0}, 790 {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, 791 {"i915_delayfreq_table", i915_delayfreq_table, 0}, 792 {"i915_inttoext_table", i915_inttoext_table, 0}, 793 {"i915_drpc_info", i915_drpc_info, 0}, 794 {"i915_emon_status", i915_emon_status, 0}, 795 {"i915_gfxec", i915_gfxec, 0}, 796 {"i915_fbc_status", i915_fbc_status, 0}, 797 {"i915_sr_status", i915_sr_status, 0}, 798 }; 799 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) 800 801 int i915_debugfs_init(struct drm_minor *minor) 802 { 803 int ret; 804 805 ret = i915_wedged_create(minor->debugfs_root, minor); 806 if (ret) 807 return ret; 808 809 return drm_debugfs_create_files(i915_debugfs_list, 810 I915_DEBUGFS_ENTRIES, 811 minor->debugfs_root, minor); 812 } 813 814 void i915_debugfs_cleanup(struct drm_minor *minor) 815 { 816 drm_debugfs_remove_files(i915_debugfs_list, 817 I915_DEBUGFS_ENTRIES, minor); 818 drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops, 819 1, minor); 820 } 821 822 #endif /* CONFIG_DEBUG_FS */ 823