xref: /linux/drivers/gpu/drm/i915/i915_debugfs.c (revision 3ea5eb68b9d624935108b5e696859304edfac202)
1 /*
2  * Copyright © 2008 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Eric Anholt <eric@anholt.net>
25  *    Keith Packard <keithp@keithp.com>
26  *
27  */
28 
29 #include <linux/sched/mm.h>
30 #include <linux/sort.h>
31 #include <linux/string_helpers.h>
32 
33 #include <linux/debugfs.h>
34 #include <drm/drm_debugfs.h>
35 
36 #include "display/intel_display_params.h"
37 
38 #include "gem/i915_gem_context.h"
39 #include "gt/intel_gt.h"
40 #include "gt/intel_gt_buffer_pool.h"
41 #include "gt/intel_gt_clock_utils.h"
42 #include "gt/intel_gt_debugfs.h"
43 #include "gt/intel_gt_pm.h"
44 #include "gt/intel_gt_pm_debugfs.h"
45 #include "gt/intel_gt_regs.h"
46 #include "gt/intel_gt_requests.h"
47 #include "gt/intel_rc6.h"
48 #include "gt/intel_reset.h"
49 #include "gt/intel_rps.h"
50 #include "gt/intel_sseu_debugfs.h"
51 
52 #include "i915_debugfs.h"
53 #include "i915_debugfs_params.h"
54 #include "i915_driver.h"
55 #include "i915_gpu_error.h"
56 #include "i915_irq.h"
57 #include "i915_reg.h"
58 #include "i915_scheduler.h"
59 #include "intel_mchbar_regs.h"
60 
61 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
62 {
63 	return to_i915(node->minor->dev);
64 }
65 
66 static int i915_capabilities(struct seq_file *m, void *data)
67 {
68 	struct drm_i915_private *i915 = node_to_i915(m->private);
69 	struct intel_display *display = &i915->display;
70 	struct drm_printer p = drm_seq_file_printer(m);
71 
72 	seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915));
73 
74 	intel_device_info_print(INTEL_INFO(i915), RUNTIME_INFO(i915), &p);
75 	i915_print_iommu_status(i915, &p);
76 	intel_gt_info_print(&to_gt(i915)->info, &p);
77 	intel_driver_caps_print(&i915->caps, &p);
78 
79 	kernel_param_lock(THIS_MODULE);
80 	i915_params_dump(&i915->params, &p);
81 	intel_display_params_dump(display, &p);
82 	kernel_param_unlock(THIS_MODULE);
83 
84 	return 0;
85 }
86 
87 static char get_tiling_flag(struct drm_i915_gem_object *obj)
88 {
89 	switch (i915_gem_object_get_tiling(obj)) {
90 	default:
91 	case I915_TILING_NONE: return ' ';
92 	case I915_TILING_X: return 'X';
93 	case I915_TILING_Y: return 'Y';
94 	}
95 }
96 
97 static char get_global_flag(struct drm_i915_gem_object *obj)
98 {
99 	return READ_ONCE(obj->userfault_count) ? 'g' : ' ';
100 }
101 
102 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
103 {
104 	return obj->mm.mapping ? 'M' : ' ';
105 }
106 
107 static const char *
108 stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len)
109 {
110 	size_t x = 0;
111 
112 	switch (page_sizes) {
113 	case 0:
114 		return "";
115 	case I915_GTT_PAGE_SIZE_4K:
116 		return "4K";
117 	case I915_GTT_PAGE_SIZE_64K:
118 		return "64K";
119 	case I915_GTT_PAGE_SIZE_2M:
120 		return "2M";
121 	default:
122 		if (!buf)
123 			return "M";
124 
125 		if (page_sizes & I915_GTT_PAGE_SIZE_2M)
126 			x += snprintf(buf + x, len - x, "2M, ");
127 		if (page_sizes & I915_GTT_PAGE_SIZE_64K)
128 			x += snprintf(buf + x, len - x, "64K, ");
129 		if (page_sizes & I915_GTT_PAGE_SIZE_4K)
130 			x += snprintf(buf + x, len - x, "4K, ");
131 		buf[x-2] = '\0';
132 
133 		return buf;
134 	}
135 }
136 
137 static const char *stringify_vma_type(const struct i915_vma *vma)
138 {
139 	if (i915_vma_is_ggtt(vma))
140 		return "ggtt";
141 
142 	if (i915_vma_is_dpt(vma))
143 		return "dpt";
144 
145 	return "ppgtt";
146 }
147 
148 static const char *i915_cache_level_str(struct drm_i915_gem_object *obj)
149 {
150 	struct drm_i915_private *i915 = obj_to_i915(obj);
151 
152 	if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 74))) {
153 		switch (obj->pat_index) {
154 		case 0: return " WB";
155 		case 1: return " WT";
156 		case 2: return " UC";
157 		case 3: return " WB (1-Way Coh)";
158 		case 4: return " WB (2-Way Coh)";
159 		default: return " not defined";
160 		}
161 	} else if (GRAPHICS_VER(i915) >= 12) {
162 		switch (obj->pat_index) {
163 		case 0: return " WB";
164 		case 1: return " WC";
165 		case 2: return " WT";
166 		case 3: return " UC";
167 		default: return " not defined";
168 		}
169 	} else {
170 		switch (obj->pat_index) {
171 		case 0: return " UC";
172 		case 1: return HAS_LLC(i915) ?
173 			       " LLC" : " snooped";
174 		case 2: return " L3+LLC";
175 		case 3: return " WT";
176 		default: return " not defined";
177 		}
178 	}
179 }
180 
181 void
182 i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
183 {
184 	struct i915_vma *vma;
185 	int pin_count = 0;
186 
187 	seq_printf(m, "%pK: %c%c%c %8zdKiB %02x %02x %s%s%s",
188 		   &obj->base,
189 		   get_tiling_flag(obj),
190 		   get_global_flag(obj),
191 		   get_pin_mapped_flag(obj),
192 		   obj->base.size / 1024,
193 		   obj->read_domains,
194 		   obj->write_domain,
195 		   i915_cache_level_str(obj),
196 		   obj->mm.dirty ? " dirty" : "",
197 		   obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
198 	if (obj->base.name)
199 		seq_printf(m, " (name: %d)", obj->base.name);
200 
201 	spin_lock(&obj->vma.lock);
202 	list_for_each_entry(vma, &obj->vma.list, obj_link) {
203 		if (!drm_mm_node_allocated(&vma->node))
204 			continue;
205 
206 		spin_unlock(&obj->vma.lock);
207 
208 		if (i915_vma_is_pinned(vma))
209 			pin_count++;
210 
211 		seq_printf(m, " (%s offset: %08llx, size: %08llx, pages: %s",
212 			   stringify_vma_type(vma),
213 			   i915_vma_offset(vma), i915_vma_size(vma),
214 			   stringify_page_sizes(vma->resource->page_sizes_gtt,
215 						NULL, 0));
216 		if (i915_vma_is_ggtt(vma) || i915_vma_is_dpt(vma)) {
217 			switch (vma->gtt_view.type) {
218 			case I915_GTT_VIEW_NORMAL:
219 				seq_puts(m, ", normal");
220 				break;
221 
222 			case I915_GTT_VIEW_PARTIAL:
223 				seq_printf(m, ", partial [%08llx+%x]",
224 					   vma->gtt_view.partial.offset << PAGE_SHIFT,
225 					   vma->gtt_view.partial.size << PAGE_SHIFT);
226 				break;
227 
228 			case I915_GTT_VIEW_ROTATED:
229 				seq_printf(m, ", rotated [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]",
230 					   vma->gtt_view.rotated.plane[0].width,
231 					   vma->gtt_view.rotated.plane[0].height,
232 					   vma->gtt_view.rotated.plane[0].src_stride,
233 					   vma->gtt_view.rotated.plane[0].dst_stride,
234 					   vma->gtt_view.rotated.plane[0].offset,
235 					   vma->gtt_view.rotated.plane[1].width,
236 					   vma->gtt_view.rotated.plane[1].height,
237 					   vma->gtt_view.rotated.plane[1].src_stride,
238 					   vma->gtt_view.rotated.plane[1].dst_stride,
239 					   vma->gtt_view.rotated.plane[1].offset);
240 				break;
241 
242 			case I915_GTT_VIEW_REMAPPED:
243 				seq_printf(m, ", remapped [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]",
244 					   vma->gtt_view.remapped.plane[0].width,
245 					   vma->gtt_view.remapped.plane[0].height,
246 					   vma->gtt_view.remapped.plane[0].src_stride,
247 					   vma->gtt_view.remapped.plane[0].dst_stride,
248 					   vma->gtt_view.remapped.plane[0].offset,
249 					   vma->gtt_view.remapped.plane[1].width,
250 					   vma->gtt_view.remapped.plane[1].height,
251 					   vma->gtt_view.remapped.plane[1].src_stride,
252 					   vma->gtt_view.remapped.plane[1].dst_stride,
253 					   vma->gtt_view.remapped.plane[1].offset);
254 				break;
255 
256 			default:
257 				MISSING_CASE(vma->gtt_view.type);
258 				break;
259 			}
260 		}
261 		if (vma->fence)
262 			seq_printf(m, " , fence: %d", vma->fence->id);
263 		seq_puts(m, ")");
264 
265 		spin_lock(&obj->vma.lock);
266 	}
267 	spin_unlock(&obj->vma.lock);
268 
269 	seq_printf(m, " (pinned x %d)", pin_count);
270 	if (i915_gem_object_is_stolen(obj))
271 		seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
272 	if (i915_gem_object_is_framebuffer(obj))
273 		seq_printf(m, " (fb)");
274 }
275 
276 static int i915_gem_object_info(struct seq_file *m, void *data)
277 {
278 	struct drm_i915_private *i915 = node_to_i915(m->private);
279 	struct drm_printer p = drm_seq_file_printer(m);
280 	struct intel_memory_region *mr;
281 	enum intel_region_id id;
282 
283 	seq_printf(m, "%u shrinkable [%u free] objects, %llu bytes\n",
284 		   i915->mm.shrink_count,
285 		   atomic_read(&i915->mm.free_count),
286 		   i915->mm.shrink_memory);
287 	for_each_memory_region(mr, i915, id)
288 		intel_memory_region_debug(mr, &p);
289 
290 	return 0;
291 }
292 
293 static int i915_frequency_info(struct seq_file *m, void *unused)
294 {
295 	struct drm_i915_private *i915 = node_to_i915(m->private);
296 	struct intel_gt *gt = to_gt(i915);
297 	struct drm_printer p = drm_seq_file_printer(m);
298 
299 	intel_gt_pm_frequency_dump(gt, &p);
300 
301 	return 0;
302 }
303 
304 static const char *swizzle_string(unsigned swizzle)
305 {
306 	switch (swizzle) {
307 	case I915_BIT_6_SWIZZLE_NONE:
308 		return "none";
309 	case I915_BIT_6_SWIZZLE_9:
310 		return "bit9";
311 	case I915_BIT_6_SWIZZLE_9_10:
312 		return "bit9/bit10";
313 	case I915_BIT_6_SWIZZLE_9_11:
314 		return "bit9/bit11";
315 	case I915_BIT_6_SWIZZLE_9_10_11:
316 		return "bit9/bit10/bit11";
317 	case I915_BIT_6_SWIZZLE_9_17:
318 		return "bit9/bit17";
319 	case I915_BIT_6_SWIZZLE_9_10_17:
320 		return "bit9/bit10/bit17";
321 	case I915_BIT_6_SWIZZLE_UNKNOWN:
322 		return "unknown";
323 	}
324 
325 	return "bug";
326 }
327 
328 static int i915_swizzle_info(struct seq_file *m, void *data)
329 {
330 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
331 	struct intel_uncore *uncore = &dev_priv->uncore;
332 	intel_wakeref_t wakeref;
333 
334 	seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
335 		   swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_x));
336 	seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
337 		   swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_y));
338 
339 	if (dev_priv->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES)
340 		seq_puts(m, "L-shaped memory detected\n");
341 
342 	/* On BDW+, swizzling is not used. See detect_bit_6_swizzle() */
343 	if (GRAPHICS_VER(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv))
344 		return 0;
345 
346 	wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
347 
348 	if (IS_GRAPHICS_VER(dev_priv, 3, 4)) {
349 		seq_printf(m, "DDC = 0x%08x\n",
350 			   intel_uncore_read(uncore, DCC));
351 		seq_printf(m, "DDC2 = 0x%08x\n",
352 			   intel_uncore_read(uncore, DCC2));
353 		seq_printf(m, "C0DRB3 = 0x%04x\n",
354 			   intel_uncore_read16(uncore, C0DRB3_BW));
355 		seq_printf(m, "C1DRB3 = 0x%04x\n",
356 			   intel_uncore_read16(uncore, C1DRB3_BW));
357 	} else if (GRAPHICS_VER(dev_priv) >= 6) {
358 		seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
359 			   intel_uncore_read(uncore, MAD_DIMM_C0));
360 		seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
361 			   intel_uncore_read(uncore, MAD_DIMM_C1));
362 		seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
363 			   intel_uncore_read(uncore, MAD_DIMM_C2));
364 		seq_printf(m, "TILECTL = 0x%08x\n",
365 			   intel_uncore_read(uncore, TILECTL));
366 		if (GRAPHICS_VER(dev_priv) >= 8)
367 			seq_printf(m, "GAMTARBMODE = 0x%08x\n",
368 				   intel_uncore_read(uncore, GAMTARBMODE));
369 		else
370 			seq_printf(m, "ARB_MODE = 0x%08x\n",
371 				   intel_uncore_read(uncore, ARB_MODE));
372 		seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
373 			   intel_uncore_read(uncore, DISP_ARB_CTL));
374 	}
375 
376 	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
377 
378 	return 0;
379 }
380 
381 static int i915_rps_boost_info(struct seq_file *m, void *data)
382 {
383 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
384 	struct intel_rps *rps = &to_gt(dev_priv)->rps;
385 
386 	seq_printf(m, "RPS enabled? %s\n",
387 		   str_yes_no(intel_rps_is_enabled(rps)));
388 	seq_printf(m, "RPS active? %s\n",
389 		   str_yes_no(intel_rps_is_active(rps)));
390 	seq_printf(m, "GPU busy? %s\n", str_yes_no(to_gt(dev_priv)->awake));
391 	seq_printf(m, "Boosts outstanding? %d\n",
392 		   atomic_read(&rps->num_waiters));
393 	seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));
394 	seq_printf(m, "Frequency requested %d, actual %d\n",
395 		   intel_gpu_freq(rps, rps->cur_freq),
396 		   intel_rps_read_actual_frequency(rps));
397 	seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
398 		   intel_gpu_freq(rps, rps->min_freq),
399 		   intel_gpu_freq(rps, rps->min_freq_softlimit),
400 		   intel_gpu_freq(rps, rps->max_freq_softlimit),
401 		   intel_gpu_freq(rps, rps->max_freq));
402 	seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
403 		   intel_gpu_freq(rps, rps->idle_freq),
404 		   intel_gpu_freq(rps, rps->efficient_freq),
405 		   intel_gpu_freq(rps, rps->boost_freq));
406 
407 	seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts));
408 
409 	return 0;
410 }
411 
412 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
413 {
414 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
415 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
416 
417 	if (!HAS_RUNTIME_PM(dev_priv))
418 		seq_puts(m, "Runtime power management not supported\n");
419 
420 	seq_printf(m, "Runtime power status: %s\n",
421 		   str_enabled_disabled(!dev_priv->display.power.domains.init_wakeref));
422 
423 	seq_printf(m, "GPU idle: %s\n", str_yes_no(!to_gt(dev_priv)->awake));
424 	seq_printf(m, "IRQs disabled: %s\n",
425 		   str_yes_no(!intel_irqs_enabled(dev_priv)));
426 #ifdef CONFIG_PM
427 	seq_printf(m, "Usage count: %d\n",
428 		   atomic_read(&dev_priv->drm.dev->power.usage_count));
429 #else
430 	seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
431 #endif
432 	seq_printf(m, "PCI device power state: %s [%d]\n",
433 		   pci_power_name(pdev->current_state),
434 		   pdev->current_state);
435 
436 	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) {
437 		struct drm_printer p = drm_seq_file_printer(m);
438 
439 		print_intel_runtime_pm_wakeref(&dev_priv->runtime_pm, &p);
440 	}
441 
442 	return 0;
443 }
444 
445 static int i915_engine_info(struct seq_file *m, void *unused)
446 {
447 	struct drm_i915_private *i915 = node_to_i915(m->private);
448 	struct intel_engine_cs *engine;
449 	intel_wakeref_t wakeref;
450 	struct drm_printer p;
451 
452 	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
453 
454 	seq_printf(m, "GT awake? %s [%d], %llums\n",
455 		   str_yes_no(to_gt(i915)->awake),
456 		   atomic_read(&to_gt(i915)->wakeref.count),
457 		   ktime_to_ms(intel_gt_get_awake_time(to_gt(i915))));
458 	seq_printf(m, "CS timestamp frequency: %u Hz, %d ns\n",
459 		   to_gt(i915)->clock_frequency,
460 		   to_gt(i915)->clock_period_ns);
461 
462 	p = drm_seq_file_printer(m);
463 	for_each_uabi_engine(engine, i915)
464 		intel_engine_dump(engine, &p, "%s\n", engine->name);
465 
466 	intel_gt_show_timelines(to_gt(i915), &p, i915_request_show_with_schedule);
467 
468 	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
469 
470 	return 0;
471 }
472 
473 static int i915_wa_registers(struct seq_file *m, void *unused)
474 {
475 	struct drm_i915_private *i915 = node_to_i915(m->private);
476 	struct intel_engine_cs *engine;
477 
478 	for_each_uabi_engine(engine, i915) {
479 		const struct i915_wa_list *wal = &engine->ctx_wa_list;
480 		const struct i915_wa *wa;
481 		unsigned int count;
482 
483 		count = wal->count;
484 		if (!count)
485 			continue;
486 
487 		seq_printf(m, "%s: Workarounds applied: %u\n",
488 			   engine->name, count);
489 
490 		for (wa = wal->list; count--; wa++)
491 			seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
492 				   i915_mmio_reg_offset(wa->reg),
493 				   wa->set, wa->clr);
494 
495 		seq_printf(m, "\n");
496 	}
497 
498 	return 0;
499 }
500 
501 static int i915_wedged_get(void *data, u64 *val)
502 {
503 	struct drm_i915_private *i915 = data;
504 	struct intel_gt *gt;
505 	unsigned int i;
506 
507 	*val = 0;
508 
509 	for_each_gt(gt, i915, i) {
510 		int ret;
511 
512 		ret = intel_gt_debugfs_reset_show(gt, val);
513 		if (ret)
514 			return ret;
515 
516 		/* at least one tile should be wedged */
517 		if (*val)
518 			break;
519 	}
520 
521 	return 0;
522 }
523 
524 static int i915_wedged_set(void *data, u64 val)
525 {
526 	struct drm_i915_private *i915 = data;
527 	struct intel_gt *gt;
528 	unsigned int i;
529 
530 	for_each_gt(gt, i915, i)
531 		intel_gt_debugfs_reset_store(gt, val);
532 
533 	return 0;
534 }
535 
536 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
537 			i915_wedged_get, i915_wedged_set,
538 			"%llu\n");
539 
540 static int
541 i915_perf_noa_delay_set(void *data, u64 val)
542 {
543 	struct drm_i915_private *i915 = data;
544 
545 	/*
546 	 * This would lead to infinite waits as we're doing timestamp
547 	 * difference on the CS with only 32bits.
548 	 */
549 	if (intel_gt_ns_to_clock_interval(to_gt(i915), val) > U32_MAX)
550 		return -EINVAL;
551 
552 	atomic64_set(&i915->perf.noa_programming_delay, val);
553 	return 0;
554 }
555 
556 static int
557 i915_perf_noa_delay_get(void *data, u64 *val)
558 {
559 	struct drm_i915_private *i915 = data;
560 
561 	*val = atomic64_read(&i915->perf.noa_programming_delay);
562 	return 0;
563 }
564 
565 DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops,
566 			i915_perf_noa_delay_get,
567 			i915_perf_noa_delay_set,
568 			"%llu\n");
569 
570 #define DROP_UNBOUND	BIT(0)
571 #define DROP_BOUND	BIT(1)
572 #define DROP_RETIRE	BIT(2)
573 #define DROP_ACTIVE	BIT(3)
574 #define DROP_FREED	BIT(4)
575 #define DROP_SHRINK_ALL	BIT(5)
576 #define DROP_IDLE	BIT(6)
577 #define DROP_RESET_ACTIVE	BIT(7)
578 #define DROP_RESET_SEQNO	BIT(8)
579 #define DROP_RCU	BIT(9)
580 #define DROP_ALL (DROP_UNBOUND	| \
581 		  DROP_BOUND	| \
582 		  DROP_RETIRE	| \
583 		  DROP_ACTIVE	| \
584 		  DROP_FREED	| \
585 		  DROP_SHRINK_ALL |\
586 		  DROP_IDLE	| \
587 		  DROP_RESET_ACTIVE | \
588 		  DROP_RESET_SEQNO | \
589 		  DROP_RCU)
590 static int
591 i915_drop_caches_get(void *data, u64 *val)
592 {
593 	*val = DROP_ALL;
594 
595 	return 0;
596 }
597 
598 static int
599 gt_drop_caches(struct intel_gt *gt, u64 val)
600 {
601 	int ret;
602 
603 	if (val & DROP_RESET_ACTIVE &&
604 	    wait_for(intel_engines_are_idle(gt), 200))
605 		intel_gt_set_wedged(gt);
606 
607 	if (val & DROP_RETIRE)
608 		intel_gt_retire_requests(gt);
609 
610 	if (val & (DROP_IDLE | DROP_ACTIVE)) {
611 		ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT);
612 		if (ret)
613 			return ret;
614 	}
615 
616 	if (val & DROP_IDLE) {
617 		ret = intel_gt_pm_wait_for_idle(gt);
618 		if (ret)
619 			return ret;
620 	}
621 
622 	if (val & DROP_RESET_ACTIVE && intel_gt_terminally_wedged(gt))
623 		intel_gt_handle_error(gt, ALL_ENGINES, 0, NULL);
624 
625 	if (val & DROP_FREED)
626 		intel_gt_flush_buffer_pool(gt);
627 
628 	return 0;
629 }
630 
631 static int
632 i915_drop_caches_set(void *data, u64 val)
633 {
634 	struct drm_i915_private *i915 = data;
635 	struct intel_gt *gt;
636 	unsigned int flags;
637 	unsigned int i;
638 	int ret;
639 
640 	drm_dbg(&i915->drm, "Dropping caches: 0x%08llx [0x%08llx]\n",
641 		val, val & DROP_ALL);
642 
643 	for_each_gt(gt, i915, i) {
644 		ret = gt_drop_caches(gt, val);
645 		if (ret)
646 			return ret;
647 	}
648 
649 	fs_reclaim_acquire(GFP_KERNEL);
650 	flags = memalloc_noreclaim_save();
651 	if (val & DROP_BOUND)
652 		i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_BOUND);
653 
654 	if (val & DROP_UNBOUND)
655 		i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_UNBOUND);
656 
657 	if (val & DROP_SHRINK_ALL)
658 		i915_gem_shrink_all(i915);
659 	memalloc_noreclaim_restore(flags);
660 	fs_reclaim_release(GFP_KERNEL);
661 
662 	if (val & DROP_RCU)
663 		rcu_barrier();
664 
665 	if (val & DROP_FREED)
666 		i915_gem_drain_freed_objects(i915);
667 
668 	return 0;
669 }
670 
671 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
672 			i915_drop_caches_get, i915_drop_caches_set,
673 			"0x%08llx\n");
674 
675 static int i915_sseu_status(struct seq_file *m, void *unused)
676 {
677 	struct drm_i915_private *i915 = node_to_i915(m->private);
678 	struct intel_gt *gt = to_gt(i915);
679 
680 	return intel_sseu_status(m, gt);
681 }
682 
683 static int i915_forcewake_open(struct inode *inode, struct file *file)
684 {
685 	struct drm_i915_private *i915 = inode->i_private;
686 	struct intel_gt *gt;
687 	unsigned int i;
688 
689 	for_each_gt(gt, i915, i)
690 		intel_gt_pm_debugfs_forcewake_user_open(gt);
691 
692 	return 0;
693 }
694 
695 static int i915_forcewake_release(struct inode *inode, struct file *file)
696 {
697 	struct drm_i915_private *i915 = inode->i_private;
698 	struct intel_gt *gt;
699 	unsigned int i;
700 
701 	for_each_gt(gt, i915, i)
702 		intel_gt_pm_debugfs_forcewake_user_release(gt);
703 
704 	return 0;
705 }
706 
707 static const struct file_operations i915_forcewake_fops = {
708 	.owner = THIS_MODULE,
709 	.open = i915_forcewake_open,
710 	.release = i915_forcewake_release,
711 };
712 
713 static const struct drm_info_list i915_debugfs_list[] = {
714 	{"i915_capabilities", i915_capabilities, 0},
715 	{"i915_gem_objects", i915_gem_object_info, 0},
716 	{"i915_frequency_info", i915_frequency_info, 0},
717 	{"i915_swizzle_info", i915_swizzle_info, 0},
718 	{"i915_runtime_pm_status", i915_runtime_pm_status, 0},
719 	{"i915_engine_info", i915_engine_info, 0},
720 	{"i915_wa_registers", i915_wa_registers, 0},
721 	{"i915_sseu_status", i915_sseu_status, 0},
722 	{"i915_rps_boost_info", i915_rps_boost_info, 0},
723 };
724 
725 static const struct i915_debugfs_files {
726 	const char *name;
727 	const struct file_operations *fops;
728 } i915_debugfs_files[] = {
729 	{"i915_perf_noa_delay", &i915_perf_noa_delay_fops},
730 	{"i915_wedged", &i915_wedged_fops},
731 	{"i915_gem_drop_caches", &i915_drop_caches_fops},
732 };
733 
734 void i915_debugfs_register(struct drm_i915_private *dev_priv)
735 {
736 	struct drm_minor *minor = dev_priv->drm.primary;
737 	int i;
738 
739 	i915_debugfs_params(dev_priv);
740 
741 	debugfs_create_file("i915_forcewake_user", S_IRUSR, minor->debugfs_root,
742 			    to_i915(minor->dev), &i915_forcewake_fops);
743 	for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
744 		debugfs_create_file(i915_debugfs_files[i].name,
745 				    S_IRUGO | S_IWUSR,
746 				    minor->debugfs_root,
747 				    to_i915(minor->dev),
748 				    i915_debugfs_files[i].fops);
749 	}
750 
751 	drm_debugfs_create_files(i915_debugfs_list,
752 				 ARRAY_SIZE(i915_debugfs_list),
753 				 minor->debugfs_root, minor);
754 
755 	i915_gpu_error_debugfs_register(dev_priv);
756 }
757