xref: /linux/drivers/gpu/drm/i915/i915_debugfs.c (revision 27258e448eb301cf89e351df87aa8cb916653bf2)
1 /*
2  * Copyright © 2008 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Eric Anholt <eric@anholt.net>
25  *    Keith Packard <keithp@keithp.com>
26  *
27  */
28 
29 #include <linux/seq_file.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drm.h"
33 #include "i915_drv.h"
34 
35 #define DRM_I915_RING_DEBUG 1
36 
37 
38 #if defined(CONFIG_DEBUG_FS)
39 
40 #define ACTIVE_LIST	1
41 #define FLUSHING_LIST	2
42 #define INACTIVE_LIST	3
43 
44 static const char *get_pin_flag(struct drm_i915_gem_object *obj_priv)
45 {
46 	if (obj_priv->user_pin_count > 0)
47 		return "P";
48 	else if (obj_priv->pin_count > 0)
49 		return "p";
50 	else
51 		return " ";
52 }
53 
54 static const char *get_tiling_flag(struct drm_i915_gem_object *obj_priv)
55 {
56     switch (obj_priv->tiling_mode) {
57     default:
58     case I915_TILING_NONE: return " ";
59     case I915_TILING_X: return "X";
60     case I915_TILING_Y: return "Y";
61     }
62 }
63 
64 static int i915_gem_object_list_info(struct seq_file *m, void *data)
65 {
66 	struct drm_info_node *node = (struct drm_info_node *) m->private;
67 	uintptr_t list = (uintptr_t) node->info_ent->data;
68 	struct list_head *head;
69 	struct drm_device *dev = node->minor->dev;
70 	drm_i915_private_t *dev_priv = dev->dev_private;
71 	struct drm_i915_gem_object *obj_priv;
72 	spinlock_t *lock = NULL;
73 
74 	switch (list) {
75 	case ACTIVE_LIST:
76 		seq_printf(m, "Active:\n");
77 		lock = &dev_priv->mm.active_list_lock;
78 		head = &dev_priv->mm.active_list;
79 		break;
80 	case INACTIVE_LIST:
81 		seq_printf(m, "Inactive:\n");
82 		head = &dev_priv->mm.inactive_list;
83 		break;
84 	case FLUSHING_LIST:
85 		seq_printf(m, "Flushing:\n");
86 		head = &dev_priv->mm.flushing_list;
87 		break;
88 	default:
89 		DRM_INFO("Ooops, unexpected list\n");
90 		return 0;
91 	}
92 
93 	if (lock)
94 		spin_lock(lock);
95 	list_for_each_entry(obj_priv, head, list)
96 	{
97 		struct drm_gem_object *obj = obj_priv->obj;
98 
99 		seq_printf(m, "    %p: %s %08x %08x %d",
100 			   obj,
101 			   get_pin_flag(obj_priv),
102 			   obj->read_domains, obj->write_domain,
103 			   obj_priv->last_rendering_seqno);
104 
105 		if (obj->name)
106 			seq_printf(m, " (name: %d)", obj->name);
107 		if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
108 			seq_printf(m, " (fence: %d)", obj_priv->fence_reg);
109 		if (obj_priv->gtt_space != NULL)
110 			seq_printf(m, " (gtt_offset: %08x)", obj_priv->gtt_offset);
111 
112 		seq_printf(m, "\n");
113 	}
114 
115 	if (lock)
116 	    spin_unlock(lock);
117 	return 0;
118 }
119 
120 static int i915_gem_request_info(struct seq_file *m, void *data)
121 {
122 	struct drm_info_node *node = (struct drm_info_node *) m->private;
123 	struct drm_device *dev = node->minor->dev;
124 	drm_i915_private_t *dev_priv = dev->dev_private;
125 	struct drm_i915_gem_request *gem_request;
126 
127 	seq_printf(m, "Request:\n");
128 	list_for_each_entry(gem_request, &dev_priv->mm.request_list, list) {
129 		seq_printf(m, "    %d @ %d\n",
130 			   gem_request->seqno,
131 			   (int) (jiffies - gem_request->emitted_jiffies));
132 	}
133 	return 0;
134 }
135 
136 static int i915_gem_seqno_info(struct seq_file *m, void *data)
137 {
138 	struct drm_info_node *node = (struct drm_info_node *) m->private;
139 	struct drm_device *dev = node->minor->dev;
140 	drm_i915_private_t *dev_priv = dev->dev_private;
141 
142 	if (dev_priv->hw_status_page != NULL) {
143 		seq_printf(m, "Current sequence: %d\n",
144 			   i915_get_gem_seqno(dev));
145 	} else {
146 		seq_printf(m, "Current sequence: hws uninitialized\n");
147 	}
148 	seq_printf(m, "Waiter sequence:  %d\n",
149 			dev_priv->mm.waiting_gem_seqno);
150 	seq_printf(m, "IRQ sequence:     %d\n", dev_priv->mm.irq_gem_seqno);
151 	return 0;
152 }
153 
154 
155 static int i915_interrupt_info(struct seq_file *m, void *data)
156 {
157 	struct drm_info_node *node = (struct drm_info_node *) m->private;
158 	struct drm_device *dev = node->minor->dev;
159 	drm_i915_private_t *dev_priv = dev->dev_private;
160 
161 	if (!IS_IGDNG(dev)) {
162 		seq_printf(m, "Interrupt enable:    %08x\n",
163 			   I915_READ(IER));
164 		seq_printf(m, "Interrupt identity:  %08x\n",
165 			   I915_READ(IIR));
166 		seq_printf(m, "Interrupt mask:      %08x\n",
167 			   I915_READ(IMR));
168 		seq_printf(m, "Pipe A stat:         %08x\n",
169 			   I915_READ(PIPEASTAT));
170 		seq_printf(m, "Pipe B stat:         %08x\n",
171 			   I915_READ(PIPEBSTAT));
172 	} else {
173 		seq_printf(m, "North Display Interrupt enable:		%08x\n",
174 			   I915_READ(DEIER));
175 		seq_printf(m, "North Display Interrupt identity:	%08x\n",
176 			   I915_READ(DEIIR));
177 		seq_printf(m, "North Display Interrupt mask:		%08x\n",
178 			   I915_READ(DEIMR));
179 		seq_printf(m, "South Display Interrupt enable:		%08x\n",
180 			   I915_READ(SDEIER));
181 		seq_printf(m, "South Display Interrupt identity:	%08x\n",
182 			   I915_READ(SDEIIR));
183 		seq_printf(m, "South Display Interrupt mask:		%08x\n",
184 			   I915_READ(SDEIMR));
185 		seq_printf(m, "Graphics Interrupt enable:		%08x\n",
186 			   I915_READ(GTIER));
187 		seq_printf(m, "Graphics Interrupt identity:		%08x\n",
188 			   I915_READ(GTIIR));
189 		seq_printf(m, "Graphics Interrupt mask:		%08x\n",
190 			   I915_READ(GTIMR));
191 	}
192 	seq_printf(m, "Interrupts received: %d\n",
193 		   atomic_read(&dev_priv->irq_received));
194 	if (dev_priv->hw_status_page != NULL) {
195 		seq_printf(m, "Current sequence:    %d\n",
196 			   i915_get_gem_seqno(dev));
197 	} else {
198 		seq_printf(m, "Current sequence:    hws uninitialized\n");
199 	}
200 	seq_printf(m, "Waiter sequence:     %d\n",
201 		   dev_priv->mm.waiting_gem_seqno);
202 	seq_printf(m, "IRQ sequence:        %d\n",
203 		   dev_priv->mm.irq_gem_seqno);
204 	return 0;
205 }
206 
207 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
208 {
209 	struct drm_info_node *node = (struct drm_info_node *) m->private;
210 	struct drm_device *dev = node->minor->dev;
211 	drm_i915_private_t *dev_priv = dev->dev_private;
212 	int i;
213 
214 	seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
215 	seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
216 	for (i = 0; i < dev_priv->num_fence_regs; i++) {
217 		struct drm_gem_object *obj = dev_priv->fence_regs[i].obj;
218 
219 		if (obj == NULL) {
220 			seq_printf(m, "Fenced object[%2d] = unused\n", i);
221 		} else {
222 			struct drm_i915_gem_object *obj_priv;
223 
224 			obj_priv = obj->driver_private;
225 			seq_printf(m, "Fenced object[%2d] = %p: %s "
226 				   "%08x %08zx %08x %s %08x %08x %d",
227 				   i, obj, get_pin_flag(obj_priv),
228 				   obj_priv->gtt_offset,
229 				   obj->size, obj_priv->stride,
230 				   get_tiling_flag(obj_priv),
231 				   obj->read_domains, obj->write_domain,
232 				   obj_priv->last_rendering_seqno);
233 			if (obj->name)
234 				seq_printf(m, " (name: %d)", obj->name);
235 			seq_printf(m, "\n");
236 		}
237 	}
238 
239 	return 0;
240 }
241 
242 static int i915_hws_info(struct seq_file *m, void *data)
243 {
244 	struct drm_info_node *node = (struct drm_info_node *) m->private;
245 	struct drm_device *dev = node->minor->dev;
246 	drm_i915_private_t *dev_priv = dev->dev_private;
247 	int i;
248 	volatile u32 *hws;
249 
250 	hws = (volatile u32 *)dev_priv->hw_status_page;
251 	if (hws == NULL)
252 		return 0;
253 
254 	for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
255 		seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
256 			   i * 4,
257 			   hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
258 	}
259 	return 0;
260 }
261 
262 static void i915_dump_pages(struct seq_file *m, struct page **pages, int page_count)
263 {
264 	int page, i;
265 	uint32_t *mem;
266 
267 	for (page = 0; page < page_count; page++) {
268 		mem = kmap(pages[page]);
269 		for (i = 0; i < PAGE_SIZE; i += 4)
270 			seq_printf(m, "%08x :  %08x\n", i, mem[i / 4]);
271 		kunmap(pages[page]);
272 	}
273 }
274 
275 static int i915_batchbuffer_info(struct seq_file *m, void *data)
276 {
277 	struct drm_info_node *node = (struct drm_info_node *) m->private;
278 	struct drm_device *dev = node->minor->dev;
279 	drm_i915_private_t *dev_priv = dev->dev_private;
280 	struct drm_gem_object *obj;
281 	struct drm_i915_gem_object *obj_priv;
282 	int ret;
283 
284 	spin_lock(&dev_priv->mm.active_list_lock);
285 
286 	list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
287 		obj = obj_priv->obj;
288 		if (obj->read_domains & I915_GEM_DOMAIN_COMMAND) {
289 		    ret = i915_gem_object_get_pages(obj);
290 		    if (ret) {
291 			    DRM_ERROR("Failed to get pages: %d\n", ret);
292 			    spin_unlock(&dev_priv->mm.active_list_lock);
293 			    return ret;
294 		    }
295 
296 		    seq_printf(m, "--- gtt_offset = 0x%08x\n", obj_priv->gtt_offset);
297 		    i915_dump_pages(m, obj_priv->pages, obj->size / PAGE_SIZE);
298 
299 		    i915_gem_object_put_pages(obj);
300 		}
301 	}
302 
303 	spin_unlock(&dev_priv->mm.active_list_lock);
304 
305 	return 0;
306 }
307 
308 static int i915_ringbuffer_data(struct seq_file *m, void *data)
309 {
310 	struct drm_info_node *node = (struct drm_info_node *) m->private;
311 	struct drm_device *dev = node->minor->dev;
312 	drm_i915_private_t *dev_priv = dev->dev_private;
313 	u8 *virt;
314 	uint32_t *ptr, off;
315 
316 	if (!dev_priv->ring.ring_obj) {
317 		seq_printf(m, "No ringbuffer setup\n");
318 		return 0;
319 	}
320 
321 	virt = dev_priv->ring.virtual_start;
322 
323 	for (off = 0; off < dev_priv->ring.Size; off += 4) {
324 		ptr = (uint32_t *)(virt + off);
325 		seq_printf(m, "%08x :  %08x\n", off, *ptr);
326 	}
327 
328 	return 0;
329 }
330 
331 static int i915_ringbuffer_info(struct seq_file *m, void *data)
332 {
333 	struct drm_info_node *node = (struct drm_info_node *) m->private;
334 	struct drm_device *dev = node->minor->dev;
335 	drm_i915_private_t *dev_priv = dev->dev_private;
336 	unsigned int head, tail;
337 
338 	head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
339 	tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
340 
341 	seq_printf(m, "RingHead :  %08x\n", head);
342 	seq_printf(m, "RingTail :  %08x\n", tail);
343 	seq_printf(m, "RingSize :  %08lx\n", dev_priv->ring.Size);
344 	seq_printf(m, "Acthd :     %08x\n", I915_READ(IS_I965G(dev) ? ACTHD_I965 : ACTHD));
345 
346 	return 0;
347 }
348 
349 static int i915_error_state(struct seq_file *m, void *unused)
350 {
351 	struct drm_info_node *node = (struct drm_info_node *) m->private;
352 	struct drm_device *dev = node->minor->dev;
353 	drm_i915_private_t *dev_priv = dev->dev_private;
354 	struct drm_i915_error_state *error;
355 	unsigned long flags;
356 
357 	spin_lock_irqsave(&dev_priv->error_lock, flags);
358 	if (!dev_priv->first_error) {
359 		seq_printf(m, "no error state collected\n");
360 		goto out;
361 	}
362 
363 	error = dev_priv->first_error;
364 
365 	seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
366 		   error->time.tv_usec);
367 	seq_printf(m, "EIR: 0x%08x\n", error->eir);
368 	seq_printf(m, "  PGTBL_ER: 0x%08x\n", error->pgtbl_er);
369 	seq_printf(m, "  INSTPM: 0x%08x\n", error->instpm);
370 	seq_printf(m, "  IPEIR: 0x%08x\n", error->ipeir);
371 	seq_printf(m, "  IPEHR: 0x%08x\n", error->ipehr);
372 	seq_printf(m, "  INSTDONE: 0x%08x\n", error->instdone);
373 	seq_printf(m, "  ACTHD: 0x%08x\n", error->acthd);
374 	if (IS_I965G(dev)) {
375 		seq_printf(m, "  INSTPS: 0x%08x\n", error->instps);
376 		seq_printf(m, "  INSTDONE1: 0x%08x\n", error->instdone1);
377 	}
378 
379 out:
380 	spin_unlock_irqrestore(&dev_priv->error_lock, flags);
381 
382 	return 0;
383 }
384 
385 static int i915_registers_info(struct seq_file *m, void *data) {
386 	struct drm_info_node *node = (struct drm_info_node *) m->private;
387 	struct drm_device *dev = node->minor->dev;
388 	drm_i915_private_t *dev_priv = dev->dev_private;
389 	uint32_t reg;
390 
391 #define DUMP_RANGE(start, end) \
392 	for (reg=start; reg < end; reg += 4) \
393 	seq_printf(m, "%08x\t%08x\n", reg, I915_READ(reg));
394 
395 	DUMP_RANGE(0x00000, 0x00fff);   /* VGA registers */
396 	DUMP_RANGE(0x02000, 0x02fff);   /* instruction, memory, interrupt control registers */
397 	DUMP_RANGE(0x03000, 0x031ff);   /* FENCE and PPGTT control registers */
398 	DUMP_RANGE(0x03200, 0x03fff);   /* frame buffer compression registers */
399 	DUMP_RANGE(0x05000, 0x05fff);   /* I/O control registers */
400 	DUMP_RANGE(0x06000, 0x06fff);   /* clock control registers */
401 	DUMP_RANGE(0x07000, 0x07fff);   /* 3D internal debug registers */
402 	DUMP_RANGE(0x07400, 0x088ff);   /* GPE debug registers */
403 	DUMP_RANGE(0x0a000, 0x0afff);   /* display palette registers */
404 	DUMP_RANGE(0x10000, 0x13fff);   /* MMIO MCHBAR */
405 	DUMP_RANGE(0x30000, 0x3ffff);   /* overlay registers */
406 	DUMP_RANGE(0x60000, 0x6ffff);   /* display engine pipeline registers */
407 	DUMP_RANGE(0x70000, 0x72fff);   /* display and cursor registers */
408 	DUMP_RANGE(0x73000, 0x73fff);   /* performance counters */
409 
410 	return 0;
411 }
412 
413 
414 static struct drm_info_list i915_debugfs_list[] = {
415 	{"i915_regs", i915_registers_info, 0},
416 	{"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
417 	{"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
418 	{"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
419 	{"i915_gem_request", i915_gem_request_info, 0},
420 	{"i915_gem_seqno", i915_gem_seqno_info, 0},
421 	{"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
422 	{"i915_gem_interrupt", i915_interrupt_info, 0},
423 	{"i915_gem_hws", i915_hws_info, 0},
424 	{"i915_ringbuffer_data", i915_ringbuffer_data, 0},
425 	{"i915_ringbuffer_info", i915_ringbuffer_info, 0},
426 	{"i915_batchbuffers", i915_batchbuffer_info, 0},
427 	{"i915_error_state", i915_error_state, 0},
428 };
429 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
430 
431 int i915_debugfs_init(struct drm_minor *minor)
432 {
433 	return drm_debugfs_create_files(i915_debugfs_list,
434 					I915_DEBUGFS_ENTRIES,
435 					minor->debugfs_root, minor);
436 }
437 
438 void i915_debugfs_cleanup(struct drm_minor *minor)
439 {
440 	drm_debugfs_remove_files(i915_debugfs_list,
441 				 I915_DEBUGFS_ENTRIES, minor);
442 }
443 
444 #endif /* CONFIG_DEBUG_FS */
445 
446