1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * 27 */ 28 29 #include <linux/seq_file.h> 30 #include <linux/debugfs.h> 31 #include <linux/slab.h> 32 #include <linux/export.h> 33 #include "drmP.h" 34 #include "drm.h" 35 #include "intel_drv.h" 36 #include "intel_ringbuffer.h" 37 #include "i915_drm.h" 38 #include "i915_drv.h" 39 40 #define DRM_I915_RING_DEBUG 1 41 42 43 #if defined(CONFIG_DEBUG_FS) 44 45 enum { 46 ACTIVE_LIST, 47 FLUSHING_LIST, 48 INACTIVE_LIST, 49 PINNED_LIST, 50 }; 51 52 static const char *yesno(int v) 53 { 54 return v ? "yes" : "no"; 55 } 56 57 static int i915_capabilities(struct seq_file *m, void *data) 58 { 59 struct drm_info_node *node = (struct drm_info_node *) m->private; 60 struct drm_device *dev = node->minor->dev; 61 const struct intel_device_info *info = INTEL_INFO(dev); 62 63 seq_printf(m, "gen: %d\n", info->gen); 64 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); 65 #define B(x) seq_printf(m, #x ": %s\n", yesno(info->x)) 66 B(is_mobile); 67 B(is_i85x); 68 B(is_i915g); 69 B(is_i945gm); 70 B(is_g33); 71 B(need_gfx_hws); 72 B(is_g4x); 73 B(is_pineview); 74 B(is_broadwater); 75 B(is_crestline); 76 B(has_fbc); 77 B(has_pipe_cxsr); 78 B(has_hotplug); 79 B(cursor_needs_physical); 80 B(has_overlay); 81 B(overlay_needs_physical); 82 B(supports_tv); 83 B(has_bsd_ring); 84 B(has_blt_ring); 85 B(has_llc); 86 #undef B 87 88 return 0; 89 } 90 91 static const char *get_pin_flag(struct drm_i915_gem_object *obj) 92 { 93 if (obj->user_pin_count > 0) 94 return "P"; 95 else if (obj->pin_count > 0) 96 return "p"; 97 else 98 return " "; 99 } 100 101 static const char *get_tiling_flag(struct drm_i915_gem_object *obj) 102 { 103 switch (obj->tiling_mode) { 104 default: 105 case I915_TILING_NONE: return " "; 106 case I915_TILING_X: return "X"; 107 case I915_TILING_Y: return "Y"; 108 } 109 } 110 111 static const char *cache_level_str(int type) 112 { 113 switch (type) { 114 case I915_CACHE_NONE: return " uncached"; 115 case I915_CACHE_LLC: return " snooped (LLC)"; 116 case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)"; 117 default: return ""; 118 } 119 } 120 121 static void 122 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) 123 { 124 seq_printf(m, "%p: %s%s %8zdKiB %04x %04x %d %d%s%s%s", 125 &obj->base, 126 get_pin_flag(obj), 127 get_tiling_flag(obj), 128 obj->base.size / 1024, 129 obj->base.read_domains, 130 obj->base.write_domain, 131 obj->last_rendering_seqno, 132 obj->last_fenced_seqno, 133 cache_level_str(obj->cache_level), 134 obj->dirty ? " dirty" : "", 135 obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); 136 if (obj->base.name) 137 seq_printf(m, " (name: %d)", obj->base.name); 138 if (obj->fence_reg != I915_FENCE_REG_NONE) 139 seq_printf(m, " (fence: %d)", obj->fence_reg); 140 if (obj->gtt_space != NULL) 141 seq_printf(m, " (gtt offset: %08x, size: %08x)", 142 obj->gtt_offset, (unsigned int)obj->gtt_space->size); 143 if (obj->pin_mappable || obj->fault_mappable) { 144 char s[3], *t = s; 145 if (obj->pin_mappable) 146 *t++ = 'p'; 147 if (obj->fault_mappable) 148 *t++ = 'f'; 149 *t = '\0'; 150 seq_printf(m, " (%s mappable)", s); 151 } 152 if (obj->ring != NULL) 153 seq_printf(m, " (%s)", obj->ring->name); 154 } 155 156 static int i915_gem_object_list_info(struct seq_file *m, void *data) 157 { 158 struct drm_info_node *node = (struct drm_info_node *) m->private; 159 uintptr_t list = (uintptr_t) node->info_ent->data; 160 struct list_head *head; 161 struct drm_device *dev = node->minor->dev; 162 drm_i915_private_t *dev_priv = dev->dev_private; 163 struct drm_i915_gem_object *obj; 164 size_t total_obj_size, total_gtt_size; 165 int count, ret; 166 167 ret = mutex_lock_interruptible(&dev->struct_mutex); 168 if (ret) 169 return ret; 170 171 switch (list) { 172 case ACTIVE_LIST: 173 seq_printf(m, "Active:\n"); 174 head = &dev_priv->mm.active_list; 175 break; 176 case INACTIVE_LIST: 177 seq_printf(m, "Inactive:\n"); 178 head = &dev_priv->mm.inactive_list; 179 break; 180 case FLUSHING_LIST: 181 seq_printf(m, "Flushing:\n"); 182 head = &dev_priv->mm.flushing_list; 183 break; 184 default: 185 mutex_unlock(&dev->struct_mutex); 186 return -EINVAL; 187 } 188 189 total_obj_size = total_gtt_size = count = 0; 190 list_for_each_entry(obj, head, mm_list) { 191 seq_printf(m, " "); 192 describe_obj(m, obj); 193 seq_printf(m, "\n"); 194 total_obj_size += obj->base.size; 195 total_gtt_size += obj->gtt_space->size; 196 count++; 197 } 198 mutex_unlock(&dev->struct_mutex); 199 200 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", 201 count, total_obj_size, total_gtt_size); 202 return 0; 203 } 204 205 #define count_objects(list, member) do { \ 206 list_for_each_entry(obj, list, member) { \ 207 size += obj->gtt_space->size; \ 208 ++count; \ 209 if (obj->map_and_fenceable) { \ 210 mappable_size += obj->gtt_space->size; \ 211 ++mappable_count; \ 212 } \ 213 } \ 214 } while (0) 215 216 static int i915_gem_object_info(struct seq_file *m, void* data) 217 { 218 struct drm_info_node *node = (struct drm_info_node *) m->private; 219 struct drm_device *dev = node->minor->dev; 220 struct drm_i915_private *dev_priv = dev->dev_private; 221 u32 count, mappable_count; 222 size_t size, mappable_size; 223 struct drm_i915_gem_object *obj; 224 int ret; 225 226 ret = mutex_lock_interruptible(&dev->struct_mutex); 227 if (ret) 228 return ret; 229 230 seq_printf(m, "%u objects, %zu bytes\n", 231 dev_priv->mm.object_count, 232 dev_priv->mm.object_memory); 233 234 size = count = mappable_size = mappable_count = 0; 235 count_objects(&dev_priv->mm.gtt_list, gtt_list); 236 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", 237 count, mappable_count, size, mappable_size); 238 239 size = count = mappable_size = mappable_count = 0; 240 count_objects(&dev_priv->mm.active_list, mm_list); 241 count_objects(&dev_priv->mm.flushing_list, mm_list); 242 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", 243 count, mappable_count, size, mappable_size); 244 245 size = count = mappable_size = mappable_count = 0; 246 count_objects(&dev_priv->mm.inactive_list, mm_list); 247 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", 248 count, mappable_count, size, mappable_size); 249 250 size = count = mappable_size = mappable_count = 0; 251 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { 252 if (obj->fault_mappable) { 253 size += obj->gtt_space->size; 254 ++count; 255 } 256 if (obj->pin_mappable) { 257 mappable_size += obj->gtt_space->size; 258 ++mappable_count; 259 } 260 } 261 seq_printf(m, "%u pinned mappable objects, %zu bytes\n", 262 mappable_count, mappable_size); 263 seq_printf(m, "%u fault mappable objects, %zu bytes\n", 264 count, size); 265 266 seq_printf(m, "%zu [%zu] gtt total\n", 267 dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total); 268 269 mutex_unlock(&dev->struct_mutex); 270 271 return 0; 272 } 273 274 static int i915_gem_gtt_info(struct seq_file *m, void* data) 275 { 276 struct drm_info_node *node = (struct drm_info_node *) m->private; 277 struct drm_device *dev = node->minor->dev; 278 uintptr_t list = (uintptr_t) node->info_ent->data; 279 struct drm_i915_private *dev_priv = dev->dev_private; 280 struct drm_i915_gem_object *obj; 281 size_t total_obj_size, total_gtt_size; 282 int count, ret; 283 284 ret = mutex_lock_interruptible(&dev->struct_mutex); 285 if (ret) 286 return ret; 287 288 total_obj_size = total_gtt_size = count = 0; 289 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { 290 if (list == PINNED_LIST && obj->pin_count == 0) 291 continue; 292 293 seq_printf(m, " "); 294 describe_obj(m, obj); 295 seq_printf(m, "\n"); 296 total_obj_size += obj->base.size; 297 total_gtt_size += obj->gtt_space->size; 298 count++; 299 } 300 301 mutex_unlock(&dev->struct_mutex); 302 303 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", 304 count, total_obj_size, total_gtt_size); 305 306 return 0; 307 } 308 309 static int i915_gem_pageflip_info(struct seq_file *m, void *data) 310 { 311 struct drm_info_node *node = (struct drm_info_node *) m->private; 312 struct drm_device *dev = node->minor->dev; 313 unsigned long flags; 314 struct intel_crtc *crtc; 315 316 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { 317 const char pipe = pipe_name(crtc->pipe); 318 const char plane = plane_name(crtc->plane); 319 struct intel_unpin_work *work; 320 321 spin_lock_irqsave(&dev->event_lock, flags); 322 work = crtc->unpin_work; 323 if (work == NULL) { 324 seq_printf(m, "No flip due on pipe %c (plane %c)\n", 325 pipe, plane); 326 } else { 327 if (!work->pending) { 328 seq_printf(m, "Flip queued on pipe %c (plane %c)\n", 329 pipe, plane); 330 } else { 331 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", 332 pipe, plane); 333 } 334 if (work->enable_stall_check) 335 seq_printf(m, "Stall check enabled, "); 336 else 337 seq_printf(m, "Stall check waiting for page flip ioctl, "); 338 seq_printf(m, "%d prepares\n", work->pending); 339 340 if (work->old_fb_obj) { 341 struct drm_i915_gem_object *obj = work->old_fb_obj; 342 if (obj) 343 seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); 344 } 345 if (work->pending_flip_obj) { 346 struct drm_i915_gem_object *obj = work->pending_flip_obj; 347 if (obj) 348 seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); 349 } 350 } 351 spin_unlock_irqrestore(&dev->event_lock, flags); 352 } 353 354 return 0; 355 } 356 357 static int i915_gem_request_info(struct seq_file *m, void *data) 358 { 359 struct drm_info_node *node = (struct drm_info_node *) m->private; 360 struct drm_device *dev = node->minor->dev; 361 drm_i915_private_t *dev_priv = dev->dev_private; 362 struct drm_i915_gem_request *gem_request; 363 int ret, count; 364 365 ret = mutex_lock_interruptible(&dev->struct_mutex); 366 if (ret) 367 return ret; 368 369 count = 0; 370 if (!list_empty(&dev_priv->ring[RCS].request_list)) { 371 seq_printf(m, "Render requests:\n"); 372 list_for_each_entry(gem_request, 373 &dev_priv->ring[RCS].request_list, 374 list) { 375 seq_printf(m, " %d @ %d\n", 376 gem_request->seqno, 377 (int) (jiffies - gem_request->emitted_jiffies)); 378 } 379 count++; 380 } 381 if (!list_empty(&dev_priv->ring[VCS].request_list)) { 382 seq_printf(m, "BSD requests:\n"); 383 list_for_each_entry(gem_request, 384 &dev_priv->ring[VCS].request_list, 385 list) { 386 seq_printf(m, " %d @ %d\n", 387 gem_request->seqno, 388 (int) (jiffies - gem_request->emitted_jiffies)); 389 } 390 count++; 391 } 392 if (!list_empty(&dev_priv->ring[BCS].request_list)) { 393 seq_printf(m, "BLT requests:\n"); 394 list_for_each_entry(gem_request, 395 &dev_priv->ring[BCS].request_list, 396 list) { 397 seq_printf(m, " %d @ %d\n", 398 gem_request->seqno, 399 (int) (jiffies - gem_request->emitted_jiffies)); 400 } 401 count++; 402 } 403 mutex_unlock(&dev->struct_mutex); 404 405 if (count == 0) 406 seq_printf(m, "No requests\n"); 407 408 return 0; 409 } 410 411 static void i915_ring_seqno_info(struct seq_file *m, 412 struct intel_ring_buffer *ring) 413 { 414 if (ring->get_seqno) { 415 seq_printf(m, "Current sequence (%s): %d\n", 416 ring->name, ring->get_seqno(ring)); 417 } 418 } 419 420 static int i915_gem_seqno_info(struct seq_file *m, void *data) 421 { 422 struct drm_info_node *node = (struct drm_info_node *) m->private; 423 struct drm_device *dev = node->minor->dev; 424 drm_i915_private_t *dev_priv = dev->dev_private; 425 int ret, i; 426 427 ret = mutex_lock_interruptible(&dev->struct_mutex); 428 if (ret) 429 return ret; 430 431 for (i = 0; i < I915_NUM_RINGS; i++) 432 i915_ring_seqno_info(m, &dev_priv->ring[i]); 433 434 mutex_unlock(&dev->struct_mutex); 435 436 return 0; 437 } 438 439 440 static int i915_interrupt_info(struct seq_file *m, void *data) 441 { 442 struct drm_info_node *node = (struct drm_info_node *) m->private; 443 struct drm_device *dev = node->minor->dev; 444 drm_i915_private_t *dev_priv = dev->dev_private; 445 int ret, i, pipe; 446 447 ret = mutex_lock_interruptible(&dev->struct_mutex); 448 if (ret) 449 return ret; 450 451 if (IS_VALLEYVIEW(dev)) { 452 seq_printf(m, "Display IER:\t%08x\n", 453 I915_READ(VLV_IER)); 454 seq_printf(m, "Display IIR:\t%08x\n", 455 I915_READ(VLV_IIR)); 456 seq_printf(m, "Display IIR_RW:\t%08x\n", 457 I915_READ(VLV_IIR_RW)); 458 seq_printf(m, "Display IMR:\t%08x\n", 459 I915_READ(VLV_IMR)); 460 for_each_pipe(pipe) 461 seq_printf(m, "Pipe %c stat:\t%08x\n", 462 pipe_name(pipe), 463 I915_READ(PIPESTAT(pipe))); 464 465 seq_printf(m, "Master IER:\t%08x\n", 466 I915_READ(VLV_MASTER_IER)); 467 468 seq_printf(m, "Render IER:\t%08x\n", 469 I915_READ(GTIER)); 470 seq_printf(m, "Render IIR:\t%08x\n", 471 I915_READ(GTIIR)); 472 seq_printf(m, "Render IMR:\t%08x\n", 473 I915_READ(GTIMR)); 474 475 seq_printf(m, "PM IER:\t\t%08x\n", 476 I915_READ(GEN6_PMIER)); 477 seq_printf(m, "PM IIR:\t\t%08x\n", 478 I915_READ(GEN6_PMIIR)); 479 seq_printf(m, "PM IMR:\t\t%08x\n", 480 I915_READ(GEN6_PMIMR)); 481 482 seq_printf(m, "Port hotplug:\t%08x\n", 483 I915_READ(PORT_HOTPLUG_EN)); 484 seq_printf(m, "DPFLIPSTAT:\t%08x\n", 485 I915_READ(VLV_DPFLIPSTAT)); 486 seq_printf(m, "DPINVGTT:\t%08x\n", 487 I915_READ(DPINVGTT)); 488 489 } else if (!HAS_PCH_SPLIT(dev)) { 490 seq_printf(m, "Interrupt enable: %08x\n", 491 I915_READ(IER)); 492 seq_printf(m, "Interrupt identity: %08x\n", 493 I915_READ(IIR)); 494 seq_printf(m, "Interrupt mask: %08x\n", 495 I915_READ(IMR)); 496 for_each_pipe(pipe) 497 seq_printf(m, "Pipe %c stat: %08x\n", 498 pipe_name(pipe), 499 I915_READ(PIPESTAT(pipe))); 500 } else { 501 seq_printf(m, "North Display Interrupt enable: %08x\n", 502 I915_READ(DEIER)); 503 seq_printf(m, "North Display Interrupt identity: %08x\n", 504 I915_READ(DEIIR)); 505 seq_printf(m, "North Display Interrupt mask: %08x\n", 506 I915_READ(DEIMR)); 507 seq_printf(m, "South Display Interrupt enable: %08x\n", 508 I915_READ(SDEIER)); 509 seq_printf(m, "South Display Interrupt identity: %08x\n", 510 I915_READ(SDEIIR)); 511 seq_printf(m, "South Display Interrupt mask: %08x\n", 512 I915_READ(SDEIMR)); 513 seq_printf(m, "Graphics Interrupt enable: %08x\n", 514 I915_READ(GTIER)); 515 seq_printf(m, "Graphics Interrupt identity: %08x\n", 516 I915_READ(GTIIR)); 517 seq_printf(m, "Graphics Interrupt mask: %08x\n", 518 I915_READ(GTIMR)); 519 } 520 seq_printf(m, "Interrupts received: %d\n", 521 atomic_read(&dev_priv->irq_received)); 522 for (i = 0; i < I915_NUM_RINGS; i++) { 523 if (IS_GEN6(dev) || IS_GEN7(dev)) { 524 seq_printf(m, "Graphics Interrupt mask (%s): %08x\n", 525 dev_priv->ring[i].name, 526 I915_READ_IMR(&dev_priv->ring[i])); 527 } 528 i915_ring_seqno_info(m, &dev_priv->ring[i]); 529 } 530 mutex_unlock(&dev->struct_mutex); 531 532 return 0; 533 } 534 535 static int i915_gem_fence_regs_info(struct seq_file *m, void *data) 536 { 537 struct drm_info_node *node = (struct drm_info_node *) m->private; 538 struct drm_device *dev = node->minor->dev; 539 drm_i915_private_t *dev_priv = dev->dev_private; 540 int i, ret; 541 542 ret = mutex_lock_interruptible(&dev->struct_mutex); 543 if (ret) 544 return ret; 545 546 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); 547 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); 548 for (i = 0; i < dev_priv->num_fence_regs; i++) { 549 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; 550 551 seq_printf(m, "Fenced object[%2d] = ", i); 552 if (obj == NULL) 553 seq_printf(m, "unused"); 554 else 555 describe_obj(m, obj); 556 seq_printf(m, "\n"); 557 } 558 559 mutex_unlock(&dev->struct_mutex); 560 return 0; 561 } 562 563 static int i915_hws_info(struct seq_file *m, void *data) 564 { 565 struct drm_info_node *node = (struct drm_info_node *) m->private; 566 struct drm_device *dev = node->minor->dev; 567 drm_i915_private_t *dev_priv = dev->dev_private; 568 struct intel_ring_buffer *ring; 569 const volatile u32 __iomem *hws; 570 int i; 571 572 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; 573 hws = (volatile u32 __iomem *)ring->status_page.page_addr; 574 if (hws == NULL) 575 return 0; 576 577 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { 578 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", 579 i * 4, 580 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); 581 } 582 return 0; 583 } 584 585 static const char *ring_str(int ring) 586 { 587 switch (ring) { 588 case RCS: return "render"; 589 case VCS: return "bsd"; 590 case BCS: return "blt"; 591 default: return ""; 592 } 593 } 594 595 static const char *pin_flag(int pinned) 596 { 597 if (pinned > 0) 598 return " P"; 599 else if (pinned < 0) 600 return " p"; 601 else 602 return ""; 603 } 604 605 static const char *tiling_flag(int tiling) 606 { 607 switch (tiling) { 608 default: 609 case I915_TILING_NONE: return ""; 610 case I915_TILING_X: return " X"; 611 case I915_TILING_Y: return " Y"; 612 } 613 } 614 615 static const char *dirty_flag(int dirty) 616 { 617 return dirty ? " dirty" : ""; 618 } 619 620 static const char *purgeable_flag(int purgeable) 621 { 622 return purgeable ? " purgeable" : ""; 623 } 624 625 static void print_error_buffers(struct seq_file *m, 626 const char *name, 627 struct drm_i915_error_buffer *err, 628 int count) 629 { 630 seq_printf(m, "%s [%d]:\n", name, count); 631 632 while (count--) { 633 seq_printf(m, " %08x %8u %04x %04x %08x%s%s%s%s%s%s%s", 634 err->gtt_offset, 635 err->size, 636 err->read_domains, 637 err->write_domain, 638 err->seqno, 639 pin_flag(err->pinned), 640 tiling_flag(err->tiling), 641 dirty_flag(err->dirty), 642 purgeable_flag(err->purgeable), 643 err->ring != -1 ? " " : "", 644 ring_str(err->ring), 645 cache_level_str(err->cache_level)); 646 647 if (err->name) 648 seq_printf(m, " (name: %d)", err->name); 649 if (err->fence_reg != I915_FENCE_REG_NONE) 650 seq_printf(m, " (fence: %d)", err->fence_reg); 651 652 seq_printf(m, "\n"); 653 err++; 654 } 655 } 656 657 static void i915_ring_error_state(struct seq_file *m, 658 struct drm_device *dev, 659 struct drm_i915_error_state *error, 660 unsigned ring) 661 { 662 BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */ 663 seq_printf(m, "%s command stream:\n", ring_str(ring)); 664 seq_printf(m, " HEAD: 0x%08x\n", error->head[ring]); 665 seq_printf(m, " TAIL: 0x%08x\n", error->tail[ring]); 666 seq_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]); 667 seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]); 668 seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]); 669 seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]); 670 if (ring == RCS && INTEL_INFO(dev)->gen >= 4) { 671 seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1); 672 seq_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr); 673 } 674 if (INTEL_INFO(dev)->gen >= 4) 675 seq_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]); 676 seq_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]); 677 seq_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]); 678 if (INTEL_INFO(dev)->gen >= 6) { 679 seq_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]); 680 seq_printf(m, " SYNC_0: 0x%08x\n", 681 error->semaphore_mboxes[ring][0]); 682 seq_printf(m, " SYNC_1: 0x%08x\n", 683 error->semaphore_mboxes[ring][1]); 684 } 685 seq_printf(m, " seqno: 0x%08x\n", error->seqno[ring]); 686 seq_printf(m, " waiting: %s\n", yesno(error->waiting[ring])); 687 seq_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]); 688 seq_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]); 689 } 690 691 struct i915_error_state_file_priv { 692 struct drm_device *dev; 693 struct drm_i915_error_state *error; 694 }; 695 696 static int i915_error_state(struct seq_file *m, void *unused) 697 { 698 struct i915_error_state_file_priv *error_priv = m->private; 699 struct drm_device *dev = error_priv->dev; 700 drm_i915_private_t *dev_priv = dev->dev_private; 701 struct drm_i915_error_state *error = error_priv->error; 702 struct intel_ring_buffer *ring; 703 int i, j, page, offset, elt; 704 705 if (!error) { 706 seq_printf(m, "no error state collected\n"); 707 return 0; 708 } 709 710 seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, 711 error->time.tv_usec); 712 seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device); 713 seq_printf(m, "EIR: 0x%08x\n", error->eir); 714 seq_printf(m, "IER: 0x%08x\n", error->ier); 715 seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); 716 717 for (i = 0; i < dev_priv->num_fence_regs; i++) 718 seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); 719 720 if (INTEL_INFO(dev)->gen >= 6) { 721 seq_printf(m, "ERROR: 0x%08x\n", error->error); 722 seq_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); 723 } 724 725 for_each_ring(ring, dev_priv, i) 726 i915_ring_error_state(m, dev, error, i); 727 728 if (error->active_bo) 729 print_error_buffers(m, "Active", 730 error->active_bo, 731 error->active_bo_count); 732 733 if (error->pinned_bo) 734 print_error_buffers(m, "Pinned", 735 error->pinned_bo, 736 error->pinned_bo_count); 737 738 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 739 struct drm_i915_error_object *obj; 740 741 if ((obj = error->ring[i].batchbuffer)) { 742 seq_printf(m, "%s --- gtt_offset = 0x%08x\n", 743 dev_priv->ring[i].name, 744 obj->gtt_offset); 745 offset = 0; 746 for (page = 0; page < obj->page_count; page++) { 747 for (elt = 0; elt < PAGE_SIZE/4; elt++) { 748 seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]); 749 offset += 4; 750 } 751 } 752 } 753 754 if (error->ring[i].num_requests) { 755 seq_printf(m, "%s --- %d requests\n", 756 dev_priv->ring[i].name, 757 error->ring[i].num_requests); 758 for (j = 0; j < error->ring[i].num_requests; j++) { 759 seq_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n", 760 error->ring[i].requests[j].seqno, 761 error->ring[i].requests[j].jiffies, 762 error->ring[i].requests[j].tail); 763 } 764 } 765 766 if ((obj = error->ring[i].ringbuffer)) { 767 seq_printf(m, "%s --- ringbuffer = 0x%08x\n", 768 dev_priv->ring[i].name, 769 obj->gtt_offset); 770 offset = 0; 771 for (page = 0; page < obj->page_count; page++) { 772 for (elt = 0; elt < PAGE_SIZE/4; elt++) { 773 seq_printf(m, "%08x : %08x\n", 774 offset, 775 obj->pages[page][elt]); 776 offset += 4; 777 } 778 } 779 } 780 } 781 782 if (error->overlay) 783 intel_overlay_print_error_state(m, error->overlay); 784 785 if (error->display) 786 intel_display_print_error_state(m, dev, error->display); 787 788 return 0; 789 } 790 791 static ssize_t 792 i915_error_state_write(struct file *filp, 793 const char __user *ubuf, 794 size_t cnt, 795 loff_t *ppos) 796 { 797 struct seq_file *m = filp->private_data; 798 struct i915_error_state_file_priv *error_priv = m->private; 799 struct drm_device *dev = error_priv->dev; 800 801 DRM_DEBUG_DRIVER("Resetting error state\n"); 802 803 mutex_lock(&dev->struct_mutex); 804 i915_destroy_error_state(dev); 805 mutex_unlock(&dev->struct_mutex); 806 807 return cnt; 808 } 809 810 static int i915_error_state_open(struct inode *inode, struct file *file) 811 { 812 struct drm_device *dev = inode->i_private; 813 drm_i915_private_t *dev_priv = dev->dev_private; 814 struct i915_error_state_file_priv *error_priv; 815 unsigned long flags; 816 817 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); 818 if (!error_priv) 819 return -ENOMEM; 820 821 error_priv->dev = dev; 822 823 spin_lock_irqsave(&dev_priv->error_lock, flags); 824 error_priv->error = dev_priv->first_error; 825 if (error_priv->error) 826 kref_get(&error_priv->error->ref); 827 spin_unlock_irqrestore(&dev_priv->error_lock, flags); 828 829 return single_open(file, i915_error_state, error_priv); 830 } 831 832 static int i915_error_state_release(struct inode *inode, struct file *file) 833 { 834 struct seq_file *m = file->private_data; 835 struct i915_error_state_file_priv *error_priv = m->private; 836 837 if (error_priv->error) 838 kref_put(&error_priv->error->ref, i915_error_state_free); 839 kfree(error_priv); 840 841 return single_release(inode, file); 842 } 843 844 static const struct file_operations i915_error_state_fops = { 845 .owner = THIS_MODULE, 846 .open = i915_error_state_open, 847 .read = seq_read, 848 .write = i915_error_state_write, 849 .llseek = default_llseek, 850 .release = i915_error_state_release, 851 }; 852 853 static int i915_rstdby_delays(struct seq_file *m, void *unused) 854 { 855 struct drm_info_node *node = (struct drm_info_node *) m->private; 856 struct drm_device *dev = node->minor->dev; 857 drm_i915_private_t *dev_priv = dev->dev_private; 858 u16 crstanddelay; 859 int ret; 860 861 ret = mutex_lock_interruptible(&dev->struct_mutex); 862 if (ret) 863 return ret; 864 865 crstanddelay = I915_READ16(CRSTANDVID); 866 867 mutex_unlock(&dev->struct_mutex); 868 869 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); 870 871 return 0; 872 } 873 874 static int i915_cur_delayinfo(struct seq_file *m, void *unused) 875 { 876 struct drm_info_node *node = (struct drm_info_node *) m->private; 877 struct drm_device *dev = node->minor->dev; 878 drm_i915_private_t *dev_priv = dev->dev_private; 879 int ret; 880 881 if (IS_GEN5(dev)) { 882 u16 rgvswctl = I915_READ16(MEMSWCTL); 883 u16 rgvstat = I915_READ16(MEMSTAT_ILK); 884 885 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); 886 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); 887 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> 888 MEMSTAT_VID_SHIFT); 889 seq_printf(m, "Current P-state: %d\n", 890 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); 891 } else if (IS_GEN6(dev) || IS_GEN7(dev)) { 892 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); 893 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); 894 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); 895 u32 rpstat; 896 u32 rpupei, rpcurup, rpprevup; 897 u32 rpdownei, rpcurdown, rpprevdown; 898 int max_freq; 899 900 /* RPSTAT1 is in the GT power well */ 901 ret = mutex_lock_interruptible(&dev->struct_mutex); 902 if (ret) 903 return ret; 904 905 gen6_gt_force_wake_get(dev_priv); 906 907 rpstat = I915_READ(GEN6_RPSTAT1); 908 rpupei = I915_READ(GEN6_RP_CUR_UP_EI); 909 rpcurup = I915_READ(GEN6_RP_CUR_UP); 910 rpprevup = I915_READ(GEN6_RP_PREV_UP); 911 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); 912 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); 913 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); 914 915 gen6_gt_force_wake_put(dev_priv); 916 mutex_unlock(&dev->struct_mutex); 917 918 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); 919 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); 920 seq_printf(m, "Render p-state ratio: %d\n", 921 (gt_perf_status & 0xff00) >> 8); 922 seq_printf(m, "Render p-state VID: %d\n", 923 gt_perf_status & 0xff); 924 seq_printf(m, "Render p-state limit: %d\n", 925 rp_state_limits & 0xff); 926 seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >> 927 GEN6_CAGF_SHIFT) * 50); 928 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & 929 GEN6_CURICONT_MASK); 930 seq_printf(m, "RP CUR UP: %dus\n", rpcurup & 931 GEN6_CURBSYTAVG_MASK); 932 seq_printf(m, "RP PREV UP: %dus\n", rpprevup & 933 GEN6_CURBSYTAVG_MASK); 934 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & 935 GEN6_CURIAVG_MASK); 936 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & 937 GEN6_CURBSYTAVG_MASK); 938 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & 939 GEN6_CURBSYTAVG_MASK); 940 941 max_freq = (rp_state_cap & 0xff0000) >> 16; 942 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", 943 max_freq * 50); 944 945 max_freq = (rp_state_cap & 0xff00) >> 8; 946 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", 947 max_freq * 50); 948 949 max_freq = rp_state_cap & 0xff; 950 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", 951 max_freq * 50); 952 } else { 953 seq_printf(m, "no P-state info available\n"); 954 } 955 956 return 0; 957 } 958 959 static int i915_delayfreq_table(struct seq_file *m, void *unused) 960 { 961 struct drm_info_node *node = (struct drm_info_node *) m->private; 962 struct drm_device *dev = node->minor->dev; 963 drm_i915_private_t *dev_priv = dev->dev_private; 964 u32 delayfreq; 965 int ret, i; 966 967 ret = mutex_lock_interruptible(&dev->struct_mutex); 968 if (ret) 969 return ret; 970 971 for (i = 0; i < 16; i++) { 972 delayfreq = I915_READ(PXVFREQ_BASE + i * 4); 973 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, 974 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); 975 } 976 977 mutex_unlock(&dev->struct_mutex); 978 979 return 0; 980 } 981 982 static inline int MAP_TO_MV(int map) 983 { 984 return 1250 - (map * 25); 985 } 986 987 static int i915_inttoext_table(struct seq_file *m, void *unused) 988 { 989 struct drm_info_node *node = (struct drm_info_node *) m->private; 990 struct drm_device *dev = node->minor->dev; 991 drm_i915_private_t *dev_priv = dev->dev_private; 992 u32 inttoext; 993 int ret, i; 994 995 ret = mutex_lock_interruptible(&dev->struct_mutex); 996 if (ret) 997 return ret; 998 999 for (i = 1; i <= 32; i++) { 1000 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); 1001 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); 1002 } 1003 1004 mutex_unlock(&dev->struct_mutex); 1005 1006 return 0; 1007 } 1008 1009 static int ironlake_drpc_info(struct seq_file *m) 1010 { 1011 struct drm_info_node *node = (struct drm_info_node *) m->private; 1012 struct drm_device *dev = node->minor->dev; 1013 drm_i915_private_t *dev_priv = dev->dev_private; 1014 u32 rgvmodectl, rstdbyctl; 1015 u16 crstandvid; 1016 int ret; 1017 1018 ret = mutex_lock_interruptible(&dev->struct_mutex); 1019 if (ret) 1020 return ret; 1021 1022 rgvmodectl = I915_READ(MEMMODECTL); 1023 rstdbyctl = I915_READ(RSTDBYCTL); 1024 crstandvid = I915_READ16(CRSTANDVID); 1025 1026 mutex_unlock(&dev->struct_mutex); 1027 1028 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? 1029 "yes" : "no"); 1030 seq_printf(m, "Boost freq: %d\n", 1031 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> 1032 MEMMODE_BOOST_FREQ_SHIFT); 1033 seq_printf(m, "HW control enabled: %s\n", 1034 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); 1035 seq_printf(m, "SW control enabled: %s\n", 1036 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); 1037 seq_printf(m, "Gated voltage change: %s\n", 1038 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); 1039 seq_printf(m, "Starting frequency: P%d\n", 1040 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); 1041 seq_printf(m, "Max P-state: P%d\n", 1042 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); 1043 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); 1044 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); 1045 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); 1046 seq_printf(m, "Render standby enabled: %s\n", 1047 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); 1048 seq_printf(m, "Current RS state: "); 1049 switch (rstdbyctl & RSX_STATUS_MASK) { 1050 case RSX_STATUS_ON: 1051 seq_printf(m, "on\n"); 1052 break; 1053 case RSX_STATUS_RC1: 1054 seq_printf(m, "RC1\n"); 1055 break; 1056 case RSX_STATUS_RC1E: 1057 seq_printf(m, "RC1E\n"); 1058 break; 1059 case RSX_STATUS_RS1: 1060 seq_printf(m, "RS1\n"); 1061 break; 1062 case RSX_STATUS_RS2: 1063 seq_printf(m, "RS2 (RC6)\n"); 1064 break; 1065 case RSX_STATUS_RS3: 1066 seq_printf(m, "RC3 (RC6+)\n"); 1067 break; 1068 default: 1069 seq_printf(m, "unknown\n"); 1070 break; 1071 } 1072 1073 return 0; 1074 } 1075 1076 static int gen6_drpc_info(struct seq_file *m) 1077 { 1078 1079 struct drm_info_node *node = (struct drm_info_node *) m->private; 1080 struct drm_device *dev = node->minor->dev; 1081 struct drm_i915_private *dev_priv = dev->dev_private; 1082 u32 rpmodectl1, gt_core_status, rcctl1; 1083 unsigned forcewake_count; 1084 int count=0, ret; 1085 1086 1087 ret = mutex_lock_interruptible(&dev->struct_mutex); 1088 if (ret) 1089 return ret; 1090 1091 spin_lock_irq(&dev_priv->gt_lock); 1092 forcewake_count = dev_priv->forcewake_count; 1093 spin_unlock_irq(&dev_priv->gt_lock); 1094 1095 if (forcewake_count) { 1096 seq_printf(m, "RC information inaccurate because somebody " 1097 "holds a forcewake reference \n"); 1098 } else { 1099 /* NB: we cannot use forcewake, else we read the wrong values */ 1100 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) 1101 udelay(10); 1102 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); 1103 } 1104 1105 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); 1106 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4); 1107 1108 rpmodectl1 = I915_READ(GEN6_RP_CONTROL); 1109 rcctl1 = I915_READ(GEN6_RC_CONTROL); 1110 mutex_unlock(&dev->struct_mutex); 1111 1112 seq_printf(m, "Video Turbo Mode: %s\n", 1113 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); 1114 seq_printf(m, "HW control enabled: %s\n", 1115 yesno(rpmodectl1 & GEN6_RP_ENABLE)); 1116 seq_printf(m, "SW control enabled: %s\n", 1117 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == 1118 GEN6_RP_MEDIA_SW_MODE)); 1119 seq_printf(m, "RC1e Enabled: %s\n", 1120 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); 1121 seq_printf(m, "RC6 Enabled: %s\n", 1122 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); 1123 seq_printf(m, "Deep RC6 Enabled: %s\n", 1124 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); 1125 seq_printf(m, "Deepest RC6 Enabled: %s\n", 1126 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); 1127 seq_printf(m, "Current RC state: "); 1128 switch (gt_core_status & GEN6_RCn_MASK) { 1129 case GEN6_RC0: 1130 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) 1131 seq_printf(m, "Core Power Down\n"); 1132 else 1133 seq_printf(m, "on\n"); 1134 break; 1135 case GEN6_RC3: 1136 seq_printf(m, "RC3\n"); 1137 break; 1138 case GEN6_RC6: 1139 seq_printf(m, "RC6\n"); 1140 break; 1141 case GEN6_RC7: 1142 seq_printf(m, "RC7\n"); 1143 break; 1144 default: 1145 seq_printf(m, "Unknown\n"); 1146 break; 1147 } 1148 1149 seq_printf(m, "Core Power Down: %s\n", 1150 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); 1151 1152 /* Not exactly sure what this is */ 1153 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", 1154 I915_READ(GEN6_GT_GFX_RC6_LOCKED)); 1155 seq_printf(m, "RC6 residency since boot: %u\n", 1156 I915_READ(GEN6_GT_GFX_RC6)); 1157 seq_printf(m, "RC6+ residency since boot: %u\n", 1158 I915_READ(GEN6_GT_GFX_RC6p)); 1159 seq_printf(m, "RC6++ residency since boot: %u\n", 1160 I915_READ(GEN6_GT_GFX_RC6pp)); 1161 1162 return 0; 1163 } 1164 1165 static int i915_drpc_info(struct seq_file *m, void *unused) 1166 { 1167 struct drm_info_node *node = (struct drm_info_node *) m->private; 1168 struct drm_device *dev = node->minor->dev; 1169 1170 if (IS_GEN6(dev) || IS_GEN7(dev)) 1171 return gen6_drpc_info(m); 1172 else 1173 return ironlake_drpc_info(m); 1174 } 1175 1176 static int i915_fbc_status(struct seq_file *m, void *unused) 1177 { 1178 struct drm_info_node *node = (struct drm_info_node *) m->private; 1179 struct drm_device *dev = node->minor->dev; 1180 drm_i915_private_t *dev_priv = dev->dev_private; 1181 1182 if (!I915_HAS_FBC(dev)) { 1183 seq_printf(m, "FBC unsupported on this chipset\n"); 1184 return 0; 1185 } 1186 1187 if (intel_fbc_enabled(dev)) { 1188 seq_printf(m, "FBC enabled\n"); 1189 } else { 1190 seq_printf(m, "FBC disabled: "); 1191 switch (dev_priv->no_fbc_reason) { 1192 case FBC_NO_OUTPUT: 1193 seq_printf(m, "no outputs"); 1194 break; 1195 case FBC_STOLEN_TOO_SMALL: 1196 seq_printf(m, "not enough stolen memory"); 1197 break; 1198 case FBC_UNSUPPORTED_MODE: 1199 seq_printf(m, "mode not supported"); 1200 break; 1201 case FBC_MODE_TOO_LARGE: 1202 seq_printf(m, "mode too large"); 1203 break; 1204 case FBC_BAD_PLANE: 1205 seq_printf(m, "FBC unsupported on plane"); 1206 break; 1207 case FBC_NOT_TILED: 1208 seq_printf(m, "scanout buffer not tiled"); 1209 break; 1210 case FBC_MULTIPLE_PIPES: 1211 seq_printf(m, "multiple pipes are enabled"); 1212 break; 1213 case FBC_MODULE_PARAM: 1214 seq_printf(m, "disabled per module param (default off)"); 1215 break; 1216 default: 1217 seq_printf(m, "unknown reason"); 1218 } 1219 seq_printf(m, "\n"); 1220 } 1221 return 0; 1222 } 1223 1224 static int i915_sr_status(struct seq_file *m, void *unused) 1225 { 1226 struct drm_info_node *node = (struct drm_info_node *) m->private; 1227 struct drm_device *dev = node->minor->dev; 1228 drm_i915_private_t *dev_priv = dev->dev_private; 1229 bool sr_enabled = false; 1230 1231 if (HAS_PCH_SPLIT(dev)) 1232 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; 1233 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) 1234 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; 1235 else if (IS_I915GM(dev)) 1236 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; 1237 else if (IS_PINEVIEW(dev)) 1238 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; 1239 1240 seq_printf(m, "self-refresh: %s\n", 1241 sr_enabled ? "enabled" : "disabled"); 1242 1243 return 0; 1244 } 1245 1246 static int i915_emon_status(struct seq_file *m, void *unused) 1247 { 1248 struct drm_info_node *node = (struct drm_info_node *) m->private; 1249 struct drm_device *dev = node->minor->dev; 1250 drm_i915_private_t *dev_priv = dev->dev_private; 1251 unsigned long temp, chipset, gfx; 1252 int ret; 1253 1254 if (!IS_GEN5(dev)) 1255 return -ENODEV; 1256 1257 ret = mutex_lock_interruptible(&dev->struct_mutex); 1258 if (ret) 1259 return ret; 1260 1261 temp = i915_mch_val(dev_priv); 1262 chipset = i915_chipset_val(dev_priv); 1263 gfx = i915_gfx_val(dev_priv); 1264 mutex_unlock(&dev->struct_mutex); 1265 1266 seq_printf(m, "GMCH temp: %ld\n", temp); 1267 seq_printf(m, "Chipset power: %ld\n", chipset); 1268 seq_printf(m, "GFX power: %ld\n", gfx); 1269 seq_printf(m, "Total power: %ld\n", chipset + gfx); 1270 1271 return 0; 1272 } 1273 1274 static int i915_ring_freq_table(struct seq_file *m, void *unused) 1275 { 1276 struct drm_info_node *node = (struct drm_info_node *) m->private; 1277 struct drm_device *dev = node->minor->dev; 1278 drm_i915_private_t *dev_priv = dev->dev_private; 1279 int ret; 1280 int gpu_freq, ia_freq; 1281 1282 if (!(IS_GEN6(dev) || IS_GEN7(dev))) { 1283 seq_printf(m, "unsupported on this chipset\n"); 1284 return 0; 1285 } 1286 1287 ret = mutex_lock_interruptible(&dev->struct_mutex); 1288 if (ret) 1289 return ret; 1290 1291 seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n"); 1292 1293 for (gpu_freq = dev_priv->min_delay; gpu_freq <= dev_priv->max_delay; 1294 gpu_freq++) { 1295 I915_WRITE(GEN6_PCODE_DATA, gpu_freq); 1296 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | 1297 GEN6_PCODE_READ_MIN_FREQ_TABLE); 1298 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & 1299 GEN6_PCODE_READY) == 0, 10)) { 1300 DRM_ERROR("pcode read of freq table timed out\n"); 1301 continue; 1302 } 1303 ia_freq = I915_READ(GEN6_PCODE_DATA); 1304 seq_printf(m, "%d\t\t%d\n", gpu_freq * 50, ia_freq * 100); 1305 } 1306 1307 mutex_unlock(&dev->struct_mutex); 1308 1309 return 0; 1310 } 1311 1312 static int i915_gfxec(struct seq_file *m, void *unused) 1313 { 1314 struct drm_info_node *node = (struct drm_info_node *) m->private; 1315 struct drm_device *dev = node->minor->dev; 1316 drm_i915_private_t *dev_priv = dev->dev_private; 1317 int ret; 1318 1319 ret = mutex_lock_interruptible(&dev->struct_mutex); 1320 if (ret) 1321 return ret; 1322 1323 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); 1324 1325 mutex_unlock(&dev->struct_mutex); 1326 1327 return 0; 1328 } 1329 1330 static int i915_opregion(struct seq_file *m, void *unused) 1331 { 1332 struct drm_info_node *node = (struct drm_info_node *) m->private; 1333 struct drm_device *dev = node->minor->dev; 1334 drm_i915_private_t *dev_priv = dev->dev_private; 1335 struct intel_opregion *opregion = &dev_priv->opregion; 1336 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); 1337 int ret; 1338 1339 if (data == NULL) 1340 return -ENOMEM; 1341 1342 ret = mutex_lock_interruptible(&dev->struct_mutex); 1343 if (ret) 1344 goto out; 1345 1346 if (opregion->header) { 1347 memcpy_fromio(data, opregion->header, OPREGION_SIZE); 1348 seq_write(m, data, OPREGION_SIZE); 1349 } 1350 1351 mutex_unlock(&dev->struct_mutex); 1352 1353 out: 1354 kfree(data); 1355 return 0; 1356 } 1357 1358 static int i915_gem_framebuffer_info(struct seq_file *m, void *data) 1359 { 1360 struct drm_info_node *node = (struct drm_info_node *) m->private; 1361 struct drm_device *dev = node->minor->dev; 1362 drm_i915_private_t *dev_priv = dev->dev_private; 1363 struct intel_fbdev *ifbdev; 1364 struct intel_framebuffer *fb; 1365 int ret; 1366 1367 ret = mutex_lock_interruptible(&dev->mode_config.mutex); 1368 if (ret) 1369 return ret; 1370 1371 ifbdev = dev_priv->fbdev; 1372 fb = to_intel_framebuffer(ifbdev->helper.fb); 1373 1374 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ", 1375 fb->base.width, 1376 fb->base.height, 1377 fb->base.depth, 1378 fb->base.bits_per_pixel); 1379 describe_obj(m, fb->obj); 1380 seq_printf(m, "\n"); 1381 1382 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { 1383 if (&fb->base == ifbdev->helper.fb) 1384 continue; 1385 1386 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ", 1387 fb->base.width, 1388 fb->base.height, 1389 fb->base.depth, 1390 fb->base.bits_per_pixel); 1391 describe_obj(m, fb->obj); 1392 seq_printf(m, "\n"); 1393 } 1394 1395 mutex_unlock(&dev->mode_config.mutex); 1396 1397 return 0; 1398 } 1399 1400 static int i915_context_status(struct seq_file *m, void *unused) 1401 { 1402 struct drm_info_node *node = (struct drm_info_node *) m->private; 1403 struct drm_device *dev = node->minor->dev; 1404 drm_i915_private_t *dev_priv = dev->dev_private; 1405 int ret; 1406 1407 ret = mutex_lock_interruptible(&dev->mode_config.mutex); 1408 if (ret) 1409 return ret; 1410 1411 if (dev_priv->pwrctx) { 1412 seq_printf(m, "power context "); 1413 describe_obj(m, dev_priv->pwrctx); 1414 seq_printf(m, "\n"); 1415 } 1416 1417 if (dev_priv->renderctx) { 1418 seq_printf(m, "render context "); 1419 describe_obj(m, dev_priv->renderctx); 1420 seq_printf(m, "\n"); 1421 } 1422 1423 mutex_unlock(&dev->mode_config.mutex); 1424 1425 return 0; 1426 } 1427 1428 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) 1429 { 1430 struct drm_info_node *node = (struct drm_info_node *) m->private; 1431 struct drm_device *dev = node->minor->dev; 1432 struct drm_i915_private *dev_priv = dev->dev_private; 1433 unsigned forcewake_count; 1434 1435 spin_lock_irq(&dev_priv->gt_lock); 1436 forcewake_count = dev_priv->forcewake_count; 1437 spin_unlock_irq(&dev_priv->gt_lock); 1438 1439 seq_printf(m, "forcewake count = %u\n", forcewake_count); 1440 1441 return 0; 1442 } 1443 1444 static const char *swizzle_string(unsigned swizzle) 1445 { 1446 switch(swizzle) { 1447 case I915_BIT_6_SWIZZLE_NONE: 1448 return "none"; 1449 case I915_BIT_6_SWIZZLE_9: 1450 return "bit9"; 1451 case I915_BIT_6_SWIZZLE_9_10: 1452 return "bit9/bit10"; 1453 case I915_BIT_6_SWIZZLE_9_11: 1454 return "bit9/bit11"; 1455 case I915_BIT_6_SWIZZLE_9_10_11: 1456 return "bit9/bit10/bit11"; 1457 case I915_BIT_6_SWIZZLE_9_17: 1458 return "bit9/bit17"; 1459 case I915_BIT_6_SWIZZLE_9_10_17: 1460 return "bit9/bit10/bit17"; 1461 case I915_BIT_6_SWIZZLE_UNKNOWN: 1462 return "unkown"; 1463 } 1464 1465 return "bug"; 1466 } 1467 1468 static int i915_swizzle_info(struct seq_file *m, void *data) 1469 { 1470 struct drm_info_node *node = (struct drm_info_node *) m->private; 1471 struct drm_device *dev = node->minor->dev; 1472 struct drm_i915_private *dev_priv = dev->dev_private; 1473 1474 mutex_lock(&dev->struct_mutex); 1475 seq_printf(m, "bit6 swizzle for X-tiling = %s\n", 1476 swizzle_string(dev_priv->mm.bit_6_swizzle_x)); 1477 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", 1478 swizzle_string(dev_priv->mm.bit_6_swizzle_y)); 1479 1480 if (IS_GEN3(dev) || IS_GEN4(dev)) { 1481 seq_printf(m, "DDC = 0x%08x\n", 1482 I915_READ(DCC)); 1483 seq_printf(m, "C0DRB3 = 0x%04x\n", 1484 I915_READ16(C0DRB3)); 1485 seq_printf(m, "C1DRB3 = 0x%04x\n", 1486 I915_READ16(C1DRB3)); 1487 } else if (IS_GEN6(dev) || IS_GEN7(dev)) { 1488 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", 1489 I915_READ(MAD_DIMM_C0)); 1490 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", 1491 I915_READ(MAD_DIMM_C1)); 1492 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", 1493 I915_READ(MAD_DIMM_C2)); 1494 seq_printf(m, "TILECTL = 0x%08x\n", 1495 I915_READ(TILECTL)); 1496 seq_printf(m, "ARB_MODE = 0x%08x\n", 1497 I915_READ(ARB_MODE)); 1498 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", 1499 I915_READ(DISP_ARB_CTL)); 1500 } 1501 mutex_unlock(&dev->struct_mutex); 1502 1503 return 0; 1504 } 1505 1506 static int i915_ppgtt_info(struct seq_file *m, void *data) 1507 { 1508 struct drm_info_node *node = (struct drm_info_node *) m->private; 1509 struct drm_device *dev = node->minor->dev; 1510 struct drm_i915_private *dev_priv = dev->dev_private; 1511 struct intel_ring_buffer *ring; 1512 int i, ret; 1513 1514 1515 ret = mutex_lock_interruptible(&dev->struct_mutex); 1516 if (ret) 1517 return ret; 1518 if (INTEL_INFO(dev)->gen == 6) 1519 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); 1520 1521 for (i = 0; i < I915_NUM_RINGS; i++) { 1522 ring = &dev_priv->ring[i]; 1523 1524 seq_printf(m, "%s\n", ring->name); 1525 if (INTEL_INFO(dev)->gen == 7) 1526 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); 1527 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); 1528 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); 1529 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); 1530 } 1531 if (dev_priv->mm.aliasing_ppgtt) { 1532 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; 1533 1534 seq_printf(m, "aliasing PPGTT:\n"); 1535 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); 1536 } 1537 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); 1538 mutex_unlock(&dev->struct_mutex); 1539 1540 return 0; 1541 } 1542 1543 static int i915_dpio_info(struct seq_file *m, void *data) 1544 { 1545 struct drm_info_node *node = (struct drm_info_node *) m->private; 1546 struct drm_device *dev = node->minor->dev; 1547 struct drm_i915_private *dev_priv = dev->dev_private; 1548 int ret; 1549 1550 1551 if (!IS_VALLEYVIEW(dev)) { 1552 seq_printf(m, "unsupported\n"); 1553 return 0; 1554 } 1555 1556 ret = mutex_lock_interruptible(&dev->mode_config.mutex); 1557 if (ret) 1558 return ret; 1559 1560 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); 1561 1562 seq_printf(m, "DPIO_DIV_A: 0x%08x\n", 1563 intel_dpio_read(dev_priv, _DPIO_DIV_A)); 1564 seq_printf(m, "DPIO_DIV_B: 0x%08x\n", 1565 intel_dpio_read(dev_priv, _DPIO_DIV_B)); 1566 1567 seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", 1568 intel_dpio_read(dev_priv, _DPIO_REFSFR_A)); 1569 seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", 1570 intel_dpio_read(dev_priv, _DPIO_REFSFR_B)); 1571 1572 seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", 1573 intel_dpio_read(dev_priv, _DPIO_CORE_CLK_A)); 1574 seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", 1575 intel_dpio_read(dev_priv, _DPIO_CORE_CLK_B)); 1576 1577 seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n", 1578 intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_A)); 1579 seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n", 1580 intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_B)); 1581 1582 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", 1583 intel_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE)); 1584 1585 mutex_unlock(&dev->mode_config.mutex); 1586 1587 return 0; 1588 } 1589 1590 static ssize_t 1591 i915_wedged_read(struct file *filp, 1592 char __user *ubuf, 1593 size_t max, 1594 loff_t *ppos) 1595 { 1596 struct drm_device *dev = filp->private_data; 1597 drm_i915_private_t *dev_priv = dev->dev_private; 1598 char buf[80]; 1599 int len; 1600 1601 len = snprintf(buf, sizeof(buf), 1602 "wedged : %d\n", 1603 atomic_read(&dev_priv->mm.wedged)); 1604 1605 if (len > sizeof(buf)) 1606 len = sizeof(buf); 1607 1608 return simple_read_from_buffer(ubuf, max, ppos, buf, len); 1609 } 1610 1611 static ssize_t 1612 i915_wedged_write(struct file *filp, 1613 const char __user *ubuf, 1614 size_t cnt, 1615 loff_t *ppos) 1616 { 1617 struct drm_device *dev = filp->private_data; 1618 char buf[20]; 1619 int val = 1; 1620 1621 if (cnt > 0) { 1622 if (cnt > sizeof(buf) - 1) 1623 return -EINVAL; 1624 1625 if (copy_from_user(buf, ubuf, cnt)) 1626 return -EFAULT; 1627 buf[cnt] = 0; 1628 1629 val = simple_strtoul(buf, NULL, 0); 1630 } 1631 1632 DRM_INFO("Manually setting wedged to %d\n", val); 1633 i915_handle_error(dev, val); 1634 1635 return cnt; 1636 } 1637 1638 static const struct file_operations i915_wedged_fops = { 1639 .owner = THIS_MODULE, 1640 .open = simple_open, 1641 .read = i915_wedged_read, 1642 .write = i915_wedged_write, 1643 .llseek = default_llseek, 1644 }; 1645 1646 static ssize_t 1647 i915_ring_stop_read(struct file *filp, 1648 char __user *ubuf, 1649 size_t max, 1650 loff_t *ppos) 1651 { 1652 struct drm_device *dev = filp->private_data; 1653 drm_i915_private_t *dev_priv = dev->dev_private; 1654 char buf[20]; 1655 int len; 1656 1657 len = snprintf(buf, sizeof(buf), 1658 "0x%08x\n", dev_priv->stop_rings); 1659 1660 if (len > sizeof(buf)) 1661 len = sizeof(buf); 1662 1663 return simple_read_from_buffer(ubuf, max, ppos, buf, len); 1664 } 1665 1666 static ssize_t 1667 i915_ring_stop_write(struct file *filp, 1668 const char __user *ubuf, 1669 size_t cnt, 1670 loff_t *ppos) 1671 { 1672 struct drm_device *dev = filp->private_data; 1673 struct drm_i915_private *dev_priv = dev->dev_private; 1674 char buf[20]; 1675 int val = 0; 1676 1677 if (cnt > 0) { 1678 if (cnt > sizeof(buf) - 1) 1679 return -EINVAL; 1680 1681 if (copy_from_user(buf, ubuf, cnt)) 1682 return -EFAULT; 1683 buf[cnt] = 0; 1684 1685 val = simple_strtoul(buf, NULL, 0); 1686 } 1687 1688 DRM_DEBUG_DRIVER("Stopping rings 0x%08x\n", val); 1689 1690 mutex_lock(&dev->struct_mutex); 1691 dev_priv->stop_rings = val; 1692 mutex_unlock(&dev->struct_mutex); 1693 1694 return cnt; 1695 } 1696 1697 static const struct file_operations i915_ring_stop_fops = { 1698 .owner = THIS_MODULE, 1699 .open = simple_open, 1700 .read = i915_ring_stop_read, 1701 .write = i915_ring_stop_write, 1702 .llseek = default_llseek, 1703 }; 1704 1705 static ssize_t 1706 i915_max_freq_read(struct file *filp, 1707 char __user *ubuf, 1708 size_t max, 1709 loff_t *ppos) 1710 { 1711 struct drm_device *dev = filp->private_data; 1712 drm_i915_private_t *dev_priv = dev->dev_private; 1713 char buf[80]; 1714 int len; 1715 1716 len = snprintf(buf, sizeof(buf), 1717 "max freq: %d\n", dev_priv->max_delay * 50); 1718 1719 if (len > sizeof(buf)) 1720 len = sizeof(buf); 1721 1722 return simple_read_from_buffer(ubuf, max, ppos, buf, len); 1723 } 1724 1725 static ssize_t 1726 i915_max_freq_write(struct file *filp, 1727 const char __user *ubuf, 1728 size_t cnt, 1729 loff_t *ppos) 1730 { 1731 struct drm_device *dev = filp->private_data; 1732 struct drm_i915_private *dev_priv = dev->dev_private; 1733 char buf[20]; 1734 int val = 1; 1735 1736 if (cnt > 0) { 1737 if (cnt > sizeof(buf) - 1) 1738 return -EINVAL; 1739 1740 if (copy_from_user(buf, ubuf, cnt)) 1741 return -EFAULT; 1742 buf[cnt] = 0; 1743 1744 val = simple_strtoul(buf, NULL, 0); 1745 } 1746 1747 DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val); 1748 1749 /* 1750 * Turbo will still be enabled, but won't go above the set value. 1751 */ 1752 dev_priv->max_delay = val / 50; 1753 1754 gen6_set_rps(dev, val / 50); 1755 1756 return cnt; 1757 } 1758 1759 static const struct file_operations i915_max_freq_fops = { 1760 .owner = THIS_MODULE, 1761 .open = simple_open, 1762 .read = i915_max_freq_read, 1763 .write = i915_max_freq_write, 1764 .llseek = default_llseek, 1765 }; 1766 1767 static ssize_t 1768 i915_cache_sharing_read(struct file *filp, 1769 char __user *ubuf, 1770 size_t max, 1771 loff_t *ppos) 1772 { 1773 struct drm_device *dev = filp->private_data; 1774 drm_i915_private_t *dev_priv = dev->dev_private; 1775 char buf[80]; 1776 u32 snpcr; 1777 int len; 1778 1779 mutex_lock(&dev_priv->dev->struct_mutex); 1780 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); 1781 mutex_unlock(&dev_priv->dev->struct_mutex); 1782 1783 len = snprintf(buf, sizeof(buf), 1784 "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >> 1785 GEN6_MBC_SNPCR_SHIFT); 1786 1787 if (len > sizeof(buf)) 1788 len = sizeof(buf); 1789 1790 return simple_read_from_buffer(ubuf, max, ppos, buf, len); 1791 } 1792 1793 static ssize_t 1794 i915_cache_sharing_write(struct file *filp, 1795 const char __user *ubuf, 1796 size_t cnt, 1797 loff_t *ppos) 1798 { 1799 struct drm_device *dev = filp->private_data; 1800 struct drm_i915_private *dev_priv = dev->dev_private; 1801 char buf[20]; 1802 u32 snpcr; 1803 int val = 1; 1804 1805 if (cnt > 0) { 1806 if (cnt > sizeof(buf) - 1) 1807 return -EINVAL; 1808 1809 if (copy_from_user(buf, ubuf, cnt)) 1810 return -EFAULT; 1811 buf[cnt] = 0; 1812 1813 val = simple_strtoul(buf, NULL, 0); 1814 } 1815 1816 if (val < 0 || val > 3) 1817 return -EINVAL; 1818 1819 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val); 1820 1821 /* Update the cache sharing policy here as well */ 1822 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); 1823 snpcr &= ~GEN6_MBC_SNPCR_MASK; 1824 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); 1825 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); 1826 1827 return cnt; 1828 } 1829 1830 static const struct file_operations i915_cache_sharing_fops = { 1831 .owner = THIS_MODULE, 1832 .open = simple_open, 1833 .read = i915_cache_sharing_read, 1834 .write = i915_cache_sharing_write, 1835 .llseek = default_llseek, 1836 }; 1837 1838 /* As the drm_debugfs_init() routines are called before dev->dev_private is 1839 * allocated we need to hook into the minor for release. */ 1840 static int 1841 drm_add_fake_info_node(struct drm_minor *minor, 1842 struct dentry *ent, 1843 const void *key) 1844 { 1845 struct drm_info_node *node; 1846 1847 node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL); 1848 if (node == NULL) { 1849 debugfs_remove(ent); 1850 return -ENOMEM; 1851 } 1852 1853 node->minor = minor; 1854 node->dent = ent; 1855 node->info_ent = (void *) key; 1856 1857 mutex_lock(&minor->debugfs_lock); 1858 list_add(&node->list, &minor->debugfs_list); 1859 mutex_unlock(&minor->debugfs_lock); 1860 1861 return 0; 1862 } 1863 1864 static int i915_forcewake_open(struct inode *inode, struct file *file) 1865 { 1866 struct drm_device *dev = inode->i_private; 1867 struct drm_i915_private *dev_priv = dev->dev_private; 1868 int ret; 1869 1870 if (INTEL_INFO(dev)->gen < 6) 1871 return 0; 1872 1873 ret = mutex_lock_interruptible(&dev->struct_mutex); 1874 if (ret) 1875 return ret; 1876 gen6_gt_force_wake_get(dev_priv); 1877 mutex_unlock(&dev->struct_mutex); 1878 1879 return 0; 1880 } 1881 1882 static int i915_forcewake_release(struct inode *inode, struct file *file) 1883 { 1884 struct drm_device *dev = inode->i_private; 1885 struct drm_i915_private *dev_priv = dev->dev_private; 1886 1887 if (INTEL_INFO(dev)->gen < 6) 1888 return 0; 1889 1890 /* 1891 * It's bad that we can potentially hang userspace if struct_mutex gets 1892 * forever stuck. However, if we cannot acquire this lock it means that 1893 * almost certainly the driver has hung, is not unload-able. Therefore 1894 * hanging here is probably a minor inconvenience not to be seen my 1895 * almost every user. 1896 */ 1897 mutex_lock(&dev->struct_mutex); 1898 gen6_gt_force_wake_put(dev_priv); 1899 mutex_unlock(&dev->struct_mutex); 1900 1901 return 0; 1902 } 1903 1904 static const struct file_operations i915_forcewake_fops = { 1905 .owner = THIS_MODULE, 1906 .open = i915_forcewake_open, 1907 .release = i915_forcewake_release, 1908 }; 1909 1910 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) 1911 { 1912 struct drm_device *dev = minor->dev; 1913 struct dentry *ent; 1914 1915 ent = debugfs_create_file("i915_forcewake_user", 1916 S_IRUSR, 1917 root, dev, 1918 &i915_forcewake_fops); 1919 if (IS_ERR(ent)) 1920 return PTR_ERR(ent); 1921 1922 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); 1923 } 1924 1925 static int i915_debugfs_create(struct dentry *root, 1926 struct drm_minor *minor, 1927 const char *name, 1928 const struct file_operations *fops) 1929 { 1930 struct drm_device *dev = minor->dev; 1931 struct dentry *ent; 1932 1933 ent = debugfs_create_file(name, 1934 S_IRUGO | S_IWUSR, 1935 root, dev, 1936 fops); 1937 if (IS_ERR(ent)) 1938 return PTR_ERR(ent); 1939 1940 return drm_add_fake_info_node(minor, ent, fops); 1941 } 1942 1943 static struct drm_info_list i915_debugfs_list[] = { 1944 {"i915_capabilities", i915_capabilities, 0}, 1945 {"i915_gem_objects", i915_gem_object_info, 0}, 1946 {"i915_gem_gtt", i915_gem_gtt_info, 0}, 1947 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, 1948 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, 1949 {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST}, 1950 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, 1951 {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, 1952 {"i915_gem_request", i915_gem_request_info, 0}, 1953 {"i915_gem_seqno", i915_gem_seqno_info, 0}, 1954 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, 1955 {"i915_gem_interrupt", i915_interrupt_info, 0}, 1956 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, 1957 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, 1958 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, 1959 {"i915_rstdby_delays", i915_rstdby_delays, 0}, 1960 {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, 1961 {"i915_delayfreq_table", i915_delayfreq_table, 0}, 1962 {"i915_inttoext_table", i915_inttoext_table, 0}, 1963 {"i915_drpc_info", i915_drpc_info, 0}, 1964 {"i915_emon_status", i915_emon_status, 0}, 1965 {"i915_ring_freq_table", i915_ring_freq_table, 0}, 1966 {"i915_gfxec", i915_gfxec, 0}, 1967 {"i915_fbc_status", i915_fbc_status, 0}, 1968 {"i915_sr_status", i915_sr_status, 0}, 1969 {"i915_opregion", i915_opregion, 0}, 1970 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, 1971 {"i915_context_status", i915_context_status, 0}, 1972 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, 1973 {"i915_swizzle_info", i915_swizzle_info, 0}, 1974 {"i915_ppgtt_info", i915_ppgtt_info, 0}, 1975 {"i915_dpio", i915_dpio_info, 0}, 1976 }; 1977 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) 1978 1979 int i915_debugfs_init(struct drm_minor *minor) 1980 { 1981 int ret; 1982 1983 ret = i915_debugfs_create(minor->debugfs_root, minor, 1984 "i915_wedged", 1985 &i915_wedged_fops); 1986 if (ret) 1987 return ret; 1988 1989 ret = i915_forcewake_create(minor->debugfs_root, minor); 1990 if (ret) 1991 return ret; 1992 1993 ret = i915_debugfs_create(minor->debugfs_root, minor, 1994 "i915_max_freq", 1995 &i915_max_freq_fops); 1996 if (ret) 1997 return ret; 1998 1999 ret = i915_debugfs_create(minor->debugfs_root, minor, 2000 "i915_cache_sharing", 2001 &i915_cache_sharing_fops); 2002 if (ret) 2003 return ret; 2004 ret = i915_debugfs_create(minor->debugfs_root, minor, 2005 "i915_ring_stop", 2006 &i915_ring_stop_fops); 2007 if (ret) 2008 return ret; 2009 2010 ret = i915_debugfs_create(minor->debugfs_root, minor, 2011 "i915_error_state", 2012 &i915_error_state_fops); 2013 if (ret) 2014 return ret; 2015 2016 return drm_debugfs_create_files(i915_debugfs_list, 2017 I915_DEBUGFS_ENTRIES, 2018 minor->debugfs_root, minor); 2019 } 2020 2021 void i915_debugfs_cleanup(struct drm_minor *minor) 2022 { 2023 drm_debugfs_remove_files(i915_debugfs_list, 2024 I915_DEBUGFS_ENTRIES, minor); 2025 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, 2026 1, minor); 2027 drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops, 2028 1, minor); 2029 drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops, 2030 1, minor); 2031 drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops, 2032 1, minor); 2033 drm_debugfs_remove_files((struct drm_info_list *) &i915_ring_stop_fops, 2034 1, minor); 2035 drm_debugfs_remove_files((struct drm_info_list *) &i915_error_state_fops, 2036 1, minor); 2037 } 2038 2039 #endif /* CONFIG_DEBUG_FS */ 2040