1*28c4c6caSZhi Wang /* 2*28c4c6caSZhi Wang * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3*28c4c6caSZhi Wang * 4*28c4c6caSZhi Wang * Permission is hereby granted, free of charge, to any person obtaining a 5*28c4c6caSZhi Wang * copy of this software and associated documentation files (the "Software"), 6*28c4c6caSZhi Wang * to deal in the Software without restriction, including without limitation 7*28c4c6caSZhi Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*28c4c6caSZhi Wang * and/or sell copies of the Software, and to permit persons to whom the 9*28c4c6caSZhi Wang * Software is furnished to do so, subject to the following conditions: 10*28c4c6caSZhi Wang * 11*28c4c6caSZhi Wang * The above copyright notice and this permission notice (including the next 12*28c4c6caSZhi Wang * paragraph) shall be included in all copies or substantial portions of the 13*28c4c6caSZhi Wang * Software. 14*28c4c6caSZhi Wang * 15*28c4c6caSZhi Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16*28c4c6caSZhi Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17*28c4c6caSZhi Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18*28c4c6caSZhi Wang * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19*28c4c6caSZhi Wang * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20*28c4c6caSZhi Wang * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21*28c4c6caSZhi Wang * SOFTWARE. 22*28c4c6caSZhi Wang */ 23*28c4c6caSZhi Wang 24*28c4c6caSZhi Wang #ifndef _GVT_SCHEDULER_H_ 25*28c4c6caSZhi Wang #define _GVT_SCHEDULER_H_ 26*28c4c6caSZhi Wang 27*28c4c6caSZhi Wang struct intel_gvt_workload_scheduler { 28*28c4c6caSZhi Wang struct list_head workload_q_head[I915_NUM_ENGINES]; 29*28c4c6caSZhi Wang }; 30*28c4c6caSZhi Wang 31*28c4c6caSZhi Wang struct intel_vgpu_workload { 32*28c4c6caSZhi Wang struct intel_vgpu *vgpu; 33*28c4c6caSZhi Wang int ring_id; 34*28c4c6caSZhi Wang struct drm_i915_gem_request *req; 35*28c4c6caSZhi Wang /* if this workload has been dispatched to i915? */ 36*28c4c6caSZhi Wang bool dispatched; 37*28c4c6caSZhi Wang int status; 38*28c4c6caSZhi Wang 39*28c4c6caSZhi Wang struct intel_vgpu_mm *shadow_mm; 40*28c4c6caSZhi Wang 41*28c4c6caSZhi Wang /* different submission model may need different handler */ 42*28c4c6caSZhi Wang int (*prepare)(struct intel_vgpu_workload *); 43*28c4c6caSZhi Wang int (*complete)(struct intel_vgpu_workload *); 44*28c4c6caSZhi Wang struct list_head list; 45*28c4c6caSZhi Wang 46*28c4c6caSZhi Wang /* execlist context information */ 47*28c4c6caSZhi Wang struct execlist_ctx_descriptor_format ctx_desc; 48*28c4c6caSZhi Wang struct execlist_ring_context *ring_context; 49*28c4c6caSZhi Wang unsigned long rb_head, rb_tail, rb_ctl, rb_start; 50*28c4c6caSZhi Wang struct intel_vgpu_elsp_dwords elsp_dwords; 51*28c4c6caSZhi Wang bool emulate_schedule_in; 52*28c4c6caSZhi Wang atomic_t shadow_ctx_active; 53*28c4c6caSZhi Wang wait_queue_head_t shadow_ctx_status_wq; 54*28c4c6caSZhi Wang u64 ring_context_gpa; 55*28c4c6caSZhi Wang }; 56*28c4c6caSZhi Wang 57*28c4c6caSZhi Wang #define workload_q_head(vgpu, ring_id) \ 58*28c4c6caSZhi Wang (&(vgpu->workload_q_head[ring_id])) 59*28c4c6caSZhi Wang 60*28c4c6caSZhi Wang #define queue_workload(workload) \ 61*28c4c6caSZhi Wang list_add_tail(&workload->list, \ 62*28c4c6caSZhi Wang workload_q_head(workload->vgpu, workload->ring_id)) 63*28c4c6caSZhi Wang 64*28c4c6caSZhi Wang #endif 65